1

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Exp No: 1
CMOS INVERTER
Aim:
a) To construct the CMOS Inverter in Tanner EDA v13.1 and to do the Transient
Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.

Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

I- M.Tech II SEM-(VLSI System Design)

Mixed Signal Lab

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Schematic Diagram:

Fig (a): CMOS Inverter

I- M.Tech II SEM-(VLSI System Design)

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Tanner Spice Code:

* SPICE export by: SEDIT 13.12
* Export time:
Fri Apr 16 11:43:07 2010
* Design:
adm705-1
* Cell:
Cell3
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\Administrator\Desktop\adm705-1
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner
Tools v13.1\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out N_2 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Out N_2 Vdd N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(Out)
.PRINT TRAN V(N_2)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVoltageSource_1 0 5 0.5
.print dc v(MNMOS_1,Gnd)
********* Simulation Settings - Additional SPICE commands *********
.end

I- M.Tech II SEM-(VLSI System Design)

Mixed Signal Lab

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Output responses:

Fig (b): CMOS Inverter Waveforms

I- M.Tech II SEM-(VLSI System Design)

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DC Analysis:

Result:
The CMOS Inverter is constructed in Tanner EDA v13.1, the spice code is
generated and waveforms are verified.

I- M.Tech II SEM-(VLSI System Design)

Mixed Signal Lab

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Exp No: 2
LOGIC GATES
Aim:
a) To construct the following Logic Gates in Tanner EDA v13.1 and to do the
Transient Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.
(i) NAND (ii) NOR (iii) OR (iv) AND (v) Ex-OR (vi) Ex-NOR

Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

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Mixed Signal Lab

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Schematic Diagram:
(i)

NAND Gate:

Fig : NAND Gate Schematic

I- M.Tech II SEM-(VLSI System Design)

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Tanner Spice Code:

* SPICE export by: SEDIT 13.12
* Export time:
Fri Mar 26 11:08:22 2010
* Design:
Prasad
* Cell:
Cell0
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\user\Desktop\705\Prasad
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\user\My Documents\Tanner EDA\Tanner Tools
v13.1\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out In1 N_4 N_3 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_4 In Gnd N_5 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 Out In Vdd N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Out In1 Vdd N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_2 In1 Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(In)
.PRINT TRAN V(In1)
.PRINT TRAN V(Out)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVoltageSource_2 0 5 0.5 sweep lin source VVoltageSource_3 0 5 0.5
.print dc v(MPMOS_1,Gnd)

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********* Simulation Settings - Additional SPICE commands *********
.end

Output responses:
INPUT A

INPUT B

OUTPUT

Fig : NAND Gate Waveforms

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Mixed Signal Lab

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(ii) NOR Gate:

Fig :NOR Gate Schematic

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Mixed Signal Lab

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Tanner Spice Code:

* SPICE export by: SEDIT 13.12
* Export time:
Fri Mar 26 12:26:28 2010
* Design:
Prasad
* Cell:
Cell3
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\user\Desktop\705\Prasad
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\user\My Documents\Tanner EDA\Tanner Tools
v13.1\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out In1 Gnd N_2 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 Out In Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_4 In Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Out In1 N_4 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 In1 Gnd PULSE(0 5 0 5n 5n 25n 50n)
VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 50n 100n)
.PRINT TRAN V(In)
.PRINT TRAN V(In1)
.PRINT TRAN V(Out)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source vvoltagesource_2 0 5 0.5 sweep lin source vvoltagesource_3 0 5 0.5
.print dc v(MPMOS_2,gnd)
********* Simulation Settings - Additional SPICE commands *********

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Mixed Signal Lab

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.end

Output responses:

Fig : NOR Gate Waveforms

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Mixed Signal Lab

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(iii) AND Gate:

Fig : AND Gate Schematic

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Tanner Spice Code:

* SPICE export by: SEDIT 13.12
* Export time:
Fri Mar 26 11:32:44 2010
* Design:
Prasad
* Cell:
Cell1
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\user\Desktop\705\Prasad
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\user\My Documents\Tanner EDA\Tanner Tools
v13.1\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_4 In1 N_2 N_3 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_2 In Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 Out N_4 Gnd N_7 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_4 In Vdd N_6 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 N_4 In1 Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_3 Out N_4 Vdd N_8 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 In1 Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(In)
.PRINT TRAN V(In1)
.PRINT TRAN V(Out)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source vvoltagesource_2 0 5 0.5 sweep lin source vvoltagesource_3 0 5 0.5
.print dc v(MPMOS_3,gnd)
********* Simulation Settings - Additional SPICE commands *********

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.end

Output responses:

Fig : AND Gate Waveforms

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Layout Diagram of AND gate:

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Layout Net list of AND:

* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;
* TDB File: Layout1
* Cell: Core Version 1.01
* Extract Definition File: lights.ext
* Extract Date and Time: 07/27/2010 - 09:56
.include lights.md
* NODE NAME ALIASES
*
1 = Vdd (-50 , 4)
*
1 = U1/NAND2C_1/Vdd (0 , 70)
*
1 = U1/NAND2C_2/Vdd (34 , 70)
*
2 = Gnd (41 , 4)
*
2 = U1/NAND2C_1/Gnd (0 , 12)
*
2 = U1/NAND2C_2/Gnd (34 , 12)
*
3 = Out (49 , 82.5)
*
3 = U1/NAND2C_2/Out1 (19 , 36)
*
4 = a (-50 , 82.5)
*
4 = U1/NAND2C_1/A (-31 , 54)
*
5 = U1/NAND2C_1/Out1 (-15 , 36)
*
5 = U1/NAND2C_2/A (3 , 54)
*
5 = U1/NAND2C_2/B (11 , 47)
*
6 = b (-50 , 4.5)
*
6 = U1/NAND2C_1/B (-23 , 47)
*
7 = U1/NAND2C_2/Out2 (27 , 38)
*
8 = U1/NAND2C_1/Out2 (-7 , 38)
M1 Vdd U1/NAND2C_1/Out1 Out Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M2 Out U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=144p PS=68u
M3 U1/NAND2C_2/Out2 Out Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u
AS=84p PS=34u
M4 Vdd b U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M5 U1/NAND2C_1/Out1 a Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M6 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M7 Gnd U1/NAND2C_1/Out1 10 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u

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M8 10 U1/NAND2C_1/Out1 Out Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M9 U1/NAND2C_2/Out2 Out Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
M10 Gnd b 9 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M11 9 a U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M12 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
* Total Nodes: 10
* Total Elements: 12
* Total Number of Shorted Elements not written to the SPICE file: 4
* Output Generation Elapsed Time: 0.016 sec
* Total Extract Elapsed Time: 2.328 sec
.END

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(iv) OR Gate:

Fig : OR Gate Schematic

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Mixed Signal Lab

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Tanner Spice Code:

* SPICE export by: SEDIT 13.12
* Export time:
Fri Mar 26 12:18:24 2010
* Design:
Prasad
* Cell:
Cell2
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Root path:
C:\Documents and Settings\user\Desktop\705\Prasad
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\user\My Documents\Tanner EDA\Tanner Tools
v13.1\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_4 In1 Gnd N_5 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_4 In Gnd N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 Out N_4 Gnd N_8 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_2 In Vdd N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 N_4 In1 N_2 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_3 Out N_4 Vdd N_7 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 In1 Gnd PULSE(0 5 0 5n 5n 25n 50n)
VVoltageSource_3 In Gnd PULSE(0 5 0 5n 5n 50n 100n)
.PRINT TRAN V(In)
.PRINT TRAN V(In1)
.PRINT TRAN V(Out)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source vvoltagesource_2 0 5 0.5 sweep lin source vvoltagesource_3 0 5 0.5
.print dc v(MNMOS_3,gnd)
********* Simulation Settings - Additional SPICE commands *********
.end

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Output responses:

Fig : OR Gate Waveforms

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Layout Diagram of OR Gate:

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OR Layout Net List:

* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;
* TDB File: Layout1
* Cell: Core Version 1.01
* Extract Definition File: lights.ext
* Extract Date and Time: 07/27/2010 - 10:05
.include lights.md
* NODE NAME ALIASES
*
1 = U1/NAND2C_3/Out2 (44 , 46)
*
2 = a (-67 , 90.5)
*
2 = U1/NAND2C_1/A (-48 , 62)
*
2 = U1/NAND2C_1/B (-40 , 55)
*
3 = U1/NAND2C_1/Out1 (-32 , 44)
*
3 = U1/NAND2C_3/A (20 , 62)
*
4 = b (-67 , 4.5)
*
4 = U1/NAND2C_2/A (-14 , 62)
*
4 = U1/NAND2C_2/B (-6 , 55)
*
5 = U1/NAND2C_2/Out2 (10 , 46)
*
6 = U1/NAND2C_1/Out2 (-24 , 46)
*
7 = Out (66 , 90.5)
*
7 = U1/NAND2C_3/Out1 (36 , 44)
*
8 = Vdd (-67 , 4)
*
8 = U1/NAND2C_1/Vdd (-17 , 78)
*
8 = U1/NAND2C_2/Vdd (17 , 78)
*
8 = U1/NAND2C_3/Vdd (17 , 78)
*
11 = Gnd (58 , 4)
*
11 = U1/NAND2C_1/Gnd (-17 , 20)
*
11 = U1/NAND2C_2/Gnd (17 , 20)
*
11 = U1/NAND2C_3/Gnd (17 , 20)
*
12 = U1/NAND2C_2/Out1 (2 , 44)
*
12 = U1/NAND2C_3/B (28 , 55)
M1 Vdd U1/NAND2C_2/Out1 Out Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M2 U1/NAND2C_3/Out2 Out Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u
AS=84p PS=34u
M3 U1/NAND2C_3/Out2 Out Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
M4 Out U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=144p PS=68u

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M5 Vdd b U1/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M6 U1/NAND2C_2/Out1 b Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M7 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M8 Vdd a U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M9 U1/NAND2C_1/Out1 a Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M10 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M11 Gnd U1/NAND2C_2/Out1 13 Gnd NMOS L=2u W=28u AD=122p PD=47u
AS=28p PS=30u
M12 13 U1/NAND2C_1/Out1 Out Gnd NMOS L=2u W=28u AD=28p PD=30u
AS=148p PS=68u
M13 Gnd b 10 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M14 10 b U1/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M15 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
M16 Gnd a 9 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M17 9 a U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M18 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
* Total Nodes: 13
* Total Elements: 18
* Total Number of Shorted Elements not written to the SPICE file: 6
* Output Generation Elapsed Time: 0.000 sec
* Total Extract Elapsed Time: 2.468 sec
.END

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(v) Ex-OR Gate:

Fig : Ex-OR Gate Schematic

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Tanner Spice Code:

********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_3 N_2 N_3 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_4 N_3 In2 Gnd N_18 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_5 N_5 In2 Gnd N_4 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_6 N_7 In1 N_2 N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_7 Out N_7 Gnd N_19 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_1 N_8 In1 Gnd N_16 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_7 N_8 N_5 N_15 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_9 N_8 Vdd N_10 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 N_3 In2 Vdd N_11 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_3 N_7 In1 N_9 N_12 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_4 N_9 In2 Vdd N_13 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_5 N_7 N_3 N_9 N_14 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_6 N_8 In1 Vdd N_17 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_7 Out N_7 Vdd N_20 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 50n 25n)
VVoltageSource_3 In1 Gnd PULSE(0 5 0 5n 5n 100n 50n)
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(Out)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVoltageSource_2 0 5 0.5 sweep lin source VVoltageSource_3 0 5 0.5
.print dc v(MNMOS_7,gnd)
********* Simulation Settings - Additional SPICE commands *********
.end

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Output responses:
INPUT A

INPUT B

OUTPUT

Fig : Ex-OR Gate Waveforms

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(vi) Ex-NOR Gate:

Fig : Ex-NOR Gate Schematic

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Tanner Spice Code:

********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner
Tools v13.1\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_26 In1 Gnd N_15 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 Out N_26 N_4 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 N_19 N_14 Gnd N_11 NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
MNMOS_4 N_14 In2 Gnd N_12 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_5 N_4 In2 Gnd N_10 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_6 Out In1 N_19 N_9 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_3 N_26 Vdd N_8 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 N_14 In2 Vdd N_7 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_3 Out In1 N_3 N_6 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_4 N_3 In2 Vdd N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_5 Out N_14 N_3 N_2 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_6 N_26 In1 Vdd N_13 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 50n 25n)
VVoltageSource_3 In1 Gnd PULSE(0 5 0 5n 5n 100n 50n)
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(Out)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVoltageSource_2 0 5 0.5 sweep lin source VVoltageSource_3 0 5 0.5
.print dc v(MNMOS_6,gnd)
********* Simulation Settings - Additional SPICE commands *********
.end

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Output responses:
INPUT A

INPUT B

OUTPUT

Fig : Ex-NOR Gate Waveforms

Result:
The Logic Gates are constructed in Tanner EDA v13.1, the spice code is
generated and wave forms are verified.

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Exp No: 3
HALF ADDER
Aim:
a) To construct the Half Adder in Tanner EDA v13.1 and to do the Transient
Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.

Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

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Schematic Diagram:

Fig (a): Half Adder Schematic

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Tanner Spice Code:

* SPICE export by: SEDIT 13.12
* Export time:
Fri Apr 16 11:24:00 2010
* Design:
adm705-1
* Cell:
Cell2
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\Administrator\Desktop\adm705-1
* Exclude global pins: no
* Control property name: SPICE

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner
Tools v13.1\Libraries\Models\Generic_025.lib" TT
*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt NAND2C A B Out1 Out2 Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: NAND2C / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NAND with complementary output.
* Date: 6/14/2007 1:47:11 AM

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* Revision: 2
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u
AD=2.25p PD=6.8u
.ends
.subckt XNOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: XNOR2 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NOR
* Date: 7/18/2008 3:58:48 AM
* Revision: 4
*-------- Devices: SPICE.ORDER > 0 -------MM3n 1 A 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM10n Out 1 5 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM9n 5 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM8n Out 1 4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM7n 4 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM4n 2 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM5p 3 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM11p Out 1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM2p 1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM1p 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM6p Out A 3 Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt XOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: XOR2 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.

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* Info: 2 Input NOR
* Date: 7/18/2008 1:30:51 AM
* Revision: 3
*-------- Devices: SPICE.ORDER == 0 -------XXinv N_1 Out Gnd Vdd INV
XXxnor A B N_1 Gnd Vdd XNOR2
.ends
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 -------XINV_1 N_1 carry Gnd Vdd INV
XNAND2C_1 In1 In2 N_1 N_2 Gnd Vdd NAND2C
XXOR2_1 In1 In2 sum Gnd Vdd XOR2
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_3 Vdd Gnd DC 5
VVoltageSource_1 In1 Gnd PULSE(0 5 0 5n 5n 50n 100n)
VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 25n 50n)
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(carry)
.PRINT TRAN V(sum)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVoltageSource_1 0 5 0.5 sweep lin source VVoltageSource_2 0 5 0.5
.print dc v(XINV_1,GND)
.print dc v(XXOR2_1,GND)
********* Simulation Settings - Additional SPICE commands *********
.end

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Output responses:

Result:
The Half Adder is constructed in Tanner EDA v13.1, the spice code is generated
and wave forms are verified.

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Exp No: 4
FULL ADDER
Aim:
a) To construct the Full Adder in Tanner EDA v13.1 and to do the Transient
Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.

Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

Schematic Diagram:
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Fig (a): Full Adder Schematic1

Fig (b): Full Adder Schematic2

Tanner Spice Code:

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********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner
Tools v13.1\Libraries\Models\Generic_025.lib" TT
*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt NAND2C A B Out1 Out2 Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: NAND2C / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NAND with complementary output.
* Date: 6/14/2007 1:47:11 AM
* Revision: 2
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u
AD=2.25p PD=6.8u
.ends
.subckt NAND3C A B C Out1 Out2 Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: NAND3C / View: Main / Page:
* Designed by: Author
* Organization: Organization
* Info: Info

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* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out1 C 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 2 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN4 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP3 Out1 C Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP4 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u
AD=2.25p PD=6.8u
.ends
.subckt XNOR2 A B Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: XNOR2 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NOR
* Date: 7/18/2008 3:58:48 AM
* Revision: 4
*-------- Devices: SPICE.ORDER > 0 -------MM3n 1 A 2 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM10n Out 1 5 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM9n 5 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM8n Out 1 4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM7n 4 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM4n 2 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MM5p 3 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM11p Out 1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM2p 1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM1p 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MM6p Out A 3 Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt XOR2 A B Out Gnd Vdd

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*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: XOR2 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NOR
* Date: 7/18/2008 1:30:51 AM
* Revision: 3
*-------- Devices: SPICE.ORDER == 0 -------XXinv N_1 Out Gnd Vdd INV
XXxnor A B N_1 Gnd Vdd XNOR2
.ends
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 -------XXOR2_2 N_8 In3 sum Gnd Vdd XOR2
XNAND3C_1 N_1 N_2 N_3 carry N_4 Gnd Vdd NAND3C
XNAND2C_1 In1 In2 N_1 N_7 Gnd Vdd NAND2C
XNAND2C_2 In2 In3 N_2 N_6 Gnd Vdd NAND2C
XNAND2C_3 In1 In3 N_3 N_5 Gnd Vdd NAND2C
XXOR2_1 In1 In2 N_8 Gnd Vdd XOR2
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_4 Vdd Gnd DC 5
VVoltageSource_1 In1 Gnd PULSE(0 5 0 5n 5n 100n 200n)
VVoltageSource_2 In2 Gnd PULSE(0 5 0 5n 5n 50n 100n)
VVoltageSource_3 In3 Gnd PULSE(0 5 0 5n 5n 25n 50n)
.PRINT TRAN V(In1)
.PRINT TRAN V(In2)
.PRINT TRAN V(In3)
.PRINT TRAN V(sum)
.PRINT TRAN V(carry)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVOLTAGESOURCE_1 0 5 0.5 sweep lin source
VVOLTAGESOURCE_2 0 5 0.5 sweep lin source VVOLTAGESOURCE_3 0 5 0.5
.print dc v(XXOR2_2,GND)
.print dc v(XXOR2_2,GND) v(XNAND3C_1,GND)
********* Simulation Settings - Additional SPICE commands *********
.end

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Output responses:
INPUT V(A)

INPUT V(B)
INPUT V(C)

OUTPUT V(SUM)

OUTPUT V(CARRY)

Fig (b): Full Adder wave forms

Layout Diagram of Full adder:

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Layout Net list:

* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;
* TDB File: Layout1
* Cell: Core Version 1.01
* Extract Definition File: lights.ext
* Extract Date and Time: 07/29/2010 - 09:41
.include lights.md
* NODE NAME ALIASES

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*
1 = CARRY (125 , 142.5)
*
1 = U2/NAND2C_9/Out1 (87 , 96)
*
2 = SUM (125 , 56.5)
*
2 = U2/NAND2C_8/Out1 (53 , 96)
*
3 = U2/NAND2C_7/Out1 (19 , 96)
*
3 = U2/NAND2C_8/B (45 , 107)
*
4 = U2/NAND2C_9/Out2 (95 , 98)
*
5 = U2/NAND2C_8/Out2 (61 , 98)
*
6 = U2/NAND2C_7/Out2 (27 , 98)
*
10 = U2/NAND2C_6/Out1 (-15 , 96)
*
10 = U2/NAND2C_8/A (37 , 114)
*
11 = U2/NAND2C_5/Out1 (-49 , 96)
*
11 = U2/NAND2C_6/B (-23 , 107)
*
11 = U2/NAND2C_7/A (3 , 114)
*
11 = U2/NAND2C_9/B (79 , 107)
*
12 = U2/NAND2C_5/A (-65 , 114)
*
12 = U2/NAND2C_6/A (-31 , 114)
*
12 = U3/NAND2C_4/Out1 (53 , -22)
*
13 = U2/NAND2C_6/Out2 (-7 , 98)
*
14 = U2/NAND2C_5/Out2 (-41 , 98)
*
17 = U3/NAND2C_3/Out1 (19 , -22)
*
17 = U3/NAND2C_4/B (45 , -11)
*
18 = U3/NAND2C_4/Out2 (61 , -20)
*
19 = U3/NAND2C_3/Out2 (27 , -20)
*
22 = Vdd (-100 , -62)
*
22 = U2/A/Vdd (-68 , 130)
*
22 = U2/NAND2C_5/Vdd (-34 , 130)
*
22 = U2/NAND2C_6/Vdd (-34 , 130)
*
22 = U2/NAND2C_7/Vdd (34 , 130)
*
22 = U2/NAND2C_8/Vdd (68 , 130)
*
22 = U2/NAND2C_9/Vdd (68 , 130)
*
22 = U3/Cin/Vdd (-34 , 12)
*
22 = U3/NAND2C_1/Vdd (-42 , 12)
*
22 = U3/NAND2C_2/Vdd (-34 , 12)
*
22 = U3/NAND2C_3/Vdd (34 , 12)
*
22 = U3/NAND2C_4/Vdd (68 , 12)
*
23 = Gnd (109 , -62)
*
23 = U2/A/Gnd (-68 , 72)
*
23 = U2/NAND2C_5/Gnd (-34 , 72)
*
23 = U2/NAND2C_6/Gnd (-34 , 72)
*
23 = U2/NAND2C_7/Gnd (34 , 72)
*
23 = U2/NAND2C_8/Gnd (68 , 72)
*
23 = U2/NAND2C_9/Gnd (68 , 72)
*
23 = U3/Cin/Gnd (-34 , -46)
*
23 = U3/NAND2C_1/Gnd (-42 , -46)
*
23 = U3/NAND2C_2/Gnd (-34 , -46)
*
23 = U3/NAND2C_3/Gnd (34 , -46)

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*
23 = U3/NAND2C_4/Gnd (68 , -46)
*
24 = U2/NAND2C_9/A (71 , 114)
*
24 = U3/NAND2C_1/Out1 (-57 , -22)
*
24 = U3/NAND2C_2/B (-23 , -11)
*
24 = U3/NAND2C_3/A (3 , -4)
*
25 = A (-100 , 142.5)
*
25 = U3/NAND2C_1/A (-73 , -4)
*
25 = U3/NAND2C_2/A (-31 , -4)
*
26 = Cin (-100 , -61.5)
*
26 = U2/NAND2C_5/B (-57 , 107)
*
26 = U2/NAND2C_7/B (11 , 107)
*
27 = B (-100 , 32.5)
*
27 = U3/NAND2C_1/B (-65 , -11)
*
27 = U3/NAND2C_3/B (11 , -11)
*
28 = U3/NAND2C_2/Out1 (-15 , -22)
*
28 = U3/NAND2C_4/A (37 , -4)
*
29 = U3/NAND2C_2/Out2 (-7 , -20)
*
30 = U3/NAND2C_1/Out2 (-49 , -20)
M1 Vdd U2/NAND2C_5/Out1 CARRY Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=84p PS=34u
M2 CARRY U2/NAND2C_9/A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=144p PS=68u
M3 U2/NAND2C_9/Out2 CARRY Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u
AS=84p PS=34u
M4 Vdd U2/NAND2C_7/Out1 SUM Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=84p PS=34u
M5 SUM U2/NAND2C_6/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=144p PS=68u
M6 U2/NAND2C_8/Out2 SUM Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u
AS=84p PS=34u
M7 Vdd Cin U2/NAND2C_7/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M8 U2/NAND2C_7/Out1 U2/NAND2C_5/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p
PD=34u AS=144p PS=68u
M9 U2/NAND2C_7/Out2 U2/NAND2C_7/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M10 Gnd U2/NAND2C_5/Out1 9 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u
M11 9 U2/NAND2C_9/A CARRY Gnd NMOS L=2u W=28u AD=28p PD=30u
AS=148p PS=68u
M12 U2/NAND2C_9/Out2 CARRY Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
M13 Gnd U2/NAND2C_7/Out1 8 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u
M14 8 U2/NAND2C_6/Out1 SUM Gnd NMOS L=2u W=28u AD=28p PD=30u
AS=148p PS=68u

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M15 U2/NAND2C_8/Out2 SUM Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
M16 Gnd Cin 7 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M17 7 U2/NAND2C_5/Out1 U2/NAND2C_7/Out1 Gnd NMOS L=2u W=28u AD=28p
PD=30u AS=148p PS=68u
M18 U2/NAND2C_7/Out2 U2/NAND2C_7/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
M19 Vdd U2/NAND2C_5/Out1 U2/NAND2C_6/Out1 Vdd PMOS L=2u W=28u
AD=84p PD=34u AS=84p PS=34u
M20 U2/NAND2C_6/Out1 U2/NAND2C_5/A Vdd Vdd PMOS L=2u W=28u AD=84p
PD=34u AS=144p PS=68u
M21 U2/NAND2C_6/Out2 U2/NAND2C_6/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M22 Vdd Cin U2/NAND2C_5/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=84p PS=34u
M23 U2/NAND2C_5/Out1 U2/NAND2C_5/A Vdd Vdd PMOS L=2u W=28u AD=84p
PD=34u AS=144p PS=68u
M24 U2/NAND2C_5/Out2 U2/NAND2C_5/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M25 Gnd U2/NAND2C_5/Out1 16 Gnd NMOS L=2u W=28u AD=122p PD=47u
AS=28p PS=30u
M26 16 U2/NAND2C_5/A U2/NAND2C_6/Out1 Gnd NMOS L=2u W=28u AD=28p
PD=30u AS=148p PS=68u
M27 U2/NAND2C_6/Out2 U2/NAND2C_6/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
M28 Gnd Cin 15 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M29 15 U2/NAND2C_5/A U2/NAND2C_5/Out1 Gnd NMOS L=2u W=28u AD=28p
PD=30u AS=148p PS=68u
M30 U2/NAND2C_5/Out2 U2/NAND2C_5/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
M31 Vdd U3/NAND2C_3/Out1 U2/NAND2C_5/A Vdd PMOS L=2u W=28u AD=84p
PD=34u AS=84p PS=34u
M32 U2/NAND2C_5/A U3/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p
PD=34u AS=144p PS=68u
M33 U3/NAND2C_4/Out2 U2/NAND2C_5/A Vdd Vdd PMOS L=2u W=28u AD=148p
PD=68u AS=84p PS=34u
M34 Vdd B U3/NAND2C_3/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
M35 U3/NAND2C_3/Out1 U2/NAND2C_9/A Vdd Vdd PMOS L=2u W=28u AD=84p
M36 U3/NAND2C_3/Out2 U3/NAND2C_3/Out1 Vdd Vdd PMOS L=2u W=28u M37
Gnd U3/NAND2C_3/Out1 21 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
M38 21 U3/NAND2C_2/Out1 U2/NAND2C_5/A Gnd NMOS L=2u W=28u AD=28p
PD=30u AS=148p PS=68u
M39 U3/NAND2C_4/Out2 U2/NAND2C_5/A Gnd Gnd NMOS L=2u W=28u AD=148p
PD=68u AS=122p PS=47u
M40 Gnd B 20 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M41 20 U2/NAND2C_9/A U3/NAND2C_3/Out1 Gnd NMOS L=2u W=28u AD=28p
PD=30u AS=148p PS=68u

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M42 U3/NAND2C_3/Out2 U3/NAND2C_3/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
M43 Vdd U2/NAND2C_9/A U3/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p
PD=34u AS=84p PS=34u
M44 U3/NAND2C_2/Out1 A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M45 U3/NAND2C_2/Out2 U3/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M46 Vdd B U2/NAND2C_9/A Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M47 U2/NAND2C_9/A A Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M48 U3/NAND2C_1/Out2 U2/NAND2C_9/A Vdd Vdd PMOS L=2u W=28u AD=148p
PD=68u AS=84p PS=34u
M49 Gnd U2/NAND2C_9/A 32 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u
M50 32 A U3/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M51 U3/NAND2C_2/Out2 U3/NAND2C_2/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
M52 Gnd B 31 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M53 31 A U2/NAND2C_9/A Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p M54
U3/NAND2C_1/Out2 U2/NAND2C_9/A Gnd Gnd NMOS L=2u W=28u AD=148p
PD=68u AS=122p PS=47u
* Total Nodes: 32
* Total Elements: 54
* Total Number of Shorted Elements not written to the SPICE file: 18
* Output Generation Elapsed Time: 0.000 sec
* Total Extract Elapsed Time: 2.422 sec
.END

Result:
The Full Adder is constructed in Tanner EDA v13.1, the spice code is generated
and wave forms are verified

Exp No: 5
D - FLIP FLOP
Aim:
a) To construct the D-Flip flop in Tanner EDA v13.1 and to do the Transient
Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.

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Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

Schematic Diagram:

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49
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Fig : D - Flip Flop Schematic

Tanner Spice Code:

* SPICE export by: SEDIT 13.12
* Export time:
Fri Apr 23 10:38:02 2010
* Design:
Prasad1
* Cell:
Cell1
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical

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50
_______________________________________________________________________
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\Administrator\Desktop\Prasad1
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner
Tools v13.1\Libraries\Models\Generic_025.lib" TT
*************** Subcircuits *****************
.subckt NAND2C A B Out1 Out2 Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: NAND2C / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NAND with complementary output.
* Date: 6/14/2007 1:47:11 AM
* Revision: 2
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u
AD=2.25p PD=6.8u
.ends

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER == 0 -------XNAND2C_1 D Clk N_5 N_8 Gnd Vdd NAND2C
XNAND2C_2 Clk N_1 N_3 N_7 Gnd Vdd NAND2C
XNAND2C_3 N_5 QBar Q N_6 Gnd Vdd NAND2C
XNAND2C_4 Q N_3 QBar N_4 Gnd Vdd NAND2C

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XNAND2C_5 D D N_1 N_2 Gnd Vdd NAND2C
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_3 Vdd Gnd DC 5
VVoltageSource_2 Clk Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_1 D Gnd BIT({0100101111} )
.PRINT TRAN V(D)
.PRINT TRAN V(Clk)
.PRINT TRAN V(Q)
.PRINT TRAN V(QBar)
********* Simulation Settings - Analysis section *********
.tran 350ns 500ns
.dc lin source VVoltageSource_2 0 5 0.5
.print dc v(Q,Gnd)
********* Simulation Settings - Additional SPICE commands *********
.end

Output responses:

I- M.Tech II SEM-(VLSI System Design)

Mixed Signal Lab

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52
_______________________________________________________________________

Fig (b): D-Flip flop waveforms

Layout Diagram:

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Mixed Signal Lab

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53
_______________________________________________________________________

Layout Net list:

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* Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;
* TDB File: Layout1
* Cell: Core Version 1.01
* Extract Definition File: lights.ext
* Extract Date and Time: 07/29/2010 - 09:47
.include lights.md
* NODE NAME ALIASES
*
1 = U1/NAND2C_5/Out2 (78 , 54)
*
2 = U1/NAND2C_4/Out2 (44 , 54)
*
3 = U1/NAND2C_3/Out2 (10 , 54)
*
6 = q (100 , 12.5)
*
6 = U1/NAND2C_3/Out1 (2 , 52)
*
6 = U1/NAND2C_4/A (20 , 70)
*
7 = Vdd (-101 , 4)
*
7 = U1/NAND2C_1/Vdd (-51 , 86)
*
7 = U1/NAND2C_2/Vdd (-17 , 86)
*
7 = U1/NAND2C_3/Vdd (-17 , 86)
*
7 = U1/NAND2C_4/Vdd (51 , 86)
*
7 = U1/NAND2C_5/Vdd (85 , 86)
*
8 = d (-101 , 106.5)
*
8 = U1/NAND2C_1/A (-82 , 70)
*
8 = U1/NAND2C_5/A (54 , 70)
*
8 = U1/NAND2C_5/B (62 , 63)
*
9 = U1/NAND2C_1/Out1 (-66 , 52)
*
9 = U1/NAND2C_3/A (-14 , 70)
*
10 = U1/NAND2C_2/Out1 (-32 , 52)
*
10 = U1/NAND2C_4/B (28 , 63)
*
11 = U1/NAND2C_2/B (-40 , 63)
*
11 = U1/NAND2C_5/Out1 (70 , 52)
*
12 = clk (-101 , 4.5)
*
12 = U1/NAND2C_1/B (-74 , 63)
*
12 = U1/NAND2C_2/A (-48 , 70)
*
13 = U1/NAND2C_2/Out2 (-24 , 54)
*
14 = U1/NAND2C_1/Out2 (-58 , 54)
*
17 = Gnd (92 , 4)
*
17 = U1/NAND2C_1/Gnd (-51 , 28)
*
17 = U1/NAND2C_2/Gnd (-17 , 28)
*
17 = U1/NAND2C_3/Gnd (-17 , 28)
*
17 = U1/NAND2C_4/Gnd (51 , 28)
*
17 = U1/NAND2C_5/Gnd (85 , 28)
*
18 = qbar (100 , 98.5)
*
18 = U1/NAND2C_3/B (-6 , 63)
*
18 = U1/NAND2C_4/Out1 (36 , 52)

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M1 Vdd d U1/NAND2C_2/B Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p

PS=34u
M2 U1/NAND2C_2/B d Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M3 U1/NAND2C_5/Out2 U1/NAND2C_2/B Vdd Vdd PMOS L=2u W=28u AD=148p
PD=68u AS=84p PS=34u
M4 Vdd U1/NAND2C_2/Out1 qbar Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M5 qbar q Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u
M6 U1/NAND2C_4/Out2 qbar Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u
AS=84p PS=34u
M7 Vdd qbar q Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34u
M8 U1/NAND2C_3/Out2 q Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p
PS=34u
M9 Gnd d 5 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M10 5 d U1/NAND2C_2/B Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M11 U1/NAND2C_5/Out2 U1/NAND2C_2/B Gnd Gnd NMOS L=2u W=28u AD=148p
PD=68u AS=122p PS=47u
M12 Gnd U1/NAND2C_2/Out1 4 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u
M13 4 q qbar Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u
M14 U1/NAND2C_4/Out2 qbar Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
M15 U1/NAND2C_3/Out2 q Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u
M16 q U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M17 Vdd U1/NAND2C_2/B U1/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p
PD=34u AS=84p PS=34u
M18 U1/NAND2C_2/Out1 clk Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=144p PS=68u
M19 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M20 Vdd clk U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p
PS=34u
M21 U1/NAND2C_1/Out1 d Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p
PS=68u
M22 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u
AD=148p PD=68u AS=84p PS=34u
M23 Gnd qbar 19 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M24 19 U1/NAND2C_1/Out1 q Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M25 Gnd U1/NAND2C_2/B 16 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p
PS=30u

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56
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M26 16 clk U1/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M27 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
M28 Gnd clk 15 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u
M29 15 d U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p
PS=68u
M30 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Gnd Gnd NMOS L=2u W=28u
AD=148p PD=68u AS=122p PS=47u
* Total Nodes: 19
* Total Elements: 30
* Total Number of Shorted Elements not written to the SPICE file: 10
* Output Generation Elapsed Time: 0.000 sec
* Total Extract Elapsed Time: 1.875 sec
.END

Result:
The D-Flip flop is constructed in Tanner EDA v13.1, the spice code is generated
and waveforms are verified.

I- M.Tech II SEM-(VLSI System Design)

Mixed Signal Lab

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57
_______________________________________________________________________

Exp No: 6
CURRENT MIRROR
Aim:
a) To construct the Current Mirror in Tanner EDA v13.1 and to do the
Voltage Analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice
code of the designed circuit.

Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

I- M.Tech II SEM-(VLSI System Design)

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58
_______________________________________________________________________

Schematic Diagram:

Fig (a): Current Mirror Schematic

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59
_______________________________________________________________________

Tanner Spice Code:

* SPICE export by: SEDIT 13.00
* Export time:
Fri Jun 11 12:15:48 2010
* Design:
msl
* Cell:
Cell8
* View:
view0
* Export as:
top-level cell
* Export mode:
hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines:
no
* Root path:
C:\Documents and Settings\user11\Desktop\msl
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib " TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_2 Out N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_1 N_2 N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 Vdd Vdd N_2 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_4 In Vdd Out Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 In Gnd SIN(2.5 500m 500k 0 0 0)
.PRINT TRAN V(Out)
.PRINT TRAN V(In)
********* Simulation Settings - Analysis section *********
*.tran 5ns 500ns
.dc lin source vvoltagesource_2 0 5 1
.print dc v(n_2,gnd)
********* Simulation Settings - Additional SPICE commands *********
.end

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Output responses:
NMOS_3_S

NMOS_1_S

Fig (b): Current Mirror Waveforms

Result:
The Current Mirror is constructed in Tanner EDA v13.1, the spice code is
generated and wave forms are verified

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Exp No: 7
DIFFERENTIAL AMPLIFIER
Aim:
a) To construct the differential amplifier in Tanner EDA v13.1 and to do the
voltage analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice
code of the designed circuit.

Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

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Schematic Diagram:

Fig(a): Differential Amplifier Schematic

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Tanner Spice Code:

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib " TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------RResistor_1 Vdd N_5 R=50
RResistor_2 Vdd N_7 R=50
MNMOS_1 N_5 N_2 N_3 N_4 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_7 N_1 N_3 N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_2 Vdd Gnd DC 5
VVoltageSource_3 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)
VVoltageSource_5 Gnd pos_PortNotFound_0 PULSE(0 5 0 5n 5n 95n 200n)
ICurrentSource_1 N_3 Gnd DC 5u
.PRINT TRAN V(N_2)
.PRINT TRAN V(N_7)
.PRINT TRAN V(N_1)
.PRINT TRAN V(N_5)
********* Simulation Settings - Analysis section *********
*.tran 5ns 500ns
.dc lin source vvoltagesource_3 -3 3 1
.print dc i(mnmos_2,n_7) i(mnmos_1,n_5)
********* Simulation Settings - Additional SPICE commands *********
.end

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Output responses:

Fig (b): Differential Amplifier Waveforms

Result:
The differential amplifier is constructed in Tanner EDA v13.1, the spice
code is generated and wave forms are verified.

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Mixed Signal Lab

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Exp No: 8
OPERATIONAL AMPLIFIER
Aim:
a) To construct the Operational Amplifier in Tanner EDA v13.1 and to do the
AC analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.

Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

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Schematic Diagram:

Fig (a): Operational Amplifier Schematic

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Tanner Spice Code:

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib " TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------CCapacitor_1 N_3 Out 1p
CCapacitor_2 Out Gnd 1p
MNMOS_1 N_2 N_6 N_11 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_3 N_5 N_11 N_4 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 N_11 N_10 Gnd N_7 NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
MNMOS_4 N_9 N_10 Gnd N_8 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_3 N_2 Vdd N_12 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 N_2 N_2 Vdd N_13 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_3 N_9 N_3 Vdd N_14 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_2 N_6 Gnd DC 5
VVoltageSource_3 N_10 Gnd DC 5
VVoltageSource_4 N_5 N_6 DC 0 AC 1 0
********* Simulation Settings - Analysis section *********
*.tran 5ns 500ns
.ac lin 10 0 10
.print ac vm(out,gnd) vp(out,gnd)
********* Simulation Settings - Additional SPICE commands *********
.end

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Output responses:
VP(OUT)

Vdb(OUT)

V(OUT)

Fig (b): Operational Amplifier Waveforms

Result:
The Operational Amplifier is constructed in Tanner EDA v13.1, the spice
code is generated and wave forms are verified.

Exp No: 09

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TRANS CONDUCTANCE AMPLIFIER

Aim:
a) To construct the Trans Conductance Amplifier in Tanner EDA v13.1 and to
do the DC analysis.
b) To analyze the response with appropriate wave forms. And to verify the Spice.

Tools used:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice

Procedure:
1. Open S-Edit window.
2. Go to File New New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.

Schematic Diagram:

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Fig (a): Trans Conductance Amplifier Schematic

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Tanner Spice Code:

********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_1 N_2 N_3 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 Out N_4 N_3 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 N_3 N_5 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_1 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 Out N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 N_2 Gnd DC 2
VVoltageSource_3 N_5 Gnd DC 700m
VVoltageSource_4 Out Gnd DC 2.5
VVoltageSource_5 N_4 N_2 DC 0
********* Simulation Settings - Analysis section *********
.dc lin source VVOLTAGESOURCE_5 -1 1 0.01
.print dc id(MNMOS_1) id(MNMOS_2)
.print dc i(vvoltagesource_4,out)
*.tran 350ns 500ns
********* Simulation Settings - Additional SPICE commands *********
.end

Output responses:
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i(VPMOS_1)

i1(VNMOS_3)

i1(VNMOS_2)

Fig (b) Trans Conductance Amplifier Waveforms

Result:
The Trans Conductance Amplifier is constructed in Tanner EDA v13.1, the
spice code is generated and wave forms are verified.

I- M.Tech II SEM-(VLSI System Design)

Mixed Signal Lab

SVCET