Aim: To design a Half Adder, Full Adder, Subtractor , Flip flops, 4-bit comparator using

Verilog coding.
Electronics Design Automation Tools: Xilinx Project Navigator 13.3

I.

HALF ADDER:
Block Diagram:

Truth Table:

module ha1(a, b, s, co);

input a, b;
output s, co;
reg s,co;
always @(a or b)
begin
s = a ^ b;
co = a &b;
end
endmodule

VERILOG HDL Test Bench for Half Adder:

Half Adder:
module ha_tst_v;
reg a;
reg b;
wire s;
wire co;
ha1 uut (
.a(a),
.b(b),
.s(s),
.co(co)
);
initial
begin
a = 0;
b = 0;
#100 a = 0;
b = 1;
#100 a = 1;
b = 0;
#100 a = 1;
b = 1;
end
endmodule;

module FA( input a,b,cin, output sum,cout );

reg sum,cout;
always @(a or b or cin)
begin
case ({a,b,cin})
3'b000: begin
sum = 1'b0;
cout = 1'b0;
end
3'b001: begin
sum = 1'b1;
cout = 1'b0;
end

3'b010: begin
sum = 1'b1;
cout = 1'b0;
end
3'b011: begin
sum = 1'b0;
cout = 1'b1;
end
3'b100: begin
sum = 1'b1;
cout = 1'b0;
end
3'b101: begin
sum = 1'b0;
cout = 1'b1;
end
3'b110: begin
sum = 1'b0;
cout = 1'b1;
end
3'b111: begin
sum = 1'b1;
cout = 1'b1;
end
default: begin
sum = 1'b0;
cout = 1'b0;
end
endcase
end

endmodule