SIMPLIFYING CLOCK GATING LOGIC BY MATCHING

FACTORED FORMS
ABSTRACT:
Gate-level clock gating starts with a net list, with partial or no gating applied; some flipflops are then selected for further gating to reduce the circuits power consumption, and a gating
logic of the smallest possible size must then be synthesized. We show how to do this by factored
form matching, in which gating functions in factored forms are matched, as far as possible, with
factored forms of the Boolean functions of existing combinational nodes in the circuit; additional
gates are then introduced, but only for the portion of gating functions that are not matched.
Strong matching identifies matches that are explicitly present in the factored forms, and weak
matching seeks matches that are implicit in the logic and thus are more difficult to discover.
Factored form matching reduces gating logic.
EXISTING SYSTEM:
Another potential approach is to synthesize gating functions automatically from a gatelevel net list, which is often called as gate-level clock gating. The key to this approach is to
minimize the number of additional gates introduced to implement the gating functions, because
these extra gates can represent a substantial overhead. Shows the proportion of circuit area
occupied by gating functions for some test circuits, which demonstrates the area overhead of
large. A few techniques are suggested to simplify gating functions.
DRAWBACKS:

Test circuit is more Complexity.

Its occupied more Area.

PROPOSED SYSTEM:

We propose a new technique to simplify gating functions. The idea is to use the existing
logic as far as possible while the gating functions are synthesized. This is achieved by matching
factored forms of the gating functions with those of existing logic nodes, thus we call this
technique as factored form matching.
PROPOSED TECHNIQUE:

FACTORED FORM MATCHING

BLOCK DIAGRAM:

FACTORED FORM MATCHING:

Strong Matching:

Weak matching:

SOFTWARE REQUIREMENT:

ModelSim6.4c.
Xilinx 9.1/13.2.

APPLICATION:

Circuit verification section

Electronic system design
Testing sequential & Combinational Circuits

ADVANTAGES:

Its Less Area Compared to Existing system

Low hardware overhead
Testing Complexity reduced

FUTURE ENHANCEMENT:
The testing method will be implemented by using different Combinational circuits.