---------------------------------------------------------------------------------- Company: IIIE

-- Engineer: Carlos Bran

--- Create Date:
10:24:54 02/09/2015
-- Design Name:
-- Module Name:
decoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder is
Port ( inp_code : in STD_LOGIC_VECTOR (3 downto 0);
enable : in STD_LOGIC;
ssd_out : out STD_LOGIC_VECTOR (7 downto 0));
end decoder;
architecture Behavioral of decoder is
signal output1: STD_LOGIC_VECTOR (7 downto 0);
signal output2: STD_LOGIC_VECTOR (7 downto 0);
begin
output1 <= x"30"; -- Codigo de error "E", SSD Anodo comun
with inp_code select -- SSD orden de los segmentos pabcdefg
output2 <= x"01" when x"0",
x"4f" when x"1",
x"12" when x"2",
x"06" when x"3",
x"4c" when x"4",
x"24" when x"5",
x"60" when x"6",
x"0f" when x"7",
x"00" when x"8",
x"0c" when x"9",
x"b0" when others;
ssd_out <= output1 when enable = '1' else output2;
end Behavioral;