A B C D E

1 1

Compal Confidential
2 2

KAWF0/KAWH0 M/B Schematics Document

Intel Penryn Processor with Cantiga + DDRII + ICH9M

3
2009-01-21 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 1 of 45
A B C D E
 A B C D E

Compal Confidential
Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control
Model Name : KAWF0/KAWH0 page 4
EMC 1402 ICS9LPRS387
uPGA-478 Package page 4 page 16
File Name : LA-4851P
(Socket P) page 4,5,6
P/N : DA600009500 (RVE0)
1 1

P/N : DA600009510 (RVE1) FSB

H_A#(3..35) 667/800/1066MHz H_D#(0..63)

LCD Conn. CRT Conn.

page 17 page 18
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel Cantiga
Dual Channel BANK 0, 1, 2, 3 page 14,15

1.8V DDRII 533/667

LVDS uFCBGA-1329
page 7,8,9,10,11,12,13

DMI C-Link USB conn x2 Bluetooth CMOS Card Reader

USB port 0, 6 Conn Camera Realtek RTS5159
page 28 page 28 page 17 page 24

PCI-Express
2
Intel ICH9-M 3.3V 48MHz USB
2

3.3V 24.576MHz/48Mhz HD Audio

S-ATA
BGA-676
New Card MINI Card x1 LAN ATHEROS page 19,20,21,22
Socket WLAN AR8132 port 0 port 1
page 28 page 27 page 26 MDC 1.5 HDA Codec Audio AMP
Conn ALC272
15 " HDD page 31 page 32 page 33
15" and 17" ODD
Conn. Conn.
page 23
RJ45 page 23
Phone Jack x2
page 27 port 4 page 33

17 " HDD LPC BUS

Conn.
3 3
page 23
LS-4851P ENE KB926 D2
RTC CKT. POWER/B Conn. page 29
page 20 page 30

Power On/Off CKT. Touch Pad Int.KBD

page 30 page 30
page 31 LS-4852P
ODD/B Conn.
page 23
DC/DC Interface CKT. BIOS
LS-4853P
page 34 BATTERY/B Conn. page 30
page 36

Power Circuit DC/DC

4
page 35,36,37,38 4
39,40,41,42

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 2 of 45
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF

+1.5V 1.5V power rail for HDA ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+2.5VS 2.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V 3.3V power rail for SB ON ON OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN 3.3V power rail for LAN ON ON ON 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 GM45 GM@
1 0.2 GL40 GL@
2 0.3 15" 15@
3 1.0 17" 17@
4 1A 8114 8114@
5 8132 8132@
6
7 PCIE table

PCIE port1 Express Card(Reserved)

EC SM Bus1 address EC SM Bus2 address USB table
PCIE port2 Wireless Card
3
Port0 MB USB Conn. 3
Device Address Device Address UHCI1
Smart Battery ADI ADT7421
Port1 PCIE port3 PCIE LAN
0001 011X b 1001 100X b
EEPROM(24C16/02) 1010 000X b
Port2
EHCI1 UHCI2 PCIE port4
GMT G781-1
Port3 CMOS Camera
1001 101X b
Port4 Card Reader PCIE port5
UHCI3
Port5 New Card(Reserved)
PCIE port6
Port6 MB USB Conn.
UHCI4
Port7 SATA table
ICH9M SM Bus address EHCI2 Port8 Blue Tooth
UHCI5
Port9 SATA port0 HDD
Device Address
Port10 Wireless Card
Clock Generator
UHCI6 SATA port1 ODD
1101 001Xb Port11
(ICS9LPRS387, SLG8SP556V)
DDR DIMM0 1001 000Xb
SATA port2
DDR DIMM2 1001 010Xb SATA port3
SATA port4 for 17" 2nd HDD
4 4
SATA port5

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 3 of 45
A B C D E
 5 4 3 2 1

H_A#[3..35]
H_A#[3..35]
H_REQ#[0..4]
H_REQ#[0..4]
H_RS#[0..2]
FAN1 Conn
H_RS#[0..2]
JCPU1A +5VS
H_A#3 J4 H1 C114 10U_0805_10V4Z +5VS
A[3]# ADS# H_ADS#

ADDR GROUP_0
H_A#4 L5 E2 H_BNR# 1 2
H_A#5 A[4]# BNR#
D L4 A[5]# BPRI# G5 H_BPRI# D

1
H_A#6 K5 R245
H_A#7 A[6]# 0_0603_5% U5 D6
M3 A[7]# DEFER# H5 H_DEFER#
H_A#8 N2 F21 @ 1 8 1SS355_SOD323-2
A[8]# DRDY# H_DRDY# VEN GND
H_A#9 J1 E1 2 7
A[9]# DBSY# H_DBSY# VIN GND
H_A#10 N3 +VCC_FAN1 3 6

2
H_A#11 A[10]# EN_DFAN1 VSET VO GND D7
P5 A[11]# BR0# F1 H_BR0# EN_DFAN1 1 2 4 VSET GND 5
H_A#12 P2 R51 330_0402_5% 1 2
A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# 1 G993P1UF_SOP8
H_A#14 A[13]# IERR# C106 BAS16_SOT23-3
P4 A[14]# INIT# B3 H_INIT#
H_A#15 P1 0.01U_0402_16V7K C122
H_A#16 A[15]# 10U_0805_10V4Z
R1 A[16]# LOCK# H4 H_LOCK# 2
H_ADSTB#0 M1 ADSTB[0]# 1 2
C1 H_RESET# H_RESET#
H_REQ#0 RESET# H_RS#0 +3VS C121
K3 REQ[0]# RS[0]# F3 20080430
H_REQ#1 H2 F4 H_RS#1 Add soft-start for +5VS drop issue 1000P_0402_50V7K
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3 1 2

1
H_REQ#3 J3 G2 H_TRDY#
H_REQ#4 REQ[3]# TRDY# R55
L1 REQ[4]#
G6 10K_0402_5%
HIT# H_HIT#
H_A#17 Y2 E4 40mil
A[17]# HITM# H_HITM#
H_A#18 U5 JP12

2
H_A#19 A[18]# +VCC_FAN1
R3 A[19]# BPM[0]# AD4 1
ADDR GROUP_1
H_A#20 W6 AD3
A[20]# BPM[1]# FAN_SPEED1 2
H_A#21 U4 AD1
H_A#22 A[21]# BPM[2]# 3
Y5 A[22]# BPM[3]# AC4 1

XDP/ITP SIGNALS
H_A#23 U1 AC2 C115 ACES_85205-03001
H_A#24 A[23]# PRDY# XDP_BPM#5 1000P_0402_50V7K CONN@
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
C H_A#26 A[25]# TCK XDP_TDI 2 C
T3 A[26]# TDI AA6 JP15
H_A#27 W2 AB3
H_A#28 A[27]# TDO XDP_TMS +VCC_FAN1
W5 A[28]# TMS AB5 1 1
H_A#29 Y4 AB6 XDP_TRST# 2
H_A#30 A[29]# TRST# XDP_DBRESET# 2
U2 A[30]# DBR# C20 XDP_DBRESET# 3 3
H_A#31 V4 FANPWM 4
H_A#32 A[31]# 4
W3 A[32]#
H_A#33 AA4 THERMAL
H_A#34 A[33]# +1.05VS ACES_85205-0400
AB2 A[34]#
H_A#35 AA3 D21 H_PROCHOT# @
A[35]# PROCHOT# H_THERMDA
H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC
THERMDC
H_A20M# A6 A20M#
ICH

A5 C7 H_THERMTRIP# XDP_TDI R43 1 2 54.9_0402_1%

H_FERR# FERR# THERMTRIP#
H_IGNNE# C4 IGNNE#
left NC if no ITP
H_STPCLK# D5 STPCLK#
C6 H CLK XDP_TMS R42 1 2 54.9_0402_1% 39Ohm
H_INTR LINT0
H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK
A3 A21 XDP_BPM#5 R16 1 2 54.9_0402_1%
H_SMI# SMI# BCLK[1] CLK_CPU_BCLK#
@
M4 RSVD[01]
N5 RSVD[02]
T2 H_PROCHOT# R70 2 1 56_0402_5%
RSVD[03]
V3 RSVD[04]
RESERVED

B2 Layout Note: H_IERR# R54 2 1 56_0402_5%

RSVD[05]
D2 RSVD[06]
D22 H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RSVD[07]
D3 RSVD[08]
B B
F6 RSVD[09]
XDP_TRST# R41 2 1 54.9_0402_1%

XDP_TCK R17 1 2 54.9_0402_1%

Penryn
CONN@

+3VS
C159
0.1U_0402_16V4Z
1 2

+1.05VS U9
BSEL2 BSEL1 BSEL0 BCLK H_THERMDA

0 0 0 266 1 VDD SMCLK 8 EC_SMB_CK2

1

1
R12 C158 2 7
DP SMDATA EC_SMB_DA2
0 1 0 200 56_0402_5%
2200P_0402_50V7K
@ 3 DN ALERT# 6 1 2 +3VS
2 R109
2

0 1 1 166 4 5 10K_0402_5%
H_THERMDC THERM# GND
2
B
E

H_PROCHOT# 3 1 OCP# EMC1402-1-ACZL-TR_MSOP8

A A
C

Q2
MMBT3904_SOT23-3
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 4 of 45
5 4 3 2 1
 5 4 3 2 1

H_D#[0..63] JCPU1C
H_D#[0..63]
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12

DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13

DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VCC[006] VCC[073]
F23 D[4]# D[36]# V23 A17 VCC[007] VCC[074] AC15
H_D#5 G25 T22 H_D#37 A18 AC17
H_D#6 D[5]# D[37]# H_D#38 VCC[008] VCC[075]
E25 D[6]# D[38]# U25 A20 VCC[009] VCC[076] AC18
H_D#7 E23 U23 H_D#39 B7 AD7
H_D#8 D[7]# D[39]# H_D#40 VCC[010] VCC[077]
K24 D[8]# D[40]# Y25 B9 VCC[011] VCC[078] AD9
H_D#9 G24 W22 H_D#41 B10 AD10
H_D#10 D[9]# D[41]# H_D#42 VCC[012] VCC[079]
J24 D[10]# D[42]# Y23 B12 VCC[013] VCC[080] AD12
H_D#11 J23 W24 H_D#43 B14 AD14
H_D#12 D[11]# D[43]# H_D#44 VCC[014] VCC[081]
H22 D[12]# D[44]# W25 B15 VCC[015] VCC[082] AD15
H_D#13 F26 AA23 H_D#45 B17 AD17
H_D#14 D[13]# D[45]# H_D#46 VCC[016] VCC[083]
K22 D[14]# D[46]# AA24 B18 VCC[017] VCC[084] AD18
H_D#15 H23 AB25 H_D#47 B20 AE9
D[15]# D[47]# VCC[018] VCC[085]
H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 C9 VCC[019] VCC[086] AE10
H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 C10 VCC[020] VCC[087] AE12
H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[029] VCC[096]
L22 D[22]# D[54]# AD20 D15 VCC[030] VCC[097] AF15
H_D#23 M23 AE22 H_D#55 D17 AF17
H_D#24 D[23]# D[55]# H_D#56 VCC[031] VCC[098]
P25 D[24]# D[56]# AF23 D18 VCC[032] VCC[099] AF18
C H_D#25 P23 AC25 H_D#57 E7 AF20 C
+1.05VS H_D#26 D[25]# D[57]# H_D#58 VCC[033] VCC[100]
P22 D[26]# D[58]# AE21 E9 VCC[034]
H_D#27 T24 AD21 H_D#59 E10 G21 +1.05VS
H_D#28 D[27]# D[59]# H_D#60 VCC[035] VCCP[01]
R24 D[28]# D[60]# AC22 E12 VCC[036] VCCP[02] V6
H_D#29 L25 AD23 H_D#61 E13 J6
D[29]# D[61]# VCC[037] VCCP[03]
2

H_D#30 T25 AF22 H_D#62 E15 K6

R386 H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04]
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
1K_0402_1% H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 E18 VCC[040] VCCP[06] J21
H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 E20 VCC[041] VCCP[07] K21
H_DINV#1 N24 AC20 H_DINV#3 F7 M21
1

DINV[1]# DINV[3]# VCC[042] VCCP[08]

Trace Close CPU < 0.5' GTL_REF0 COMP0 R393 27.4_0402_1%
F9 VCC[043] VCCP[09] N21
AD26 GTLREF COMP[0] R26 1 2 F10 VCC[044] VCCP[10] N6
Width=4 mil , R406 2 1 @ 1K_0402_5% TEST1 C23 MISC U26 COMP1 R394 1 2 54.9_0402_1% F12 R21
R405 TEST1 COMP[1] VCC[045] VCCP[11]
2 1 @ 1K_0402_5% TEST2 D25 AA1 COMP2 R15 1 2 27.4_0402_1% F14 R6
Spacing: 15mil TEST2 COMP[2] VCC[046] VCCP[12]
2

T2 PAD @ TEST3 C24 TEST3 COMP[3] Y1 COMP3 R14 1 2 54.9_0402_1% F15 VCC[047] VCCP[13] T21
(55Ohm) R387 C438 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F17 T6
@ TEST5 TEST4 VCC[048] VCCP[14]
2K_0402_1% T26 PAD AF1 TEST5 DPRSTP# E5 H_DPRSTP# F18 VCC[049] VCCP[15] V21
@ TEST6 A26 B5 F20 W21
T27 PAD TEST6 DPSLP# H_DPSLP# VCC[050] VCCP[16]
C3 D24 H_DPWR# AA7 20mils
1

TEST7 DPWR# H_PWRGOOD VCC[051]

CPU_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD AA9 VCC[052] VCCA[01] B26 +1.5VS
CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26
BSEL[1] SLP# H_CPUSLP# VCC[053] VCCA[02]
CPU_BSEL2 C21 BSEL[2] PSI# AE6 PSI# AA12 VCC[054] 1 1
AA13 AD6 CPU_VID0 C156 C157
Penryn VCC[055] VID[0]
AA15 VCC[056] VID[1] AF5 CPU_VID1
CONN@ AA17 AE5 CPU_VID2 0.01U_0402_16V7K
VCC[057] VID[2] 2 2
TRACE CLOSELY CPU < 0.5' AA18 VCC[058] VID[3] AF4 CPU_VID3
AA20 VCC[059] VID[4] AE3 CPU_VID4
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB9 AF3 CPU_VID5 10U_0805_10V4Z
VCC[060] VID[5]
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) AC10 VCC[061] VID[6] AE2 CPU_VID6
B B
AB10 VCC[062] 1 2 +CPU_CORE
AB12 R376 100_0402_1%
VCC[063] VCCSENSE
AB14 VCC[064] VCCSENSE AF7 VCCSENSE
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE
VCC[067] VSSSENSE
Penryn 1 2
CONN@ . R375 100_0402_1%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 5 of 45
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
2 x 330uF(6mOhm/2) 2 x 330uF(6mOhm/2)
JCPU1D 1 1 1 1
A4 VSS[001] VSS[082] P6
A8 P21 C98 + C113 + C107 + C90 +
VSS[002] VSS[083]
A11 VSS[003] VSS[084] P24
A14 R2 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
VSS[004] VSS[085] 2 2 2 2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
D A23 VSS[007] VSS[088] R25 D
AF2 VSS[008] VSS[089] T1 South Side Secondary North Side Secondary
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 T26 +CPU_CORE
VSS[011] VSS[092]
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24 1 1 1 1 1 1 1 1
B24 V2 C465 C466 C451 C95 C111 C94 C93 C458
VSS[016] VSS[097]
C5 VSS[017] VSS[098] V5
C8 V22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M
VSS[018] VSS[099] 2 2 2 2 2 2 2 2
C11 VSS[019] VSS[100] V25
C14 W1 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M
VSS[020] VSS[101]
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23 (Place these capacitors on South side,Secondary Layer)
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 Y6 +CPU_CORE
VSS[025] VSS[106]
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5 1 1 1 1 1 1 1 1
D13 AA8 C108 C103 C102 C92 C91 C457 C456 C96
VSS[030] VSS[111]
D16 VSS[031] VSS[112] AA11
D19 AA14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M
VSS[032] VSS[113] 2 2 2 2 2 2 2 2
D23 VSS[033] VSS[114] AA16
D26 AA19 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M
VSS[034] VSS[115]
E3 VSS[035] VSS[116] AA22
C E6 AA25 (Place these capacitors on North side,Secondary Layer) C
VSS[036] VSS[117]
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 AB8 +CPU_CORE
VSS[039] VSS[120]
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19 1 1 1 1 1 1 1 1
F5 AB23 C112 C105 C104 C97 C440 C444 C110 C109
VSS[044] VSS[125]
F8 VSS[045] VSS[126] AB26
F11 AC3 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M
VSS[046] VSS[127] 2 2 2 2 2 2 2 2
F13 VSS[047] VSS[128] AC6
F16 AC8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M
VSS[048] VSS[129]
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14 (Place these capacitors on South side,Primary Layer)
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 AC21 +CPU_CORE
VSS[053] VSS[134]
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8 1 1 1 1 1 1 1 1
H6 AD11 C455 C450 C442 C441 C469 C443 C468 C467
VSS[058] VSS[139]
H21 VSS[059] VSS[140] AD13
H24 AD16 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M
VSS[060] VSS[141] 2 2 2 2 2 2 2 2
J2 VSS[061] VSS[142] AD19
J5 AD22 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M @ 10U_0805_6.3V6M
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25
B
J25 VSS[064] VSS[145] AE1 (Place these capacitors on North side,Primary Layer) B
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14 +CPU-CORE C,uF ESR, mohm ESL,nH
L3 AE16
L6
VSS[069] VSS[150]
AE19 Decoupling
VSS[070] VSS[151]
L21 VSS[071] VSS[152] AE23 SPCAP,Polymer 4X330uF 6m ohm/4 1.8nH/6
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2 32X22uF 3m ohm/32 0.6nH/32
M5 VSS[074] VSS[155] AF6 MLCC 0805 X5R
M22 VSS[075] VSS[156] AF8 32X10uF 3m ohm/32 0.6nH/32
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 A25 +1.05VS
VSS[081] VSS[162]
VSS[163] AF25
Penryn 1
CONN@ . 1 1 1 1 1 1
C13 + C119 C120 C118 C78 C77 C79

330U_D2E_2.5VM_R9 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 6 of 45
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35]
H_D#[0..63] U23A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
D H_D#5 H6 J13 H_A#9 D
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
+1.05VS H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
1

H_D#25 N5 H20 H_A#29

R126 H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
221_0402_1% H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
2

H_SWING H_D#30 H_D#_29 H_A#_33 H_A#34

N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
width=10mil Y3 H_D#_32
2

1 H_D#33 AD14 H12 H_ADS#

H_D#_33 H_ADS# H_ADS#
C R125 C206 H_D#34 Y6 B16 H_ADSTB#0 C
H_D#_34 H_ADSTB#_0 H_ADSTB#0
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1
100_0402_1% 0.1U_0402_16V4Z H_D#36 Y12 A9 H_BNR#
2 H_D#_36 H_BNR# H_BNR#

HOST
H_D#37 Y14 F11 H_BPRI#
H_BPRI#
1

H_D#38 H_D#_37 H_BPRI# H_BR0#

Y7 H_D#_38 H_BREQ# G12 H_BR0#
H_D#39 W2 E9 H_DEFER#
H_D#_39 H_DEFER# H_DEFER#
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY#
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK
H_RCOMP H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK#
H_D#43 AA9 J11 H_DPWR#
H_D#_43 H_DPWR# H_DPWR#
width=10mil H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY#
1

H_D#45 AD11 H9 H_HIT#

H_D#_45 H_HIT# H_HIT#
R395 H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM#
H_D#47 AD13 H11 H_LOCK#
H_D#_47 H_LOCK# H_LOCK#
24.9_0402_1% H_D#48 AE12 C9 H_TRDY#
H_D#_48 H_TRDY# H_TRDY#
H_D#49 AE9
2

H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
AA3 H_D#_52
H_D#53 AD3 J8 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 H_DINV#0
AD7 H_D#_54 H_DINV#_1 L3 H_DINV#1
H_D#55 AE14 Y13 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 H_DINV#2
AF3 H_D#_56 H_DINV#_3 Y1 H_DINV#3
H_D#57 AC1
H_D#58 H_D#_57 H_DSTBN#0
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0
H_D#59 AC3 M7 H_DSTBN#1
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 H_DSTBN#1
AE11 H_D#_60 H_DSTBN#_2 AA5 H_DSTBN#2
H_D#61 AE8 AE6 H_DSTBN#3 U23
H_D#62 H_D#_61 H_DSTBN#_3 H_DSTBN#3
AG2 H_D#_62
B H_D#63 H_DSTBP#0 B
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0
M8 H_DSTBP#1
H_DSTBP#_1 H_DSTBP#2 H_DSTBP#1
H_DSTBP#_2 AA6 H_DSTBP#2
H_SWING C5 AE5 H_DSTBP#3
H_RCOMP H_SWING H_DSTBP#_3 H_DSTBP#3 GM@
E3 H_RCOMP H_REQ#[0..4] NB
+1.05VS B15 H_REQ#0
H_REQ#_0 H_REQ#1
H_REQ#_1 K13
F13 H_REQ#2
H_REQ#_2
2

B13 H_REQ#3
R139 H_RESET# H_REQ#_3 H_REQ#4
H_RESET# C12 H_CPURST# H_REQ#_4 B14
H_CPUSLP# E11 U23 U23
H_CPUSLP# H_CPUSLP# H_RS#[0..2]
1K_0402_1% B6 H_RS#0
H_RS#_0 H_RS#1
F12
1

H_AVREF H_RS#_1 H_RS#2

width:spacing=10mil:20mil (<0.5") A11 H_AVREF H_RS#_2 C8
B11 H_DVREF
1

1
R134 C216 CANTIGA ES_FCBGA1329 NB GMA1@ NB GLA1@
@ GL@
2K_0402_1% 0.1U_0402_16V4Z
2
2

within 100mil to Ball A9,B9

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 7 of 45
5 4 3 2 1
 5 4 3 2 1

U23B +1.8V

M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0

1
N36 RSVD2 SA_CK_1 AT21 DDRA_CLK1
R33 AV24 R363
RSVD3 SB_CK_0 DDRB_CLK0
T33 AU20

COMPENSATION
RSVD4 SB_CK_1 DDRB_CLK1
AH9 1K_0402_1%
RSVD5
AH10 AR24 DDRA_CLK0#

2
RSVD6 SA_CK#_0 SM_RCOMP_VOH
AH12 RSVD7 SA_CK#_1 AR21 DDRA_CLK1#
AH13 RSVD8 SB_CK#_0 AU24 DDRB_CLK0#
K12 RSVD9 SB_CK#_1 AV20 DDRB_CLK1# 1 1

1
AL34 C419 C423
RSVD10 R369
AK34 RSVD11 SA_CKE_0 BC28 DDRA_CKE0
AN35 AY28 2.2U_0603_6.3V6K 0.01U_0402_16V7K
D RSVD12 SA_CKE_1 DDRA_CKE1 2 2 D
AM35 AY36 SM_DRAMRST# would be 3.01K_0402_1%
RSVD13 SB_CKE_0 DDRB_CKE0
T24 BB36 DDRB_CKE1 needed for DDR3 only

2
RSVD14 SB_CKE_1
All RSVD balls on GMCH should be left No
Connect. SA_CS#_0 BA17 DDRA_SCS0#
AY16 SM_RCOMP_VOL
SA_CS#_1 DDRA_SCS1#
B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# For Cantiga 80 Ohm

1
B2 RSVD16 SB_CS#_1 AR13 DDRB_SCS1# 1 1

DDR CLK/ CONTROL/

M1 R362 C418 C422
RSVD17

RSVD
SA_ODT_0 BD17 DDRA_ODT0
AY17 1K_0402_1% 2.2U_0603_6.3V6K 0.01U_0402_16V7K
SA_ODT_1 DDRA_ODT1 2 2
AY21 BF15 DDRB_ODT0

2
RSVD20 SB_ODT_O +1.8V +1.8V
SB_ODT_1 AY13 DDRB_ODT1
BG22 SMRCOMP R368 1 2 80.6_0402_1%
SM_RCOMP

2
BG23 BH21 SMRCOMP# R367 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# R220
BF23 RSVD23
BH18 BF28 SM_RCOMP_VOH 1K_0402_1%
RSVD24 SM_RCOMP_VOH SM_RCOMP_VOL
BF18 RSVD25 SM_RCOMP_VOL BH28 @
20mil

1
AV42 SM_VREF 1 2 +DIMM_VREF
SM_VREF SM_PWROK R181 1
SM_PWROK AR36 2 0_0402_5% R221

2
BF17 SM_REXT R366 1 2 499_0402_1% 1 0_0402_5%
SM_REXT C278 R222
SM_DRAMRST# BC36
1K_0402_1%
0.1U_0402_16V4Z @
CLK_DREF_96M 2
B38 CLK_DREF_96M

1
DPLL_REF_CLK CLK_DREF_96M#
DPLL_REF_CLK# A38 CLK_DREF_96M#
E41 CLK_DREF_SSC
DPLL_REF_SSCLK CLK_DREF_SSC
F41 CLK_DREF_SSC#
DPLL_REF_SSCLK# CLK_DREF_SSC#

CLK
F43 CLK_MCH_3GPLL
PEG_CLK CLK_MCH_3GPLL
E43 CLK_MCH_3GPLL#
C PEG_CLK# CLK_MCH_3GPLL#
Strap Pin Table C

011 = FSB667
AE41 DMI_ITX_MRX_N0 CFG[2:0] 010 = FSB800
DMI_RXN_0 DMI_ITX_MRX_N0
AE37 DMI_ITX_MRX_N1 000 = FSB1067
DMI_RXN_1 DMI_ITX_MRX_N1
AE47 DMI_ITX_MRX_N2
DMI_RXN_2 DMI_ITX_MRX_N2
AH39 DMI_ITX_MRX_N3 0 = DMI x 2
DMI_RXN_3 DMI_ITX_MRX_N3
DMI_ITX_MRX_P0
CFG5 1 = DMI x 4 * (Default)
DMI_RXP_0 AE40 DMI_ITX_MRX_P0
MCH_CLKSEL0 T25 AE38 DMI_ITX_MRX_P1 0 = iTPM Host Interface is enabled
MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_ITX_MRX_P1
MCH_CLKSEL1 DMI_ITX_MRX_P2 CFG6
MCH_CLKSEL1
MCH_CLKSEL2
R25
P25
CFG_1 DMI_RXP_2 AE48
AH40 DMI_ITX_MRX_P3
DMI_ITX_MRX_P2 1 = iTPM Host Interface is Disabled *(Default)
MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3
P20 CFG_3 DMI_MTX_IRX_N0
0 = Lane Reversal Enable
P24 CFG_4 DMI_TXN_0 AE35 DMI_MTX_IRX_N0 CFG9 1 = Normal Operation * (Default)
2 PM_EXTTS#0 MCH_CFG_5 DMI_MTX_IRX_N1

DMI
+3VS 1 C25 CFG_5 DMI_TXN_1 AE43 DMI_MTX_IRX_N1
R177 10K_0402_5% MCH_CFG_6 N24 AE46 DMI_MTX_IRX_N2 0 = PCIe Loopback Enable
CFG_6 DMI_TXN_2 DMI_MTX_IRX_N2
1 2 PM_EXTTS#1 MCH_CFG_7 M24 CFG_7 CFG DMI_TXN_3 AH42 DMI_MTX_IRX_N3
DMI_MTX_IRX_N3 CFG10 1 = Disable * (Default)
R202 10K_0402_5% E21 CFG_8
1 2 MCH_CLKREQ# MCH_CFG_9 C23 CFG_9 DMI_TXP_0 AD35 DMI_MTX_IRX_P0
DMI_MTX_IRX_P0 00 = Reserved
R189 10K_0402_5% MCH_CFG_10 C24 AE44 DMI_MTX_IRX_P1 CFG[13:12] 01 = XOR Mode Enabled
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1
N21 AF46 DMI_MTX_IRX_P2 10 = All Z Mode Enabled
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2
MCH_CFG_12 P21 AH43 DMI_MTX_IRX_P3 11 = Normal Operation * (Default)
CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3
MCH_CFG_13 T21
VGATE GMCH_PWROK CFG_13
VGATE 1
R224
2
@ 0_0402_5%
R20 CFG_14 0 = Dynamic ODT Disabled
ICH_PWROK 1 MCH_CFG_16
M20 CFG_15 CFG16 1 = Dynamic ODT Enabled * (Default)
ICH_PWROK 2 L21 CFG_16
R223 0_0402_5% 0 = Normal Operation
H21 CFG_17 *(Default)
P29 CFG19 1 = DMI Lane Reversal Enable
GRAPHICS VID

MCH_CFG_19 CFG_18
R28 CFG_19
MCH_CFG_20 T28 B33 0 = Only PCIE or SDVO is operational.
CFG_20 GFX_VID_0
GFX_VID_1 B32 CFG20 * (Default)
G33
B GFX_VID_2
F33 (PCIE/SDVO select) 1 = PCIE/SDVO are operating simu. B
R141 1 PM_SYNC#_R GFX_VID_3
PM_SYNC# 2 0_0402_5% R29 PM_SYNC# GFX_VID_4 E33
R135 1 2 0_0402_5% PM_DPRSTP#_R 0 = No SDVO Card Present
H_DPRSTP#
PM_EXTTS#0
B7 PM_DPRSTP# * (Default)
PM_EXTTS#0 N33 PM_EXT_TS#_0 SDVO_CTRLDATA 1 = SDVO Card Present
PM

PM_EXTTS#1 PM_EXTTS#1 P32

GMCH_PWROK PM_EXT_TS#_1
AT40 PWROK GFX_VR_EN C34 0 = LFP Disable * (Default)
PLT_RST# R133 1 2 100_0402_5% MCH_RSTIN# AT11 RSTIN# L_DDC_DATA 1 = LFP Card Present; PCIE disable
R143 1 2 0_0402_5% THERMTRIP#_R T20 +1.05VS
H_THERMTRIP# THERMTRIP#
R140 1 0_0402_5% DPRSLPVR_R 0 = Digital DisplayPort Disable
PM_DPRSLPVR 2 R32 DPRSLPVR * (Default)
1 = Digital DisplayPort Device Present
DDPC_CTRLDATA

2
BG48 AH37 R183
NC_1 CL_CLK CL_CLK0
BF48 AH36 1K_0402_1%
NC_2 CL_DATA CL_DATA0
ME

BD48 AN36 ICH_PWROK

NC_3 CL_PWROK MCH_CFG_5
BC48 AJ35 CL_RST#0 2 1

1
NC_4 CL_RST# CL_VREF R175 @ 2.21K_0402_1%
BH47 NC_5 CL_VREF AH34
BG47 MCH_CFG_6 2 1
NC_6

2
BE47 R142 @ 4.02K_0402_1%
NC_7 C264 1 R182 MCH_CFG_7
BH46 NC_8 DDPC_CTRLCLK N28 2 1
NC

BF46 M28 511_0402_1% R162 @ 2.21K_0402_1%

NC_9 DDPC_CTRLDATA MCH_CFG_9
BG45 NC_10 SDVO_CTRLCLK G36 2 1
+3VS BH44 E36 0.1U_0402_16V4Z R158 @ 2.21K_0402_1%

1
NC_11 SDVO_CTRLDATA MCH_CLKREQ# 2 MCH_CFG_10
BH43 NC_12 CLKREQ# K36 MCH_CLKREQ# 2 1
MISC

BH6 H36 MCH_ICH_SYNC# R161 @ 2.21K_0402_1%

NC_13 ICH_SYNC#
1

+3VS BH5 MCH_CFG_12 2 1

R404 NC_14 R154 @ 2.21K_0402_1%
BG4 NC_15
1K_0402_5% BH3 B12 MCH_TSATN# MCH_CFG_13 2 1
NC_16 TSATN#
1

+1.05VS BF3 R153 @ 2.21K_0402_1%

R403 NC_17 MCH_CFG_16
BH2 2 1
2

1K_0402_5% NC_18 R155 @ 2.21K_0402_1%

MCH_TSATN_EC# BG2 NC_19
1

BE2 NC_20 HDA_BCLK B28

1

R398 C BG1 B30

2

A 54.9_0402_1% Q33 NC_21 HDA_RST# A

2 BF1 NC_22 HDA_SDI B29
B MMBT3904_SOT23-3 BD1 C29 MCH_CFG_19 2 1
R397 NC_23 HDA_SDO +3VS
1

C E BC1 A28 R159 @ 4.02K_0402_1%

HDA
2

MCH_TSATN# Q34 NC_24 HDA_SYNC MCH_CFG_20

1 2 2 F1 NC_25 2 1
B MMBT3904_SOT23-3 A47 R163 @ 4.02K_0402_1%
330_0402_5% E NC_26
3

CANTIGA ES_FCBGA1329
GL@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401636 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 09, 2009 Sheet 8 of 45
5 4 3 2 1
 5 4 3 2 1

DDRA_SDQ[0..63] DDRB_SDQ[0..63]
DDRA_SDQ[0..63] DDRB_SDQ[0..63]
DDRA_SDM[0..7] DDRB_SDM[0..7]
DDRA_SDM[0..7] DDRB_SDM[0..7]

D DDRA_SMA[0..14] DDRB_SMA[0..14] D
DDRA_SMA[0..14] DDRB_SMA[0..14]

U23D U23E
DDRA_SDQ0 AJ38 BD21 DDRB_SDQ0 AK47 BC16
SA_DQ_0 SA_BS_0 DDRA_SBS0# SB_DQ_0 SB_BS_0 DDRB_SBS0#
DDRA_SDQ1 AJ41 BG18 DDRB_SDQ1 AH46 BB17
SA_DQ_1 SA_BS_1 DDRA_SBS1# SB_DQ_1 SB_BS_1 DDRB_SBS1#
DDRA_SDQ2 AN38 AT25 DDRB_SDQ2 AP47 BB33
SA_DQ_2 SA_BS_2 DDRA_SBS2# SB_DQ_2 SB_BS_2 DDRB_SBS2#
DDRA_SDQ3 AM38 DDRB_SDQ3 AP46
DDRA_SDQ4 SA_DQ_3 DDRB_SDQ4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDRA_SRAS# AJ46 SB_DQ_4
DDRA_SDQ5 AJ40 BD20 DDRB_SDQ5 AJ48 AU17
SA_DQ_5 SA_CAS# DDRA_SCAS# SB_DQ_5 SB_RAS# DDRB_SRAS#
DDRA_SDQ6 AM44 AY20 DDRB_SDQ6 AM48 BG16
SA_DQ_6 SA_WE# DDRA_SWE# SB_DQ_6 SB_CAS# DDRB_SCAS#
DDRA_SDQ7 AM42 DDRB_SDQ7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDRB_SWE#
DDRA_SDQ8 AN43 DDRB_SDQ8 AU47
DDRA_SDQ9 SA_DQ_8 DDRB_SDQ9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDRA_SDQ10 AU40 DDRB_SDQ10 BA48
DDRA_SDQ11 SA_DQ_10 DDRB_SDQ11 SB_DQ_10
AT38 SA_DQ_11 AY48 SB_DQ_11
DDRA_SDQ12 AN41 DDRB_SDQ12 AT47
DDRA_SDQ13 SA_DQ_12 DDRA_SDM0 DDRB_SDQ13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDRA_SDQ14 AU44 AT41 DDRA_SDM1 DDRB_SDQ14 BA47
DDRA_SDQ15 SA_DQ_14 SA_DM_1 DDRA_SDM2 DDRB_SDQ15 SB_DQ_14 DDRB_SDM0
AU42 SA_DQ_15 SA_DM_2 AY41 BC47 SB_DQ_15 SB_DM_0 AM47
DDRA_SDQ16 AV39 AU39 DDRA_SDM3 DDRB_SDQ16 BC46 AY47 DDRB_SDM1
DDRA_SDQ17 SA_DQ_16 SA_DM_3 DDRA_SDM4 DDRB_SDQ17 SB_DQ_16 SB_DM_1 DDRB_SDM2
AY44 SA_DQ_17 SA_DM_4 BB12 BC44 SB_DQ_17 SB_DM_2 BD40
DDRA_SDQ18 BA40 AY6 DDRA_SDM5 DDRB_SDQ18 BG43 BF35 DDRB_SDM3
C DDRA_SDQ19 SA_DQ_18 SA_DM_5 DDRA_SDM6 DDRB_SDQ19 SB_DQ_18 SB_DM_3 DDRB_SDM4 C
BD43 SA_DQ_19 SA_DM_6 AT7 BF43 SB_DQ_19 SB_DM_4 BG11
DDRA_SDQ20 AV41 AJ5 DDRA_SDM7 DDRB_SDQ20 BE45 BA3 DDRB_SDM5
DDRA_SDQ21 SA_DQ_20 SA_DM_7 DDRB_SDQ21 SB_DQ_20 SB_DM_5 DDRB_SDM6
AY43 BC41 AP1

B
SA_DQ_21 SB_DQ_21 SB_DM_6
A

DDRA_SDQ22 BB41 DDRB_SDQ22 BF40 AK2 DDRB_SDM7

DDRA_SDQ23 SA_DQ_22 DDRA_SDQS0 DDRB_SDQ23 SB_DQ_22 SB_DM_7
BC40 SA_DQ_23 SA_DQS_0 AJ44 DDRA_SDQS0 BF41 SB_DQ_23
DDRA_SDQ24 AY37 AT44 DDRA_SDQS1 DDRB_SDQ24 BG38
SA_DQ_24 SA_DQS_1 DDRA_SDQS1 SB_DQ_24
DDRA_SDQ25 BD38 BA43 DDRA_SDQS2 DDRB_SDQ25 BF38 AL47 DDRB_SDQS0
SA_DQ_25 SA_DQS_2 DDRA_SDQS2 SB_DQ_25 SB_DQS_0 DDRB_SDQS0

MEMORY
DDRA_SDQ26 DDRA_SDQS3 DDRB_SDQ26 DDRB_SDQS1
MEMORY

AV37 SA_DQ_26 SA_DQS_3 BC37 DDRA_SDQS3 BH35 SB_DQ_26 SB_DQS_1 AV48 DDRB_SDQS1
DDRA_SDQ27 AT36 AW12 DDRA_SDQS4 DDRB_SDQ27 BG35 BG41 DDRB_SDQS2
SA_DQ_27 SA_DQS_4 DDRA_SDQS4 SB_DQ_27 SB_DQS_2 DDRB_SDQS2
DDRA_SDQ28 AY38 BC8 DDRA_SDQS5 DDRB_SDQ28 BH40 BG37 DDRB_SDQS3
SA_DQ_28 SA_DQS_5 DDRA_SDQS5 SB_DQ_28 SB_DQS_3 DDRB_SDQS3
DDRA_SDQ29 BB38 AU8 DDRA_SDQS6 DDRB_SDQ29 BG39 BH9 DDRB_SDQS4
SA_DQ_29 SA_DQS_6 DDRA_SDQS6 SB_DQ_29 SB_DQS_4 DDRB_SDQS4
DDRA_SDQ30 AV36 AM7 DDRA_SDQS7 DDRB_SDQ30 BG34 BB2 DDRB_SDQS5
SA_DQ_30 SA_DQS_7 DDRA_SDQS7 SB_DQ_30 SB_DQS_5 DDRB_SDQS5
DDRA_SDQ31 AW36 DDRB_SDQ31 BH34 AU1 DDRB_SDQS6
SA_DQ_31 SB_DQ_31 SB_DQS_6 DDRB_SDQS6
DDRA_SDQ32 BD13 DDRB_SDQ32 BH14 AN6 DDRB_SDQS7
SA_DQ_32 SB_DQ_32 SB_DQS_7 DDRB_SDQS7
DDRA_SDQ33 AU11 AJ43 DDRA_SDQS0# DDRB_SDQ33 BG12
SA_DQ_33 SA_DQS#_0 DDRA_SDQS0# SB_DQ_33
DDRA_SDQ34 BC11 AT43 DDRA_SDQS1# DDRB_SDQ34 BH11
SA_DQ_34 SA_DQS#_1 DDRA_SDQS1# SB_DQ_34
DDRA_SDQ35 BA12 BA44 DDRA_SDQS2# DDRB_SDQ35 BG8 AL46 DDRB_SDQS0#
SA_DQ_35 SA_DQS#_2 DDRA_SDQS2# SB_DQ_35 SB_DQS#_0 DDRB_SDQS0#

SYSTEM
DDRA_SDQ36
SYSTEM

AU13 BD37 DDRA_SDQS3# DDRB_SDQ36 BH12 AV47 DDRB_SDQS1#

SA_DQ_36 SA_DQS#_3 DDRA_SDQS3# SB_DQ_36 SB_DQS#_1 DDRB_SDQS1#
DDRA_SDQ37 AV13 AY12 DDRA_SDQS4# DDRB_SDQ37 BF11 BH41 DDRB_SDQS2#
SA_DQ_37 SA_DQS#_4 DDRA_SDQS4# SB_DQ_37 SB_DQS#_2 DDRB_SDQS2#
DDRA_SDQ38 BD12 BD8 DDRA_SDQS5# DDRB_SDQ38 BF8 BH37 DDRB_SDQS3#
SA_DQ_38 SA_DQS#_5 DDRA_SDQS5# SB_DQ_38 SB_DQS#_3 DDRB_SDQS3#
DDRA_SDQ39 BC12 AU9 DDRA_SDQS6# DDRB_SDQ39 BG7 BG9 DDRB_SDQS4#
SA_DQ_39 SA_DQS#_6 DDRA_SDQS6# SB_DQ_39 SB_DQS#_4 DDRB_SDQS4#
DDRA_SDQ40 BB9 AM8 DDRA_SDQS7# DDRB_SDQ40 BC5 BC2 DDRB_SDQS5#
SA_DQ_40 SA_DQS#_7 DDRA_SDQS7# SB_DQ_40 SB_DQS#_5 DDRB_SDQS5#
DDRA_SDQ41 BA9 DDRB_SDQ41 BC6 AT2 DDRB_SDQS6#
SA_DQ_41 SB_DQ_41 SB_DQS#_6 DDRB_SDQS6#
DDRA_SDQ42 AU10 DDRB_SDQ42 AY3 AN5 DDRB_SDQS7#
SA_DQ_42 SB_DQ_42 SB_DQS#_7 DDRB_SDQS7#
DDRA_SDQ43 AV9 DDRB_SDQ43 AY1
DDRA_SDQ44 SA_DQ_43 DDRA_SMA0 DDRB_SDQ44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44
DDRA_SDQ45 BD9 BC24 DDRA_SMA1 DDRB_SDQ45 BF5 AV17 DDRB_SMA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDRA_SDQ46 AY8 BG24 DDRA_SMA2 DDRB_SDQ46 BA1 BA25 DDRB_SMA1

DDRA_SDQ47 SA_DQ_46 SA_MA_2 DDRA_SMA3 DDRB_SDQ47 SB_DQ_46 SB_MA_1 DDRB_SMA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
B DDRA_SDQ48 DDRA_SMA4 DDRB_SDQ48 DDRB_SMA3 B
AV5 SA_DQ_48 SA_MA_4 BG25 AV2 SB_DQ_48 SB_MA_3 AU25
DDRA_SDQ49 AV7 BA24 DDRA_SMA5 DDRB_SDQ49 AU3 AW25 DDRB_SMA4
DDRA_SDQ50 SA_DQ_49 SA_MA_5 DDRA_SMA6 DDRB_SDQ50 SB_DQ_49 SB_MA_4 DDRB_SMA5
AT9 SA_DQ_50 SA_MA_6 BD24 AR3 SB_DQ_50 SB_MA_5 BB28
DDRA_SDQ51 AN8 BG27 DDRA_SMA7 DDRB_SDQ51 AN2 AU28 DDRB_SMA6
DDRA_SDQ52 SA_DQ_51 SA_MA_7 DDRA_SMA8 DDRB_SDQ52 SB_DQ_51 SB_MA_6 DDRB_SMA7
AU5 SA_DQ_52 SA_MA_8 BF25 AY2 SB_DQ_52 SB_MA_7 AW28
DDRA_SDQ53 AU6 AW24 DDRA_SMA9 DDRB_SDQ53 AV1 AT33 DDRB_SMA8
DDRA_SDQ54 SA_DQ_53 SA_MA_9 DDRA_SMA10 DDRB_SDQ54 SB_DQ_53 SB_MA_8 DDRB_SMA9
AT5 SA_DQ_54 SA_MA_10 BC21 AP3 SB_DQ_54 SB_MA_9 BD33
DDRA_SDQ55 AN10 BG26 DDRA_SMA11 DDRB_SDQ55 AR1 BB16 DDRB_SMA10
DDRA_SDQ56 SA_DQ_55 SA_MA_11 DDRA_SMA12 DDRB_SDQ56 SB_DQ_55 SB_MA_10 DDRB_SMA11
AM11 SA_DQ_56 SA_MA_12 BH26 AL1 SB_DQ_56 SB_MA_11 AW33
DDRA_SDQ57 AM5 BH17 DDRA_SMA13 DDRB_SDQ57 AL2 AY33 DDRB_SMA12
DDRA_SDQ58 SA_DQ_57 SA_MA_13 DDRA_SMA14 DDRB_SDQ58 SB_DQ_57 SB_MA_12 DDRB_SMA13
AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
DDRA_SDQ59 AJ8 DDRB_SDQ59 AH1 AU33 DDRB_SMA14
DDRA_SDQ60 SA_DQ_59 DDRB_SDQ60 SB_DQ_59 SB_MA_14
AN12 SA_DQ_60 AM2 SB_DQ_60
DDRA_SDQ61 AM13 DDRB_SDQ61 AM3
DDRA_SDQ62 SA_DQ_61 DDRB_SDQ62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
DDRA_SDQ63 AJ12 DDRB_SDQ63 AJ3
SA_DQ_63 SB_DQ_63
GL@ CANTIGA ES_FCBGA1329 GL@ CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 9 of 45
5 4 3 2 1
 5 4 3 2 1

U23C

DPST_PWM L32 L_BKLT_CTRL

ENBKL 1 2 LBKLT_EN G32 T37 PEG_COMP 1 2 +1.05VS
R180 0_0402_5% LCTLA_CLK L_BKLT_EN PEG_COMPI R184 49.9_0402_1%
LCTLB_DATA
M32 L_CTRL_CLK PEG_COMPO T36 10mils
M33 L_CTRL_DATA
GMCH_LCD_CLK GMCH_LCD_CLK K33
GMCH_LCD_DATA L_DDC_CLK
D GMCH_LCD_DATA J33 L_DDC_DATA PEG_RX#_0 H44 D
GMCH_ENVDD M29 L_VDD_EN PEG_RX#_1 J46
PEG_RX#_2 L44
1 2 LVDS_IBG C44 L40
R396 2.37K_0402_1% LVDS_IBG PEG_RX#_3
B43 LVDS_VBG PEG_RX#_4 N41
2 1 E37 LVDS_VREFH PEG_RX#_5 P48
R185 E38 N44
0_0402_5% LVDS_VREFL PEG_RX#_6
PEG_RX#_7 T43
GMCH_TXCLK- C41 U43
GMCH_TXCLK- LVDSA_CLK# PEG_RX#_8
GMCH_TXCLK+ C40 Y43
GMCH_TXCLK+ LVDSA_CLK PEG_RX#_9
GMCH_TZCLK- B37 Y48
GMCH_TZCLK- LVDSB_CLK# PEG_RX#_10
GMCH_TZCLK+ A37 Y36
GMCH_TZCLK+ LVDSB_CLK PEG_RX#_11

LVDS
PEG_RX#_12 AA43
GMCH_TXOUT0- H47 AD37
GMCH_TXOUT0- LVDSA_DATA#_0 PEG_RX#_13
GMCH_TXOUT1- E46 AC47
GMCH_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
GMCH_TXOUT2- G40 AD39
GMCH_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15
A40 LVDSA_DATA#_3
PEG_RX_0 H43
GMCH_TXOUT0+ H48 J44
GMCH_TXOUT0+ LVDSA_DATA_0 PEG_RX_1
GMCH_TXOUT1+ D45 L43
GMCH_TXOUT1+ LVDSA_DATA_1 PEG_RX_2

GRAPHICS
GMCH_TXOUT2+ F40 L41
GMCH_TXOUT2+ LVDSA_DATA_2 PEG_RX_3
B40 LVDSA_DATA_3 PEG_RX_4 N40
PEG_RX_5 P47
GMCH_TZOUT0- A41 N43
GMCH_TZOUT0- LVDSB_DATA#_0 PEG_RX_6
GMCH_TZOUT1- H38 T42
GMCH_TZOUT1- LVDSB_DATA#_1 PEG_RX_7
GMCH_TZOUT2- G37 U42
GMCH_TZOUT2- LVDSB_DATA#_2 PEG_RX_8
J37 LVDSB_DATA#_3 PEG_RX_9 Y42
PEG_RX_10 W47
GMCH_TZOUT0+ B42 Y37
GMCH_TZOUT0+ LVDSB_DATA_0 PEG_RX_11
C GMCH_TZOUT1+ G38 AA42 C
GMCH_TZOUT1+ LVDSB_DATA_1 PEG_RX_12
GMCH_TZOUT2+ F37 AD36
GMCH_TZOUT2+ LVDSB_DATA_2 PEG_RX_13
K37 LVDSB_DATA_3 PEG_RX_14 AC48

PCI-EXPRESS
PEG_RX_15 AD40

PEG_TX#_0 J41
PEG_TX#_1 M46
GMCH_TV_COMPS F25 M47
GMCH_TV_LUMA TVA_DAC PEG_TX#_2
H25 TVB_DAC PEG_TX#_3 M40
GMCH_TV_CRMA K25 M42
TVC_DAC PEG_TX#_4
PEG_TX#_5 R48
2

TV
H24 TV_RTN PEG_TX#_6 N38
R157 R156 R160 T40
PEG_TX#_7
PEG_TX#_8 U37
PEG_TX#_9 U40
75_0402_1% TV_DCONSEL_0 C31 Y40
1

75_0402_1% TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10

E32 TV_DCONSEL_1 PEG_TX#_11 AA46
75_0402_1% AA37
PEG_TX#_12
PEG_TX#_13 AA40
PEG_TX#_14 AD43
PEG_TX#_15 AC46
Change to 0Ohm when use PM chip
GMCH_CRT_B E28 CRT_BLUE PEG_TX_0 J42
2 1 PEG_TX_1 L46
R173 150_0402_1% G28 M48
GMCH_CRT_G CRT_GREEN PEG_TX_2
2 1 PEG_TX_3 M39

VGA
R172 150_0402_1% J28 M43
GMCH_CRT_R CRT_RED PEG_TX_4
2 1 PEG_TX_5 R47
R171 150_0402_1% G29 N37
B CRT_IRTN PEG_TX_6 B
PEG_TX_7 T39
GMCH_CRT_CLK H32 U36
GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8
GMCH_CRT_DATA J32 U39
GMCH_CRT_DATA CRT_DDC_DATA PEG_TX_9
GMCH_CRT_HSYNC J29 CRT_HSYNC PEG_TX_10 Y39
CRT_IREF E29 Y46
CRT_TVO_IREF PEG_TX_11
PEG_TX_12 AA36
PEG_TX_13 AA39
GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42
PEG_TX_15 AD46
+3VS
2

R174 GL@ CANTIGA ES_FCBGA1329

R187 1 2 2.2K_0402_5% GMCH_LCD_CLK 1.02K_0402_1%

R191 1 2 2.2K_0402_5% GMCH_LCD_DATA

1

R188 1 2 10K_0402_5% LCTLB_DATA

R190 1 2 10K_0402_5% LCTLA_CLK

R178 1 2 2.2K_0402_5% GMCH_CRT_CLK

R164 1 2 2.2K_0402_5% GMCH_CRT_DATA

A A

R186 0_0402_5% TV_DCONSEL_0

R176 0_0402_5% TV_DCONSEL_1

R179 1 2 100K_0402_5% LBKLT_EN Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 10 of 45
5 4 3 2 1
 5 4 3 2 1

U23F
+1.05VS
+1.8V

2600mA VCC_AXG_NTCF_1 W28

AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26 Place close to the GMCH
BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
D
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25
+1.05VS VCC: 1930.4mA (GMCH), 1210.34mA (MCH) D
BF32 V25
BD32
VCC_SM_5 VCC_AXG_NCTF_6
W24 (270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
VCC_SM_6 VCC_AXG_NCTF_7
BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
BB32 W23 +1.05VS
VCC_SM_8 VCC_AXG_NCTF_9 1

VCC
BA32 V23 1 1 U23G
VCC_SM_9 VCC_AXG_NCTF_10 @ + C485 C255 C265 C266 C256
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21
AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21 AG34 VCC_1
AV32 AK21 220U_D2_4VM_R15 0.22U_0402_6.3V6K 0.1U_0402_16V4Z AC34
VCC_SM_12 VCC_AXG_NCTF_13 2 2 2 VCC_2
AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21 AB34 VCC_3
AT32 V21 10U_0805_10V4Z 0.22U_0402_6.3V6K AA34

SM
VCC_SM_14 VCC_AXG_NCTF_15 VCC_4
AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21 Y34 VCC_5
AP32 AM20 Cavity Capacitors V34

VCC CORE
VCC_SM_16 VCC_AXG_NCTF_17 VCC_6
AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20 U34 VCC_7
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 AM33 VCC_8
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 AK33 VCC_9
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AJ33 VCC_10
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AG33 VCC_11
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19 AF33 VCC_12
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
+1.05VS VCC_AXG: 6326.84mA
BD29 AG19
BC29
VCC_SM_25 VCC_AXG_NCTF_26
AF19 (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2) AE33
VCC_SM_26 VCC_AXG_NCTF_27 VCC_13
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 AC33 VCC_14
Reference PILLAR_ROCK CRB Rev1.0 BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19 AA33 VCC_15
AY29 AA19 C243 C244 C234 1 C235 1 C236 1 C242 1 Y33
VCC_SM_29 VCC_AXG_NCTF_30 VCC_16
GFX NCTF
AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19 W33 VCC_17
Pins BA36, BB24, BD16,

POWER
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 V33 VCC_18
BB21, AW16, AW13, AT13 AU29 V19 0.47U_0603_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z U33
VCC_SM_32 VCC_AXG_NCTF_33 2 2 2 2 VCC_19
AT29 U19 AH28
could be left NC for DDR2 AR29
VCC_SM_33 VCC_AXG_NCTF_34
AM17 1U_0402_6.3V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z AF28
VCC_20
board. VCC_SM_34 VCC_AXG_NCTF_35 VCC_21
AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17 AC28 VCC_22
VCC_AXG_NCTF_37 AH17 Cavity Capacitors AA28 VCC_23
C C
VCC_AXG_NCTF_38 AG17 AJ26 VCC_24
VCC_AXG_NCTF_39 AF17 AG26 VCC_25
VCC_SM_BA36 BA36 AE17 AE26
VCC_SM_BB24 VCC_SM_36/NC VCC_AXG_NCTF_40 VCC_26
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AC26 VCC_27 +1.05VS
VCC

VCC_SM_BD16 BD16 AB17 AH25

VCC_SM_38/NC VCC_AXG_NCTF_42 VCC_28
BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AG25 VCC_29
VCC_SM_AW16 AW16 W17 1 AF25
VCC_SM_40/NC VCC_AXG_NCTF_44 VCC_30
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AG24 VCC_31 VCC_NCTF_1 AM32
VCC_SM_AT13 AT13 AM16 C482 + AJ23 AL32
VCC_SM_42/NC VCC_AXG_NCTF_46 VCC_32 VCC_NCTF_2
VCC_AXG_NCTF_47 AL16 AH23 VCC_33 VCC_NCTF_3 AK32
AK16 330U_D2E_2.5VM_R9 AF23 AJ32
POWER

VCC_AXG_NCTF_48 2 VCC_34 VCC_NCTF_4

VCC_AXG_NCTF_49 AJ16 T32 VCC_35 VCC_NCTF_5 AH32
+1.05VS AH16 AG32
VCC_AXG_NCTF_50 VCC_NCTF_6
VCC_AXG_NCTF_51 AG16 VCC_NCTF_7 AE32
VCC_AXG_NCTF_52 AF16 Place close to the GMCH VCC_NCTF_8 AC32
Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16 VCC_NCTF_9 AA32
AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16 VCC_NCTF_10 Y32
AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16 VCC_NCTF_11 W32
AA25 VCC_AXG_4 VCC_AXG_NCTF_56 AA16 VCC_NCTF_12 U32
AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16 VCC_NCTF_13 AM30
AC24 VCC_AXG_6 VCC_AXG_NCTF_58 W16 VCC_SM: 2600mA VCC_NCTF_14 AL30
AA24 V16 AK30
Y24
VCC_AXG_7 VCC_AXG_NCTF_59
U16 +1.8V (330UF*1, 22UF*2, 0.1UF*1) VCC_NCTF_15
AH30
VCC_AXG_8 VCC_AXG_NCTF_60 VCC_NCTF_16
AE23 VCC_AXG_9 VCC_NCTF_17 AG30
AC23 VCC_AXG_10 VCC_NCTF_18 AF30
AB23 VCC_AXG_11 1 VCC_NCTF_19 AE30
AA23 1 1 1 AC30

NCTF
VCC_AXG_12 C269 + C252 C251 C263 VCC_NCTF_20
AJ21 VCC_AXG_13 VCC_NCTF_21 AB30
AG21 VCC_AXG_14 VCC_NCTF_22 AA30
AE21 330U_D2E_2.5VM_R9 10U_0805_10V4Z Y30
VCC_AXG_15 2 2 2 2 VCC_NCTF_23
AC21 VCC_AXG_16 VCC_NCTF_24 W30
AA21 10U_0805_10V4Z 0.1U_0402_16V4Z V30
B VCC_AXG_17 VCC_NCTF_25 B
Y21 VCC_AXG_18 VCC_NCTF_26 U30
VCC

VCC
AH20 VCC_AXG_19 Place on the edge VCC_NCTF_27 AL29
AF20 VCC_AXG_20 VCC_NCTF_28 AK29
AE20 VCC_AXG_21 VCC_NCTF_29 AJ29
AC20 VCC_AXG_22 Reference PILLAR_ROCK CRB Rev1.0 VCC_NCTF_30 AH29
AB20 VCC_AXG_23 VCC_NCTF_31 AG29
AA20 AE29
GFX

VCC_AXG_24 VCC_SM_BA36 VCC_NCTF_32

T17 VCC_AXG_25 VCC_NCTF_33 AC29
T16 VCC_SM_BB24 AA29
VCC_AXG_26 VCC_SM_BD16 VCC_NCTF_34
AM15 VCC_AXG_27 VCC_NCTF_35 Y29
AL15 VCC_SM_AW16 W29
VCC_AXG_28 VCC_SM_AT13 VCC_NCTF_36
AE15 VCC_AXG_29 VCC_NCTF_37 V29
AJ15 VCC_AXG_30 VCC_NCTF_38 AL28
AH15 VCC_AXG_31 1 1 1 1 1 VCC_NCTF_39 AK28
AG15 C214 C229 C228 C240 C271 AL26
VCC_AXG_32 @ @ @ @ @ VCC_NCTF_40
AF15 VCC_AXG_33 VCC_NCTF_41 AK26
AB15 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K AK25
VCC_AXG_34 2 2 2 2 2 VCC_NCTF_42
AA15 VCC_AXG_35 VCC_NCTF_43 AK24
Y15 0.1U_0402_16V7K 0.1U_0402_16V7K AK23
VCC_AXG_36 VCC_NCTF_44
V15 VCC_AXG_37
U15 VCC_AXG_38
AN14 VCC_AXG_39
AM14 VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC SM LF

VCC_AXG_41 VCC_SM_LF1 VCCSM_LF2

T14 VCC_AXG_42 VCC_SM_LF2 BA37
AM40 VCCSM_LF3
VCC_SM_LF3 VCCSM_LF4
VCC_SM_LF4 AV21
AY5 VCCSM_LF5
@ VCC_AXG_SENSE VCC_SM_LF5 VCCSM_LF6 CANTIGA ES_FCBGA1329
T17 PAD AJ14 VCC_AXG_SENSE VCC_SM_LF6 AM10
PAD @ VSS_AXG_SENSE AH14 BB13 VCCSM_LF7
T18 VSS_AXG_SENSE VCC_SM_LF7
1 1 1 1 1 1 1 GL@
C213 C215 C205 C230 C272 C270 C279
A A
0.1U_0402_16V7K 0.22U_0402_6.3V6K 0.47U_0603_16V4Z 1U_0402_6.3V4Z
2 2 2 2 2 2 2
0.1U_0402_16V7K 0.22U_0402_6.3V6K 1U_0402_6.3V4Z
CANTIGA ES_FCBGA1329

GL@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 11 of 45
5 4 3 2 1
 5 4 3 2 1

+1.05VS_HPLL
FOR EMI 20080226 +1.05VS_DPLLA
+1.05VS L18 1 2
MBK1608121YZF_0603 1 1 +1.05VS L22 1 2
VCCA_HPLL: 24mA C433 C434 MBK1608121YZF_0603 1 1 U23H VTT: 852mA
C464 +1.05VS
(4.7UF*1, 0.1UF*1) 4.7U_0805_10V4Z C479 + (270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)
2 2 852mA
Please check Power 2
73mA VTT_1 U13
0.1U_0402_16V4Z VCCA_DPLLA 220U_D2_4VM_R15 B27 T13 1
source if want 2 0.1U_0402_16V4Z
+3VS_CRTDAC VCCA_CRT_DAC_1 VTT_2
Please check Power VCCA_DPLLB: 64.8mA A26 VCCA_CRT_DAC_2 VTT_3 U12 1 1 1 1
support IAMT T12 C481 + C154 C155 C153 C152
+1.05VS_MPLL source if want (220UF*1, 0.1UF*1) VTT_4
VTT_5 U11
120Ohm@100MHz support IAMT 2.69mA T11 220U_D2_4VM_R15 4.7U_0805_10V4Z 0.47U_0603_16V4Z
+1.05VS_DPLLB VTT_6 2 2 2 2 2

CRT
D L6 1 D
2 +3VS_DACBG A25 VCCA_DAC_BG VTT_7 U10
MBK1608121YZF_0603 1 T10 4.7U_0805_10V4Z 2.2U_0603_6.3V6K
VTT_8

1
VCCA_MPLL: 139.2mA C189 L12 1 2 B25 U9
R108 MBK1608121YZF_0603 VSSA_DAC_BG VTT_9
(22UF*1, 0.1UF*1) 1 1 VTT_10 T9
0.5_0603_1% C290 U8
2 VTT_11
FOR EMI 20080226 64.8mA VTT_12 T8

VTT
0.1U_0402_16V4Z C305 +1.05VS_DPLLA F47 U7

2
2
10U_0805_10V4Z 2 VCCA_DPLLA VTT_13
1 VTT_14 T7
0.1U_0402_16V4Z +1.05VS_DPLLB L48 U6
C151 VCCA_DPLLB VTT_15
VTT_16 T6
24mA

PLL
22U_0805_6.3V6M +1.05VS_HPLL AD1 VCCA_HPLL VTT_17 U5
2 R262 +1.8V_TX_LVDS VTT_18 T5
@ 0_0402_5% 1 AE1 139.2mA V3
+1.05VS_MPLL VCCA_MPLL VTT_19
+3VS 1 2 C291 U3
VTT_20
+VCCA_PEG_BG
VCCA_LVDS: 13.2mA 13.2mA VTT_21 V2

A PEG A LVDS
R261 1000P_0402_50V7K J48 U2
0_0402_5% 2 (1000PF*1) VCCA_LVDS VTT_22
T2
VTT_23
+1.5VS 1 2 J47 VSSA_LVDS VTT_24 V1
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) +3VS_CRTDAC U1
1 VTT_25
Please check Power C289 VCCA_PEG_BG: 0.414mA 0.414mA Please check Power
+3VS 1 2 source if want (0.1UF*1) AD48 VCCA_PEG_BG source if want
L21 0.1U_0402_16V4Z VCC_AXF: 321.35mA
MBK1608221YZF_0603 1 1
support IAMT 2 +1.05VS_AXF support IAMT
C475 C462 (10UF*1, 1UF*1)
1 50mA
No CIS Symbol AA48 VCCA_PEG_PLL 1 2 +1.05VS
C483 + 0.1U_0402_16V4Z L10 1 2 +1.05VS_PEGPLL R399
2 2 +1.05VS
MBK1608221YZF_0603 1 VCCA_PEG_PLL: 50mA 1 1 0_0603_5%
220U_D2_4VM_R15 0.01U_0402_16V7K 2 1 1 2 C288 C471 C459
2 C304 R201 (0.1UF*1) @
Close to Ball A26, B27 10U_0805_6.3V6M 1_0402_1% 0.1U_0402_16V4Z 480mA 10U_0805_6.3V6M
2
AR20 VCCA_SM_1
POWER 2 2
+1.05VS_A_SM AP20 1U_0402_6.3V4Z
C VCCA_SM_2 C
VCCA_SM: AN20 VCCA_SM_3
+1.05VS 1 2 (22UF*2, 4.7UF*1, 1UF*1) AR17 VCCA_SM_4 +1.8V_SM_CK
VCC_SM_CK: 119.85mA

A SM
1 R152 1 1 1 AP17
0_0805_5% C233 C231 C232 AN17
VCCA_SM_5
B22
(10UF*1, 0.1UF*1) 1uH 30%
VCCA_SM_6 VCC_AXF_1

AXF
Please check Power C478 + AT16 B21 1 2
VCCA_SM_7 VCC_AXF_2 +1.8V
@ 4.7U_0805_10V4Z AR16 A21 L17
source if want 220U_D2_4VM_R15 2 2 2 VCCA_SM_8 VCC_AXF_3 MBK1608121YZF_0603
AP16 VCCA_SM_9 1
support IAMT 2 22U_0805_6.3V6M 1U_0402_6.3V4Z C424
1 2 1 2
Please check Power 0.1U_0402_16V4Z R361 C250
2 1_0402_1% 10U_0805_6.3V6M
source if want VCC_SM_CK_1 BF21

SM CK
VCCA_DAC_BG: 2.6833333mA support IAMT +1.05VS_A_SM_CK VCC_SM_CK_2 BH20
(0.1UF*1, 0.01UF*1) +3VS_DACBG
VCCA_SM_CK: 24mA VCC_SM_CK_3 BG20
(22UF*1, 2.2UF*1, 0.1UF*1) 24mA VCC_SM_CK_4 BF20
+1.8V_TX_LVDS
+1.05VS 1 2 AP28 VCCA_SM_CK_1 +1.8V_TX_LVDS: 118.8mA
1 2 R170 1 1 1 AN28 0.1uH 20%
+3VS
L20 0_0603_5% C241 C254 C253 AP25
VCCA_SM_CK_2 (22UF*1, 1000PF*1) 1 2
VCCA_SM_CK_3 +1.8V
MBK1608221YZF_0603 1 1 1 @ AN25 118.8mA 1 1 R226
C473 C461 C474 2.2U_0603_6.3V6K 0.1U_0402_16V4Z VCCA_SM_CK_4 C292 C293 0_0603_5%
AN24 VCCA_SM_CK_5 VCC_TX_LVDS K47
2 2 2

A CK
@ AM28
0.1U_0402_16V4Z 10U_0805_6.3V6M 22U_0805_6.3V6M VCCA_SM_CK_NCTF_1 1000P_0402_50V7K
AM26 VCCA_SM_CK_NCTF_2
2 2 2 2 2 10U_0805_10V4Z
AM25 VCCA_SM_CK_NCTF_3 105.3mA VCC_HV: 105.3mA
0.01U_0402_16V7K NO_STUFF AL25 C35 +3VS
VCCA_SM_CK_NCTF_4 VCC_HV_1
AM24 VCCA_SM_CK_NCTF_5 VCC_HV_2 B35 1

HV
Close to Ball A25 AL24 A35 C267
VCCA_SM_CK_NCTF_6 VCC_HV_3
AM23 VCCA_SM_CK_NCTF_7 Please check Power
AL23 0.1U_0402_16V4Z
VCCA_SM_CK_NCTF_8 2 source if want
1782mA support IAMT
VCC_PEG_1 V48 +1.05VS_PEG: 1782mA +1.05VS_PEG
VCC_PEG_2 U48 (220UF*1, 22UF*1, 4.7UF*1)

PEG
VCCA_TV_DAC: 40mA (0.1UF*1, VCC_PEG_3 V47 1 2 +1.05VS
87.79mA U47 1 R264
B 0.01UF*1 for each DAC) B24
VCC_PEG_4
U46 0_0805_5% B
+3VS_TVDAC VCCA_TV_DAC_1 VCC_PEG_5 1
+3VS_TVDAC A24 C311 + C312
VCCA_TV_DAC_2

TV
+3VS L19 1 2 VCCD_HDA: 50mA 10U_0805_10V4Z 220U_D2_4VM_R15
MBK1608221YZF_0603 2 2
(0.1UF*1) 50mA 456mA +1.05VS
180Ohm@100MHz 1 1 +1.5VS_HDA A32 AH48
VCC_HDA VCC_DMI_1

HDA
C472 C460 AF48
VCC_DMI_2
1

DMI
VCC_DMI_3 AH47
0.1U_0402_16V4Z R402 <BOM Structure> AG47 +1.05VS_DMI 1 2
2 2 0_0402_5% VCC_DMI_4 R225
58.696mA
0.01U_0402_16V7K +1.5VS_TVDAC M25 VCC_DMI: 456mA 1 0_0805_5%
VCCD_TVDAC

D TV/CRT
C287
(0.1UF*1)
2

L28 48.363mA
+1.5VS_QDAC VCCD_QDAC 0.1U_0402_16V4Z
2
VCCD_HPLL: 157.2mA (0.1UF*1) 157.2mA
+1.05VS_HPLL AF1 VCCD_HPLL
A8 VTTLF_CAP1
+1.05VS_PEGPLL 50mA VTTLF1 VTTLF_CAP2
Please check Power AA47 VCCD_PEG_PLL VTTLF2 L1

VTTLF
VCCD_TVDAC: 58.696mA source if want VTTLF3 AB2 VTTLF_CAP3
+1.5VS_TVDAC 60.31mA
(0.1UF*1, 0.01UF*1) support IAMT M38 VCCD_LVDS_1 1 1 1
LVDS

+1.5VS 1 2 L37 C190 C445 C470

L7 VCCD_LVDS_2
1 1
MBK1608221YZF_0603 C246 C245 Also power for internal VCCD_PEG_PLL: 50mA 0.47U_0603_16V4Z 0.47U_0603_16V4Z
2 2 2
0.1U_0402_16V4Z
Thermal Sensor (0.1UF*1) CANTIGA ES_FCBGA1329 0.47U_0603_16V4Z
2 2 +1.8V_LVDS
+1.8V 1 2
0.022U_0402_16V7K R192 GL@
0_0603_5% 1 1
C274 C273

10U_0805_6.3V6M
A 2 2 A
VCCD_QDAC: 48.363mA +1.5VS_QDAC R263
1U_0402_6.3V4Z D15
(0.1UF*1, 0.01UF*1) 2 1 1 2
+1.05VS +3VS
+1.5VS 1 2 VCCD_LVDS: 60.311111mA
R144 1 1 10_0603_5%
(1UF*1)
1

100_0603_1% C247 C257 CH751H-40PT_SOD323-2

180Ohm@100MHz R165
0.1U_0402_16V4Z 0_0402_5%
2 2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
0.01U_0402_16V7K 2009/01/21 2010/01/21 Title
Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 12 of 45
5 4 3 2 1
 5 4 3 2 1

U23I U23J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
C C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259 VSS_NCTF_1 AF32
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_2 AB32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_3 V32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_5 AM29
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_6 AF29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_7 AB29
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
B B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1
VSS SCB

VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
CANTIGA ES_FCBGA1329 E48
NC_40
NC_41 C48
GL@ NC_42 B48

CANTIGA ES_FCBGA1329

A A
GL@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 13 of 45
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

JDIMM2 +1.8V
+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ4 +DIMM_VREF
VSS DQ4

1
DDRA_SDQ0 5 6 DDRA_SDQ5 20mils
DDRA_SDQ1 DQ0 DQ5 R200
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
9 DDRA_SDQS0# DDRA_SDQS0
11 DQS0# VSS 12
DDRA_SDQ6 C286
1 1
C285
20mils
13 14 To SODIMM and GMCH

2
9 DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7 @
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18 0.1U_0402_16V4Z
DQ2 VSS

1
DDRA_SDQ3 DDRA_SDQ12 2 2
19 DQ3 DQ12 20
D DDRA_SDQ13 R195 D
21 VSS DQ13 22
DDRA_SDQ8 23 24 2.2U_0603_6.3V6K
DDRA_SDQ9 DQ8 VSS DDRA_SDM1 1K_0402_1%
25 DQ9 DM1 26
27 28

2
DDRA_SDQS1# VSS VSS
9 DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0
DDRA_SDQS1 31 32
9 DDRA_SDQS1 DQS1 CK0# DDRA_CLK0#
33 VSS VSS 34
DDRA_SDQ10 35 36 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
37 DQ11 DQ15 38
39 40 DDRA_SMA[0..14]
VSS VSS DDRA_SMA[0..14]
DDRA_SDQ[0..63]
9 DDRA_SDQ[0..63]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDM[0..7]
DQ16 DQ20 DDRA_SDM[0..7] +1.8V
DDRA_SDQ17 45 46 DDRA_SDQ21
DQ17 DQ21
47 VSS VSS 48
DDRA_SDQS2# 49 50
9 DDRA_SDQS2# DQS2# NC PM_EXTTS#0
DDRA_SDQS2 51 52 DDRA_SDM2
9 DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54 1 1 1 1 1
DDRA_SDQ18 55 56 DDRA_SDQ22 C148 C186 C185 C134 C202
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23
57 DQ19 DQ23 58
59 60 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DDRA_SDQ24 VSS VSS DDRA_SDQ28 2 2 2 2 2
61 DQ24 DQ28 62
DDRA_SDQ25 63 64 DDRA_SDQ29 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DQ25 DQ29
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3#
DM3 DQS3# DDRA_SDQS3 DDRA_SDQS3# 9
69 NC DQS3 70 DDRA_SDQS3 9
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ30 +1.8V
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 +0.9VS
75 DQ27 DQ31 76
77 VSS VSS 78
DDRA_CKE0 79 80 DDRA_CKE1 DDRA_CKE0 1 4
C DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 C
81 82 DDRA_SBS2# 2 3 1 1 1 1
VDD VDD RP28 56_0404_4P2R_5% C415 C412 C413 C414
83 NC NC/A15 84
DDRA_SBS2# 85 86 DDRA_SMA14
DDRA_SBS2# BA2 NC/A14
87 88 DDRA_SMA12 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA12 VDD VDD DDRA_SMA11 DDRA_SMA5 2 2 2 2
89 A12 A11 90 2 3
DDRA_SMA9 91 92 DDRA_SMA7 RP27 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA8 A9 A7 DDRA_SMA6
93 A8 A6 94
95 96 DDRA_SMA8 1 4
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_SMA9
97 A5 A4 98 2 3
DDRA_SMA3 99 100 DDRA_SMA2 RP19 56_0404_4P2R_5%
DDRA_SMA1 A3 A2 DDRA_SMA0
101 A1 A0 102
103 104 DDRA_SMA3 1 4
DDRA_SMA10 VDD VDD DDRA_SBS1# DDRA_SMA1 +0.9VS
105 A10/AP BA1 106 DDRA_SBS1# 2 3
DDRA_SBS0# 107 108 DDRA_SRAS# RP18 56_0404_4P2R_5%
DDRA_SBS0# BA0 RAS# DDRA_SRAS#
DDRA_SWE# 109 110 DDRA_SCS0#
DDRA_SWE# WE# S0# DDRA_SCS0#
111 112 DDRA_SMA10 1 4
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_SBS0#
DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 2 3 1 1 1 1 1
DDRA_SCS1# 115 116 DDRA_SMA13 RP10 56_0404_4P2R_5% C187 C149 C146 C183 C188
DDRA_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRA_ODT1 119 120 DDRA_SWE# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_ODT1 NC/ODT1 NC 2 2 2 2 2
121 122 DDRA_SCAS# 2 3
DDRA_SDQ32 VSS VSS DDRA_SDQ36 RP9 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
123 DQ32 DQ36 124
DDRA_SDQ33 125 126 DDRA_SDQ37
DQ33 DQ37 DDRA_ODT1
127 VSS VSS 128 1 4
DDRA_SDQS4# 129 130 DDRA_SDM4 DDRA_SCS1# 2 3
9 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 RP3 56_0404_4P2R_5% +0.9VS
9 DDRA_SDQS4 131 DQS4 VSS 132
133 134 DDRA_SDQ38
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
135 DQ34 DQ39 136
DDRA_SDQ35 137 138
DQ35 VSS DDRA_SDQ44 DDRA_SMA6
139 VSS DQ44 140 1 4 1 1 1 1 1
DDRA_SDQ40 141 142 DDRA_SDQ45 DDRA_SMA11 2 3 C147 C203 C150 C135 C201
DDRA_SDQ41 DQ40 DQ45 RP25 56_0404_4P2R_5%
143 DQ41 VSS 144
B DDRA_SDQS5# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
145 VSS DQS5# 146 DDRA_SDQS5# 9
DDRA_SDM5 DDRA_SDQS5 DDRA_SMA14 2 2 2 2 2
147 DM5 DQS5 148 DDRA_SDQS5 9 1 4
149 150 DDRA_SMA7 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ42 VSS VSS DDRA_SDQ46 RP26 56_0404_4P2R_5%
151 DQ42 DQ46 152
DDRA_SDQ43 153 154 DDRA_SDQ47
DQ43 DQ47 DDRA_SMA2
155 VSS VSS 156 1 4
DDRA_SDQ48 157 158 DDRA_SDQ52 DDRA_SMA4 2 3 +0.9VS
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 RP17 56_0404_4P2R_5%
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDRA_SMA0 1 4
NC,TEST CK1 DDRA_CLK1
165 166 DDRA_SBS1# 2 3 1 1 1
VSS CK1# DDRA_CLK1#
DDRA_SDQS6# 167 168 RP16 56_0404_4P2R_5% C204 C184 C200
9 DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
9 DDRA_SDQS6 169 DQS6 DM6 170
171 172 DDRA_SRAS# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ50 VSS VSS DDRA_SDQ54 DDRA_SCS0# 2 2 2
173 DQ50 DQ54 174 2 3
DDRA_SDQ51 175 176 DDRA_SDQ55 RP8 56_0404_4P2R_5% 0.1U_0402_16V4Z
DQ51 DQ55
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60 DDRA_ODT0 1 4
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61 DDRA_SMA13
181 DQ57 DQ61 182 2 3
183 184 RP7 56_0404_4P2R_5%
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 DM7 DQS7# 186 DDRA_SDQS7# 9
187 188 DDRA_SDQS7 DDRA_CKE1 1 2
DDRA_SDQ58 VSS DQS7 DDRA_SDQS7 9 R138 56_0402_5%
189 DQ58 VSS 190
DDRA_SDQ59 191 192 DDRA_SDQ62
DQ59 DQ62 DDRA_SDQ63
193 VSS DQ63 194
D_CK_SDATA 195 196
15,16 D_CK_SDATA SDA VSS
D_CK_SCLK 197 198 R351 1 2 10K_0402_5%
15,16 D_CK_SCLK SCL SAO
+3VS 199 200 R350 1 2 10K_0402_5%
VDDSPD SA1
203 GND GND 204

FOX_AS0A426-N2RN-7F
CONN@
A +3VS A

1 1
DIMM0 REV H:5.2mm (BOT)
C411 C410

0.1U_0402_16V4Z
2
2.2U_0603_6.3V6K 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 14 of 43
5 4 3 2 1
 A B C D E

+DIMM_VREF +1.8V

+1.8V +1.8V
1 1
1 1
JDIMM1 C284 C283 C282 + +C227
+DIMM_VREF 1 2 @ @
VREF VSS DDRB_SDQ4 2.2U_0603_6.3V6K 330U_D2E_2.5VM_R9
3 VSS DQ4 4
DDRB_SDQ0 DDRB_SDQ1 2 2
0.1U_0402_16V4Z 2 2
5 DQ0 DQ5 6
DDRB_SDQ5 7 8 330U_D2E_2.5VM_R9
DQ1 VSS DDRB_SDM0
9 VSS DM0 10
DDRB_SDQS0# 11 12
1 DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6 1
DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
DDRB_SDQ9 DQ8 VSS DDRB_SDM1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
DDRB_SDQS1# DQS1# CK0 DDRB_CLK0
DDRB_SDQS1 31 32
DDRB_SDQS1 DQS1 CK0# DDRB_CLK0#
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14 DDRB_SMA[0..14]
DQ10 DQ14 DDRB_SMA[0..14]
DDRB_SDQ11 37 38 DDRB_SDQ15
DQ11 DQ15 DDRB_SDQ[0..63]
39 VSS VSS 40 DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SDM[0..7]
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
47 VSS VSS 48
DDRB_SDQS2# 49 50
DDRB_SDQS2# DQS2# NC PM_EXTTS#1
DDRB_SDQS2 51 52 DDRB_SDM2
DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29
63 DQ25 DQ29 64
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3# +1.8V
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# +0.9VS
69 NC DQS3 70 DDRB_SDQS3
71 VSS VSS 72
2 DDRB_SDQ26 DDRB_SDQ30 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31 DDRB_CKE0 1 4 1 1 1 1 1
DQ27 DQ31 DDRB_SBS2# C197 C181 C143 C198 C144
77 VSS VSS 78 2 3
DDRB_CKE0 79 80 DDRB_CKE1 RP30 56_0404_4P2R_5%
DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1
81 82 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
VDD VDD DDRB_SMA12 2 2
2.2U_0603_6.3V6K 2 2
2.2U_0603_6.3V6K 2
83 NC NC/A15 84 1 4
DDRB_SBS2# 85 86 DDRB_SMA14 DDRB_SMA9 2 3
DDRB_SBS2# BA2 NC/A14
87 88 RP24 56_0404_4P2R_5%
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 DDRB_SMA8 1 4
DDRB_SMA8 A9 A7 DDRB_SMA6 DDRB_SMA5 +1.8V
93 A8 A6 94 2 3
95 96 RP23 56_0404_4P2R_5%
DDRB_SMA5 VDD VDD DDRB_SMA4
97 A5 A4 98
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA3 1 4
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA1
101 A1 A0 102 2 3 1 1 1 1
103 104 RP15 56_0404_4P2R_5% C182 C210 C180 C142
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 A10/AP BA1 106 DDRB_SBS1#
DDRB_SBS0# 107 108 DDRB_SRAS# DDRB_SMA10 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SBS0# BA0 RAS# DDRB_SRAS# 2 2 2 2
DDRB_SWE# 109 110 DDRB_SCS0# DDRB_SBS0# 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SWE# WE# S0# DDRB_SCS0#
111 112 RP14 56_0404_4P2R_5%
DDRB_SCAS# VDD VDD DDRB_ODT0
DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0
DDRB_SCS1# 115 116 DDRB_SMA13 DDRB_SWE# 1 4
DDRB_SCS1# NC/S1# NC/A13
117 118 DDRB_SCAS# 2 3
DDRB_ODT1 VDD VDD RP6 56_0404_4P2R_5%
DDRB_ODT1 119 NC/ODT1 NC 120
121 VSS VSS 122
DDRB_SDQ32 123 124 DDRB_SDQ36 DDRB_SCS1# 1 4
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37 DDRB_ODT1 +0.9VS
125 DQ33 DQ37 126 2 3
127 128 RP2 56_0404_4P2R_5%
DDRB_SDQS4# VSS VSS DDRB_SDM4
DDRB_SDQS4# 129 DQS4# DM4 130
DDRB_SDQS4 131 132
DDRB_SDQS4 DQS4 VSS DDRB_SDQ38
133 VSS DQ38 134 1 1 1 1 1
DDRB_SDQ34 135 136 DDRB_SDQ39 DDRB_SMA11 1 4 C131 C212 C133 C179 C211
3 DDRB_SDQ35 DQ34 DQ39 DDRB_SMA14 3
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP22 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
141 DQ40 DQ45 142
DDRB_SDQ41 143 144 DDRB_SMA6 1 4
DQ41 VSS DDRB_SDQS5# DDRB_SMA7
145 VSS DQS5# 146 DDRB_SDQS5# 2 3
DDRB_SDM5 147 148 DDRB_SDQS5 RP21 56_0404_4P2R_5%
DM5 DQS5 DDRB_SDQS5
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46 DDRB_SMA2 1 4 +0.9VS
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA4
153 DQ43 DQ47 154 2 3
155 156 RP13 56_0404_4P2R_5%
DDRB_SDQ48 VSS VSS DDRB_SDQ52
157 DQ48 DQ52 158
DDRB_SDQ49 159 160 DDRB_SDQ53 DDRB_SBS1# 1 4 1 1 1 1 1
DQ49 DQ53 DDRB_SMA0 C196 C199 C132 C209 C141
161 VSS VSS 162 2 3
163 164 RP12 56_0404_4P2R_5%
NC,TEST CK1 DDRB_CLK1
165 166 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS CK1# DDRB_CLK1# 2 2 2 2 2
DDRB_SDQS6# 167 168 DDRB_SCS0# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SRAS#
DDRB_SDQS6 169 DQS6 DM6 170 2 3
171 172 RP5 56_0404_4P2R_5%
DDRB_SDQ50 VSS VSS DDRB_SDQ54
173 DQ50 DQ54 174
DDRB_SDQ51 175 176 DDRB_SDQ55 DDRB_SMA13 1 4 +0.9VS
DQ51 DQ55 DDRB_ODT0
177 VSS VSS 178 2 3
DDRB_SDQ56 179 180 DDRB_SDQ60 RP1 56_0404_4P2R_5%
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61
181 DQ57 DQ61 182
183 184 DDRB_CKE1 1 2 1 1 1
DDRB_SDM7 VSS VSS DDRB_SDQS7# R137 56_0402_5% C140 C178 C145
185 DM7 DQS7# 186 DDRB_SDQS7#
187 188 DDRB_SDQS7
DDRB_SDQ58 VSS DQS7 DDRB_SDQS7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
189 DQ58 VSS 190
DDRB_SDQ59 DDRB_SDQ62 2 2
0.1U_0402_16V4Z 2
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 R52 1 2 10K_0402_5%
D_CK_SCLK SCL SAO
+3VS 199 200 R53 1 2 10K_0402_5% +3VS
4 VDDSPD SA1 4
201 GND GND 202

FOX_AS0A426-NARN-7F
CONN@

DIMM1 REV H:9.2mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 15 of 45
A B C D E
 A B C D E F G H

FSLC FSLB FSLA CPU SRC PCI

+CLK_VDDSRC +CLK_VDD
Clock Generator
CLKSEL2 CLKSEL1 CLKSEL0 L15 2 L16 2
MHz MHz MHz +1.05VS 1
FBMA-L11-201209-221LMA30T_0805
+3VS 1
FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 266 100 33.3 C358 C371 C387 C370 C380 C381 C386 C384 C356 C357 C355 C352 C372 C385
C347 C390
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 1 0 200 100 33.3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

0 1 1 166 100 33.3 U16

1 1
+CLK_VDD ICS9LPRS387, PN:SA000020H10
Table : ICS9LPRS387 D_CK_SDATA
SLG8SP556V, PN:SA000020K00 SDATA 9 D_CK_SDATA
CLK_REQ# Control Free-Run 6 VDDREF D_CK_SCLK
SCLK 10 D_CK_SCLK
CR#_10(WLAN) PCIEX10 PCIEX0 19 VDD48
CR#_6(MCH) PCIEX6 PCIEX1 72 71 CLK_CPU_BCLK
VDDCPU CPUT0_LPR_F CLK_CPU_BCLK
CR#_4(NEW CARD) PCIEX4 12 70 CLK_CPU_BCLK#
VDDPCI CPUC0_LPR_F CLK_CPU_BCLK#
+3VS
CR#_9(MINI CARDII) PCIEX9 27 VDDPLL3
68 CLK_MCH_BCLK
CPUT1_LPR_F CLK_MCH_BCLK
SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable] 55 VDDSRC

2
67 CLK_MCH_BCLK#
CPUC1_LPR_F CLK_MCH_BCLK#
R301
10K_0402_5% +CLK_VDDSRC 52 VDDSRC_IO
+3VS 24 CLK_DREF_96M
@ SRCT0_LPR/DOTT_96_LPR CLK_DREF_96M
38

1
CLK_PCI2 CK505_PWRGD VDDSRC_IO CLK_DREF_96M#
1 2 SRCC0_LPR/DOTC_96_LPR 25 CLK_DREF_96M#
R306 10K_0402_5% 62 VDDSRC_IO

1
D
CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed) VGA: disable this pair by BIOS
2 31 28 CLK_DREF_SSC
CLK_ENABLE# VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 CLK_DREF_SSC
mount to Enable ITP_CLK G
1 2 S Q28 66 29 CLK_DREF_SSC#
CLK_DREF_SSC#

3
R312 @ 10K_0402_5% VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2
2N7002_SOT23

CLK_PCI5
@ 23 VDD96_IO CLK_PCIE_SATA
VGA: disable this pair by BIOS
1 2 SRCT2_LPR/SATAT_LPR 32 CLK_PCIE_SATA
R310 10K_0402_5%
2 33 CLK_PCIE_SATA# 2
SRCC2_LPR/SATAC_LPR CLK_PCIE_SATA#
CLK_PCI5=0, Pin63,64 is SRC_CLK H_STP_CPU# 53
H_STP_CPU# CPU_STOP#
CLK_PCI5=1, Pin63,64 is ITP_CLK H_STP_PCI# CLK_PCIE_ICH
H_STP_PCI# 54 PCI_STOP# SRCT3_LPR 35 CLK_PCIE_ICH
1 2 CLK_PCI4 36 CLK_PCIE_ICH#
SRCC3_LPR CLK_PCIE_ICH#
R308 10K_0402_5%
CLK_PCI4=0, Pin28, 29 is SRC_CLK
13 39 CLK_PCIE_CARD
Pin24, 25 is DOT96_CLK PCI1 SRCT4_LPR CLK_PCIE_CARD
1 2 CK_PWRGD CLK_PCI2 14 40 CLK_PCIE_CARD#
PCI2/TME SRCC4_LPR CLK_PCIE_CARD#
R292 @ 10K_0402_5%
CLK_PCI_LPC R307 2 1 33_0402_5% CLK_PCI3 15
CLK_PCI_LPC PCI3
57 CLK_MCH_3GPLL
SRCT6_LPR CLK_MCH_3GPLL
CLK_PCI4 16
C345 1 PCI4/27_SELECT
2 @ 10P_0402_50V8J CLK_PCI_LPC
SRCC6_LPR 56 CLK_MCH_3GPLL#
CLK_MCH_3GPLL#
CLK_PCI_ICH R309 2 1 33_0402_5% CLK_PCI5 17
CLK_PCI_ICH PCI_F5/ITP_EN
C346 1 2 @ 10P_0402_50V8J CLK_PCI_ICH
SRCT7_LPR 61
For EMI 10/9 0_0402_5% 2 1 R303 CK505_PWRGD1 UMA: disable this pair by BIOS
CK_PWRGD CK_PWRGD/PD#
0_0402_5% 2 @ 1 R302 60
VGATE SRCC7_LPR
+1.05VS C354
1 2 CLK_XTALIN 5 64
X1 CPUT2_ITP_LPR/SRCT8_LPR
2

R327 27P_0402_50V8J CLK_XTALOUT 4 63

@ 56_0402_5% Y2 X2 CPUC2_ITP_LPR/SRCC8_LPR
C353 14.31818MHz_20P_FSX8L14.318181M20FDB
R326 R313 27P_0402_50V8J 11 44 CLK_PCIE_MINI2
CLK_PCIE_MINI2
2

3 2.2K_0402_5% 1K_0402_5% NC SRCT9_LPR 3

1 2
1

CLKSEL0 1 2 1 2 45 CLK_PCIE_MINI2#
MCH_CLKSEL0 SRCC9_LPR CLK_PCIE_MINI2#
CLK_ICH_48M R325 2 1 22_0402_5% CLKSEL0 20
CLK_ICH_48M USB_48MHz/FSLA
1 2 1 2 CPU_BSEL0 CLK_SD_48M R311 2 1 22_0402_5% 50
CLK_SD_48M SRCT10_LPR
R328 R314 CLKSEL1 2
@ 1K_0402_5% 0_0402_5% FSLB/TEST_MODE
SRCC10_LPR 51
CLK_ICH_14M R304 2 1 33_0402_5% CLKSEL2 7
CLK_ICH_14M FSLC/TEST_SEL/REF0
+1.05VS 8 48 CLK_PCIE_LAN
REF1 SRCT11_LPR CLK_PCIE_LAN
47 CLK_PCIE_LAN#
SRCC11_LPR CLK_PCIE_LAN#
2

R384
@ 1K_0402_5% +3VS 69
R305 GNDCPU
R383 4.7K_0402_5% 3 37
GNDREF CR#3
2

1K_0402_5%
G

1 2 +3VS 1 2 +3VS
1

CLKSEL1 1 2 18 41 R337 10K_0402_5%

MCH_CLKSEL1 GNDPCI CR#4 EXP_CLKREQ#
ICH_SMBDATA 1 3 D_CK_SDATA
22 58
D

GND48 CR#6 MCH_CLKREQ#

1 2 1 2 CPU_BSEL1 Q22 (Pull High to +3VS at GMCH side)
R379 R380 2N7002_SOT23 30 65
@ 0_0402_5% 0_0402_5% GND CR7#
1 2 +3VS
+3VS 26 43 R336 10K_0402_5%
GND CR#9 MINI2_CLKREQ#
R293
4.7K_0402_5% 34 49
GNDSRC CR10#
2

+1.05VS
G

1 2 +3VS 1 2 +3VS
59 46 R364 10K_0402_5%
GNDSRC CR#11 LAN_CLKREQ#
ICH_SMBCLK 1 3 D_CK_SCLK
4 4
2

R389 42 21
D

GNDSRC CR#A SATA_CLKREQ#

@ 1K_0402_5% Q23 73 (Pull High to +3VS at ICH side)
2N7002_SOT23 GND_THERMAL_PAD
R388 R392 ICS9LPRS387BKLFT_MLF72_10x10
10K_0402_5% 1K_0402_5%
1

CLKSEL2 1 2 1 2 MCH_CLKSEL2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title
1
R390
2 1
R391
2 CPU_BSEL2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
@ 0_0402_5% 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 16 of 45
A B C D E F G H
 5 4 3 2 1

LCD POWER CIRCUIT

D D

+LCDVDD
+3V +3VS
W=60mils

1
R415

1
300_0603_5% 1
R414 C495
100K_0402_5%

3 2
4.7U_0805_10V4Z
2

2
Q36B

3
S
G
2N7002DW-T/R7_SOT363-6 5 2 1 2 Q37
R413 1K_0402_5% AO3413_SOT23-3
D
1
4

1
6
C491 +LCDVDD

Q36A 0.047U_0402_16V7K
W=60mils
2
GMCH_ENVDD 1 2 2
2N7002DW-T/R7_SOT363-6 1 1
R408 0_0402_5% C494 C493

1
1

4.7U_0805_10V4Z 0.1U_0402_16V4Z
R407 2 2
100K_0402_5%
2

C C

+3VS +3VS

5
U24
R411

P
NC
INVTPWM 4 2
Y A DPST_PWM
4.7K_0402_5%
D20

G
2
BKOFF# 1 2 DISPOFF# NC7SZ14P5X_NL_SC70-5
BKOFF#

3
+INVPWR_B+ CH751H-40PT_SOD323-2

2
L24 2

G
1 B+ R412
W=40mils FBMA-L11-201209-221LMA30T_0805
DAC_BRIG 1 2 +3VS 1 2 INVTPWM 1 3
L23 2 1 C484 220P_0402_50V7K

S
FBMA-L11-201209-221LMA30T_0805 INVTPWM 1 2 10K_0402_5%
1 1 C486 220P_0402_50V7K
C489 C490 DISPOFF# @ Q35
1 2
C487 220P_0402_50V7K 2N7002_SOT23 For GMCH DPST
680P_0402_50V7K 68P_0402_50V8J @
2 2

B B

LCD/PANEL BD. Conn.

JLVDS1
42 41 DAC_BRIG
GND GND DAC_BRIG
+INVPWR_B+ 40 40 39 39
38 37 INVTPWM R410 1 @ 2 0_0402_5%
38 37 INVT_PWM
+3VS 36 35 DISPOFF#
GMCH_LCD_CLK 36 35
GMCH_LCD_CLK 34 34 33 33 +LCDVDD
GMCH_LCD_DATA 32 31
GMCH_LCD_DATA 32 31
GMCH_TZOUT0-
30 30 29 29 W=60mils
GMCH_TZOUT0- 28 28 27 27
GMCH_TZOUT0+ 26 25 GMCH_TXOUT0- +LCDVDD
GMCH_TZOUT0+ 26 25 GMCH_TXOUT0-
24 23 GMCH_TXOUT0+
24 23 GMCH_TXOUT0+
GMCH_TZOUT1+ 22 21
GMCH_TZOUT1+ 22 21
GMCH_TZOUT1- 20 19 GMCH_TXOUT1-
GMCH_TZOUT1- 20 19 GMCH_TXOUT1-
18 17 GMCH_TXOUT1+ 1 1
18 17 GMCH_TXOUT1+
GMCH_TZOUT2+ 16 15 C492 C488
GMCH_TZOUT2+ 16 15
GMCH_TZOUT2- 14 13 GMCH_TXOUT2+
GMCH_TZOUT2- 14 13 GMCH_TXOUT2+
12 11 GMCH_TXOUT2- 10U_0805_10V4Z 0.1U_0402_16V4Z
12 11 GMCH_TXOUT2- 2 2
GMCH_TZCLK- 10 9
GMCH_TZCLK- 10 9
GMCH_TZCLK+ 8 7 GMCH_TXCLK-
GMCH_TZCLK+ 8 7 GMCH_TXCLK-
6 5 GMCH_TXCLK+
6 5 GMCH_TXCLK+
USB20_N3 4 4 3 3
USB20_P3 2 2 1 1 +3VS
ACES_88242-4001
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 17 of 45
5 4 3 2 1
 A B C D E

D27 D26 D25

W=40mils
+5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D4 F1 W=40mils
CRT Connector

1
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
1
C12

3
0.1U_0402_16V4Z
2
1
+3VS 1

GMCH_CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1

GMCH_CRT_R
L42 FCM2012C-800_0805 L41 FCM2012C-800_0805 6
11
GMCH_CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 1
GMCH_CRT_G
L31 FCM2012C-800_0805 L40 FCM2012C-800_0805 7
12
GMCH_CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 2
GMCH_CRT_B
L30 FCM2012C-800_0805 L39 FCM2012C-800_0805 8

1
13

1
R464 R443 1 1 1 1 1 1 1 1 1 3
R442 C547 C534 C532 C546 C535 C533 9
C560 C559 C558 14
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4

2
2 2 2 2 2 2 2 2 2
10 16

2
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 15 17
150_0402_1% 22P_0402_50V8J 22P_0402_50V8J 1 5
10P_0402_50V8J C557
SUYIN_070549FR015S208CR
1 2 CRT_HSYNC_2 CONN@
L4 10_0603_5% 2
CRT_DET#
100P_0402_50V8J
1 2 CRT_VSYNC_2
L3 10_0603_5% 1 1 DSUB_12

2
+CRT_VCC C76
C89 1 R463
1 2 2 1 10P_0402_50V8J 10P_0402_50V8J 100K_0402_5%
C88 0.1U_0402_16V4Z R40 10K_0402_5% 2 2
DSUB_15

1
5

1
2 U4 C101 2 2
68P_0402_50V8J 1

OE#
R47 1 2 30.1_0402_1% CRT_HSYNC 2 4 CRT_HSYNC_1
GMCH_CRT_HSYNC A Y C62 +CRT_VCC

G
68P_0402_50V8J
74AHCT1G125GW_SOT353-5 2

3
+CRT_VCC

1 2
C75 0.1U_0402_16V4Z

1
U3

OE#
R30 1 2 30.1_0402_1% CRT_VSYNC 2 4 CRT_VSYNC_1
GMCH_CRT_VSYNC A Y

G
74AHCT1G125GW_SOT353-5

3
+CRT_VCC

Place closed to chipset

+3VS

1
R50 R29
4.7K_0402_5% 4.7K_0402_5%

2
3 3

G
DSUB_12 1 3
GMCH_CRT_DATA

S
Q6

2
2N7002_SOT23

G
DSUB_15 1 3 GMCH_CRT_CLK

S
Q4
2N7002_SOT23

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 18 of 45
A B C D E
 5 4 3 2 1

DMI for ESI-compatible operation

+3VS
Low= DMI for ESI-compatible operation
PCI_GNT#1 High= Default* (Internal pull-up)
RP4
1 8 PCI_DEVSEL#
2 7 PCI_FRAME#
D 3 6 PCI_REQ#1 D
4 5 PCI_REQ#2
U11B
8.2K_1206_8P4R_5% D11 F1 PCI_REQ#0
AD0 REQ0# PCI_GNT#0
C8 AD1 GNT0# G4
RP20 PCI_REQ#1
1 8 PCI_PLOCK#
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_GNT#1 @
AD3 GNT1#/GPIO51 PAD T12
2 7 PCI_IRDY# E9 F13 PCI_REQ#2
PCI_PERR# AD4 REQ2#/GPIO52 PCI_GNT#2 @
3 6 C9 AD5 GNT2#/GPIO53 F12 PAD T9
4 5 PCI_PIRQB# E10 E6 PCI_REQ#3
AD6 REQ3#/GPIO54 PCI_GNT#3
B7 AD7 GNT3#/GPIO55 F6
8.2K_1206_8P4R_5% C7 AD8 PCI_CBE#0 @
C5 AD9 C/BE0# D8 PAD T11
G11 B4 PCI_CBE#1 @ PAD
AD10 C/BE1# T15
F8 D6 PCI_CBE#2 @ PAD
AD11 C/BE2# T13
F11 A5 PCI_CBE#3 @ PAD
+3VS AD12 C/BE3# T14
E7 AD13
A3 D3 PCI_IRDY#
RP29 AD14 IRDY# PCI_PAR @
D2 AD15 PAR E3 PAD T16
1 8 PCI_PIRQG# F10 R1 PCI_RST#
AD16 PCIRST# PCI_RST#
2 7 PCI_PIRQE# D5 C6 PCI_DEVSEL#
PCI_REQ#0 AD17 DEVSEL# PCI_PERR#
3 6
PCI_PIRQH#
D10 AD18 PERR# E4
PCI_PLOCK#
Place closely pin B10
4 5 B3 AD19 PLOCK# C2
F7 J4 PCI_SERR#
8.2K_1206_8P4R_5% AD20 SERR# PCI_STOP# CLK_PCI_ICH
C3 AD21 STOP# A4
F3 F5 PCI_TRDY#
AD22 TRDY#

2
RP31 F4 D7 PCI_FRAME#
PCI_PIRQF# AD23 FRAME#
1 8 C1 AD24
2 7 PCI_SERR# G7 C14 PLT_RST# R132
AD25 PLTRST# PLT_RST#
C 3 6 PCI_PIRQA# H7 D4 CLK_PCI_ICH 10_0402_5% C
AD26 PCICLK CLK_PCI_ICH
4 5 PCI_PIRQC# D1 R2 @

1
AD27 PME#
G5 AD28
8.2K_1206_8P4R_5% H6 1
AD29 C194
G1 AD30
RP11 H3 10P_0402_50V8J
PCI_STOP# AD31 @
1 8
PCI_PIRQD# 2
2 7
PCI_REQ#3
3
4
6
5 PCI_TRDY# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
8.2K_1206_8P4R_5% PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2
ICH9-M ES_FCBGA676

A16 Swap Override Strap

Low= A16 swap override Enable
PCI_GNT#3 High= Default*

R123 1 2 1K_0402_5% PCI_GNT#3

@
B B

+3VS

5
U8
Boot BIOS Strap PLT_RST# 2 B

P
Y 4 PLT_RST_BUF#
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction 1 A

1
NC7SZ08P5X_NL_SC70-5

3
R83
0 1 SPI 100K_0402_5%

1 0 PCI

2
1 1 LPC*

R124 1 2 1K_0402_5% PCI_GNT#0

@

R131 1 2 1K_0402_5% SPI_CS#1

@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 19 of 45
5 4 3 2 1
 5 4 3 2 1

+RTCVCC
C164
18P_0402_50V8J
2 1 ICH_RTCX1 +1.05VS

10M_0402_5%
R113 X1 H_DPRSTP# 2 1

1
3 4 R231 @ 56_0402_5%
NC OUT

R130
1M_0402_5% H_DPSLP# 2 1
32.768KHZ_12.5P_MC-306 2 1 R233 @ 56_0402_5%
2

SM_INTRUDER# NC IN
C163 U11A

2
D 18P_0402_50V8J C23 K5 LPC_AD0 D
RTCX1 FWH0/LAD0 LPC_AD0
2 1 ICH_RTCX2 C24 K4 LPC_AD1
+RTCVCC RTCX2 FWH1/LAD1 LPC_AD1
L6 LPC_AD2
FWH2/LAD2 LPC_AD2
+RTCVCC 1 2 ICH_RTCRST# A25 K2 LPC_AD3
RTCRST# FWH3/LAD3 LPC_AD3
R89 +RTCVCC 1 2 ICH_SRTCRST# F20
20K_0402_5% R90 SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME#
1

20K_0402_5%

RTC

LPC
R112 ICH_INTVRMEN B22 J3
332K_0402_1% INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1 2 1 2 R169 2 1 10K_0402_5% +3VS
J1 @ J2 @ E25 N7 EC_GA20
EC_GA20
2

10K_0603_5% 10K_0603_5% GLAN_CLK A20GATE H_A20M#

A20M# AJ27 H_A20M#
ICH_INTVRMEN C129 C136 C13
1U_0603_10V6K 1U_0603_10V6K LAN_RSTSYNC DPRSTP# R207 1 0_0402_5% H_DPRSTP#
DPRSTP# AJ25 2 H_DPRSTP#
1 2 1 2 F14 AE23 DPSLP# R210 1 2 0_0402_5% H_DPSLP#
LAN_RXD0 DPSLP# H_DPSLP#
G13 LAN_RXD1
D14 AJ26 FERR# 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR#

LAN / GLAN
R206 56_0402_5%
+3VS D13 AD22 H_PWRGOOD 2 1
LAN_TXD_0 CPUPWRGD H_PWRGOOD +1.05VS
D12 R230 56_0402_5%
LAN_TXD_1 H_IGNNE#
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE#
1

R214 PROJECT_ID2 B10 AE22 H_INIT# 2 1

GPIO56 INIT# H_INIT# +3VS
AG25 H_INTR R146 10K_0402_5%

CPU
INTR H_INTR
10K_0402_5% +1.5VS_PCIE_ICH 1 2 GLAN_COMP B28 L3 EC_KBRST#
GLAN_COMPI RCIN# EC_KBRST#
R129 24.9_0402_1% B27
2

HDA_BITCLK_ICH GLAN_COMPO H_NMI

HDA_BITCLK_MDC 1 2 NMI AF23 H_NMI
SATA_LED# R243 33_0402_5% AF6 AF24 H_SMI#
HDA_BIT_CLK SMI# H_SMI#
HDA_SYNC_MDC 1 2 HDA_SYNC_ICH AH4
C R250 33_0402_5% HDA_SYNC H_STPCLK# C
STPCLK# AH27 H_STPCLK#
1 2 HDA_RST_ICH# AE7
HDA_RST_MDC# HDA_RST#
R240 33_0402_5% AG26 THRMTRIP_ICH# R205 1 2 54.9_0402_1% H_THERMTRIP#
+3V THRMTRIP# H_THERMTRIP#
HDA_SDIN0 AF4 HDA_SDIN0
HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27 2 1 +1.05VS
HDA_SDIN2 AH3 R204 56_0402_5%
HDA_SDIN2
AE5

IHDA
HDA_SDIN3
1

AH11 SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_N4 +RTCBATT

@ R117 HDA_SDOUT_ICH SATA4RXN SATA_DTX_C_IRX_P4
HDA_SDOUT_MDC 1 2 AG5 HDA_SDOUT SATA4RXP AJ11 SATA_DTX_C_IRX_P4 17 HDD
R246 33_0402_5% AG12 SATA_ITX_DRX_N4
SATA4TXN

2
10K_0402_5% AG7 AF12 SATA_ITX_DRX_P4
HDA_DOCK_EN#/GPIO33 SATA4TXP R382
AE8
2

HDA_DOCK_RST#/GPIO34
1K_0402_5%
PROJECT_ID2 SATA_LED# SATA_LED# AG8 SATALED#
AH9

1 1
SATA_DTX_C_IRX_N0 SATA5RXN
SATA_DTX_C_IRX_N0 AJ16 SATA0RXN SATA5RXP AJ9
1

15 HDD SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 AH16 AE10 D19

R118 SATA_ITX_DRX_N0 SATA0RXP SATA5TXN
AF17 SATA0TXN SATA5TXP AF10
SATA_ITX_DRX_P0 AG17
10K_0402_5% SATA0TXP CLK_PCIE_SATA#
SATA_CLKN AH18 CLK_PCIE_SATA#

SATA
SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA +RTCVCC
CLK_PCIE_SATA
2

SATA_DTX_C_IRX_P1 SATA1RXN SATA_CLKP SATARBIAS

SATA_DTX_C_IRX_P1 AJ13 AJ7

2
SATA_ITX_DRX_N1 SATA1RXP SATARBIAS# R215 1
AG14 SATA1TXN SATARBIAS AH7 2 24.9_0402_1%
SATA_ITX_DRX_P1 AF14 BAS40-04_SOT23-3
SATA1TXP
+CHGRTC
1
ICH9-M ES_FCBGA676 C435

1 2 HDA_BITCLK_ICH 0.1U_0402_16V4Z
B HDA_BITCLK_AUDIO 2 B
R242 33_0402_5%
HDA_SYNC_AUDIO 1 2 HDA_SYNC_ICH
R251 33_0402_5% SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0
HDA_RST_ICH# C307 0.01U_0402_16V7K SATA_ITX_C_DRX_N0
HDA_RST_AUDIO# 1 2
R241 33_0402_5% SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0
HDA_SDOUT_ICH C306 0.01U_0402_16V7K SATA_ITX_C_DRX_P0
HDA_SDOUT_AUDIO 1 2
R247 33_0402_5%
15@
SATA_ITX_DRX_N1 1 2 SATA_ITX_C_DRX_N1_15
SATA_ITX_C_DRX_N1_15 MAINPWON
C397 0.01U_0402_16V7K 15 ODD
SATA_ITX_DRX_P1 1 2 SATA_ITX_C_DRX_P1_15
C398 0.01U_0402_16V7K SATA_ITX_C_DRX_P1_15 R203

1
15@ @ 330_0402_5% C
17@ +1.05VS 1 2 2 Q12
1 2 SATA_ITX_C_DRX_N1_17 B
C402 0.01U_0402_16V7K SATA_ITX_C_DRX_N1_17 E 2SC2411K_SOT23

3
1 2 SATA_ITX_C_DRX_P1_17 17 ODD @
C401 0.01U_0402_16V7K SATA_ITX_C_DRX_P1_17
17@ H_THERMTRIP#

SATA_ITX_DRX_N4 1 2 SATA_ITX_C_DRX_N4
C405 0.01U_0402_16V7K SATA_ITX_C_DRX_N4
SATA_ITX_DRX_P4 1 2 SATA_ITX_C_DRX_P4
C406 0.01U_0402_16V7K SATA_ITX_C_DRX_P4

A close Con. sdie A

+VCC_HDA_ICH
ICH_TP3

R92 Security Classification Compal Secret Data Compal Electronics, Inc.

R248 1K_0402_5% 2009/01/21 2010/01/21 Title
1K_0402_5%
Issued Date Deciphered Date
@
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
HDA_SDOUT_ICH Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 20 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS
Place closely pin B2 Place closely pin AC1
1 2 SERIRQ U11C
R151 10K_0402_5% ICH_SMBCLK ICH_SMBCLK G16 AH23 PROJECT_ID1 CLK_ICH_48M CLK_ICH_14M
PM_CLKRUN# ICH_SMBDATA SMBCLK SATA0GP/GPIO21 PROJECT_ID0
R147
1 2
8.2K_0402_5%
ICH_SMBDATA
LINKALERT#
A13 SMBDATA SMB SATA1GP/GPIO19 AF19
R234 1 2 10K_0402_5%

SATA
GPIO
E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21

1
1 2 EC_THERM# ICH_SMLINK0 C17 AD20
R209 8.2K_0402_5% ICH_SMLINK1 SMLINK0 SATA5GP/GPIO37 R252 R136
B18 SMLINK1
1 2 H_STP_PCI# H1 CLK_ICH_14M 10_0402_5% 10_0402_5%
CLK14 CLK_ICH_14M
R81 @ 10K_0402_5% EC_SWI# CLK_ICH_48M @ @
1 2 H_STP_CPU# EC_SWI# F19 RI# clocks CLK48 AF3 CLK_ICH_48M

2
R95 @ 10K_0402_5% PAD @ SUS_STAT# R4 P1 SUS_CLK PAD 1 1
T20 SUS_STAT#/LPCPD# SUSCLK T19
1 2 SB_SPKR XDP_DBRESET# G19 @ C308 C225
XDP_DBRESET# SYS_RESET#
R168 @ 1K_0402_5% C16 PM_SLP_S3# 10P_0402_50V8J 10P_0402_50V8J
D SLP_S3# PM_SLP_S3# D
PM_SYNC# M6 E16 PM_SLP_S4# @ @
PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S4# 2 2
G17 PM_SLP_S5#

SYS / GPIO
SLP_S5# PM_SLP_S5#
EC_LID_OUT# A17
EC_LID_OUT# SMBALERT#/GPIO11
C10 S4_STATE#
OCP# H_STP_PCI# S4_STATE#/GPIO26
1 2 H_STP_PCI# A14 STP_PCI#
R238 10K_0402_5% H_STP_CPU# E19 G20 ICH_PWROK
H_STP_CPU# STP_CPU# PWROK ICH_PWROK
PM_CLKRUN# L4 M2 DPRSLPVR 1 2

Power MGT
PM_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR
1 2 ICH_GPIO17 R150 0_0402_5%
R258 @ 10K_0402_5% ICH_PCIE_WAKE# E20 B13 PM_BATLOW#
ICH_PCIE_WAKE# WAKE# BATLOW#
1 2 ICH_GPIO18 SERIRQ M5
SERIRQ SERIRQ
R145 @ 10K_0402_5% EC_THERM# AJ23 R3 PBTN_OUT# ICH_PWROK 1 2
EC_THERM# THRM# PWRBTN# PBTN_OUT#
1 2 ICH_GPIO20 No used Integrated LAN, R88 10K_0402_5%
R213 @ 10K_0402_5% VGATE 2 1 ICH_VGATE D21 D20 LAN_RST# 1 2
VGATE VRMPWRGD LAN_RST# connecting LAN_RST# to GND
1 2 SATA_CLKREQ# R75 0_0402_5% R80 10K_0402_5%
R166 10K_0402_5% PAD @ ICH_TP11 A20 D22 SB_RSMRST# EC_PWROK 1 2
T3 TP11 RSMRST#
1 2 ICH_GPIO38 R76 10K_0402_5%
R257 @ 10K_0402_5% OCP# AG19 R5 CK_PWRGD
OCP# GPIO1 CK_PWRGD CK_PWRGD
1 2 ICH_GPIO39 CRT_DET AH21
R235 @ 10K_0402_5% GPIO6 ICH_PWROK
AG21 GPIO7 CLPWROK R6
1 2 ICH_GPIO48 EC_SMI# A21
EC_SMI# GPIO8 +3VS
R212 10K_0402_5% C12 B16 PM_SLP_M# PAD
EC_SCI# GPIO12 SLP_M# T7
CP_PE# C21 @
+3V CP_PE# GPIO13
ICH_GPIO17 AE18 F24
GPIO17 CL_CLK0 CL_CLK0

5
ICH_GPIO18 K1 B19 U7

GPIO
Controller Link
ICH_SMBCLK ICH_GPIO20 GPIO18 CL_CLK1 EC_PWROK
1 2 AF8 2

P
GPIO20 B EC_PWROK
R97 2.2K_0402_5% AJ22 F22 ICH_PWROK 4
+3V SCLOCK/GPIO22 CL_DATA0 CL_DATA0 Y
1 2 ICH_SMBDATA @ ICH_GPIO27 A9 C19 1 VGATE
T10 PAD GPIO27 CL_DATA1 A

G
R98 2.2K_0402_5% PAD @ ICH_GPIO28 D19
T5 GPIO28
1 2 EC_SWI# SATA_CLKREQ# L1 C25 CL_VREF0_ICH NC7SZ08P5X_NL_SC70-5
SATA_CLKREQ#

3
SATACLKREQ#/GPIO35 CL_VREF0
1

R256 10K_0402_5% ICH_GPIO38 AE19 A19 CL_VREF1_ICH

ICH_SMLINK0 R119 ICH_GPIO39 SLOAD/GPIO38 CL_VREF1
1 2 AG22 SDATAOUT0/GPIO39
C R93 10K_0402_5% 10K_0402_5% ICH_GPIO48 C
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0
1 2 ICH_SMLINK1 @ ICH_GPIO49 AH24 D18
R91 10K_0402_5% ICH_GPIO57 GPIO49 CL_RST1#
A8
2

LINKALERT# ICH_GPIO57 GPIO57/CLGPIO5 ICH_GPIO24 @ Q10

1 2 MEM_LED/GPIO24 A16 PAD T8 2 1 +3V
R79 10K_0402_5% SB_SPKR M7 C18 ICH_GPIO10 R99 100K_0402_5% MMBT3906_SOT23-3
SB_SPKR SPKR GPIO10/SUS_PWR_ACK
1

1 2 XDP_DBRESET# AJ24 C11 ICH_ACIN 2 1 SB_RSMRST# 1 3

C
MISC
MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ACIN EC_RSMRST#
R127 10K_0402_5% R121 B21 C20 ICH_GPIO9 @ D9

E
ICH_TP3 TP3 WOL_EN/GPIO9 PAD T4
1 2 ICH_PCIE_WAKE# 100K_0402_5%
T22 PAD @ ICH_TP8 AH20 TP8
CH751H-40PT_SOD323-2

1
R229 1K_0402_5% @ ICH_TP9 AJ20

B
T23 PAD

2
PM_BATLOW# @ ICH_TP10 TP9 R254
1 2 T21 PAD AJ21 1 2 +3V
2

R82 8.2K_0402_5% TP10 R227 4.7K_0402_5%

10K_0402_5%
1 2 EC_LID_OUT# ICH9-M ES_FCBGA676
R94 10K_0402_5% D14A

2
1 2 ICH_GPIO10 U11D 1
R78 10K_0402_5% PCIE_PTX_C_IRX_N1 N29 V27 DMI_MTX_IRX_N0 6
PCIE_PTX_C_IRX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0
1 2 CP_PE# PCIE_PTX_C_IRX_P1 N28 V26 DMI_MTX_IRX_P0 2
PCIE_PTX_C_IRX_P1 PERP1 DMI0RXP DMI_MTX_IRX_P0
R77 10K_0402_5% For Express Card PCIE_ITX_C_PRX_N1 C248 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N1 P27 U29 DMI_ITX_MRX_N0
PETN1 DMI0TXN DMI_ITX_MRX_N0
1 2 S4_STATE# C249 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P1 P26 U28 DMI_ITX_MRX_P0 BAV99DW-7_SOT363

Direct Media Interface

PCIE_ITX_C_PRX_P1 PETP1 DMI0TXP DMI_ITX_MRX_P0
R120 @ 10K_0402_5%
PCIE_PTX_C_IRX_N2 L29 Y27 DMI_MTX_IRX_N1 D14B
PCIE_PTX_C_IRX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1
1 2 PROJECT_ID0 PCIE_PTX_C_IRX_P2 L28 Y26 DMI_MTX_IRX_P1 4
PCIE_PTX_C_IRX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1
R237 17@ 10K_0402_5% For MINI_CARD1 PCIE_ITX_C_PRX_N2 C238 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N2 M27 W29 DMI_ITX_MRX_N1 3
PETN2 DMI1TXN DMI_ITX_MRX_N1
1 2 PCIE_ITX_C_PRX_P2 C239 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P2 M26 W28 DMI_ITX_MRX_P1 5
PETP2 DMI1TXP DMI_ITX_MRX_P1

1
R236 15@ 10K_0402_5%

PCI - Express
1 2 PROJECT_ID1 PCIE_PTX_C_IRX_N3 J29 AB27 DMI_MTX_IRX_N2 BAV99DW-7_SOT363 R228
PCIE_PTX_C_IRX_N3 PERN3 DMI2RXN DMI_MTX_IRX_N2
R232 10K_0402_5% PCIE_PTX_C_IRX_P3 J28 AB26 DMI_MTX_IRX_P2 2.2K_0402_5%
PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2
1 2 PM_DPRSLPVR For PCIE LAN PCIE_ITX_C_PRX_N3 C237 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 K27 AA29 DMI_ITX_MRX_N2
PETN3 DMI2TXN DMI_ITX_MRX_N2
R148 100K_0402_5% PCIE_ITX_C_PRX_P3 C220 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 K26 AA28 DMI_ITX_MRX_P2
DMI_ITX_MRX_P2

2
ICH_GPIO49 PETP3 DMI2TXP
1 2
R208 @ 1K_0402_5% G29 AD27 DMI_MTX_IRX_N3
PERN4 DMI3RXN DMI_MTX_IRX_N3
G28 AD26 DMI_MTX_IRX_P3
PD just for ES1 sample +3VS PERP4 DMI3RXP DMI_MTX_IRX_P3
H27 AC29 DMI_ITX_MRX_N3
B PETN4 DMI3TXN DMI_ITX_MRX_N3 B
H26 AC28 DMI_ITX_MRX_P3
PETP4 DMI3TXP DMI_ITX_MRX_P3 +3VS
2

E29 T26 CLK_PCIE_ICH#

PERN5 DMI_CLKN CLK_PCIE_ICH#
R211 E28 T25 CLK_PCIE_ICH
PERP5 DMI_CLKP CLK_PCIE_ICH
+3V 1 2 USB_OC#1 10K_0402_5% F27 PETN5
R149 10K_0402_5% High: CRT Plugged F26 AF29 R196 24.9_0402_1% Within 500 mils R110
PETP5 DMI_ZCOMP
1 2 USB_OC#4 AF28 DMI_IRCOMP 1 2 +1.5VS_PCIE_ICH 3.24K_0402_1%
1

R167 10K_0402_5% CRT_DET DMI_IRCOMP

C29 PERN6/GLAN_RXN
C28 AC5 USB20_N0
PERP6/GLAN_RXP USBP0N USB20_N0
1

D USB20_P0 CL_VREF0_ICH
RP33
D27 PETN6/GLAN_TXN USBP0P AC4 USB20_P0 MB USB Conn.
CRT_DET# 2 D26 PETP6/GLAN_TXP USBP1N AD3
1 8 USB_OC#5 Q11G AD2 SUB 1
USB_OC#9 2N7002_SOT23 USBP1P C191 R111
2 7 S D23 AC1
3

USB_OC#8 SPI_CLK USBP2N 453_0402_1%

3 6
USB_OC#11
D24 SPI_CS0# USBP2P AC2
USB20_N3
SUB 0.1U_0402_16V4Z
4 5 SPI_CS#1 F23 SPI_CS1#GPIO58/CLGPIO6 USBP3N AA5 USB20_N3
USB20_P3 2
10K_1206_8P4R_5% USBP3P AA4
USB20_N4
USB20_P3 CMOS Camera
D25 SPI_MOSI SPI USBP4N AB2
USB20_P4
USB20_N4
RP32
E23 SPI_MISO USBP4P AB3
USB20_N5
USB20_P4 Card-Reader
USBP5N AA1 USB20_N5
1 8 USB_OC#10 USB_OC#0 N4 AA2 USB20_P5 NEW CARD
USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 +3V
2 7 USB_OC#3 USB_OC#1 N5 W5 USB20_N6
OC1#/GPIO40 USBP6N USB20_N6
USB_OC#7 Project_ID0 Project_ID1 Project_ID2 USB_OC#2 USB20_P6
3
4
6
5 USB_OC#2 USB_OC#3
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3
USB20_P6 MB HS USB CONN
USB_OC#4 OC3#/GPIO42 USBP7N
M1 OC4#/GPIO43 USBP7P Y2
10K_1206_8P4R_5% KAWF0 0 0 0 USB_OC#5 N2 W1 USB20_N8 R115
OC5#/GPIO29 USBP8N USB20_N8
USB_OC#6 M4 W2 USB20_P8 Bluetooth 3.24K_0402_1%
USB_OC#6 OC6#/GPIO30 USBP8P USB20_P8
USB_OC#7 M3 V2
USB_OC#8 OC7#/GPIO31 USBP9N
KAWH0 1 0 0 N3 OC8#/GPIO44 USBP9P V3
USB_OC#9 N1 U5 USB20_N10 CL_VREF1_ICH
OC9#/GPIO45 USBP10N USB20_N10
USB_OC#10 P5 U4 USB20_P10 MINI CARD
OC10#/GPIO46 USBP10P USB20_P10
USB_OC#11 P3 U1 1
OC11#/GPIO47 USBP11N C193 R114
USBP11P U2
A USBRBIAS 453_0402_1% A
AG2
2 1 AG1
USBRBIAS
USBRBIAS#
No Reboot Strap 0.1U_0402_16V4Z
R197 2
22.6_0402_1%
Within 500 mils ICH9-M ES_FCBGA676 Low= Default*
SB_SPKR High= "No Reboot"

Internal TPM Strap DMI Termination Voltage Security Classification Compal Secret Data Compal Electronics, Inc.
Low= Disable* Low= Desktop used Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title
SPI_MOSI High= iTPM enable by MCH strap GPIO49 High= Mobile* (Internal pull-up) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401636 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 09, 2009 Sheet 21 of 45
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS U11F

+RTCVCC A23 A15 +1.05VS U11E
VCCRTC VCC1_05[01]
1 1 VCC1_05[02] B15 AA26 VSS[001] VSS[107] H5

2
C192 C162 +ICH_V5REF A6 C15 1 1 AA27 J23
R122 D10 V5REF VCC1_05[03] C171 C170 VSS[002] VSS[108]
VCC1_05[04] D15 AA3 VSS[003] VSS[109] J26
100_0402_5% CH751H-40PT_SOD323-2 0.1U_0402_16V4Z E15 AA6 J27
2 2 +ICH_V5REF_SUS VCC1_05[05] 0.1U_0402_16V4Z VSS[004] VSS[110]
AE1 V5REF_SUS VCC1_05[06] F15 AB1 VSS[005] VSS[111] AC22
1U_0402_6.3V4Z 2 2
L11 AA23 K28
1

1
+ICH_V5REF VCC1_05[07] 0.1U_0402_16V4Z VSS[006] VSS[112]
AA24 VCC1_5_B[01] VCC1_05[08] L12 AB28 VSS[007] VSS[113] K29
2 AA25 VCC1_5_B[02] VCC1_05[09] L14 AB29 VSS[008] VSS[114] L13
C175 AB24 L16 AB4 L15
VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
AB25 VCC1_5_B[04] VCC1_05[11] L17 AB5 VSS[010] VSS[116] L2
1U_0402_6.3V4Z +5VALW +5V +3V AC24 VCC1_5_B[05] VCC1_05[12] L18 AC17 VSS[011] VSS[117] L26
1 +1.5VS_DMIPLL_ICH
AC25 VCC1_5_B[06] VCC1_05[13] M11 AC26 VSS[012] VSS[118] L27
AD24 VCC1_5_B[07] VCC1_05[14] M18 AC27 VSS[013] VSS[119] L5

2
L8 1

CORE
D AD25 VCC1_5_B[08] VCC1_05[15] P11 2 +1.5VS AC3 VSS[014] VSS[120] L7 D
R194 R193 D13 AE25 P18 MBK1608301YZF_0603 AD1 M12
100_0402_5% VCC1_5_B[09] VCC1_05[16] VSS[015] VSS[121]
CH751H-40PT_SOD323-2 AE26 VCC1_5_B[10] VCC1_05[17] T11 1 (10UF*1, 0.01UF*1) AD10 VSS[016] VSS[122] M13
10_0402_5% AE27 T18 C260 AD12 M14
@ VCC1_5_B[11] VCC1_05[18] C258 VSS[017] VSS[123]
AE28 U11 AD13 M15
1

1
+ICH_V5REF_SUS VCC1_5_B[12] VCC1_05[19] VSS[018] VSS[124]
AE29 VCC1_5_B[13] VCC1_05[20] U18 10U_0805_10V4Z AD14 VSS[019] VSS[125] M16
2
2 F25 VCC1_5_B[14] VCC1_05[21] V11 AD17 VSS[020] VSS[126] M17
C276 G25 V12 0.01U_0402_16V7K AD18 M23
VCC1_5_B[15] VCC1_05[22] VSS[021] VSS[127]
H24 VCC1_5_B[16] VCC1_05[23] V14 AD21 VSS[022] VSS[128] M28
1U_0402_6.3V4Z H25 V16 AD28 M29
1 VCC1_5_B[17] VCC1_05[24] VSS[023] VSS[129]
J24 VCC1_5_B[18] VCC1_05[25] V17 +1.05VS AD29 VSS[024] VSS[130] N11

VCCA3GP
J25 VCC1_5_B[19] VCC1_05[26] V18 AD4 VSS[025] VSS[131] N12
K24 VCC1_5_B[20] 1 (4.7UF*1) AD5 VSS[026] VSS[132] N13
K25 C167 AD6 N14
VCC1_5_B[21] VSS[027] VSS[133]
L23 VCC1_5_B[22] AD7 VSS[028] VSS[134] N15
+1.5VS_PCIE_ICH L24 R29 4.7U_0805_10V4Z AD9 N16
VCC1_5_B[23] VCCDMIPLL 2 VSS[029] VSS[135]
(220UF*1, 22UF*2, 2.2UF*1) L25 VCC1_5_B[24] AE12 VSS[030] VSS[136] N17
+1.5VS L9 2 1 M24 W23 AE13 N18
FBMA-L11-201209-221LMA30T_0805 VCC1_5_B[25] VCC_DMI[1] VSS[031] VSS[137]
1 M25 VCC1_5_B[26] VCC_DMI[2] Y23 AE14 VSS[032] VSS[138] N26
1 1 N23 VCC1_5_B[27] AE16 VSS[033] VSS[139] N27
C280 + C268 C275 C259 N24 AB23 AE17 P12
VCC1_5_B[28] V_CPU_IO[1] +1.05VS VSS[034] VSS[140]
N25 VCC1_5_B[29] V_CPU_IO[2] AC23 1 1 AE2 VSS[035] VSS[141] P13
220U_D2_4VM_R15 10U_0805_10V4Z P24 C137 C169 C168 (4.7UF*1, 0.1UF*2) AE20 P14
2 2 2 VCC1_5_B[30] VSS[036] VSS[142]
P25 VCC1_5_B[31] VCC3_3[01] AG29 AE24 VSS[037] VSS[143] P15
10U_0805_10V4Z 2.2U_0603_6.3V6K R24 AJ6 4.7U_0805_10V4Z 0.1U_0402_16V4Z AE3 P16
VCC1_5_B[32] VCC3_3[02] 2 2 VSS[038] VSS[144]
R25 VCC1_5_B[33] VCC3_3[07] AC10 AE4 VSS[039] VSS[145] P17
R26 0.1U_0402_16V4Z AE6 P2
VCC1_5_B[34] VSS[040] VSS[146]
R27 VCC1_5_B[35] VCC3_3[03] AD19 AE9 VSS[041] VSS[147] P23

VCCP_CORE
T24 VCC1_5_B[36] VCC3_3[04] AF20 AF13 VSS[042] VSS[148] P28
T27 VCC1_5_B[37] VCC3_3[05] AG24 close to AG29 close to AD19 close to G6 AF16 VSS[043] VSS[149] P29
T28 VCC1_5_B[38] VCC3_3[06] AC20 AF18 VSS[044] VSS[150] P4
T29 VCC1_5_B[39] +3VS AF22 VSS[045] VSS[151] P7
+1.5VS_SATAPLL_ICH U24 AH26 R11
C VCC1_5_B[40] VSS[046] VSS[152] C
U25 VCC1_5_B[41] VCC3_3[08] B9 1 1 1 1 1 1 AF26 VSS[047] VSS[153] R12
+1.5VS L11 1 2 V24 F9 C281 C300 C294 C223 C224 C173 AF27 R13
MBK1608301YZF_0603 VCC1_5_B[42] VCC3_3[09] VSS[048] VSS[154]
V25 VCC1_5_B[43] VCC3_3[10] G3 AF5 VSS[049] VSS[155] R14
1 1 U23 G6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AF7 R15
VCC1_5_B[44] VCC3_3[11] 2 2 2 2 2 2 VSS[050] VSS[156]

PCI
C295 W24 J2 AF9 R16
C296 VCC1_5_B[45] VCC3_3[12] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[051] VSS[157]
W25 VCC1_5_B[46] VCC3_3[13] J7 AG13 VSS[052] VSS[158] R17
10U_0805_10V4Z K23 VCC1_5_B[47] VCC3_3[14] K7 AG16 VSS[053] VSS[159] R18
2 1U_0402_6.3V4Z
2
(10UF*1, 1UF*1) Y24 VCC1_5_B[48] close to AJ6 close to B9 close to K7 AG18 VSS[054] VSS[160] R28
Y25 VCC1_5_B[49] AG20 VSS[055] VSS[161] T12
AJ4 +VCC_HDA_ICH AG23 T13
VCCHDA VSS[056] VSS[162]
AG3 VSS[057] VSS[163] T14
AJ3 @ +1.5VS AG6 T15
+5VALW VCCSUSHDA R216 0_0603_5% VSS[058] VSS[164]
AJ19 VCCSATAPLL 1 AG9 VSS[059] VSS[165] T16
C302 +3VS AH12 T17
VSS[060] VSS[166]
VCCSUS1_05[1] AC8 TP_VCCSUS1_05_ICH_1 @ PAD T24
R217 0_0603_5% AH14 VSS[061] VSS[167] T23
+1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 TP_VCCSUS1_05_ICH_2 @ PAD T6
0.1U_0402_16V4Z AH17 VSS[062] VSS[168] B26
3

S
2
G AD15 VCC1_5_A[02] AH19 VSS[063] VSS[169] U12
SBPWR_EN# 2 1 1 AD16 VCC1_5_A[03] AH2 VSS[064] VSS[170] U13
C298 C299 AE15 AD8 TP_VCCSUS1_5_ICH_1 @ +VCCSUS_HDA_ICH AH22 U14
VCC1_5_A[04] VCCSUS1_5[1] PAD T25 VSS[065] VSS[171]
ARX

1 Q8 D AF15 AH25 U15

1

C277 AO3413_SOT23-3 1U_0402_6.3V4Z VCC1_5_A[05] +VCCSUS1_5_ICH_INT_2 @ VSS[066] VSS[172]

AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 +1.5V AH28 VSS[067] VSS[173] U16
2 2 R219 0_0603_5%
AH15 VCC1_5_A[07] 1 AH5 VSS[068] VSS[174] U17
0.1U_0402_16V4Z AJ15 C165 1 +3V AH8 AD23
2 +5V VCC1_5_A[08] C303 R218 0_0603_5% VSS[069] VSS[175]
VCCSUS3_3[01] A18 AJ12 VSS[070] VSS[176] U26
1U_0402_6.3V4Z AC11 D16 0.1U_0402_16V4Z AJ14 U27
VCCPSUS

VCC1_5_A[09] VCCSUS3_3[02] 2 0.1U_0402_16V4Z VSS[071] VSS[177]

AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ17 VSS[072] VSS[178] U3
2
AE11 VCC1_5_A[11] VCCSUS3_3[04] E22 AJ8 VSS[073] VSS[179] V1
AF11 VCC1_5_A[12] B11 VSS[074] VSS[180] V13
ATX

AG10 VCC1_5_A[13] B14 VSS[075] VSS[181] V15

AG11 VCC1_5_A[14] B17 VSS[076] VSS[182] V23
AH10 VCC1_5_A[15] B2 VSS[077] VSS[183] V28
AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 +3V B20 VSS[078] VSS[184] V29
B B23 VSS[079] VSS[185] V4 B
AC9 VCC1_5_A[17] 1 1 B5 VSS[080] VSS[186] V5
C166 C261 C262 B8 W26
VSS[081] VSS[187]
AC18 VCC1_5_A[18] C26 VSS[082] VSS[188] W27
AC19 0.022U_0402_16V7K 0.1U_0402_16V4Z (0.1UF*1, 0.022UF*2) C27 W3
VCC1_5_A[19] 2 2 VSS[083] VSS[189]
VCCSUS3_3[06] T1 E11 VSS[084] VSS[190] Y1
AC21 T2 0.022U_0402_16V7K E14 Y28
VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
VCCSUS3_3[08] T3 E18 VSS[086] VSS[192] Y29
G10 VCC1_5_A[21] VCCSUS3_3[09] T4 E2 VSS[087] VSS[193] Y4
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 close to A18 close to T1 E21 VSS[088] VSS[194] Y5
VCCSUS3_3[11] T6 E24 VSS[089] VSS[195] AG28
AC12 U6 E5 AH6
VCCPUSB

VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]

AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 E8 VSS[091] VSS[197] AF2
close to AC7 AC14 VCC1_5_A[25] VCCSUS3_3[14] V6 F16 VSS[092] VSS[198] B25
VCCSUS3_3[15] V7 F28 VSS[093]
+1.5VS AJ5 VCCUSBPLL VCCSUS3_3[16] W6 F29 VSS[094]
1 1 VCCSUS3_3[17] W7 G12 VSS[095]
USB CORE

C301 C297 AA7 Y6 G14 A1

VCC1_5_A[26] VCCSUS3_3[18] VSS[096] VSS_NCTF[01]
close to AJ5 AB6 VCC1_5_A[27] VCCSUS3_3[19] Y7 G18 VSS[097] VSS_NCTF[02] A2
0.1U_0402_16V4Z AB7 T7 G21 A28
2 2 VCC1_5_A[28] VCCSUS3_3[20] VSS[098] VSS_NCTF[03]
AC6 VCC1_5_A[29] G24 VSS[099] VSS_NCTF[04] A29
0.1U_0402_16V4Z AC7 G26 AH1
VCC1_5_A[30] VSS[100] VSS_NCTF[05]
G27 VSS[101] VSS_NCTF[06] AH29
2 1 +VCCLAN1_05_INT_ICH A10 VCCLAN1_05[1] G8 VSS[102] VSS_NCTF[07] AJ1
C174 A11 G22 +VCCCL1_05_INT_ICH H2 AJ2
0.1U_0402_16V4Z VCCLAN1_05[2] VCCCL1_05 +VCCCL1_5_INT_ICH VSS[103] VSS_NCTF[08]
VCCCL1_5 G23 H23 VSS[104] VSS_NCTF[09] AJ28
+3VS +VCCLAN_ICH A12 H28 AJ29
R116 0_0603_5% VCCLAN3_3[1] VSS[105] VSS_NCTF[10]
1 B12 VCCLAN3_3[2] 1 1 1 H29 VSS[106] VSS_NCTF[11] B1
C172 A24 +3VS C222 C221 C208 B29
VCCCL3_3[1] @ @ VSS_NCTF[12]
VCCCL3_3[2] B24 (0.1UF*1)
GLAN POWER

+1.5VS +VCC_GLANPLL_ICH A27 1U_0402_6.3V4Z

2 R87 0_0603_5% VCCGLANPLL 2 2 2 ICH9-M ES_FCBGA676
1
0.1U_0402_16V4Z C161 D28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A
C160 VCCGLAN1_5[1] A
D29 VCCGLAN1_5[2]
(10UF*1, 2.2UF*1)10U_0805_10V4Z
2
E26 VCCGLAN1_5[3]
E27 VCCGLAN1_5[4] (1UF*1, 0.1UF*1)
2.2U_0603_6.3V6K
A26 VCCGLAN3_3
+1.5VS +VCCGLAN_ICH
R128 0_0603_5% ICH9-M ES_FCBGA676
C207
(4.7UF*1)
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
4.7U_0805_10V4Z 2009/01/21 2010/01/21 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1
C497 C498 C499 C502 C501 C500

2 2 2 2 2 2

1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 10U_0805_10V4Z

SATA_DTX_C_IRX_N4 1 2 SATA_DTX_IRX_N4
D
SATA HDD Conn. SATA_DTX_C_IRX_N4
C404 0.01U_0402_16V7K
D

JSATA2 SATA_DTX_C_IRX_P4 SATA_DTX_C_IRX_P4 1 2 SATA_DTX_IRX_P4

C403 0.01U_0402_16V7K
1 GND
SATA_ITX_C_DRX_P0 2
SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 HTX+
SATA_ITX_C_DRX_N0 3 HTX-
4 GND
SATA_DTX_IRX_N0 5
SATA_DTX_IRX_P0 HRX-
6 HRX+
7 GND

+3VS 8 VCC3.3
9 VCC3.3
10 VCC3.3
11 GND
SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 1 2 SATA_DTX_IRX_N0 12
C504 0.01U_0402_16V7K GND
13 GND
+5VS 14 VCC5
SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 1 2 SATA_DTX_IRX_P0 15
C503 0.01U_0402_16V7K VCC5
16 VCC5
17 JP2
GND
18 RESERVED 1 1 2 2 +5VS
19 SATA_ITX_C_DRX_P4 3 4
GND SATA_ITX_C_DRX_P4 SATA_ITX_C_DRX_N4 3 4
20 VCC12 SATA_ITX_C_DRX_N4 5 5 6 6
21 VCC12 GND 24 7 7 8 8
C 22 23 SATA_DTX_IRX_N4 9 10 C
VCC12 GND SATA_DTX_IRX_P4 9 10
11 11 12 12
13 13 14 14
OCTEK_SAT-22SU1G_NR SATA_ITX_C_DRX_P1_17 15 16
SATA_ITX_C_DRX_P1_17 15 16 +3VS
CONN@ SATA_ITX_C_DRX_N1_17 17 18
SATA_ITX_C_DRX_N1_17 17 18
19 19 20 20
SATA_DTX_IRX_N1_17 21 22
SATA_DTX_IRX_P1_17 21 22
23 23 24 24
25 25 26 26
27 28
SATA ODD Conn. 29
27 28
30

GND
GND
GND
GND
GND
GND
29 30

+5VS JSATA1 ACES_88018-304G

31
32
33
34
35
36
0.1U_0402_16V4Z 1 CONN@
SATA_ITX_C_DRX_P1_15 GND
1 SATA_ITX_C_DRX_P1_15 2 A+
1 1 1 SATA_ITX_C_DRX_N1_15 3
+ C570 C393 C394 C392 SATA_ITX_C_DRX_N1_15 A-
4 GND
SATA_DTX_IRX_N1_15 5
150U_B2_6.3VM_R45M SATA_DTX_IRX_P1_15 B-
6 B+
2 2 2 2 +5VS +3VS
7 GND
1000P_0402_50V7K 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R347 1 @ 2 1K_0402_1% 8 DP
+5VS 9 +5V 1 1 1 1 1 1 1
10 C338 C339 C337 C496 C322 C329 C328
+5V @ @ @ @ @ @ @
11 MD
12 GND GND 15
B 2 2 2 2 2 2 2 B
13 GND GND 14
1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 10U_0805_10V4Z
SANTA_206401-1_13P
15@ CONN@
SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1_15
C396 0.01U_0402_16V7K
15@
SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 1 2 SATA_DTX_IRX_P1_15
C395 0.01U_0402_16V7K
17@
1 2 SATA_DTX_IRX_N1_17
C400 0.01U_0402_16V7K
17@
1 2 SATA_DTX_IRX_P1_17
C399 0.01U_0402_16V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 23 of 45
5 4 3 2 1
 5 4 3 2 1

2 1
R316 0_0402_5%

U14

2 1 1 AV_PLL
C359 0.1U_0402_16V4Z 3 NC
40~60 mil +XDPWR_SDPWR_MSPWR
7
9
NC
CARD_3V3
+3VS 1 2 11 D3V3
R468 0_0603_5% 33 10 +REG18 1 2
D3V3 VREG
+3VALW 1 2 1 1 C349 MS_D4 22 C341 1U_0402_6.3V4Z
+3VS R469 @ 0_0603_5% C350 0.1U_0402_16V4Z 30
@ NC
D 8 3V3_IN
D
RST# 44 RST#

2
4.7U_0603_6.3V6K 2 2 MODE_SEL 45
XTLO MODE_SEL XDCLE
47 XTLO XD_CLE_SP19 43
@ R333 XTLI 48 42 XDCE#
100K_0402_5% XTLI XD_CE#_SP18 XDALE
XD_ALE_SP17 41
USB20_N4 4 40 SDDAT2_XDRE#
USB20_N4

1
USB20_P4 DM SD_DAT2/XD_RE#_SP16 SDDAT3_XDWE#
USB20_P4 5 DP SD_DAT3/XD_WE#_SP15 39
14 38 XD_RDY
5IN1_LED# GPIO0 XD_RDY_SP14
RST# SDDAT4_XDWP#_MSD7
Vender suggesttion 1
R334
2
0_0402_5% SD_DAT4/XD_WP#/MS_D7_SP13 37
35 SDDAT5_XDD0_MSD6
1 SD_DAT5/XD_D0/MS_D6_SP12
34 SDCLK_XDD1_MSCLK_L 2 1 SDCLK_XDD1_MSCLK
C377 SD_CLK/XD_D1/MS_CLK_SP11 SDDAT6_XDD7_MSD3 R317 0_0402_5%
SD_DAT6/XD_D7/MS_D3_SP10 31
1U_0402_6.3V4Z 29 MS_INS#
2 MS_INS#_SP9 SDDAT7_XDD2_MSD2
SD_DAT7/XD_D2/MS_D2_SP8 28
27 SDDAT0_XDD6_MSD0
SD_DAT0/XD_D6/MS_D0_SP7 SDDAT1_XDD3_MSD1
SD_DAT1/XD_D3/MS_D1_SP6 26
25 XDD5_MSBS
XD_D5_SP5 XDD4_SDDAT1
XD_D4/SD_DAT1_SP4 23
21 SDCD
MODE_SEL SD_CD#_SP3 SDWP
SD_WP_SP2 20
19 XDCD
XD_CD#_SP1
EEDI 18

1
1
R332 2 1 2 13 XTAL_CTR 2 1 +3VS
@ C376 0_0402_5% R315 6.19K_0402_1% RREF XTAL_CTR R277 0_0603_5%
MS_D5 24
47P_0402_50V8J 12
2 DGND
32 15

2
DGND EEDO
EECS 16
6 AGND EESK 17
46 36 SD_CMD
AGND SD_CMD

2
CLK_SD_48M 1 2
R330 0_0402_5% RTS5159E-GR_LQFP48_7X7
C C
R331
@ 0_0603_5%

1
1 2 XTLI
C374 6P_0402_50V8D
1

R329
@ 33_0402_5%

1
@ Y3
2

1 12MHZ_16PF_6X12000012

2
@ C373 +CARDPWR
22P_0402_50V8J
2 @
1 2 XTLO
C375 6P_0402_50V8D 1 1 1
EMI C476 C342 C480
0.1U_0402_16V4Z
@ 2 2 2

10U_0805_10V4Z 0.1U_0402_16V4Z

+XDPWR_SDPWR_MSPWR

+CARDPWR
JREAD1
1 2 +CARDPWR +CARDPWR 3 21
R318 0_0603_5% XD-VCC SD-VCC
MS-VCC 28
B SDDAT5_XDD0_MSD6 32 B
SDCLK_XDD1_MSCLK XD-D0 SDCLK_XDD1_MSCLK
10 XD-D1 7 IN 1 CONN SD_CLK 20
2

1 SDDAT7_XDD2_MSD2 9 14 SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1 XD-D2 SD-DAT0 XDD4_SDDAT1
8 XD-D3 SD-DAT1 12
R294 C348 XDD4_SDDAT1 7 30 SDDAT2_XDRE#
100K_0402_5% 0.1U_0402_16V4Z XDD5_MSBS XD-D4 SD-DAT2 SDDAT3_XDWE#
6 XD-D5 SD-DAT3 29
2 SDDAT0_XDD6_MSD0 SDDAT4_XDWP#_MSD7
5 27
1

SDDAT6_XDD7_MSD3 XD-D6 SD-DAT4 SDDAT5_XDD0_MSD6

4 XD-D7 SD-DAT5 23
18 SDDAT6_XDD7_MSD3
SDDAT3_XDWE# SD-DAT6 SDDAT7_XDD2_MSD2
34 XD-WE SD-DAT7 16
SDDAT4_XDWP#_MSD7 33 25 SD_CMD
XDALE XD-WP SD-CMD SDCD
35 XD-ALE SD-CD-SW 1
XDCD 40 SDCLK_XDD1_MSCLK
XD_RDY XD-CD SDWP
39 XD-R/B SD-WP-SW 2 1
SDDAT2_XDRE# 38
XDCE# XD-RE C477
37 XD-CE
XDCLE 36 26 SDCLK_XDD1_MSCLK @ 22P_0402_50V8J
XD-CLE MS-SCLK SDDAT0_XDD6_MSD0 2
MS-DATA0 17
11 15 SDDAT1_XDD3_MSD1
7IN1 GND MS-DATA1 SDDAT7_XDD2_MSD2
31 7IN1 GND MS-DATA2 19
24 SDDAT6_XDD7_MSD3
MS-DATA3 MS_INS#
MS-INS 22
13 XDD5_MSBS
MS-BS
41 7IN1 GND
42 7IN1 GND
TAITW_R015-B10-LM
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401636 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 09, 2009 Sheet 24 of 45
5 4 3 2 1
 A B C D E

Layout Notice : Place as close

+3V_LAN +3V_LAN chip as possible.
+3V_LAN

0.1U_0402_16V4Z
1 2 +1.8_VDD/LX 1 2
+3VALW

1
R48 8114@ 0_0603_5% 1 R44 0_1206_5%

C11
R18 1 1 1
1 2 4.7K_0402_1% C87 C72 C86 C85

1
L5 8132@ 2

2
4.7UH_1008HC-472EJFS-A_5%_1008 R21 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4 U1 4.7K_0402_1% 2 2 2 4
1 8 4.7U_0805_10V4Z 0.1U_0402_16V4Z
+AVDD_CEN 1 +AVDD_CEN_C1 R45 +2.5V_VDDH/VDD17 +2.5V_VDDH A0 VCC
+AVDD_CEN 2 2 1 2 2 7

2
R49 8132@ 0_0603_5% R46 8114@ 0_0603_5% A1 WP TWSI_SCL
1 3 A2 SCL 6
0_0603_5% 4 5 TWSI_SDA
C99 C100 GND SDA
4.7U_0805_10V4Z 0.1U_0402_16V4Z AT24C02BN-SH-T_SO8
8132@ 2 8132@ 8114@

+1.2_AVDDL
L2 FBMA-L11-201209-221LMA30T_0805
1 2 +1.2_DVDDL
8114@

60mil U2

2 1 +1.8_VDD/LX 1 29 TWSI_SCL R39 0_0603_5%

C84 8114@ 1U_0603_10V4Z VDD18O TWSI_CLK TWSI_SDA AVDDVCO1
TWSI_DATA 30 1 2 1 2
8114@ +3V_LAN 2 R28 1@ 1
VDD33 LAN_ACTIVITY# 0_0603_5% C67
LED_ACTn 47 LAN_ACTIVITY#
2 1 +2.5V_VDDH/VDD17 6 48 LAN_LINK# 1000P_0402_50V7K C80
VDDHO LED_10_100n LAN_LINK#
C83 1U_0603_10V4Z 1U_0603_10V4Z 8114@
LAN_CLKREQ# 2 2
2 1 CTR12 5 27
C70 0.1U_0402_16V7K CTR12 LED_DUPLEXn R35 49.9_0402_1%C64 0.1U_0402_16V4Z
8132@ 3 13 LAN_MIDI0+ 2 1 1 2
PLT_RST# PERSTn TRXP0
EC_PME# 4 14 LAN_MIDI0- 2 1
WAKEn TRXN0 LAN_MIDI1+ R34 49.9_0402_1%
TRXP1 17
LAN_MIDI1- 2 R33 49.9_0402_1% L1 FBMA-L11-201209-221LMA30T_0805
+3V_LAN
R37
1 2
4.7K_0402_5%
2
8114@ C69
1
1000P_0402_50V7K
7 VBG1P18V TRXN1 18
2
1
1 1 2
Place Close to Chip 1 2 AVDDVCO2
CLK_PCIE_LAN 2 1 CLK_PCIE_LAN_C 41 11 AVDDVCO1 1
3 C57 0.1U_0402_16V7K REFCLKP AVDDL_REG AVDDVCO2 R27 49.9_0402_1% C55 0.1U_0402_16V4Z 3
AVDDL/AVDDL_REG 42
CLK_PCIE_LAN# 2 1 CLK_PCIE_LAN#_C 40 C59
REFCLKN

A
t
h
e
r
o
s
C56 0.1U_0402_16V7K 0.1U_0402_16V4Z
2
PCIE_ITX_C_PRX_P3 43 RX_P
28 +1.2_DVDDL
DVDDL0 If overclocking, R39, L1 stuffed and R28 removed.
PCIE_ITX_C_PRX_N3 44 RX_N DVDDL1 32
DVDDL2 45 If not overclocking, R28, L1 stuffed and R39 removed.
PCIE_PTX_C_IRX_P3 2 1 PCIE_PTX_IRX_P3 38 AR8132L 10/100 LAN 46
C20 0.1U_0402_16V7K TX_P DVDDL3
AR8132:
PCIE_PTX_C_IRX_N3 2 1 PCIE_PTX_IRX_N3 37 8 +1.2_AVDDL L1=0ohm(SD002000080),C67=0.1uF(SE070104Z80). remove C80
C19 0.1U_0402_16V7K TX_N AVDDL0
AVDDL1 16
Place Close to Chip LAN_X1 9
AVDDL2 22
36
LAN_X2 XTLO AVDDL3
10 XTLI AVDDL4 39

31 15 +2.5V_VDDH
SMCLK AVDDH0
33 SMDATA AVDDH1 19
AVDDH2 25 Place Close to Pin 28、32、45、46
20 C17 C16
RBIAS NC_0 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 1 12 RBIAS NC_1 21
R36 2.37K_0402_1% 34 23 +1.2_DVDDL
TESTMODE NC_2
NC_3 24 1 1 1 1 1
NC_4 26
49 35 C74
GND NC_5 0.1U_0402_16V4Z
Y1 2 2 2 2 2
C73
LAN_X1 1 2 LAN_X2 AR8132L-AL1E_QFN48_6X6 8132@ 8114@
1U_0603_10V4Z C58
0.1U_0402_16V4Z
1 25MHZ_20P 1
2 C82 C81 2
27P_0402_50V8J 27P_0402_50V8J
2 2
Place Close to Pin15、19、25
C65
LAN_MIDI0+ LAN_MIDI0+ 0.1U_0402_16V4Z
LAN_MIDI0- LAN_MIDI0- +2.5V_VDDH
1 1 1
LAN_MIDI1+ LAN_MIDI1+ C66
LAN_MIDI1- LAN_MIDI1- 0.1U_0402_16V4Z

C15 2 2 2
1U_0603_10V4Z

+3V_LAN

1
1

8132@
C521 R38 1 2 +2.5V_VDDH
Place Close to Pin8、16、22、36、39
0.1U_0402_16V4Z 10K_0402_1% R432 0_0402_5%
3

8114@ 2 Q39 8114@

C63 C54
2

1 CTR12 +1.2_AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
1 1 1 1 1 1
MMJT9435T1G_SOT223 C71 C60 C18
4
2

8114@ 0.1U_0402_16V4Z 8132@ 0.1U_0402_16V4Z

+1.2_AVDDL 2 8132@ 1U_0603_10V4Z
1 2 2 2 2 2 2 1
1 1
C516 C520 C68
10U_0805_10V4Z 0.1U_0402_16V4Z 8114@ C61
8114@ 8114@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401636 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 09, 2009 Sheet 25 of 45
A B C D E
 5 4 3 2 1

D D
+AVDD_CEN

2
R7
0_0603_5% 10/100 : TL8515C_LF
GBE : GSL5009-1

1
T1 JRJ45
LAN_ACTIVITY# 2 1 LAN_ACTIVITY#_1 12
LAN_MIDI0+ RJ45_MIDI0+ LAN_ACTIVITY# R11 510_0402_5% Amber LED+
LAN_MIDI0+ 1 RD+ RX+ 16

2
LAN_MIDI0- LAN_MIDI0- 2 15 RJ45_MIDI0- 2 11
RD- RX- R8 Amber LED-
3 CT CT 14 SHLD2 16
4 13 5.1K_0402_5% C4 8 Guide Pin
NC NC PR4-
5 NC NC 12 220P_0402_50V7K SHLD1 15
1
6 11 7

1
LAN_MIDI1+ CT CT RJ45_MIDI1+ PR4+
LAN_MIDI1+ 7 TD+ TX+ 10
LAN_MIDI1- LAN_MIDI1- 8 9 RJ45_MIDI1- RJ45_MIDI1- 6
TD- TX- PR2-
5 PR3-
Pulse H0013
4 PR3+
RJ45_MIDI1+ 3 PR2+
RJ45_MIDI0- 2
C
PR1- C
SHLD2 14

1
RJ45_MIDI0+ 1 PR1+
SHLD1 13
R3 R4 LAN_LINK# 10
75_0402_1% 75_0402_1% LAN_LINK# Green LED-
LAN_TCT 2 1 9
+3V_LAN

2
R10 510_0402_5% Green LED+
FOX_JM36113-L2R8-7F
1 1 CONN@
C2 C3 1 2

40mil C9
2 2 RJ45_GND 220P_0402_50V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z

RJ45_GND 1 2 LANGND 40mil

1 1
Place close to TCT pin C8
1000P_1206_2KV7K C556 C555
4.7U_0805_10V4Z
2 2

0.1U_0402_16V4Z

B B

LAN_ACTIVITY#_1

LAN_LINK#
LAN_ACTIVITY#_1 1 2

3
C10
68P_0402_50V8J
@ D29
@
LAN_LINK# 1 2 PJDLC05_SOT23
C7

1
68P_0402_50V8J
@

For EMI

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 26 of 45
5 4 3 2 1
 A B C D E

Mini Card Power Rating

For Wireless LAN
Power Primary Power (mA) Auxiliary Power (mA)
+3VS_WLAN +1.5VS Peak Normal Normal
+3VS 1000 750
+3VS_WLAN R378 1 2 0_1206_5% +3VS 1 1 1 1 1 1 +3V 330 250 250 (wake enable)
C432 C431 C425 C428 C426 C427
R370 1 @ 2 0_1206_5% +3V +1.5VS 500 375 5 (Not wake enable)
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 2 2 2 2 2 1

JMINI2
R381 1 @ 2 0_0402_5% 1 (WAKE#) 2 +3VS_WLAN
ICH_PCIE_WAKE# 1 2
WLAN_BT_DATA 3 4
WLAN_BT_DATA 3 4
WLAN_BT_CLK 5 6 +1.5VS
WLAN_BT_CLK 5 6
MINI2_CLKREQ# 7 7 8 8
9 9 10 10
CLK_PCIE_MINI2# 11 11 12 12
CLK_PCIE_MINI2 13 13 14 14
15 15 16 16

17 17 18 18
19 20 WL_OFF#
19 20 WL_OFF#
21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF#
23 24 +3V_WLAN R373 1 2 0_0603_5% +3VS
PCIE_PTX_C_IRX_N2 23 24
25 26 R374 1 @ 2 0_0603_5% +3V
PCIE_PTX_C_IRX_P2 25 26
27 27 28 28
29 30 MINI_SMBCLK R372 1 @ 2 0_0402_5% ICH_SMBCLK
29 30 ICH_SMBCLK
PCIE_ITX_C_PRX_N2 31 32 MINI_SMBDATA R357 1 @ 2 0_0402_5% ICH_SMBDATA
31 32 ICH_SMBDATA
PCIE_ITX_C_PRX_P2 33 33 34 34
35 35 36 36 USB20_N10
37 37 38 38 USB20_P10
+3VS_WLAN 39 39 40 40
41 42 (LED_WWAN#)
41 42
43 44 (LED_WLAN#) MINI1_LED#
43 44
For MINICARD Port80 Debug 45 45 46 46

E51TXD_P80DATA R377 1 2 0_0402_5% E51TXD_P80DATA_R

47
49
47 48 48
50
(9~16mA)
E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52
2 E51RXD_P80CLK 51 52 2

G1
G2
G3
G3
FOX_AS0B226-S99N-7F

53
54
55
56
CONN@

H1 H14 H19 H26 H25 H24 H23 H17

H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4

@ @ @ @ @ @ @ @

1
H7 H9 H4 H18 H16
H_3P4 H_3P4 H_3P4 H_3P4 H_4P2

@ @ @ @ @

1
H11 H10 H20 H6
H_4P2 H_4P2 H_3P4 H_2P8

@ @ @ @

1
3 3

H5 H8 H2 H3 H12 H22 H27

H_2P8 H_4P0N H_3P3 H_3P3 H_3P3 H_3P3 H_2P8

@ @ @ @ @ @ @

1
H15 H21
H_4P2 H_4P6X4P0N

@ @

1
FD1 FD4 FD3 FD2

@ @ @ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 27 of 45
A B C D E
 A B C D E

New Card Power Switch

New Card Socket (Left/TOP)
U17 +3VALW_CARD +3VS_CARD +1.5VS_CARD
40mil JEXP1
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD Imax = 0.275A Imax = 1.35A Imax = 0.75A
14 1.5Vin 1.5Vout 13
1 GND
60mils C334
1 1
C327 C335
1 1
C336 C321
1 1
C326
USB20_N5 2 USB_D-
+3VS 2 3.3Vin 3.3Vout 3 +3VS_CARD USB20_P5 3 USB_D+
1 NC@ NC@ NC@ NC@ NC@ NC@ CP_USB# 1
4 3.3Vin 3.3Vout 5 4 CPUSB#
40mil 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 5
2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z RSV
+3V 17 AUX_IN AUX_OUT 15 +3VALW_CARD 6 RSV
ICH_SMBCLK 7 SMB_CLK
PCI_RST# 6 19 ICH_SMBDATA 8
PCI_RST# SYSRST# OC# SMB_DATA
+1.5VS_CARD 9 +1.5V
SYSON 20 8 PERST1# 10
SYSON SHDN# PERST# +1.5V
ICH_PCIE_WAKE# 11 WAKE#
SUSP# 1 16 +3VALW_CARD 12
SUSP# STBY# NC +3.3VAUX
PERST1# 13
CP_PE# PERST#
10 CPPE# GND 7 +3VS_CARD 14 +3.3V
(Internal Pull High to AUXIN) +3VS 15
CP_USB# CLKREQ1# +3.3V
9 CPUSB# Thermal_Pad 21 16 CLKREQ#
(Internal Pull High to AUXIN) CP_PE# CP_PE# 17
RCLKEN1 +3VS CPPE#
18 RCLKEN 1 CLK_PCIE_CARD# 18 REFCLK-
C388 19
CLK_PCIE_CARD REFCLK+
G577NSR91U_TQFN20_4x4 20 GND

1
0.1U_0402_16V4Z 21
2 NC@ PCIE_PTX_C_IRX_N1 PERn0
NC@ R338 22
PCIE_PTX_C_IRX_P1 PERp0

5
10K_0402_5% U18 23
CLKREQ1# GND
2 24

G Vcc
B PCIE_ITX_C_PRX_N1 PETn0
NC@ 4 PCIE_ITX_C_PRX_P1 25
EXP_CLKREQ#

2
Y PETp0
1 A 26 GND

1
+3VS +3V +1.5VS D NC7SZ32P5X_NL_SC70-5 NC@ 27 29

3
RCLKEN1 2 Q30 GND GND
28 GND GND 30
G 2N7002_SOT23
1 1 1 S NC@ FOX_1CH4110C_LT

3
C382 C378 C360 CONN@
NC@ NC@ NC@ Don't Connect to GND
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 2008/02/22
2 2 2
2 2

USB CONN.
Bluetooth Conn.
+USB_VCCA +USB_VCCA
W=80mils
+USB_VCCA
W=80mils
+USB_VCCA
+3VALW +3VS
1 1
1 1
+ C538 C549 + C537 C548

1 1 150U_B2_6.3VM_R45M 150U_B2_6.3VM_R45M
C324 C323 2 2 2 2
@
BT@ BT@ 470P_0402_50V7K 470P_0402_50V7K
0.1U_0402_16V4Z 1U_0603_10V4Z
3

2 2
S
G
3 JUSB2 JUSB1 3
BT_ON# 1 2 2
R274 BT@ 10K_0402_5% Q20 1 1
AO3413_SOT23-3 USB20_N6 VCC USB20_N0 VCC
D
USB20_N6 2 USB20_N0 2
1

BT@ USB20_P6 D- USB20_P0 D-

1 USB20_P6 3 D+ USB20_P0 3 D+
C330 W=40mils 4 4
BT@ GND GND
+BT_VCC
0.1U_0402_16V4Z 5 5
2 GND1 GND1
1 1 6 GND2 6 GND2
1

C317 C316 7 7
BT@ R269 GND3 GND3
8 GND4 8 GND4
4.7U_0805_10V4Z BT@ 300_0603_5%
2 2 BT@ SUYIN_020173MR004G565ZR SUYIN_020173MR004G565ZR
0.1U_0402_16V4Z CONN@ CONN@
2
1

D
2 Q21
G 2N7002_SOT23 +3V
S BT@ 80mil
3

+5VALW

1
+USB_VCCA
+BT_VCC U28
1 8 R461
GND OUT USB_OC#6
JBT1 2 7 100K_0402_5%
D23 IN OUT
8 9 3 6

2
8 GND USB20_P0 USB20_P6 IN OUT
7 7 6 CH3 CH2 3 1 4 EN# FLG 5 1 2 USB_OC#0
6 C540 R460
USB20_P8 6
5 TPS2061DRG4_SO8 10K_0402_5% 1
USB20_N8 5
4 4.7U_0805_10V4Z C539
4 2
WLAN_BT_DATA 3 3 +USB_VCCA 5 Vp Vn 2
2 0.1U_0402_16V4Z
WLAN_BT_CLK 2 2
1 1 GND 10
4 4
SYSON#
ACES_87213-0800G USB20_N6 4 1 USB20_N0
CH4 CH1
CONN@
CM1293-04SO_SOT23-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 28 of 45
A B C D E
 5 4 3 2 1

+3VALW For EC Tools

L13
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 +EC_VCCA +3VALW
1 1 C369 1 1 2
1
2 FBM-L11-160808-800LMT_0603 JP13 Place on RAM door
C365 1 KSI[0..7] 1
+3VALW KSI[0..7] 1
C319 C344 C343 C331 2 E51RXD_P80CLK
KSO[0..17] 2 E51RXD_P80CLK
1000P_0402_50V7K 1000P_0402_50V7K C421 3 E51TXD_P80DATA
2 2 2 2 1 1 KSO[0..17] 3 E51TXD_P80DATA
1 2 EC_PME# 4
R319 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 4

ECAGND
@ ACES_85205-0400
@
D
+3VALW Place on MiniCard D
JP9

111
125
PLT_RST#

22
33
96

67
1 2 1 1

9
R467 100K_0402_5% U13 2 E51RXD_P80CLK
2 E51TXD_P80DATA
3

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
3
4 4
ACES_85205-0400 +3VALW
1 21 INVT_PWM @
EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM
2 23 BEEP#
EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP#
3 26 FANPWM 2 1
SERIRQ SERIRQ# FANPWM1/GPIO12 FANPWM
4 27 R31 100K_0402_5%
LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF
C340 LPC_AD3 5 2 1 ECAGND 3S/4S# 1 2
LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C332 0.01U_0402_16V7K R324 4.7K_0402_5%
LPC_AD2 LAD2
2 1 R289 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP @
LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP
LPC_AD0 BATT_OVP
LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP
ADP_I/AD2/GPIO3A 65 ADP_I
12 AD Input 66 AD_BID0
CLK_PCI_LPC PCICLK AD3/GPIO3B
PLT_RST# 13 75
PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 +3VALW
37 ECRST# SELIO2#/AD5/GPIO43 76
EC_SCI# 20
EC_SCI# SCI#/GPIO0E
+3VALW 2 1 38 15@
R270 47K_0402_5% PM_CLKRUN# CLKRUN#/GPIO1D DAC_BRIG ID_15_17
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG 2 1
2 1 70 EN_DFAN1 R321 100K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_DFAN1
C320 0.1U_0402_16V4Z DA Output 71 IREF 2 1
IREF/DA2/GPIO3E IREF
KSI0 55 72 R322 100K_0402_5%
KSI0/GPIO30 DA3/GPIO3F CALIBRATE#
KSI1 56 17@
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE#
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE#
C KSI4 59 84 C
+3VALW KSI5 KSI4/GPIO34 PSDAT1/GPIO4B +3VALW
60 KSI5/GPIO35 PSCLK2/GPIO4C 85
KSI6 61 PS2 Interface 86 TLOCK_LED#
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK 65W/90W#
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK 2 1
2

KSO0 39 88 TP_DATA R323 100K_0402_5%

KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA
R276 KSO1 40
10K_0402_5% KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97 3S/4S#
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S#
KSO4 43 98 65W/90W#
65W/90W#
1

KSO5 KSO4/GPIO24 SDICLK/GPXOA01 SBPWR_EN

KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
SBPWR_EN Analog Board ID definition,
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW#
EC_RCIRRX KSO7 46 SPI Device Interface Please see page 3.
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 EC_SPIDI/FWR#
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO +3VALW
+5VS KSO10 49 120 EC_SPIDO/FRD#
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK
KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL#

2
1 2 TP_CLK KSO13 52 KSO13/GPIO2D
R290 4.7K_0402_5% KSO14 53 R272
KSO14/GPIO2E
1 2 TP_DATA KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 EC_RCIRRX Ra 100K_0402_5%
R291 4.7K_0402_5% KSO16 81 74
KSO17 KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG
82 89 FSTCHG

1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# AD_BID0
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED#
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED#

2
EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# 1
EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_AMB_LED#
EC_SMB_DA1 78 93 PWR_LED R273 C325
EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED
EC_SMB_CK2 79 SM Bus 95 SYSON Rb
+3VALW EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON
EC_SMB_DA2 80 121 VR_ON 33K_0402_5%
EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 2
127 ACIN 0.1U_0402_16V4Z
ACIN

1
B AC_IN/GPIO59 B
1 2 EC_SMB_CK1
R279 2.2K_0402_5%
1 2 EC_SMB_DA1 PM_SLP_S3#
PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST#
R280 2.2K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT#
PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT#
1 2 KSO1 EC_SMI#
EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON
EC_ON
R295 47K_0402_5% 16 103
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI#
1 2 KSO2 17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 EC_PWROK
EC_PWROK
EC_CRY1 EC_CRY2
R296 47K_0402_5% 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF#
1 2 LID_SW# 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WL_OFF#
WL_OFF# 1 1
R320 100K_0402_5% 25 107 ID_15_17 C368 C367
MCH_TSATN_EC# EC_THERM#/GPIO11 GPXO10

4
FAN_SPEED1 28 108
FAN_SPEED1 BT_ON# FAN_SPEED1/FANFB1/GPIO14 GPXO11 15P_0402_50V8J 15P_0402_50V8J
29

OUT
IN
BT_ON# FANFB2/GPIO15 2 2
E51TXD_P80DATA 30
E51RXD_P80CLK EC_TX/GPIO16
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4#
ON/OFF 32 112 ENBKL
+3VS ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL
PWR_SUSP_LED EAPD

NC

NC
PWR_SUSP_LED 34 PWR_LED#/GPIO19 GPXID3 114 EAPD
NUM_LED# 36 GPI 115
NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM#
116 SUSP#
SUSP#

3
GPXID5
1 2 EC_SMB_CK2 GPXID6 117 PBTN_OUT#
PBTN_OUT#
R281 2.2K_0402_5% 118 EC_PME#
GPXID7 EC_PME#
1 2 EC_SMB_DA2 EC_CRY1 122 XCLK1
X2
R282 2.2K_0402_5% EC_CRY2 123 124 32.768KHZ_12.5P_MC-306
XCLK0 V18R
1
AGND

C366
GND
GND
GND
GND
GND

4.7U_0805_10V4Z C333 100P_0402_50V8J

KB926QFD3_LQFP128_14X14 2 BATT_TEMP 2 1
11
24
35
94
113

69

20mil C420 100P_0402_50V8J

L14 BATT_OVP 2 1
A A
ECAGND 2 1 C364 100P_0402_50V8J
FBM-L11-160808-800LMT_0603 ACIN 2 1

<BOM Structure>

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 29 of 45
5 4 3 2 1
 U20
To TP/B Conn.
+3VALW 1 2 C417 1 2 0.1U_0402_16V4Z EC_SPICS#/FSEL# 1 8 +SPI_VCC JTP1
R358 0_0603_5% SPI_WP# CS# VCC EC_SPICLK_R
3 WP# SCLK 6 +5VS 6
SPI_HOLD# 7 5 EC_SO_SPI_SI TP_CLK
HOLD# SI TP_CLK 5
+SPI_VCC 4 2 EC_SI_SPI_SO TP_DATA
GND SO TP_DATA 4
LEFT_BTN#
U21 MX25L512AMC-12G_SO8 RIGHT_BTN# 3
EC_SPICS#/FSEL# @ 2
EC_SPICS#/FSEL# 1 CE# VDD 8 1
R359 1 2 4.7K_0402_5% SPI_WP# 3 6 EC_SPICLK_R R356 1 2 0_0402_5% Reserved for BIOS simulator. 1 1
WP# SCK EC_SPICLK
R371 1 2 4.7K_0402_5% SPI_HOLD# 7 5 R355 1 2 0_0402_5% C217 ACES_85201-0605
+3VALW HOLD# SI R360 1
EC_SO_SPI_SI Footprint SO8
4 VSS SO 2 2 0_0402_5% EC_SI_SPI_SO
C218 CONN@
100P_0402_50V8J 100P_0402_50V8J
MX25L8005M2C-15G_SOP8 2 2

ENE suggestion SPI Frequency over 66MHz EC_SPICLK_R FOR EMI

SST: 50MHz

2
MXIC: 70MHz LEFT_BTN# TP_CLK
R354
ST: 40MHz 22_0402_5% RIGHT_BTN# +5VS TP_DATA
@

3
1
C219
KSI[0..7] 2 D12 D11
INT_KBD Conn. KSO[0..17]
KSI[0..7]
C416
@
PJDLC05_SOT23
0.1U_0402_16V4Z @
PJDLC05_SOT23
KSO[0..17]
10P_0402_50V8J

1
1
@
To POWER/B
15" 17 " 15" SW4 15@
SMT1-05-A_4P
SW3 15@
SMT1-05-A_4P
LEFT_BTN# 3 1 RIGHT_BTN#3 1

JKB1 JKB2 +3VS +3VALW +5VS 4 2 4 2

(Left) JP14
KSO0 26 28 KSO0 26 28

5
6

5
6
KSO1 26 G2 KSO1 26 G2 1
25 25 G1 27 25 25 G1 27 2
KSO2 24 KSO2 24
KSO3 24 KSO3 24 3
23 23 23 23 4
KSO4 22 KSO4 22
KSO5 22 KSO5 22 5
21 21 21 21 LID_SW# 6
KSO6 20 KSO6 20 TP_LOCK_LED#
20 20 TLOCK_LED# 7
KSO7 19 KSO7 19 KSO0
KSO8
KSO9
18
17
19
18
KSO8
KSO9
18
17
19
18
KSO0
KSI2 KSI2
PWR_SUSP_LED#
8
9 17" SW2 17@
SMT1-05-A_4P
SW1 17@
SMT1-05-A_4P
KSO10 17 KSO10 17 PWR_LED# 10 LEFT_BTN# 3 RIGHT_BTN#3
16 16 16 16 11 1 1
KSO11 15 KSO11 15 ON/OFFBTN# ON/OFFBTN#
KSO12 15 KSO12 15 KSI1 12
14 14 14 14 KSI1 13 4 2 4 2
KSO13 13 KSO13 13 MINI1_LED#
13 13 MINI1_LED# 14
KSO14 12 KSO14 12 MEDIA_LED#

5
6

5
6
KSO15 12 KSO15 12 NUM_LED# 15
11 11 11 11 NUM_LED# 16
KSO16 10 KSO16 10 CAPS_LED#
10 10 CAPS_LED# 17
KSO17 9 KSO17 9
KSI0 9 KSI0 9 18
8 8 8 8 19
KSI1 7 KSI1 7
KSI2 7 KSI2 7 20
6 6 6 6
KSI3 5 KSI3 5 ACES_85201-20051
KSI4 5 KSI4 5
4 4 4 4
KSI5 3 KSI5 3
KSI6 3 KSI6 3
2 2 2 2
KSI7 1 KSI7 1 KSO0
1 1
(Right)
ACES_85201-26051 ACES_85201-26051
KSI1 WL_BTN#
CONN@ CONN@ KSI2 TLOCK_BTN#

KSO16 C30
KSI3
1 2 @ 100P_0402_50V8J
KSO15 C31 1 2 @ 100P_0402_50V8J KSI4
KSO17 C29 1 2 @ 100P_0402_50V8J
KSO14 C32 1 2 @ 100P_0402_50V8J KSI5
KSO13 C33 1 2 @ 100P_0402_50V8J KSO7 C39 1 2 @ 100P_0402_50V8J

KSO12 C34 1 2 @ 100P_0402_50V8J KSO6 C40 1 2 @ 100P_0402_50V8J

KSO5 C41 1 2 @ 100P_0402_50V8J PWR_LED# PWR_SUSP_LED#

KSI0 C28 1 2 @ 100P_0402_50V8J

3
KSO4 C42 1 2 @ 100P_0402_50V8J
KSO11 C35 1 2 @ 100P_0402_50V8J Q3A Q3B
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
KSO10 C36 1 2 @ 100P_0402_50V8J KSO3 C43 1 2 @ 100P_0402_50V8J PWR_LED 2 PWR_SUSP_LED 5 FOR EMI
1

1
KSI1 C27 1 2 @ 100P_0402_50V8J KSI4 C24 1 2 @ 100P_0402_50V8J
1

4
R22 R32
KSO2 C46 1 2 @ 100P_0402_50V8J PWR_LED# C51 1 2 @ 100P_0402_50V8J
KSI2 C26 1 2 @ 100P_0402_50V8J 10K_0402_5% 10K_0402_5%
KSO1 C47 1 2 @ 100P_0402_50V8J ON/OFFBTN# C52 1 2 @ 100P_0402_50V8J
2

2
KSO9 C37 1 2 @ 100P_0402_50V8J
MINI1_LED# C44 1 2 @ 100P_0402_50V8J
KSI3 C25 1 2 @ 100P_0402_50V8J KSO0 C48 1 2 @ 100P_0402_50V8J

KSO8 C38 1 2 @ 100P_0402_50V8J KSI5 C23 1 2 @ 100P_0402_50V8J

+3VS PWR_SUSP_LED#C50 1 2 @ 100P_0402_50V8J
KSI6 C22 1 2 @ 100P_0402_50V8J
Q5A NUM_LED# C45 1 2 @ 100P_0402_50V8J
2

KSI7 C21 1 2 @ 100P_0402_50V8J 2N7002DW-T/R7_SOT363-6

5IN1_LED# 1 6
LED2 MEDIA_LED# C49 1 2 @ 100P_0402_50V8J
SATA_LED# 4 3 MEDIA_LED#
Compal Footprint +5VALW 1 2 4 A 3 PWR_SUSP_LED#
SATA_LED#
R345 1.2K_0402_5%
3 4 Q5B
5

+5VS 1 2 2 YG 1 PWR_LED# +3VS 2N7002DW-T/R7_SOT363-6

1 2 R344 1K_0402_5%

HT-297DQ-GQ_AMB-YG

LED1

1 2 4 3 BATT_AMB_LED#
+5VALW
R343 1.2K_0402_5%
A
BATT_AMB_LED# Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title
BATT_GRN_LED#
+5VALW 1 2
R342 1K_0402_5%
2 YG 1 BATT_GRN_LED#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
HT-297DQ-GQ_AMB-YG B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 30 of 45
 A B C D E

Power Button
ON/OFF switch HDA MDC Conn.
+3V

@ 1
JMDC1 15mil 1 2 C389
+1.5V
R339 0_0402_5% @
1 +MDC_VCC 1U_0603_10V4Z 1
1 GND1 RES0 2 1 2 +3V
+3VALW 2
TOP Side HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4 R340 0_0402_5%
5 GND2 3.3V 6 +3V
1 2 HDA_SYNC_MDC 7 IAC_SYNC GND3 8
R341 @ 10K_0603_5% HDA_SDIN1 1 2 HDA_SDIN1_MDC 9 10
IAC_SDATA_IN GND4

2
R346 33_0402_5% 11 12
HDA_RST_MDC# IAC_RESET# IAC_BITCLK HDA_BITCLK_MDC
1 2 R271

1
R416 @ 10K_0603_5%
100K_0402_5% R335

GND
GND
GND
GND
GND
GND
Bottom Side 0_0402_5%

1
D17 @
2 ACES_88018-124G
ON/OFF

13
14
15
16
17
18

2
ON/OFFBTN# 1 CONN@ 1
ON/OFFBTN#
3 51ON# C383
51ON#
Connector for MDC Rev1.5 @
DAN202UT106_SC70-3 22P_0402_50V8J
2

For EMI
1

D
EC_ON 2 Q19
EC_ON
G
2

2 S 2N7002_SOT23 2
3

R268

10K_0402_5%
1

Power ON Circuit
+3VS

+3VALW +3VALW
1

U19A U19B
R349 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

180K_0402_5%
D18 @
P

P
2

1 2 1 2 3 4 SYS_PWROK 1 2
VR_ON I O I O EC_PWROK
R348 @ 0_0402_5%
G

CH751H-40PT_SOD323-2 2
@
For South Bridge
7

C408 @ @
1U_0603_10V6K
@ 1

3 3

+3VS

+3VALW +3VALW
1

R352
U19C U19D
14

14

R353 @ @ 10K_0402_1% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

10K_0402_1%
P

P
2

SUSP# 1 2 5 I O 6 9 I O 8 VS_ON
2
1

D C409
SUSP 2
For +VCCP/+1.05VS
SUSP
7

G 0.1U_0402_16V4Z @ @ @
Q31 S 1
3

2N7002_SOT23
@

+3VALW +3VALW
C407
1 2 0.1U_0402_16V4Z

U19E U19F
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
@
P

11 I O 10 13 I O 12
G

4 4
7

@ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 31 of 45
A B C D E
 A B C D E F G H

+VDDA

1
1 2
R419 R441 0_0805_5%
10K_0402_5%

+5VAMP

2
U27
1 2 +5VS L28 1 2 0.1U_0402_16V4Z 60mil 1 IN
40mil
C507 1U_0402_6.3V4Z FBMA-L11-201209-221LMA30T_0805 5 +VDDA 4.75V
OUT

1
1 1 2 GND
R424 L29 1 2 C544 C545
10K_0402_5% FBMA-L11-201209-221LMA30T_0805 3 4 1 2
1 0.1U_0402_16V4Z SHDN BYP C531 1
2 2 G9191-475T1U_SOT23-5 0.01U_0402_25V7K

2
C514 @
1 2 MONO_IN
1U_0402_6.3V4Z HD Audio Codec (output = 300 mA)

1
C 1 2
C508 1 R420 Q38 R425
BEEP# 2 1 2 2
1U_0402_6.3V4Z B 2SC2411KT146_SOT23-3 2.4K_0402_1%
560_0402_5% E L25

3
MBK1608121YZF_0603
10mil 0.1U_0402_16V4Z +3VS_DVDD 1 2 +3VS
C505 1 R417
SB_SPKR 2 1 2 1 1 1

2
1U_0402_6.3V4Z C509 C510 C506

1
560_0402_5% R239

1
10U_0805_10V4Z 0_0805_5%
R421 D21 2 2 2
10K_0402_5% CH751H-40PT_SOD323-2

1
0.1U_0402_16V4Z MIC2_VREFO

2
Change D21 from RB751 to CH751

1
@ R430
+AVDD_HDA 10mil +1.5VS_DVDD 1 2 2.2K_0402_5%
+1.5VS
1
C512
1
C513 L26 MBK1608121YZF_0603
15mil
40mil

2
L27 1 2 0.1U_0402_16V4Z INT_MIC_R
+VDDA
FBM-L11-160808-800LMT_0603 1 1 1 0.1U_0402_16V4Z
C517 C528 2 2
1
C529 10U_0805_10V4Z C519
2 10U_0805_10V4Z 2

25

38

9
2 2 2 U26 220P_0402_50V7K
0.1U_0402_16V4Z 2

DVDD
AVDD1

AVDD2

DVDD_IO
14 35 AMP_LEFT
LINE2_L LOUT1_L AMP_LEFT
15 36 AMP_RIGHT
LINE2_R LOUT_R AMP_RIGHT
R431 1K_0402_1% 1 2 MIC2_C_L 16 39
INT_MIC_R INT_MIC C515 4.7U_0805_6.3V6K MIC2_L LOUT2_L
2 1
1 2 MIC2_C_R 17 41 15mil
C518 4.7U_0805_6.3V6K MIC2_R LOUT2_R
JMIC2
23 45 INT_MIC_R 1
LINE1_L SPDIFO2 1
2 2
24 LINE1_R DMIC_CLK1/2 46

2
18 LINE1_VREFO NC 43 3 G1
D3 4 G2
20 LINE2_VREFO DMIC_CLK3/4 44 1 2 1 2 C511 SM05T1G_SOT23-3
R422 0_0402_5% 22P_0402_50V8J For EMI @ ACES_88266-02001
19 CONN@
MIC2_VREFO MIC2_VREFO
6 HDA_BITCLK_AUDIO

1
MIC1_L MIC1_C_L BITCLK
MIC1_L 1 2 21 MIC1_L
C522 4.7U_0805_6.3V6K
MIC1_R 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2 HDA_SDIN0
MIC1_R MIC1_R SDATA_IN
C523 4.7U_0805_6.3V6K R423 33_0402_5%
MONO_IN 12 37
PCBEEP_IN MONO_OUT

CBP 29
11 2.2U_0402_6.3VM
3 HDA_RST_AUDIO# RESET# 3
31 C524 1 2
CPVEE HP_RIGHT
HDA_SYNC_AUDIO 10 SYNC 10mil 1 HP_RIGHT
MIC1_VREFO 28 MIC1_VREFO_L
HDA_SDOUT_AUDIO 5 C525 HP_LEFT
SDATA_OUT HP_LEFT
32 HP_RIGHT 2.2U_0402_6.3VM
HPOUT_R 2
2 GPIO0/DMIC_DATA1/2
3 GPIO1/DMIC_DATA3/4 CBN 30
R428 2 1 20K_0402_1% SENSE_A 13 10mil
MIC_PLUG# SENSE A
R433 2 1 5.11K_0402_1% SENSE_B 34 27 CODEC_VREF
HP_PLUG# SENSE B VREF
1 1

10U_0805_10V4Z

0.1U_0402_16V4Z
EAPD 1 2 47 EAPD JDREF 40

20K_0402_1%

C526

C527
R427 0_0402_5%

1
48 33 HP_LEFT
SPDIFO1 HPOUT_L 2 2

R429
4 DVSS1 AVSS1 26
7 DVSS2 AVSS2 42

2
ALC272-GR_LQFP48_7X7
Sense Pin Impedance Codec Signals 1
R466
2
0_0805_5%
1
R438
2
0_0805_5%

39.2K DGND AGND

1 2 1 2
R437 0_0805_5% R434 0_0805_5%
20K PORT-B (PIN 21, 22)
SENSE A
1 2 1 2
10K R426 0_0805_5% R435 0_0805_5%

5.1K
4
GND GNDA GND GNDA 4
39.2K

20K
SENSE B
10K
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 32,33) Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 32 of 45
A B C D E F G H
 A B C D E

+5VAMP
0.1U_0402_16V4Z Int. Speaker Conn.
1 1
C562 C541 JSPK1
10U_0805_10V4Z SPKL+ R23 1 2 0_0603_5% SPK_L+ 1
2 2 SPKL- R24 SPK_L- 1
1 2 0_0603_5% 2 2
20mil Left

2
10 dB 3 G1
D5 4
1 +5VAMP G2 1
PJDLC05_SOT23-3

1
@ ACES_88266-02001

16
15
6
U29 R440 @ R439 CONN@

1
100K_0402_5% 100K_0402_5%

VDD
PVDD1
PVDD2
JSPK2
SPKR+ R85 1 2 0_0603_5% SPK_R+ 1

2
SPKR- R86 1
1 2 0_0603_5% SPK_R- 2 2
C542 1 2 0.47U_0603_10V7K 7 2 GAIN0 20mil
RIN+ GAIN0 Right

2
3 GAIN1 3
GAIN1 D8 G1
4 G2

1
1 2 1 2 AMP_C_RIGHT 17 PJDLC05_SOT23-3
AMP_RIGHT C561 3900P_0402_50V7K R465 0_0603_5% RIN- SPKR+ @ R457 R456 @ ACES_88266-02001
ROUT+ 18
100K_0402_5% 100K_0402_5% CONN@

1
14 SPKR-

2
C543 1 ROUT-
2 0.47U_0603_10V7K 9 LIN+
4 SPKL+
LOUT+
1 2 1 2 AMP_C_LEFT 5
AMP_LEFT C530 3900P_0402_50V7K R458 0_0603_5% LIN- SPKL-
LOUT- 8

HPF 600Hz
NC 12

EC_MUTE# BYPASS 10 Keep 10 mil width

EC_MUTE# 19 SHUTDOWN
2

GND5
GND1
GND2
GND3
GND4
2 C554 2
0.47U_0603_10V7K
21
1 LINE Out/Headphone Out
20
13
11
1
TPA6017A2_TSSOP20 JHP1
8
7
2 2
C553 C552
HP_PLUG# 5
HP_PLUG#
20mil 330P_0402_50V7K 330P_0402_50V7K
1 1
4

HP_RIGHT HP_RIGHT 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3

R462 56.2_0402_1% L43 FBM-11-160808-700T_0603 6
HP_LEFT HP_LEFT 1 2 HPOUT_L_1 1 2 HPOUT_L_2 2
R454 56.2_0402_1% L38 FBM-11-160808-700T_0603 1

SINGA_2SJ-E351-S03
CONN@

MIC1_VREFO_L MIC1_VREFO_L

3 3

2
Change D24,D28 from RB751 to CH751 D24 D28 MIC JACK
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
JMIC1
8

1
7

1
MIC_PLUG# 5
MIC_PLUG#
R452 R453
4.7K_0402_5% 4.7K_0402_5% 4

2
1 2 1 2 FBM-11-160808-700T_0603 MIC2_R_1 3
MIC1_R
R455 1K_0603_1% L37 6
MIC1_L 1 2 1 2 FBM-11-160808-700T_0603 MIC2_L_1 2
R436 1K_0603_1% L36 1
1 1
SINGA_2SJ-E351-S01
C550 C551 CONN@
220P_0402_50V7K 220P_0402_50V7K
2 2
(HDA Jack)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 33 of 45
A B C D E
 A B C D E

+5VALW TO +5VS +3VALW TO +3V_SB(ICH8M AUX Power) +5VALW

+5VALW +5VS +3VALW +3V

2
U10
U15 8 1 R287
D S 100K_0402_5%
8 D S 1 7 D S 2
7 D S 2 6 D S 3

2
6 3 1 1 1 1 5 4 1 1

1
D S C379 C361 C318 C116 R298 D G C176 C177 R198
1 1 1 1 5 D G 4 1
C439 C117 C362 C363 @ C226 AP4800_SO8 470_0603_5% SYSON#
SYSON#
AP4800_SO8 10U_0805_10V4Z 1000P_0402_50V7K 470_0603_5% 10U_0805_10V4Z

6
2 2 2 2 2 2

5VS_GATE
100P_0402_50V8J 10U_0805_10V4Z 1U_0603_10V4Z 1U_0603_10V4Z

1
1 2 2 2 2 100P_0402_50V8J 2
10U_0805_10V4Z 1
1000P_0402_50V7K 10U_0805_10V4Z Q26A
SYSON 2
SYSON

1
D 2N7002DW-T/R7_SOT363-6

1
D
2 SBPWR_EN#

1
+VSB 2 1 2 1 2 SUSP +VSB 2 1 3V_GATE G R284
R299 R470 G R199 S Q42 100K_0402_5%

3
33K_0402_5% 120K_0402_5% S Q41 200K_0402_5% 1 2N7002_SOT23

3
1 @ C195

2
1
<BOM Structure>
C351 2N7002_SOT23 D

1
D SBPWR_EN# 0.1U_0603_25V7K
2
SUSP Q47 0.1U_0603_25V7K G 2 +5VALW
2
G 2 Q45 S

3
S 2N7002_SOT23
3

2
2N7002_SOT23
R285
100K_0402_5%

+1.5V to +1.5VS

1
SUSP
+3VALW TO +3VS 1
R244
2
SUSP

3
+3VALW +3VS +1.5V 0_0805_5% +1.5VS

U22 U12 Q26B

8 D S 1 8 D S 1 SUSP# 5
7 2 7 2 1 1 2N7002DW-T/R7_SOT363-6
D S D S

2
6 3 1 1 6 3 C315 C310

4
D S D S

1
1 1 5 4 C437 C436 R385 1 1 5 4 R267
C430 C429 D G 470_0603_5% C309 C313 D G 10U_0805_10V4Z 470_0603_5% R286
AP4800_SO8 10U_0805_10V4Z AP4800_SO8 @ 2 2
1U_0603_10V4Z @ 10K_0402_5%
10U_0805_10V4Z 2 2
1U_0603_10V4Z 10U_0805_10V4Z @ @
1 1

1
2 2 2
10U_0805_10V4Z @ 2 2
10U_0805_10V4Z 2

2
D @
2 SUSP
G

1
Q32 D
S
3

+VSB 2 1 3VS_GATE 2N7002_SOT23 +VSB 2 1 1.5VS_GATE 2 SUSP

R365 R266 G
200K_0402_5% 1 510K_0402_5% 1 S Q43

3
C391 @ C314 @ 2N7002_SOT23 +5VALW
1

D 0.1U_0603_25V7K 0.1U_0603_25V7K

2
SUSP 2 D 2 @
2
G SUSP 2 R300
Q46 S G 100K_0402_5%
3

1
2N7002_SOT23 Q44 S

3
2N7002_SOT23 R297

1
@ 2.2M_0402_5%
@
SBPWR_EN# SBPWR_EN#

2
1
D

1
D
ACIN 2
G SBPWR_EN 2
Q29 S G

3
2N7002_SOT23 Q27 S

3
1
@ 2N7002_SOT23
R288
100K_0402_5%

2
3 3

+1.5VS +1.05VS +0.9VS +1.8V +1.5V

Reserve for EMI request
2

R253 R283 R260 R259 R265

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% +1.8V +1.8V B+ B++ +1.05VS +3VS
@ @ 1 1 1 1 1 1
C563 C564 C565 C566 C567 C568
1

@ @ @ 1000P_0402_50V7K @ @
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_25V4K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1

D D D D D 2 2 2 2 2 2
2 SUSP 2 SUSP 2 SUSP 2 SYSON# 2 SYSON#
G G G G G
S Q13 S Q24 S Q14 S Q16 S Q17
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

@ @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 34 of 45
A B C D E
 A B C D

1 1

DC231000500 VIN <38> PR1

1M_0402_1%
1 2
SINGA_2DC-G756I200 PL1 <38> VIN VIN <38>
SMB3025500YA_2P VS
1 DC_IN_S1 1 2

1
@PR2
@ PR2 PR3
G 2 10K_0402_5% 84.5K_0402_1%
G PR5

8
3 PC3 PR6 PR4 22K_0402_5%

2
PC1 PC2 100P_0402_50V8J PC4 0_0402_5% 10K_0402_1% 3 1 2

P
PJP1 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
1 2 1 2 1

2
ACIN 0

20K_0402_1%
- 2

1
G

PR7
PU1A

1
PC6
0.1U_0603_25V7K
LM358DT_SO8 PC5

4
PR8 PD1 1000P_0402_50V7K

2
10K_0402_5% GLZ4.3B_LL34-2

2
2

2
PR9
10K_0402_5%
1 2
RTCVREF

2 2

Vin Dectector
Min. Typ Max.
- PBJ1 + H-->L 16.976V 17.525V 17.728V
2 1 +RTCBATT L-->H 17.430V 17.901V 18.384V
+RTCBATT

ML1220T13RE

VIN <38> 2
PJ1
1
+3VALWP 2 1 +3VALW
JUMP_43X118
2

1000P_0402_50V7K

100P_0402_50V8J
PD2

680P_0402_50V7K

1
LL4148_LL34-2

PC100

PC131
2

2
PD3

2
1

LL4148_LL34-2

PC130
<36,38> BATT+ 2 1
1

3 3

PR10 PR11
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR12
2

200_0603_5% PJ2
CHGRTCP 1 2 N1 3 1 2 1
VS PJ3
+1.5VP 2 1 +1.5V
JUMP_43X118
1

+5VALWP 2 2 1 1 +5VALW
1

PR13 PC8
100K_0402_1% PC7 0.1U_0603_25V7K JUMP_43X118
0.22U_1206_25V7K
2

PR14
2

22K_0402_1% PJ4
PJ5
1 2 2 1
51ON# 2 1 +0.9VSP 2 1 +0.9VS
+VSBP 2 1 +VSB
JUMP_43X79
JUMP_43X39

RTCVREF
1

PJ7 PJ6
PR15
PU2 200_0603_5% +1.05VSP 2 2 1 1 +1.05VS +1.8VP 2 2 1 1 +1.8V
PR16 PR17 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V JUMP_43X118 JUMP_43X118
2

1 2 1 2 3 2 N2
OUT IN
+CHGRTC
1

GND PC10 PJ9 PJ8

4
PC9 1U_0805_25V4Z +1.05VSP 2 2 1 1 +1.05VS +1.8VP 2 1 +1.8V
4

10U_0805_10V4Z 1 2 1
2

JUMP_43X118 JUMP_43X118

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 35 of 45
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 70 degree C
VL
VL
VL
VMB <38>

2
PL2 PR18

1
1 1

PJP2 SMB3025500YA_2P 100K_0402_1%

1 1 BATT_S1 1 2 BATT+ <35,38> PH1 PC11
MAINPWON
2 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR19

1
2 100K_0402_1%
3 3

1
4 EC_SMCA 1 2

2
4 EC_SMDA PC12 PC13 PR20 PQ2
5 5

8
6 1000P_0402_50V7K 0.01U_0402_25V7K 18K_0402_1% DTC115EUA_SC70-3

2
6 PD4
7 1 2 3

P
7 +
GND 8 O 1 2 1 2
9 TM_REF1 2
GND -

G
PU3A LL4148_LL34-2
SUYIN_200045MR007G180ZR_7P-T LM393DG_SO8

3
2

0.22U_0603_16V7K
PR21 PR22

11.3K_0402_1%
100_0402_1% 100_0402_1%

1
PC14
PR24

1000P_0402_50V7K
PR23
100K_0402_1%
1

2 1 VL

1
PR25

PC15
6.49K_0402_1%

2
2 1 +3VALWP

1
1

PR26
PR27 100K_0402_1%
1K_0402_1%

2
2

2 2

BATT_TEMP

EC_SMB_CK1 PH2 near main Battery CONN :

BAT. thermal protection at 90 degree C
EC_SMB_DA1
Recovery at 70 degree C
VMB <38> VL

2
PJP3 @ PR28
@PR28
VL 47K_0402_1%
1 2 @PR29
@ PR29
1 2 47K_0402_1%

1
3 3 4 4 1 2

1
5 5 6 6
@PH2
@ PH2
7 8 100K_0603_1%_TH11-4H104FT VL
7 8

2
EC_SMCA 9 10
9 10 PR31

8
11 12 EC_SMDA @ 13.7K_0402_1% @PD5
@ PD5
11 12 LL4148_LL34-2
1 2 5

P
+
13 13 14 14 O 7 2 1
TM_REF1 6 -

G
3 3

15 16 PU3B
15 16

1
LM393DG_SO8

4
17 18 @ PC18
@PC18 @ PR33
@PR33
17 18 0.22U_0603_16V7K 15.4K_0402_1%

2
19 20

2
19 20
SUYIN_200109MS020G209ZR

PQ3
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
0.22U_1206_25V7K

0.1U_0603_25V7K

<36,37,38,39,40,42>
1

1
PC16

PC17

PR30
100K_0402_1%
@ @
2

PR32
2

VL 22K_0402_1%
1 2
2

PR34
100K_0402_1%
4 4

PR35
1

0_0402_5% D
1 2 2 PQ4
SPOK G SSM3K7002FU_SC70-3
0.1U_0402_16V7K

S
3
1

PC19

@ Security Classification Compal Secret Data Compal Electronics, Inc.

2

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 36 of 45
A B C D
 5 4 3 2 1

<36,37,38,39,40,42>

B++ ISL6237_B+ ISL6237_B+

B+ ISL6237_B+
12/25_DVT_EMI
PL13 PJ10 PL14 PR36 PL15
HCB4532KF-800T90_1812 JUMP_43X118 FBMA-L11-322513-151LMA50T_1210 0_0805_5% FBMA-L11-322513-151LMA50T_1210
1 2 2 2 1 1 1 2 1 2 1 2

100P_0402_50V8J
D D

4.7U_1206_25V6K
4.7U_1206_25V6K

2200P_0402_50V7K

2200P_0402_50V7K
1000P_0402_50V7K
1

1000P_0402_50V7K
100P_0402_50V8J
1

1
PC126

4.7U_1206_25V6K

4.7U_1206_25V6K
1
1

PC21
PC20

5
6
7
8
PC22
2

8
7
6
5

1
PC25
VL

PC127 2

PC23

PC24
1U_0603_10V6K
2
2
PQ6

PC129
2

2
2

PC128

2
PQ5 PC26 AO4466_SO8

2
AO4466_SO8 0.1U_0603_25V7K

4.7U_0805_6.3V6K
4
12/25_DVT_EMI

1
PC27
4

PC28
1
+5VALWP

3
2
1
PL3

1
2
3
PL4 10UH_1164AY-100M=P3_4.7A_20%

7
10UH_1164AY-100M=P3_4.7A_20% PU4 PC29 2 1
1 2 1U_0603_10V6K

V5FILT

LDO
VIN
+3VALWP 33 19 1 2
TP V5DRV

5
6
7
8

1
4.7_1206_5%
1

8
7
6
5

PR41
DH3 26 15 DH5
PR37 DRVH2 DRVH1 PR39 2.2_0603_5% PQ8
PR38
4.7_1206_5% PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
VBST2 VBST1
2

1 AO4712_SO8 2.2_0603_5%

2
2

61.9K_0402_1%
PR40 PC32 4

2
PC30 + 0_0402_5% 4 PC31 0.1U_0603_25V7K

2
680P_0402_50V7K
0.1U_0603_25V7K @

1
1

PR42
330U_6.3V_M LX3 25 16 LX5 1
1

2 LL2 LL1

PC34
PC33

3
2
1

2
C 680P_0402_50V7K + PC35 C

1
2
3
DL3 23 18 DL5 220U_6.3V_M

1
DRVL2 DRVL1
2
2

10K_0402_1%
PGND 22

2
FB3 30 VOUT2

PR44
@ PR43
10K_0402_1% 10
VOUT1
VL 32
1

REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 VREF2
PC36 0.22U_0603_10V7K
VSW 9
8 LDOREFIN
+3.3VALWP Ipeak=5.01A ; Imax=0.7*Ipeak=3.507A @ PR45 0_0402_5%
29 2 1 VL
Choke DCRmax=33.6m ohm, DCRtyp=28m ohm SKIPSEL
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) PR46 0_0402_5%
1 2
Vlimit=(5E-06 * 330K)/10=165mV 20 28
PD6 PR47 NC PGOOD2
Ilimit=165mV/18m ~ 165mV/15m
GLZ5.1B_LL34-2 100K_0402_1%
=9.167A ~ 11A 1 2 1 2 4 13 SPOK
Iocp=Ilimit+Delta I/2 VS EN_LDO PGOOD1 PR49
2
200K_0402_5%

330K_0402_1%
=9.621A ~ 11.454A
2

B B
PR48

14 12 ILM1 2 1
EN1 TRIP1
Delta I=0.9089A (Freq=300KHz) PC37
0.22U_0603_25V7K

TONSE
VREF3
1

27 31 ILIM2 2 1

GND
1

EN2 TRIP2
1

0_0402_5%
PD7 PR50
1SS355_SOD323-2 VL @ PR51
2
TPS51427_QFN32_5X5 330K_0402_1%

21
PR52

0_0402_5%
2
2

PR53
1

1
1U_0603_10V6K
806K_0603_1%
2VREF_ISL6237 1

PR55 @ PR56 PR54

+5VALWP Ipeak=6.97A ; Imax=0.7*Ipeak=4.879A
1

2
PC38

0_0402_5% 47K_0402_5% 0_0402_5%

2 1 1 2
2VREF_ISL6237 2
Choke DCRmax=33.6m ohm, DCRtyp=28m ohm
1

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)

0.047U_0603_16V7K

MAINPWON
Vlimit=(5E-06 * 330K)/10=165mV
1

PC39

Ilimit=165mV/18m ~ 165mV/15m
2

=9.167A ~ 11A
1

@ PC40 Iocp=Ilimit+Delta I/2

3

0.047U_0402_16V7K
2

=9.627A ~ 11.460A
Delta I=0.921A (Freq=400KHz)
2 PQ9
A A
TP0610K-T1-E3_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 37 of 45
5 4 3 2 1
 A B C D

B+
PQ10 PQ11 <36,37,38,39,40,42>
AO4407A_SO8 AO4407A_SO8 PR57
VIN 8 1 1 8 0.015_2512_1%
<35> 7 2 2 7 PJ11
6 3 3 6 1 4 2 1 CHG_B+
2 1

1
5 5

2
2200P_0402_25V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
2 3 JUMP_43X118 PR59
PR58 CHGEN# PC41 100K_0402_1%

2
0.01U_0402_25V7K
3.3_1210_5% 0.01U_0402_25V7K

1
100K_0402_1%

PC42

PC43

PC44

2
1
PC46 PC47

1
2

5
6
7
8

3
2
1
1 1

PC45

PR60
0.1U_0402_16V7K PU5 0.1U_0805_25V7K
1 2 1 28 PVCC 1 2 PQ12
CHGEN PVCC

1
AO4407A_SO8

1
PR61 PR63 /BATDRV 4

2
3.3_1210_5% PC48 PC49 PQ13
2.2_0603_5%
0.1U_0603_25V7K 0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8

2
BTST

2
2
PR62
340K_0402_1% ACN 2 26 DH_CHG
ACN HIDRV
1

ACP 3

3
2
1

5
6
7
8
PC50 ACP PR64

1
2.2U_0805_25V6K ACDRV 4 25 LX_CHG PL5 0.02_2512_1%
2

ACDET ACDRV PH PD8 10UH_PCMB104T-100MS_6A_20%

5 ACDET
2 1 1 2 1 2 1 4
BATT+

10U_1206_25V6M
Place close to back to back MOS

10U_1206_25V6M
LL4148_LL34-2 PC51 <35,36>

REGN
2 3

2
0.1U_0603_25V7K

5
6
7
8

1
PR66

PC53
24751_VREF PR65

PC52
CELLS GND 3 Cell 54.9K_0402_1% ACSET 6 4.7_1206_5%
ACSET
24

2
REGN
VREF 4 Cell
1
2

1
PC54 PQ14

680P_0402_50V7K
PR67 1U_0603_10V6K 4 AO4466_SO8

1
PC56
47K_0402_1% @ PR68
@PR68 PC55

2
2

0_0402_5% 0.47U_0603_16V7K PC57

1 2 1 2 7 10U_1206_25V6M
1

2
PR69 ACOP DL_CHG
23

3
2
1
340K_0402_1% LODRV
CELLS
1

PGND 22
OVPSET 8 PC58
OVPSET
1

2 D PQ15 0.1U_0402_16V7K 2

2 3S/4S# 1 2
G 9 21 ACOFF
AGND LEARN
2

S SSM3K7002FU_SC70-3
3

1
PR70
54.9K_0402_1% PC59 @PC60
@PC60
24751_VREF CELLS 0.1U_0603_25V7K 0.1U_0603_25V7K
Cells selector 20

2
SI2301BDS-T1-E3_SOT23-3 CELLS
1

24751_VREF 10
VREF
1

1
PR71 PQ16 PC61
3

1U_0603_10V6K
100K_0402_1% 19 SE_CHG+

2
SRP
CP Point Setting 11 18 SE_CHG-
2

PQ15_GATE VDAC SRN

2
CP point=Iadapter*85% BAT 17
1

1
90W adapter PC63 VADJ 12
0.1U_0603_25V7K VADJ PC62
Vacset=3.3*(100K/(64.9K+100K))=2.001V
2

0.1U_0603_25V7K
Icharge Setting
1

2
65W adapter R=(100K*100K)/(100K+100K)=50K ACSET 29
ACGOOD# TP For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
13 ACGOOD ICHG setting PR72 For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A 24751_VREF 24751_VREF 17.4K_0402_1%
200K_0402_1%

16 SRSET 2 1 Icharge=(Vsrset/Vdac)*(0.1/PR64)
SRSET IREF
1

/BATDRV
100K_0402_1%

Vacset=3.3*(50K/(50K+64.9K))=1.436V 14 BATDRV IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge

1

1
PR74

PQ15_GATE PR75

1
PR73

CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A 10_0603_5% PR76

15 1 2 100K_0402_1% @PC64
@PC64 IREF=0.7748*Icharge
IADAPT
1

D 0.01U_0402_25V7K
2

2
PQ17 BQ24751ARHDR_QFN28_5X5 24751_VREF
Input OVP : 22.3V 2
2

2
3 3

0.1U_0402_16V7K G SSM3K7002FU_SC70-3 RTCVREF

1

1
PC65 D
Input UVP : 17.26V S
3

2
ACOFF 1 2 2 VMB <36> PC66
Fsw : 300KHz G PQ18 100P_0402_50V8J @ PR77
@PR77

100K_0402_1%
S SSM3K7002FU_SC70-3 100K_0402_1%
3
1

1
340K_0402_1%

VS ADP_I @PR81
@ PR81
PR78

PR80
0_0402_5% 24751_VREF

1
PR79 1 2
0.01U_0402_25V7K

340K_0402_1% ACIN

2
1
2

1
PR82 @ D @
1

PC67

887K_0402_1% ACGOOD# 2 PQ19

PQ20@
1

G SSM3K7002FU_SC70-3
PR83 SI2301BDS-T1-E3_SOT23-3 PR84 @ S
2

3
499K_0402_1% 0_0402_5%
LI-4S :18.0V----BATT-OVP=2.001V

S
REGN VADJ

D
3 1 1 2
24751_VREF
BATT-OVP=0.1112*VMB(18)
2
8

PR85 PU1B EVT_02_03

1
10K_0402_1% LM358DT_SO8

G
5 LI-3S :13.5V----BATT-OVP=1.5012V
P

2
+

2
499K_0402_0.1%
1 2 7 0 PR86
BATT_OVP PC68 @

1
- 6 BATT-OVP=0.1112*VMB(13.5) 100K_0402_1% PR89
G

PR88
@ PR87 1000P_0402_50V7K 100K_0402_1%

2
1

0.01U_0402_25V7K

PR90 Per cell=4.5V 210K_0402_0.1%

4

2
1

64.9K_0402_1% PR91

1
PC69

24751_VREF 1 2 ACSET 105K_0402_1% CHGEN#

2
2

1
D
2

PQ21 @
1

1
D
2
CALIBRATE# G SSM3K7002FU_SC70-3 EVT_02_03 2 PQ22
PR92
FSTCHG SSM3K7002FU_SC70-3
S G

3
100K_0402_1% S

3
1

4 4
2

PR93
100K_0402_1% VBATT Calibrate# VDAC=3.3
1

D
65W/90W# 2 PQ23
2

G SSM3K7002FU_SC70-3
S
4.0V L=0
3

1.8755V
Security Classification Compal Secret Data Compal Electronics, Inc.
4.2V 2009/01/21 2010/01/21 Title
Issued Date Deciphered Date
2.8132V SCHEMATIC, M/B A4851
4.3V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom D
4.35V H=3.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 38 of 45
A B C D
 A B C D

5
6
7
8
PQ24
AO4466_SO8

1 1

3
2
1
5
6
7
8
PQ25
<36,37,38,39,40,42>

D
D
D
D
FDS6670AS_NL_SO8
PJ12
JUMP_43X118
4 G
1.8VP_B+ 2 2 1 1 B++

4.7U_1206_25V6K
PR95

1
300K_0402_5%

S
S
S
PR96 1 2

PC70
0_0402_5%

3
2
1

2
1 2
SYSON
PR97 PC71
PL6
2.2_0603_5% 0.1U_0603_25V7K

15

14
1

1
VFB=0.75V
@PC72
@PC72
PU6 BST_1.8VP_1..5V
1 2VBST_1..5V-11 2 1 2 +1.8VP

EN_PSV

TP

VBST
Vo=VFB*(1+PR100/PR101)=0.75*(1+14K/10K)=1.8V 0.1U_0402_16V7K 1.8UH_SIL104R-1R8PF_9.5A_30%

2
Fsw=262KHz(by Caculation TooL) 2 13 DH_1.8VP_1..5V
TON DRVH

1
3 12 LX_1.8VP_1..5V 1
VOUT LL
<Vo=1.8V> VFB=0.75V PR160 +
4 VFB=0.75V 11 +5VALW PC73
Vo=VFB*(1+PR100/PR101)=0.75*(1+14K/10K)=1.8V V5FILT TRIP 4.7_1206_5%
330U_6.3V_M
Fsw=262KHz Cout ESR=15m ohm Rdson(max)=11.5m 5 10

2
VFB V5DRV 2
Rdson(min)=9m 6 9 DL_1.8V DL_1.8V
PGOOD DRVL

1
PGND
Ipeak=8.76A(by power budget), Imax=Ipeak*0.7=6.132A PR98

GND

1
13.7K_0402_1%
2
300_0402_5% PC119 2

Delta I=((19-1.8)*(1.8/19))/(L*Fsw)=3.455A

PR99
1 2 @ PC75
@PC75 PC74 680P_0402_50V7K
+5VALW

2
=>1/2DeltaI=1.7275A 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K

2
Vtrip=Rtrip*10uA=13.7K*10uA=0.137V 1 2

2
Iocpmin=Vtrip/Rdsonmax*1.3+1.7275 PC76
=0.137/(0.0115*1.3)+1.7275=10.8914A 1U_0603_10V6K
<36,37,38,39,40,42>
Iocpmax=(0.137/(0.009*1.1))+1.7275A=15.5659 2 PR100
Iocp=10.8914~15.5659A 14K_0402_1%
1 2 PL12
1.05VSP_B+ 2 1 B+
1
HCB4532KF-800T90_1812

5
6
7
8
note: Reference AO4712&TPS51117 spec
PR101
@

2200P_0402_50V7K PC125

2200P_0402_50V7K PC124
10K_0402_1% PQ26 @
AO4466_SO8

1
2

PR110 4

2
10K_0402_5%
1 2
SUSP#

3
2
1

4.7U_1206_25V6K
1
5
6
7
8

PC77
D
D
D
D

2
PR103
300K_0402_5% PQ27
PR104 @
3 3

1 2 4 FDS6670AS_NL_SO8
0_0402_5% G
1 2
VS_ON

S
S
S
3
2
1
PR105 PC78
PL7
2.2_0603_5% 0.1U_0603_25V7K +1.05VSP
15

14
1

PU7 BST_1.05VSP_1..5V
1 2BST_1.05VSP_1..5V-1
1 2 1 2
VFB=0.75V PC79
EN_PSV

TP

VBST

0.1U_0402_16V7K 1UH_PCMB103E-1R0MS_20A_20%
2

Vo=VFB*(1+PR108/PR109)=0.75*(1+12K/30K)=1.05V

1
2 13 DH_1.05VSP_1..5V
TON DRVH
Ton=19*e-12*143000(((2/3)*Vo+100mV)/19)+50ns
3 12 LX_1.05VSP_1..5V PR161 1
=2.645e-7 us VOUT LL 4.7_1206_5% C-test
=>Vo/Vin=D=Ton/Ts =>Ts=3.35us VFB=0.75V + PC80
4 11 +5VALW

1 2
V5FILT TRIP 330U_D2E_2.5VM
Fsw=261KHz(by caculation tool) 5 10
VFB V5DRV 2
6 9 DL_1.05V DL_1.05V PC120

2
PGOOD DRVL
PGND

<Vo=1.05V> VFB=0.75V PR106 680P_0402_50V7K

GND

1
15K_0402_1%
300_0402_5%
Vo=VFB*(1+PR108/PR109)=0.75*(1+12K/30K)=1.05V
PR107
1 2 @ PC82
@PC82 PC81
Fsw=261KHz Cout ESR=15m ohm +5VALW 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K
7

2
1 2
Rdson(max.)=11.5m Rdson(min)=9m
1

Ipeak=9A, Imax=Ipeak*0.7=6.3A PC83

1U_0603_10V6K
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=2.11A
2

=>1/2DeltaI=1.055A PR108
12K_0402_1%
Vtrip=Rtrip*10uA=15K*10uA=0.15V
1 2
4
Iocpmin=Vtrip/Rdsonmax*1.3+1.055 4

=0.15/(0.011*1.3)+1.055=11.0892A
2

Iocpmax=(0.15/(0.009*1.1))+1.055A=16.2073A PR109
Iocp=11.0892A~16.2073A 30K_0402_1%
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 39 of 45
A B C D
 5 4 3 2 1

5
6
7
8
PQ28
AO4466_SO8

PR162

3
2
1
D 0_0402_5% 12/24_DVT_EMI D

SUSP# 1 2

5
6
7
8
PL16

4.7U_1206_25V6K
FBMA-L11-322513-151LMA50T_1210

PR111
51117_B+ 1 2 B++

PC84
300K_0402_5% 4 PQ29
PR112 @ 1 2 AO4712_SO8
0_0402_5% <36,37,38,39,40,42>

2
1 2 12/24_DVT_EMI
SYSON

3
2
1
PR113 PC86 PL8
2.2_0603_5% 0.1U_0603_25V7K 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%

15

14
1

1
@PC85
@PC85
PU8 BST_1..5V 1 2BST_1..5V-1 1 2 1 2 +1.5VP

EN_PSV

TP

VBST
0.1U_0402_16V7K

2
2 13 DH_1..5V
TON DRVH

1
3 12 LX_1..5V 1
VOUT LL PR163
VFB=0.75V 4.7_1206_5% +
4 VFB=0.75V 11 +5VALW PC87
Vo=VFB*(1+PR116/PR117)=0.75*(1+10K/10K)=1.5V V5FILT TRIP 220U_6.3V_M

2
Ton=19*e-12*143000(((2/3)*Vo+100mV)/19)+50ns 5 VFB V5DRV 10
2
=2.645e-7 us 6 9 DL_1.5V DL_1.5V
PGOOD DRVL

1
PGND
=>Vo/Vin=D=Ton/Ts =>Ts=3.35us PR114

GND

1
7.5K_0402_1%
300_0402_5% PC121
Fsw=262KHz

PR115
1 2 @ PC89
@PC89 PC88 680P_0402_50V7K
+5VALW

2
C 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K C

2
1 2

1
<Vo=1.5V> VFB=0.75V

2
PC90
Vo=VFB*(1+PR116/PR117)=0.75*(1+10K/10K)=1.5V 1U_0603_10V6K

2
Fsw=262KHz Cout ESR=15m ohm Rdson(max)=18m
PR116
Rdson(min)=15m 10K_0402_1% 12/24_DVT_EMI
Ipeak=3.51A, Imax=2.457A 1 2
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=2.3969A

1
=>1/2DeltaI=1.198A
Vtrip=Rtrip*10uA=7.5K*10uA=0.075V PR117
Iocpmin=Vtrip/Rdsonmax*1.2+1.198 10K_0402_1%
=0.075/(0.018*1.3)+1.198=4.4035A
2

Iocpmax=(0.075/(0.015*1.1))+1.198A=5.7439A
Iocp=4.4035A~5.7439A

+1.8V

1
B PJ14 B

1
JUMP_43X79

22 PU9
1 VIN VCNTL 6 +3VALW
2 GND NC 5
2

1
1
PC91 3 7 PC92
4.7U_0805_6.3V6K PR118 REFEN NC 1U_0603_6.3V6M
1

2
1K_0402_1% 4 8
VOUT NC
9
2
GND
RT9173DPSP_SO8

0.1U_0402_16V7K
PR119 PQ30
+0.9VSP
1

1
0_0402_5% 2N7002W-T/R7_SOT323-3 D
PC93

SUSP 1 2 2 PR120

1
G 1K_0402_1%
2
1

S PC95
3

PC94 10U_0805_6.3V6M
2

0.1U_0402_16V7K 2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 40 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS

D D

10K_0402_1%
1.91K_0402_1%
1

1
PR121

PR122
VGATE

2
@

PM_DPRSLPVR
CLK_ENABLE# 1 2
PR123 +CPU_B+ PL9
@ 0_0402_5% +3VS +5VS HCB4532KF-800T90_1812 <36,37,38,39,40,42>

VR_ON
1 2 B+

2200P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M
0_0402_5%

1CPU_VREF 0_0402_5%
@

1
PC96

PC97

PC98
1

220U_25V_M
PR124

PR125
PC122
+ 2200P_0402_50V7K

2
PC99
0_0402_5%

499_0402_1%
@

5
2

124K_0402_1%

0_0402_5%

0_0402_5%

2
1

1
4

CPU_DPRSLPVR
PQ31

CPU_CLK_EN#
CPU_TRIPSEL

CPU_VR_ON 2

1
CPU_OSRSEL

CPU_TONSEL

PR130

PR126
SI7686DP-T1-E3_SO8

CPU_V5FILT

CPU_ISLEW
PL10

2
PR127

PR128

PR129
2 1 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
PC101 1 4 +CPU_CORE
1U_0402_6.3V6K

5
6
7
8

5
6
7
8
C CPU_CSP1-1 C
2 3

1
+5VS

SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8

1
17.8K_0402_1%
PR158
41

40

39

38

37

36

35

34

33

32

31

PR132
4.7_1206_5%

2
CPU_VREF
1 2
ISLEW

OSRSEL

TONSEL

TRIPSEL

CLK_EN#
GND

V5FILT

PWRMON

VR_ON

DPRSLPVR

PGOOD
PR131 PD9 4 4 PR133

1 2
PQ32

PQ33
5.76K_0402_1% 1SS355_SOD323-2 69.8K_0402_1%

2
1 2CPU_DROOP 1 DROOP DRVH1 30 UGATE_CPU1 PC117 1 2
PC102 68P_0402_50V8J 680P_0402_50V7K

1
CPU_CSP1 2 1 1 2CPU_VREF 2 29 BOOT_CPU1
1 PR135 2BOOT_CPU1-1
1 2

3
2
1

3
2
1

2
VREF VBST
PR134 470_0402_1% PC103 0.22U_0603_10V7K 2.2_0603_5% PC104 1 2CPU_SN-1
1 2
2

3 28 PHASE_CPU1 0.22U_0603_10V7K PR136 PH3

GND LL1

CPU_CSN1
CPU_CSP1
PC105 28.7K_0402_1% 100K_0603_1%_TH11-4H104FT
100P_0402_50V8J 1 2 CPU_CSP1-2 4 27 LGATE_CPU1 +CPU_B+ 1 2
1

CPU_CSN1 2 PC106 33P_0402_50V8J CSP1 DRVL1 PC107

1 +5VS

10U_1206_25V6M

10U_1206_25V6M
PR137 470_0402_1% 1 2 CPU_CSN1-1 5 CSN1 V5IN 26 1 2 0.033U_0402_16V7K

1
CPU_CSN2 2 1 PC108 33P_0402_50V8J PC109 10U_0603_6.3V6M

PC111

PC112
PR138 470_0402_1% 1 2 CPU_CSN2-1 6 CSN2
PU10
PGND 25
2

PC110 33P_0402_50V8J TPS51620RHAR_QFN40_6X6

2
PC113 1 2 CPU_CSP2-2 7 CSP2 DRVL2 24 LGATE_CPU2
100P_0402_50V8J PC114 33P_0402_50V8J 4
1

CPU_CSP2 2 1 CPU_GNDSNS 8 23 PHASE_CPU2

PR139 470_0402_1% GNDSNS LL2 PQ34
CPU_VSNS 9 22 BOOT_CPU2
1 PR140 2BOOT_CPU2-1
1 2 SI7686DP-T1-E3_SO8 PL11
VSNS VBST2
EVT_01_23 2.2_0603_5% PC115 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
CPU_THERM UGATE_CPU2 0.22U_0603_10V7K
DPRSTP#

10 THERM DRVH2 21 1 4
1

VR_TT#
0_0402_5%

0_0402_5%

1 2 CPU_CSP2-1
2 3
VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

+5VS

5
6
7
8

5
6
7
8

1
SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8
PD10
1

1
PR141

PR142

17.8K_0402_1%
1SS355_SOD323-2 PR159

PR144
4.7_1206_5%
2

11

12

13

14

15

16

17

18

19

20

B PR143 B
20K_0402_1% PR145
1CPU_DPRSTP#

1 2
4 4 69.8K_0402_1%
2

2
VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

PQ35

PQ36
PC118 1 2
680P_0402_50V7K
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

2
1 2CPU_SN-2
1 2

3
2
1

3
2
1
PR148 PH4
1

CPU_CSN2
CPU_CSP2
PR146 PR147 28.7K_0402_1% 100K_0603_1%_TH11-4H104FT
100_0402_1% 100_0402_1% 1 2
2

PC116
0.033U_0402_16V7K
PR149

PR150

PR151

PR152

PR153

PR154

PR155

PR156

PR157
2

1
VSSSENSE

VCCSENSE
+CPU_CORE

PSI#
H_DPRSTP#

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 41 of 45
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 3 of PWR

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

1 Add PC57 :10U_1206_25V_6M 0.1 38 Add PC57 :10U_1206_25V_6M 20080902 EVT

D 2 Add snubber for EMI 0.1 42 Add snubber for EMI 20080915 EVT D

3 Shift PC99 from +cpu_B+ to B+ 0.1 42 Shift PC99 from +cpu_B+ to B+ 20080915 EVT

4 Add PJ15 to B+ 0.1 39 Add PJ15 to B+ 20080915 EVT

5 PR135 and PR140 change to 0_0603_5% 0.1 42 PR135 and PR140 change to 0_0603_5% 20080915 EVT

6 Charger feedback trace too long ADD PC49 0.2 38 ADD PC49 20081124 DVT

+1.5VP: enable pin change from SUSP# to SYSON +1.5VP: enable pin change from SUSP# to SYSON
7 Power sequence error 0.2 40 20081124 DVT
+0.9VSP: enable pin change from SUSP# to SUSP +0.9VSP: enable pin change from SUSP# to SUSP
Load line over spec
8
PR131: change to 5.76K_0402_1% 0.2 42 PR131: change to 5.76K_0402_1% 20081124 DVT

Charger PR63:change to 2.2_0603_5% Charger PR63:change to 2.2_0603_5%

C 9 3D hang
PR66:Add 4.7_1206_5% 0.2 38 PR66:Add 4.7_1206_5% 20081124 DVT C
PC56:Add 680P_0402_50V7K PC56:Add 680P_0402_50V7K

+1.8VP PR97:change to 2.2_0603_5% +1.8VP PR97:change to 2.2_0603_5%

10 3D hang PR160:Add 4.7_1206_5% 0.2 39 PR160:Add 4.7_1206_5% 20081124 DVT
PC119:Add 680P_0402_50V7K PC119:Add 680P_0402_50V7K

+1.05VSP PR105:change to 2.2_0603_5% +1.05VSP PR105:change to 2.2_0603_5%

11 3D hang PR161:Add 4.7_1206_5% 0.2 39
PR161:Add 4.7_1206_5%
20081124 DVT
PC120:Add 680P_0402_50V7K PC120:Add 680P_0402_50V7K
Add bead between B+ and 1.05VSP_B+ Add bead between B+ and 1.05VSP_B+

EMI solution +5VALW/+3VALW PR37: Add 4.7_1206_5% +5VALW/+3VALW PR37: Add 4.7_1206_5%
PR41: Add 4.7_1206_5% PR41: Add 4.7_1206_5%
12 PC33:
PC34:
Add 680P_0402_50V7K
Add 680P_0402_50V7K 0.2 37
PC33:
PC34:
Add 680P_0402_50V7K
Add 680P_0402_50V7K 20081124 DVT
PR38: change to 2.2_0603_5% PR38: change to 2.2_0603_5%
B PR39: change to 2.2_0603_5% PR39: change to 2.2_0603_5% B

EMI solution +CPU CORE PR158: Add 4.7_1206_5% +CPU CORE PR158: Add 4.7_1206_5%
PR159: Add 4.7_1206_5% PR159: Add 4.7_1206_5%
PC117: Add 680P_0402_50V7K PC117: Add 680P_0402_50V7K
13 PC118: Add 680P_0402_50V7K 0.2 42 PC118: Add 680P_0402_50V7K 20081124 DVT
PR135: change to 2.2_0603_5% PR135: change to 2.2_0603_5%
PR140: change to 2.2_0603_5% PR140: change to 2.2_0603_5%

16 EMI solution +CPU CORE PC122: Reserve 2200P_0402_50V7K on B+ 0.2 +CPU CORE PC122: Reserve 2200P_0402_50V7K on B+ 20081124 DVT
42

+1.05VSP PR105 : change to 2.2_0603_5% +1.05VSP PR105 : change to 2.2_0603_5%

17 EMI solution PL12 : Add HCB4532KF-800T90_1812

PC124: Reserve 2200P_0402_50V7K on B+
0.2 39 PL12 : Add HCB4532KF-800T90_1812
PC124: Reserve 2200P_0402_50V7K on B+
20081124 DVT

PC125: Reserve 2200P_0402_50V7K on B+ PC125: Reserve 2200P_0402_50V7K on B+

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 42 of 45

5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 3

for PWR

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D D

Charger Charger
PQ20:Reserve(@)SI2301BDS-T1-E3_SOT23-3 PQ20:Reserve(@)SI2301BDS-T1-E3_SOT23-3
PQ21:Reserve(@)SSM3K7002FU_SC70-3 PQ21:Reserve(@)SSM3K7002FU_SC70-3
PR82:Reserve(@)887K_0402_1% PR82:Reserve(@)887K_0402_1%
Battery PR84:Reserve(@)0_0402_5% PR84:Reserve(@)0_0402_5%
38 PC68:Reserve(@)1000P_0402_50V7K
& HW solution PC68:Reserve(@)1000P_0402_50V7K PR87:change to 210K_0402_1%
PR87:change to 210K_0402_1%
PR88:change to 499K_0402_1%
18 PR88:change to 499K_0402_1% 0.2
39 20081124 DVT
+1.05VSP 40 +1.05VSP
PR104: Reserve(@)0_0402_5%
C PR104: Reserve(@)0_0402_5% C
PR110: change to 10K_0402_5%
PR110: change to 10K_0402_5%
PR79 : Add 0.1U_0402_16V7K
PR79 : Add 0.1U_0402_16V7K
+1.5VP
PR112: Reserve(@) 0_0402_5%
+1.5VP
PR112: Reserve(@) 0_0402_5%

+3VALWP/+3VALW +3VALWP/+3VALW

19
PC100: 680P_0402_50V7K PC100: 680P_0402_50V7K
B EMI soultion 0.3 35 PC130: 1000P_0402_50V_7K B
PC130: 1000P_0402_50V_7K
PC131: 1000P_0402_50V_8J
PC131: 1000P_0402_50V_8J 20081224 PVT
+1.5VP 40 +1.5VP
ADD PR113: 2.2_0603_5% ADD PR113: 2.2_0603_5%
ADD PR163: 4.7_1206_5% ADD PR163: 4.7_1206_5%
ADD PC121: 680P_0402_50V7K ADD PC121: 680P_0402_50V7K
ADD PL16 :FBMA-L11-322513-151LMA50T_1210 ADD PL16 :FBMA-L11-322513-151LMA50T_1210

+3VALWP/+5VALWP
20090111 PVT
A
20 POWER Solution
+3VALWP/+5VALWP
0.3 37 PR42: Reserve 61.9K_0402_1%
A
COMPAL ELECTRONICS
Title
RT8206- Fix output 5V for HW no HDMI
SCHEMATIC, M/B A4851
Size Document Number Rev
401636 D
Date: Monday, February 09, 2009 Sheet 43 of 45
5 4 3 2 1
 5 4 3 2 1

Page 2 of 2
Version change list (P.I.R. List) for PWR

Item Fixed Issue Reason for change Rev.PG# Modify List Date Phase
D D

Add PL 13 ( HCB4532KF-800T90_1812)
Add PL 14 ( FBMA-L11-322513-151LMA50T_1210) 20090112 PVT
21 EMI solution Reduce the Noise
0.3 37 Add PL 15 ( FBMA-L11-322513-151LMA50T_1210)
Add PC126 ( 100P_0402_50V8J)

Add PC128 ( 100P_0402_50V8J)

Add PC129 ( 1000P_0402_50V7K)

C PVT C
Adjust battery voltage 0.3 38 Reserve PR86 ( 100K_0402_1%)
22 Battery solution
20090112

1.8u choke saturation

change PL7 to 1UH_PCMB103E-1R0MS_20A_20% 20090113 PVT
23 Saturation current current too small 0.3 39

Change PC106 to 33P_0402_50V8J

24
B B
GP BOM Tolerance: K:+-10% ; J:+-5% Change PC108 to 33P_0402_50V8J 20090123
0.4 42 Change PC110 to 33P_0402_50V8J PVT
Change PC114 to 33P_0402_50V8J

A COMPAL ELECTRONICS A

Title
SCHEMATIC, M/B A4851
Size Document Number Rev
A D
401636
Date: Monday, February 09, 2009 Sheet 44 of 45
5 4 3 2 1
 5 4 3 2 1

11/11
1. Page 17;Un-POP R412,Q35
2. Page 32;Un-POP R340,POP R339
3. Page 32;Un-POP D3
4. Change C13,C269,C282,C482 P/N to SGA1933D10 (ESR From 15 to 9 ohm)
5. DEL HDMI Schematic (del HDMI@/NHDMI@)

D
11/19 D
1. Change C538,C539 to B size 150U
2. POP D11,D12,D29 and change P/N to SCA00000A00
11/24
1.Add LAN_CLKREQ# on CLK Gen and AR8132
11/25
1.Add C563~C568 for EMI request
2.Add L44 for EMI request
3.Add +3VS and +3V for SB HDA bus
4.Add 0 ohm resistor for Audio DVDD_IO bus
5.Add 0 ohm between +1.5V and +1.5VS
6.Add 3VS_GATE schematic on +3VALW to +3VS
7.remove c318 and D16
8.add R400 and C439 for soft-off
9.add R244 to connect +1.5v to +1.5vs
C C
11/25
1. Change R325,R311 Form 11ohm to 22 ohm
2. Change D21,D24,D28 from RB751 to CH751
3. Reserve C485,C282
12/18
1. Change R299 to 47K,ADD R470 (100K)
1/20
1. Change R299 to 22K and R470 to 120K
2. Add R570 (150U) in pgae 23
3.change board ID R273 to 33K

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/21 Deciphered Date 2010/01/21 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B A4851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401636
Date: Monday, February 09, 2009 Sheet 45 of 45
5 4 3 2 1