LIBRARY ieee;

USE ieee.std_logic_1164.all;
ENTITY part1 IS
PORT ( SW

: IN STD_LOGIC_VECTOR(17 DOWNTO 0);

KEY

: IN STD_LOGIC_VECTOR(0 DOWNTO 0);

LEDG

: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);

LEDR

: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);

END part1;

ARCHITECTURE Behavior OF part1 IS

COMPONENT flipflop
PORT ( D, Clock, Resetn, Setn : IN STD_LOGIC;
Q

: OUT STD_LOGIC);

END COMPONENT;

SIGNAL Clock, Resetn, R, G, K : STD_LOGIC;

SIGNAL y_present, y_next : STD_LOGIC_VECTOR(8 downto 0) ;

BEGIN
PROCESS (Clock, Reset)
BEGIN

Clock <= KEY(0);

Resetn <= SW(16);
K <= SW(17);

IF Reset = '1' THEN

y_present <= "000000000" ; -- resets to state A

ELSIF (Clock'EVENT AND Clock = '1') THEN

y_present <= y_next ; END IF ;
END PROCESS ;

y_next(0) <= '1';

U0: flipflop PORT MAP (y_next(0), Clock, Resetn, y_present(0));

y_next(1) <= ((y_present(8)) OR y_present(4) OR NOT y_present(0))

AND(K);
U1: flipflop PORT MAP (y_next(1), Clock, Resetn, y_present(1));

y_next(2) <= y_present(1) AND (K);

U2: flipflop PORT MAP (y_next(2), Clock, Resetn, y_present(2));

y_next(3) <= y_present(2) AND (K);

U3: flipflop PORT MAP (y_next(3), Clock, Resetn, y_present(3));

y_next(4) <= y_present(3) AND (K);

U4: flipflop PORT MAP (y_next(4), Clock, Resetn, y_present(4));

y_next(5) <= (NOT(y_present(0)) OR y_present(4) OR y_present(8)) AND

NOT (K);
U5: flipflop PORT MAP (y_next(5), Clock, Resetn, y_present(5));

y_next(6) <= ((y_present(1)) OR y_present(5)) AND NOT (K);

U6: flipflop PORT MAP (y_next(6), Clock, Resetn, y_present(6));

y_next(7) <= ((y_present(2)) OR y_present(6)) AND NOT (K);

U7: flipflop PORT MAP (y_next(7), Clock, Resetn, y_present(7));

y_next(8) <= ((y_present(3)) OR y_present(7)) AND NOT (K);

U8: flipflop PORT MAP (y_next(8), Clock, Resetn, y_present(8));

G <= y_present(4) OR y_present(8);

R <= (NOT y_present(4)) OR (NOT y_present(8));
LEDR(8 DOWN TO 0) <= R;
LEDR (17 DOWN TO 9)<= y_present(8 DOWNTO 0);
LEDG (4 DOWN TO 0) <= G;

END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY flipflop IS
PORT ( D, Clock, Resetn, Setn : IN STD_LOGIC;
Q

: OUT STD_LOGIC);

END flipflop;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF (Resetn = '0') THEN -- synchronous clear
Q <= '0';
ELSIF (Setn = '0') THEN -- synchronous set
Q <= '1';

ELSE
Q <= D;
END IF;
END IF;
END PROCESS;
END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- A sequence detector FSM
-- SW0 is the active low synchronous reset, SW1 is the w input, and KEY0 is the
clock.
-- The z output appears on LEDG0, and the state is indicated on LEDR8..0
ENTITY part2 IS
PORT ( SW

: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

KEY

: IN STD_LOGIC_VECTOR(0 DOWNTO 0);

LEDG

: OUT STD_LOGIC_VECTOR(0 DOWNTO 0);

LEDR

: OUT STD_LOGIC_VECTOR(8 DOWNTO 0));

END part2;

ARCHITECTURE Behavior OF part2 IS

SIGNAL Clock, Resetn, K, R, G : STD_LOGIC;
TYPE State_type IS (A, B, C, D, E, F, G, H, I);
SIGNAL y_present, y_next : State_type;
BEGIN
Clock <= KEY(0);
Resetn <= SW(16);
K <= SW(17);

PROCESS (K, y_present) -- state table

BEGIN
CASE y_present IS
WHEN A => IF (K = '1') THEN y_next <= B;
ELSE y_next <= F;
END IF;
WHEN B => IF (K = '1') THEN y_next <= C;
ELSE y_next <= G;
END IF;
WHEN C => IF (K = '1') THEN y_next <= D;
ELSE y_next <= H;
END IF;
WHEN D => IF (K = '1') THEN y_next <= E;
ELSE y_next <= I;
END IF;
WHEN E => IF (K = '1') THEN y_next <= F;
ELSE y_next <= B;
END IF;
WHEN F => IF (K = '0') THEN y_next <= G;
END IF;
WHEN G => IF (K = '0') THEN y_next <= H;
END IF;
WHEN H => IF (K = '0') THEN y_next <= I;
END IF;
WHEN I => IF (K = '1') THEN y_next <= B;
ELSE y_next <= F;
END IF;
WHEN OTHERS => y_next <= A;

END CASE;
END PROCESS; -- state_table

PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF (Resetn = '0') THEN -- synchronous clear
y_present <= A;
ELSE
y_present <= y_next;
END IF;
END IF;
END PROCESS;

R <= '0' WHEN ((y_present = E) OR (y_present = I)) ELSE '1';

G <= '1' WHEN ((y_present = E) OR (y_present = I)) ELSE '0';
LEDR(17 DOWN TO 10) <= R;
LEDG(4 DOWN TO 0) <= G;

PROCESS (y_present) -- drive the red LEDs for each state

BEGIN
LEDR <= "000000000";
case y_present IS
WHEN A => LEDR <= "000000000";
WHEN B => LEDR <= "000000011";
WHEN C => LEDR <= "000000101";
WHEN D => LEDR <= "000001001";

WHEN E => LEDR <= "000010001";

WHEN F => LEDR <= "000100001";
WHEN G => LEDR <= "001000001";
WHEN H => LEDR <= "010000001";
WHEN I => LEDR <= "100000001";
END CASE;
END PROCESS; -- LEDs

END Behavior;