entity DFF is

Port ( data : in STD_LOGIC;

clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF;
architecture Behavioral of DFF is
begin
process(clk,reset) begin
if (reset = '1') then
Q <= '0';
elsif(clk'event and clk = '1') then
Q <= data;
end if;
end process;
end Behavioral;

entity Johnson_Counter is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0));
end Johnson_Counter;
architecture Behavioral of Johnson_Counter is
component DFF is
Port ( data : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal w,x,y,z,f: std_logic;
begin
f<=not w;
U3: DFF port map (f,clk,reset,x);
U2: DFF port map (x,clk,reset,y);
U1: DFF port map (y,clk,reset,z);
U0: DFF port map (z,clk,reset,w);
led(0)<= (not x )and (not w);
led(1)<= x and (not y);
led(2)<= (not z) and y;
led(3)<= z and (not w);
led(4)<= x and w;
led(5)<= (not x) and y;
led(6)<= z and (not y);

led(7)<= w and (not z);

end Behavioral;