Verilog Quiz # 1

Use Verilog to describe the 2:1 multiplexer as shown in the following figure.

1. Use gate-level modeling.

module mux2_1 (SEL, A, B, OUT)

OR
(

input SEL, A, B;
) ;

output OUT ;
NOT (

endmodule

) ;

2. Use continuous assignment

statements.

AND

module mux2_1 (SEL, A, B, OUT)

(
) ;

input SEL, A, B;
output OUT ;

AND

assign Out

=
) ;

;
endmodule

3. Use an "always" procedure block.

module mux2_1 (SEL, A, B, OUT)
input SEL, A, B;
output OUT ;
reg OUT ;
always
@(
) begin
if (SEL)

;
else

;
end
endmodule