Stressing of redundant memory bits during burn-in test

Mayank Parasrampuria, Neetin Singh: Freescale Semiconductor

Introduction
Burn-in stressing of a SOC has a few disadvantages, one of them being non-uniform stressing of logic. Here
we will discuss non-uniform stressing of memories logic.
Device when under burn-in stress can have repaired or non-repaired memories. If device has a repaired
memory then only the selected redundant columns (or rows) of memory will be accessed during the burnin stress and the un-used remaining redundant columns (or rows) will not be accessed which will leave
certain portion of memory un-stressed. Similar is the case with a non-repaired memory, here all the
redundant columns (or rows) are left un-stressed. This translates into inability to repair a device after
burn-in and infield repair. If repair (after burn-in or infield) is attempted, it will expose an un-stressed
logic, which means reliability concerns.

Proposed Design Change:

A circuit which get active during Memory BIST burn-in mode and enables the access to every redundant
column or row) of memory during the burn-in run. By this circuit uniform stressing of all redundant
columns (or rows) is achieved.
The proposed circuit has the following components:
1. Event detector: detects the completion of selected March Algorithm run of Memory BIST during
BURNIN.
2. Repair data logic controller: Changes the data loaded into the repair data register after completion
of each full Memory BIST run to ensure a uniform stress distribution.
Event
Counter

Repair Data
Calculator

Control override
during stress mode

Repair data & control signals

from repair data calculator
Repair data & control signals
to repair data register
Repair
Logic/Processor
Repair data & control signals
from repair controller

Repair information is loaded by Memory BIST controller from the fuse or flash into the repair data register
which enable the replacement of faulty column (or row) with the redundant columns (or rows) in-order
to repair a device.
During the Memory BIST burn-in stressing, the BIST is set to run in an infinite loop, here the event detector
detects the completion of selected MARCH Algorithm run and with each run completion its generates a
trigger which goes to repair data calculator and changes the selected column (or row) as faulty and
resulting in removing it from test for that run. This process repeats for each run, selecting a new column
(or row) as faulty. This process results in applying a uniform stress on the memory during the process.

Memory BIST Burn-in starts

Repair Data Register equal to all zero

Run initiated

Event detector detects run

completion

New
run

Increment the contents of repair

data register. If it contains all 1s
then reset to all 0s.

Memory BIST Bunin Run Complete

(Terminated by Test Engineer based on
stressing requirements)

Conclusion
With the above proposed circuitry in place, we can ensure that during burn-in stressing of memories the
entire memory array is uniformly stressed. This circuit does not require any change in in memory design
or Memory BIST logic, so is easy to implement.
Additionally this is a fully automated process (achieved via hardware), which does not require any input
or control from outside the device, which fits well with the burn-in tester requirements of minimum
interactions during testing.