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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
Port ( Clk : in STD_LOGIC;
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector(3 downto 0);
R : out std_logic_vector(3 downto 0);
op: in std_logic_vector(3 downto 0);
Nul : out boolean;
Cout : out STD_LOGIC);
Cin, x, y
s, Cout

: IN

STD_LOGIC;

: OUT

STD_LOGIC;

end ALU;

architecture behavioral of alu is


type op_type is ( op_a_suma_b, op_a_resta_b , op_a_inc_uno , op_a_dec_uno ,
op_a_mul_b , op_a_div_b , op_a_comp_b , op_a_and_b,
op_a_nand_b, op_a_or_b,
op_a_nor_b,op_a_xor_b,
op_a_nexor_b,op_not_a ,op_not_b , op_nsu);

BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;

signal enum_op : op_type ;


signal a_minus_b : std_logic_vector ( 3 downto 0 );
signal a_plus_b : std_logic_vector ( 3 downto 0 );

signal reg

: std_logic_vector ( 3 downto 0 );

begin

a_minus_b <= std_logic_vector ( signed ( a ( a 'high ) & a ) - signed ( b ( b


'high ) & b ));
a_plus_b <= std_logic_vector ( signed ( a ( a 'high ) & a ) + signed ( b ( b
'high ) & b ));
a_inc1 <= std_logic_vector (signed ( a ( a 'high ) & a ) + '0001' );

process ( op )
begin
case op is
when "0000" => enum_op <= op_a_suma_b,
when "0001" => enum_op <= op_a_resta_b,;
when "0010" => enum_op <= op_a_inc_uno ;
when "0011" => enum_op <= op_a_dec_uno ;
when "0100" => enum_op <= op_a_mul_b ;
when "0101" => enum_op <= op_a_div_b ;
when "0110" => enum_op <= op_a_comp_b ;
when "0111" => enum_op <= op_nsu ;
when "1000" => enum_op <= op_a_and_b ;
when "1001" => enum_op <= op_a_nand_b;
when "1010" => enum_op <= op_a_or_b;
when "1011" => enum_op <= op_a_nor_b;
when "1100" => enum_op <= op_a_xor_b ;
when "1101" => enum_op <= op_a_nexor_b ;
when "1110" => enum_op <= op_not_a ;
when "1111" => enum_op <= op_not_ b ;
when others => enum_op <= op_nsu ;

end case ;
end process ;

process ( clk )
begin
if rising_edge ( clk ) then
case enum_op is

when op_a_suma_b => reg <= a(0)+b(0), a(1)+b(1), a(2)+b(2),


a(3)+b(3);

when op_a_resta_b => reg <= a or (not b) ;


when op_a_inc_uno => reg <= ;
when op_a_dec_uno ;
when op_a_mul_b => reg <= a and b ;
when op_a_div_b ;
when op_a_comp_b =>
reg ( 4 ) <= '0' ;
reg ( 3 downto 1 ) <= ( others => '0' );
reg ( 0 ) <= a_minus_b ( 4 );
when op_nsu => reg ( 4 ) <= '0' ;
when op_a_and_b => reg <= a and b;
when op_a_nand_b => reg <= not (a and b);
when op_a_or_b => reg <= a or b ;
when op_a_nor_b => reg <= a or (not b);
when op_a_xor_b => reg <= a xor b ;
when op_a_nexor_b => reg <= not (a xor b);

when op_not_a => reg <= not a;


when op_not_ b => reg <= not b;
when op_nsu

=>

reg ( 4 ) <= '0' ;


end if ;
end process ;

y <= reg ( 3 downto 0 );


count <= reg ( 4 );
nul <= unsigned ( reg ) = '0' ;

end architecture ;

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