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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Clk : in STD_LOGIC;
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector(3 downto 0);
R : out std_logic_vector(3 downto 0);
op: in std_logic_vector(3 downto 0);
Nul : out boolean;
Cout : out STD_LOGIC);
Cin, x, y
s, Cout
: IN
STD_LOGIC;
: OUT
STD_LOGIC;
end ALU;
BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
signal reg
: std_logic_vector ( 3 downto 0 );
begin
process ( op )
begin
case op is
when "0000" => enum_op <= op_a_suma_b,
when "0001" => enum_op <= op_a_resta_b,;
when "0010" => enum_op <= op_a_inc_uno ;
when "0011" => enum_op <= op_a_dec_uno ;
when "0100" => enum_op <= op_a_mul_b ;
when "0101" => enum_op <= op_a_div_b ;
when "0110" => enum_op <= op_a_comp_b ;
when "0111" => enum_op <= op_nsu ;
when "1000" => enum_op <= op_a_and_b ;
when "1001" => enum_op <= op_a_nand_b;
when "1010" => enum_op <= op_a_or_b;
when "1011" => enum_op <= op_a_nor_b;
when "1100" => enum_op <= op_a_xor_b ;
when "1101" => enum_op <= op_a_nexor_b ;
when "1110" => enum_op <= op_not_a ;
when "1111" => enum_op <= op_not_ b ;
when others => enum_op <= op_nsu ;
end case ;
end process ;
process ( clk )
begin
if rising_edge ( clk ) then
case enum_op is
=>
end architecture ;