Beruflich Dokumente
Kultur Dokumente
INSTRUMENTS
Theory, Algorithms,
and Implementations
Volume 3
1990
Volume 3
Edited by
Panos Papamichalis, Ph.D.
Digital Signal Processing
Semiconductor Group
Texas Instruments
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
CONTENTS
v
FOREWORD ....... .
PREFACE ............. .
. ......... vii
PART I. INTRODUCTION
1. The TMS320 Family and Book Overview ................................................... .
iii
PART V. COMPUTERS
12. A DSP-Based Three-Dimensional Graphics System
(Nat Seshan) ........................................................................... 423
PART VI. TOOLS
13. The TMS320C30 Applications Board Functional Description
(Tony Coomes and Nat Seshan) ........................................................... 467
TMS320 BIBLIOGRAPHY .................................................................... 533
iv
Foreword
Much has happened in the TMS320 Family since Volume 1 of Digital Signal Processing
Applications with the TMS320 Family was published, and Volumes 2 and 3 are a timely update to
the family history.
The DSP microcomputers keep changing the perspective of the systems designers by offering more computational power and better interfacing capabilities. The steps of change are coming
more quickly, and the potential impact is greater and greater. Because things change so rapidly in
this area, there is a pressing need for ways to quickly learn how to utilize the new technology. These
new volumes respond to that need.
As with Volume 1, the purpose of these books is to teach us about the issues and techniques
that are important in implementing digital signal processing systems using microprocessors in the
TMS320 Family. Volume 2 highlights the TMS320C25; and Volume 3, the TMS320C30 chip. A
large part of the books is devoted to such matters as characteristics of the TMS320C25 and
TMS320C30 chips, useful program code for implementing special DSP functions, and details on
interfacing the new chips to external devices. The remainder of the books illustrates how these
chips can be used in communications, control, and computer graphics applications.
What these two volumes make clear is how remarkably fast the field ofDSP microcomputing
is evolving. IC technologists and designers are simply packing more and more of the right kind of
computing power into affordable microprocessor chips. The high-speed floating-point computing
power and huge address spaces of chips like the TMS320C30 open the door to a whole new class
of applications that were difficult or impractical with earlier generations of fixed-point DSP chips.
The signal processing theorists and system designers are clearly being challenged to match the creativity of the chip designers.
The present books differ from Volume 1 in the inclusion of a small section on tools. This is
a hopeful sign, because it is progress in this area that is likely to have the greatest impact on speeding
the widespread application of DSP microprocessors. While useful design tools are beginning to
emerge, much more can be done to help system designers manage the complexity of sophisticated
DSP systems, which often involve a unique combination of theory, numerical and symbolic processing algorithms, real-time programming, and multiprocessing. No doubt future volumes ofDigital Signal Processing Applications with the TMS320 Family will have more to say about this important topic. Until then, Volumes 2 and 3 have much useful information to help system designers
keep up with the TMS320 Family.
Ronald W. Schafer
Atlanta, Georgia
November 14, 1989
vi .
Preface
The newer, floating-point DSP devices, such as the TMS320C30, have brought an added dimension to DSP applications. With the TMS20C30, programming is much easier because the designer does not have to worry about dynamic range and accuracy issues. An algorithm implemented
in floating-point in a high-level language can be easily ported to such a device. The new architecture
contains other features, besides the floating point capability, that simplify programming. Some of
these features (such as the software stack, the large register file, etc.) were added to facilitate the
development of high-level language compilers. Currently, C and Ada compilers have been introduced. In addition, Spectron Microsystems introduced an operating system for DSPs (called
SPOX) that further facilitates the development of algorithms on the DSP devices.
Volume 3 of Digital Signal Processing Applications with the TMS320 F amity contains application reports primarily on the third generation of the TMS320 Family (floating-point devices).
This book is a continuation of Volumes 1 and 2 in the sense that it addresses the same needs of the
designer. The designer still has the task of selecting the DSP device with the appropriate cost, performance, and support, developing the DSP algorithm that will solve the problem, and implementing the algorithm on the processor. This volume tries to help by bringing the designer up to date
on the applications of newer processors or in different applications of earlier processors.
The objectives remain the same as in earlier volumes. First, the application reports supply
examples of device use and serve as tutorials in programming the devices. Of course, the same purpose is served on a more elementary basis by the software and hardware applications sections of
the corresponding user's guides. Second, since the source code of each application is provided with
the report, the designer can take it intact (or extract a portion of it) and place it in the application.
I t is assumed that the reader has exposure to the TMS320 devices or, at least, has the necessary
manuals (such as the appropriate TMS320 user's guides) that will help the reader understand the
explanations in the reports. The reports themselves include as references the necessary background
material. Additionally, the Introduction gives a brief overview of the available devices at the time
of the writing and points to the source of more information.
The reports are grouped by application area. The term report is used here in a broad sense,
since some articles from technical publications are also included. The authors of the reports are either the digital signal processing engineering staff of the Texas Instruments Semiconductor Group
(including both field and factory personnel, and sUmmer students) or third parties.
The source code associated with the reports is also available in electronic form, and the reader
can download it from the TI DSP Electronic Bulletin Board (telephone (713) 274-2323). If more
information is needed, the DSP Hotline can be called at (713) 274-2320.
The editor thanks all the authors and the reviewers for their contribution to this volume of
application reports.
Panos E. Papamichalis, Ph.D.
Senior Member of Technical Staff
vii
viii
Part I. Introduction
1. The TMS320C20 Family and Book Overview
TMS320C4x
*TMS320C40
TMS320C30
*TMS320C3026,-I--'-"'--_ _
*TMS320C31
e f
I
TMS320C2x
o
o p
r
TMS320Clx
m /
a m
n i
C P
e s
TMS320Cl0, 14
TMS320Cl025
TMS320C15/E15
TMS320C1525
TMS320C17/E17
TMS320C14/E14
TMS32020
TMS320C25
TMS320E25
TMS320C2550
*TMS320C26
*TMS320C50
*TMS320C51
Generation
The following article, "The TMS320 Family of Digital Signal Processors," by Lin, et. al.,
is reprinted from the Proceedings of the IEEE and gives an overview of the TMS320 family. Since
additional devices have been developed from the time the article was written, this section highlights
these newer devices. Table 1 shows a comprehensive list ofthe currently available TMS320 devices
and their salient characteristics.
1st
2nd
Data
Type
Device
TMS320ClO ~
TMS320ClO-25
TMS320ClO-14
TMS320E14
TMS320C15'
TMS320CI5-25
TMS320E15'
TMS320E15-25
TMS320C17
TMS320EI7
Integer
Integer
Integer
Integer
TMS32020 ~
TMS320C25 ~
TMS320C25-50'
TMS320E25'
TMS320C26
Time
RAM
(ns)
Integer
Integer
Integer
Integer
Integer
200
160
280
160
200
160
200
160
200
200
144
144
144
256
256
256
256
256
256
256
Integer
Integer
Integer
Integer
Integer
200
100
80
100
100
544
544
544
544
UK
Integer
~
Cycle
OnChip
ROM
EPROM
UK
I.5K
UK
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
256
I/O
aITChip
8x16
8xl6
8xl6
7x16
8x16
8xl6
8xl6
8x16
6xl6
6xl6
128K
128K
128K
128K
128K
16xl6
16xl6
16xl6
16xl6
1
1
1
1
1
16Mx32
16xl6
3rd
TMS320C30
Float Pt
60
2K
4K
16M
TMS320C50
Integer
50
8.5K
2K
128K
Serial
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
5th
t
t
Parallel
DMA
OnChip
Timers
Package
2
2
1
1
DIPIPLCC
DlPIPLCC
DIPIPLCC
CERQUAD
DIPIPLCC
DIPIPLCC
DIP/CERQUAD
DIP/CERQUAD
DIPIPLCC
DIP/CERQUAD
t
t
t
t
t
1
1
1
1
1
PGA
PGAlPLCC
PGAlPLCC
CERQUAD
PLCC
PGA
CLCC
External DMA
Extemalnntemal DMA
For information on military versions of these devices, contact your local 11 sales office.
The additions to the first generation are the TMS320C14 and the TMS320E14; the latter is
identical with the former, except that the latter's on-chip program memory is EPROM. The
TMS320C14/E14 devices have features that make them suitable for control applications. Figure
2 shows the components of these devices. The memory and the CPU are identical to
TMS320C15/E15, while the peripherals reflect the orientation of the devices toward control.
16x16-bit
Multiply
32-bitALU
Watchdog Timer
32-bit ACC
0,1 A-bit Shift
Timer/Counter 2
16 bitl/O
32-bit P-Reg
2 Auxiliary Registers
SERIAL PORT
Event Manager
tation of certain applications, the TMS320C25-50 was designed as a faster version of the
TMS320C25 and has a clock frequency of 50 MHz instead of 40 MHz.
The TMS320C26 is a modification of the TMS320C25 in which the program ROM has been
exchanged for RAM. The memory space of the TMS320C26 has l.5K words of on-chip RAM and
256 words of on-chip ROM, making it ideal for applications requiring larger RAM but minimal
external memory.
A new generation of higher-performance fixed-point processors has been introduced in the
TMS320 Family: the TMS320C5x devices. This generation shares many features with the first and
the second generations, but it also encompasses significant new features. Figure 3 shows the basic
components of the first device in that generation, the TMS320C50.
Serial Port
Timer
S{WWaitsts
16x16
Inputs
16x16
Outputs
The software and hardware development tools for the TMS320 family make the development of applications easy. Such tools include assemblers, linkers, simulators, and Ccompilers for
the software. They include evaluation modules, software development boards, and extended development systems for hardware. These tools are mentioned in the following paper by Lin, et. al. The
interested reader can find much more information in the additional literature that is published by
Texas Instruments and mentioned in the next section. In particular, the TMS320 Family Development Support Reference Guide is an excellent source.
One important addition to the list of tools is the SPOX operating system, developed by Spectron Microsystems. SPOX permits you to write an application in a high-level language (C) and run
it on actual DSP hardware. The operating system of SPOX hides the details of the interface from
you and lets you concentrate on your algorithm while running it at supercomputer speeds on the
TMS320C30.
References
Texas Instruments publishes an extensive bibliography to help designers use the TMS320 devices effectively. Besides the user's guides for corresponding generations, there are manuals for
the software and the hardware tools. The TMS320 Family Development Support Reference Guide
is particularly useful because it provides information, not only on development tools offered by TI,
but also on those produced by third parties. Here is a partial list of the literature available (the literature number is in parentheses)
TMS320 Family Development Support Reference Guide (SPRUOllA)
TMS320Clx User's Guide (SPRU013A)
You can request this literature by calling the Customer Response Center at 1-800-232-3200,
or the DSP Hotline at 1-713-274-2320.
10
Kun-Shan Lin
Gene A. Frantz
Ray Simar, Jr.
Digital Signal Processor Products-Semiconductor Group
Texas Instruments
Reprinted from
PROCEEDINGS OF THE IEEE
Vol. 75, No.9, September 1987
11
12
IEEE,
GENE A. FRANTZ,
AND
This paper begins with a discussion of the characteristics of digital signal processing, which are the driving force behind the design
of digital signal processors. The remainder of the paper describes
the three generations of the TMS320 family of digital signal processors available from Texas Instruments. The evolution in architec-
tural design of these processors and key features of each generation of processors are discussed. More detailed information ~s
real-time operation,
= 2:
;=1
ali) x(n - i)
.! din
(1)
where yin) is the output sample at time n, ali) is the ith coefficient or weighting factor, and x(n - i) is the (n - i)th input
sample.
With this example in mind, we can discuss the various
- 1)
.! din
5
- 3) +
+.!'d(n-5)
.! din
- 2)
.! din
5
- 4)
(2)
where din - i) is the daily stock closing price for the (n i)th day. Equation (2) assumes the same form as (1). This is
also the general form of the convolution of two sequences
of numbers, ali) and xli) [5], [6]. Both FIR filtering and convolution are fundamental to digital Signal processing.
Real Time Processing
In addition to being mathematically intensive, DSP algorithms must be performed in real time. Real time can be
defined as a process that is accomplished by the DSP without creating a delay noticeable to the user. In the stock market example, as long as the new average value can be computed priortothe next day when it is needed, it is considered
to be completed in real time. In digital signal processing
applications, processes happen faster than on a daily basis.
In the FIR filter example in (1), the sum of products must
13
able delay between a word being spoken and being recognized would be unacceptable and not considered realtime. Another example is in image processing, where it is
considered real-time if the processor finishes the processing within the frame update period. If the pixel information
cannot be updated within the frame update period, problems such as flicker, smearing, or missing information will
occur.
Application
Control
Telecommunications
Speech processing
Audio processing
Video frame rate
Video pixel rate
Nominal
Sample Rate
1 kHz
'8 kHz
8-10 kHz
40-48 kHz
30 Hz
14MHz
14
A recent development in DSP technology is the singlechip digital Signal processor, such as the TMS320 family of
processors. These processors give the designer a DSP solution with its performance attainable only by the array processors a few years ago. Fig. 1 shows the TMS320 family in
graphical form with the y-axis indicating the hypothetical
performance and the x-axis being the evolution of the semiconductor processing technology. The first member of the
family, the TMS32010, was disclosed to the market in 1982
[11], [12]. It gave the system designer the first microcomputer capable of performing five million DSP operations
per second (5 MIPS), including the add and multiply functions [13] required in (1). Today there are a dozen spinoffs
from the TMS32010 in the first generation of the TMS320
family. Some of these devices are the TMS320C10,
TMS320C15, and TMS320C17 [14]. The second generation
of devices include the TMS32020 [15] and TMS320C25 [16].
The TMS320C25 can perform 10 MIPS [16]. In addition,
expanded memory space, combined single-cycle multiply/
accumulate operation, multiprocessing capabilities, and
expanded I/O functions have given the TMS320C25 a
2 to 4 times performance improvement over its predecessors. The third generation of the TMS320 family of processors, the TMS320C30 [26], [27]. has a computational rate ot'
33 million DSP floating-point operations per second (33
MFlOPS). Its performance (speed, throughput, and precision) has far exceeded the digital Signal processors available today and has reached the level of a supercomputer.
It we look closely at the TMS320 family as shown in Fig.
1, we can see that devices in the same generation, such as
the TMS320C10, TMS320C15, and TMS320C17, are assembly
object-code compatible. Devices across generations, such
as the TMS320C10 and TMS320C25, are assembly sourcecode compatible. Software investment on DSP algorithms
therefore can be maintained during the system upgrade.
Another point is that since the introduction of the
TMS32010, semiconductor processing technology has
emerged from 3-l'm NMOS to 2-l'm CMOS to 1-l'm CMOS.
2.0~m
CMOS
These concepts were designed into the TMS320 digital signal processors to handle the vast amount of data characteristic of DSP operations, and to allow most DSP operations to be executed in a single-cycle instruction.
Furthermore, the TMS320 processors are programmable
devices, providing the flexibility and ease of use of generalpurpose microprocessors. The following paragraphs discuss how each of the above concepts is used in the TMS320
family of devices to make them useful in digital signal processing applications.
Harvard Architecture
15
CLKOUT1
Pfefetch
decode
execute
N-2
N-1
(the closing price five days ago) was dropped and a new one
(today's closing price) was added. Or, each piece of the old
data is delayed or moved one sample period to make room
for the incoming most current sample. This delay is the
function of the DMOV instruction. Another special instruction in the TMS32010 is the LTD instruction. It executes the
LT, DMOV, and APAC instructions in a single cycle. The LTD
and MPY instruction then reduce the number of instruction
cycles per FIR filtertap from four to two. In the second-generation TMS320, such as the TMS320C25, two more special
instructions have been included (the RPT and MACD
instructions) to reduce the number of cycles per tap to one,
as shown in the following:
RPTK 255
MACD
(N
1)
DedicatedHardware Multiplier
As we saw in the general form of an FIR filter, multiplication is an important part of digital signal processing. For
each filter tap (denoted by i), a multiplication and an addition must take place. The faster a multiplication can be performed, the higher the performance of the digital signal
processor. In general-purpose microprocessors, the multiplication instruction is constructed by a series of addi-
16
give the DSP devices instruction cycle times less than 200
ns. The speCific instruction cycle times for the TMS320 family are given in Table 2. These fast cycle times have made
Table 2 TM5320 Cycle Times
Cycle Time
Device
(ns)
TMS320C10'
TMS32020
TMS320C25
TMS320C30
160-200
160-200
100-125
60-75
the TM5320 family of processors highly suited for mahy realtime DSP applications. Table 1 showed the sample rates for
some typical DSP applications. This table can be combined
with the cycle times indicated in Table 2 to show how many
instruction cycles per sample can be achieved by the various generations of the TMS320 for real-time applications
(see Fig. 3).
As we can see from Fig. 3, many instruction cycles are
Third-Generation TMS320
5000
Second-Generation TMS320
First-Generation TMS320
600
0
l
50
I
0
1 kHz
I
0
E
0
c
0
M
j j
10 kHz
100 kHz
10 MHz
Sample Rata
Fig. 3. Number of instruction cycles/sample versus sample rate for the TMS320 family_
ond and third generations of the TMS320 with their multiprocessing capabilities and high throughput are better
suited.
Now that we have discussed the basic characteristics of
digital Signal processors, we can concentrate on specific
details of each of the three generations of the TMS320 family devices.
THE FIRST GENERATION
OF
17
I.
WE
DEN
MEN
BiO
INSTRUCTION
MC/MP
iNf
PROGRAM
OS
ROM
11536 x 161
LEGEND:
DATA RAM
1144" 161
Ace == Accumulator
AAP =
ARO =
Auxiliary register 0
DATA
PC
'" P register
T register
I.
I.
18
TMS320C151E15
The TMS320C15 and TMS320E15 are fu lIy object-code and
pin-for-pin compatible with the TMS32010 and offer
expanded on-chip RAM of 256 words and on-chip program
ROM (TMS320C15) or EPROM (TMS320E15) of 4Kwords. The
TMS320C15 is available in either a 200ns version or a 160ns version (TMS320C15-25).
TMS320C171E17
The TMS320C17/E17 is a dedicated microcomputer with
4K words of on-chip program ROM (TMS320C17) or EPROM
(TMS320E17), a dualchannel serial port for full-duplex serial
communication, on-chip companding hardware (u-Iawl
Alaw), a serial port timer for stand-alone serial communication, and a coprocessor interface for zero glue interface
between t~e processor and any 4lB/16-bit microprocessor.
The TMS320C17/E17 isalsoobject-code compatible with the
TMS32010 and can use the same development tools. The
Instruction
Cycle Time
Devices
(ns)
Process
TMS32010
TMS32010-25
TMS32010-14
TMS32011
TMS320Cl0
TMS320Cl0-25
TMS320C15
TMS320C15-25
TMS320E15
TMS320C17
TMS320C17-25
TMS320E17
200
160
280
200
200
160
200
160
200
200
160
200
NMOS
NMOS
NMOS
NMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
On-Chip
Prog ROM
(words)
OF
On-Chip
Data RAM
Off-Chip
(words)
(words)
(words)
Ref
144
144
144
144
144
144
256
256
256
256
256
256
4K
4K
4K
[13]
[13]
[13]
[17]
[13]
[13]
[13]
[14]
1.5K
1.5K
l.5K
I.5K
l.5K
l.5K
4.0K
4.0K
4.0K
4.0K
4.0K
On-Chip
Prog EPROM
forms (TMS320C25).
Extended-precision arithmetic and adaptive filtering
support (TMS320C25).
Full-speed operation of MAC/MACD instructions from
external memory (TMS320C25).
Accumulator carry bit and related instructions
(TMS320C25).
1.B-l'm CMOS technology (TMS320C25):
-6B-pin grid array (PGA) package.
-6B-pin lead chip carrier (PLCC) package.
2.4-l'm NMOS technology (TMS32020):
-68-pin PGA package.
4.0K
Prog
4K
4K
4K
4K
4K
[14]
[14]
[14]
[14]
TMS320C25 Architecture
The TMS320C25 is the latest member in the second generation ofTMS320 digital signal processors. It is a pin-compatible CMOS version of the TMS32020 microprocessor,
but with an instruction cycle time twice as fast and the inclusion of additional hardware and software features. The
instruction set is a superset of both the TMS32010 and
TMS32020, maintaining source-code compatibility. In addition, it is completely object-code compatible with the
TMS32020 so that TMS32020 programs run unmodified on
the TMS320C25.
The 100-ns instruction cycle time provides a significant
throughput advantage for many existing applications. Since
most instructions are capable of executing in a single cycle,
the processor is capable of executing ten million instruc-
19
RIW
STRB
READY
iiii
XF
MP/MC
0012-01-+'----'
A1S-AO
D)(R(161
TlM{161
PROl161
IMRt61
GREGIBI
01500
LEGEND'
ACCH
- Accumulator high
ACCl
AlU
ARAU
ARB
ARP
OP
ORR
OXR
~
~
~
=.
=
Accumulator low
Arithmetic logic unit
Audla.y ,egiste. arithmetic unit
AUkiliel.,. regisle. pointe. buffer
AUk,lia.v regi$ler pointer
Oal8 memory pege pointer
Serial port data receive legister
Serial port data transmit register
IFR
PC
PFC
- Prefetch counter
IR
RPTC
GREG
RSR
XSR
AROAR7
STO.ST1
_
_
_
QlR
PRO
TIM
- Product .egister
Period 'egiste. for lime.
- Timer
Pfo9.em counter
- Tempore.y regisle.
20
a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32bit Arithmetic logic Unit (AlU), and a 32bit accumulator.
The scaling shifter has a 16-bit input connected to the data
bus and a 32bit output connected to the AlU. This shifter
produces a leftshift of 0 to 16 bits on the input data, as programmed in the instruction. Additional shifters at the outputs of both the accumulator and the multiplier are suitable
for numerical scaling, bit extraction, extended-precision
arithmetic, and overflow prevention.
21
Operation
direct addressing
indirect; no change to AR.
indirect; current AR is incremented.
indirect; current AR is decremented.
indirect; ARO is added to current AR.
indirect; ARO is subtracted from
current AR.
indirect; ARO is added to current AR
(with reverse carry propagation).
indirect; ARO is subtracted from
current AR (with reverse carry
propagation),
Note: The optional NARP field specifies a new value of the ARP.
The flexibility of the TMS320C25 allows systems configurations to satisfy a wide range of application requirements
[16]. The TMS320C25 can be used in the following configurations:
a stand-alone system (a single processor using 4K
words of on-chip ROM and 544words of on-chip RAM),
parallel multiprocessing systems with shared global
data memory, or
host/peripheral coprocessing using interface control
signals.
A minimal processing system is shown in Fig. 6 using
external data RAM. and PROM/EPROM. Parallel multiprocessing and host/peripheral coprocessing systems can be
designed by taking advantage of the TMS320C25's direct
memory access and global memory configuration capabilities.
TMS320
FAMILY
The TMS320C30 [26]-[27] is Texas Instruments third-generation member of the TMS320 family of compatible digital
signal processors. With a computational rate of 33 MFLOPS
(million floating-point operations per second), the
TMS320C30 far exceeds the performance of any programmable DSP available today. Total system performance has
been maximized through internal parallelism, more than
twenty-four thousand bytes of on-chip memory, Single-cycle
floating-point operations, and concurrent I/O. Thetotal system cost is minimized with on-chip memory and on-chip
peripherals such as timers qnd serial ports. Finally, the user's
system design time is dramatically reduced with the availability of the floating-point operations, general-purpose
instructions and features, and quality development tools.
The TMS320C30 provides the user with a level of performance that, at one time, was the exclusive domain of
supercomputers. The strong architectural emphasis of providing a low-cost system solution to demanding arithmetic
algorithms has resulted in the architecture shown in Fig. 7.
The key features of the TMS320C30 [26], [27] are as follows:
60-ns single-cycle execution time, l-l'm CMOS.
Two 1K x 32-bit Single-cycle dual-access RAM blocks.
One 4K x 32-bit single-cycle dual-access ROM block.
64 x 32-bit instruction cache.
32-bit instruction and data words, 24-bit addresses.
32/40bit floating-pOint and integer multiplier.
32/40-bit floating-point, integer, and logical ALU.
32-bit barrel shifter.
Eight extended-precision registers.
Two address-generators with eight auxiliary registers.
On-chip Direct Memory Access (DMA) controller for
concurrent I/O and CPU operation.
Peripheral bus and modules for easy customization.
High-level language support.
Interlocked instructions for multiprocessing support.
Zero overhead loops and single-cycle branches.
The architecture of the TMS320C30 is targeted at 60-ns
and faster cycle times. To achieve such high-performance
Fig. 6. Minimal processing system With external data RAM and PROM/EPRO~.
22
RAM
PROGRAM
RAM
ROM
CACHE
BLOCK 0
BLOCK 1
BLOCK 0
(64 X 321
11K X 321
(1K X 321
(4K X 321
R5Y
H'OCD
Hl)[OA
mm
RiI'i
0(3101
A/2301
FSXO
OXO
IIlm
iNf(301
iACK
INTEGERJ
INTEGER!
FLOA TlNGPOINT
FlOA TlNGPOINT
ADDRESS GENERATORS
MULTiPliER
ALU
FSXl
EXTENDEDPRECISION
OX,
REGISTERS (RO-R7)
CLKXl
X2/ClKIN
Vce/ 7D)
VSS11001
VBBP
SUBS
CLKRO
MC!MP
x,
FSRO
ORO
CONTROL REGISTERS
XF(lO)
CLKXO
ADDRESS
ADDRESS
GENERATOR 0
GENERATOR 1
FSRl
DR.
ClKRl
AUXILIARY REGISTERS
IAROAR7)
TClKD
CONTROL REGISTERS 1121
TClKl
The CPU consists of the following elements: floatingpoint/integer mu Itiplier; ALU for performing floating-poi nt,
integer, and logical operations; auxiliary register arithmetic
The register file contains 28 registers, which may be operated upon by the multiplier and ALU. Thefirsteightofthese
registers (RO-R7) are the extended-precision registers,
which support operations on 40-bit floating-point numbers
and 32-bit integers.
The next eight registers (ARO-AR7) are the auxiliary registers, whose primary function is related to the generation
of addresses. However, they also may be used as generalpurpose 32-bit registers. Two auxiliary register arithmetic
units (ARAUO and ARAU1) can generate two addresses in
a single cycle. The ARAUs operate in parallel with the multiplier and ALU. They support addressing with displacements, index registers (lRO and IR1), and circular and bitreversed addressing.
The remaining registers support a variety of system functions: addressing, stack management, processor status,
The three floating-point formats are assumed to be normalized, thus providing an extra bit of precision. The first
23
is a 16-bit short floating-point format for immediate floating-point operands, which consists of a 4-bit exponent, 1
sign bit, and an 11-bit fraction. The second is a single-precision format consisting of an 8-bit exponent, 1 sign bit, and
a 23-bit fraction. The third is an extended-precision format
consisting of an 8-bit exponent, 1 sign bit, and a 31-bit fraction.
The total memory space of the TMS320C30 is 16M (million) x 32 bits. A machine word is 32 bits, and all addressing
is performed byword. Program, data, and 1/0 space are contained within the 16M-word address space.
RAM blocks 0 and 1 are each 1K x 32 bits. The ROM block
is 4K x 32 bits. Each RAM block and ROM block is capable
of supporting two data accesses in a single cycle. For example, the user may, in a single cycle, access a program word
and a data word from the ROM block.
The separate program data, and DMA buses allow for parallel program fetches, data reads and writes, and DMAoperations. Management of memory resources and busing is
handled by the memory controller. For example, a typical
mode of operation could involve a program fetch from the
on-chip program cache, two data fetches from RAM block
0, and the DMA moving data from off-chip memory to RAM
block 1. All of this can be done in parallel with no impact
on the performance of the CPU.
A 64 x 32-bit instruction cache allows for maximum system performance with minimal system cost. The instruction
cache stores often repeated sections of code. The code may
then be fetched from the cache, thus greatly reducing the
number of off-chip accesses necessary. This allows for code
to be stored off-chip in slower, lower cost memories. Also,
the external buses are freed, thus allowing for their use by
the DMA or other devices in the system.
DMA
All peripheral modules are manipulated through memory-mapped registers located on a dedicated peripheral bus.
This peripheral bus allows for the straightforward addition,
removal, and creation of peripheral modules. The initial
TMS320C30 peripheral library will include timers and serial
ports. The peripheral library concept allows Texas Instru-
24
The TMS320C30 provides two external interfaces: the parallel interface and the 1/0 interface. The parallel interface
consists of a 32-bit data bus, a 24-bit address bus, and a set
of control Signals. The 110 interface consists of a 32-bit data
bus, a 13-bit address bus, and a set of control Signals. Both
ports support an external ready Signal for wait-state generation and the use of software-controlled wait states.
TheTMS320C30 supports four external interrupts, a number of internal interrupts, and a nonmaskable external reset
signal. Two dedicated, general-purpose, external 1/0 flags,
XFO and XF1, may be configured as input or output pins
under software control. These pins are also used by the
interlocked instructions to support multiprocessor communication.
Pipelining In the TMS320C30
While the pipelining of the different phases of an instruction is key to the performance of the TMS320C30, the
designers felt it essential to avoid pipelining the operation
of the multiplier or AlU. By ruling out this additional level
of pipelining it was possible to greatly improve the processor's useability.
Instructions
THREE MPYF
THREE MPYF
25
The interlocked operations instructions support multiprocessor communication. Through the use of external signals, these instructions allow for powerful synchronization
mechanisms, such as semaphores, to be implemented. The
interlocked operations use the two external flag pins, XFO
and XF1. XFO signals an interlocked-operation request and
XF1 acts as an acknowledge signal for the requested interlocked operation. The interlocked operations include interlocked loads and stores. When an interlocked operation is
performed the external request and acknowledge signals
can be used to arbitrate between multiple processors sharing memory, semaphores, or counters.
DEVELOPMENT. AND SUPPORT TOOLS
Digital signal processors are essentially application-specific microprocessors (or microcomputers). Like any other
microprocessor, no matter how impressive the performance of the processor or the ease of interfacing, without
26
guage according to his application. The C compiler is supported on the TMS320C25 and the TMS320C30.
Hardware Tools
Evaluation Modu/e (EVM): The EVM is a stand-alone single-board module that contains all of the tools necessary
to evaluate the device as well as provide basic in-circuit
emulation. The EVM contains a debug monitor, editor,
assembler, reverse assembler, and software communica-
The TMS320 is designed for real-time DSP and other computation-intensive applications [4]. In these applications,
the TMS320 provides an excellent means for executing signal processing algorithms such as fast Fourier transforms
(FFTs), digital filters, frequency synthesis, correlation, and
convolution. The TMS320 also provides for more generalpurpose functions via bit-manipulation instructions, block
data move capabilities, large program and data memory
address spaces, and flexible memory mapping.
To introduce applications performed by the TMS320, digital filters will be used as examples. The remaining portion
of this section will briefly cover applications, and conclude
by showing some benchmarks.
Digital Filtering
1) = bk(i)
where bk(i + 1) is the weighting coefficient for the next sample period, bk(i) is the weighting coefficient for the present
sample period, B is the gain factor or adaptation step size,
e(;) is the error function, and x(i - k) is the input of the filter.
In an adaptive filter, it is important to update the coefficients bk(i) in order to minimize the error function e(i),
which is the difference between the output of the filter and
a reference signal. Quantizationerrors are critical to the
performance of the filter when updating the coefficients
and can be minimized if the result is obtained by rounding
rather than truncating. For each coefficient in the filter at
a given point in time, the factor 2*B*e(i) is a constant. This
factor can then be computed once and stored in the T register for each of the. updates. Thus the computational
requirement has become one multiply/accumulate plus
rounding. Without the new instructions, the adaptation of
each coefficient is five instructions corresponding to five
clock cycles. This is shown in the following instruction
sequence:
LRLK
AR2,COEFFD
LRLK
AR3,LASTAP
LARP
LT
AR2
ERRF
ZALH
ADD
MPY
APAC
',AR3
ONE,15
'-,AR2
SACH
'+
; LOAD ADDRESS OF
COEFFICIENTS.
; LOAD ADDRESS OF DATA
SAMPLES.
; errf
2'B'e(i)
; ACC
; ACC
=
=
; ACC
bk(i)'2"16
bk(i)'2"16 + 2"15
bk(i)'2"16
+ errf'x(i-k) + 2"15
; SAVE bk(i+l).
; LOAD ADDRESS OF
COEFFICIENTS.
; LOAD ADDRESS OF DATA
SAMPLES.
LRLK
AR2,COEFFD
LRLK
AR3,LASTAP
LARP
LT
AR2
ERRF
; errf
ZALR
MPYA
',AR3
'-,AR2
; ACC
; ACC
SACH
'+
2'B'e(i)
=
=
bk(i)'2"16 + 2"15
bk(i)'2"16
+ errf'x(i-k) + 2"15
; PREG = errf'x(i-k+l)
; SAVE bk(i+l).
The adaptive filter coefficient update can further be simplified using the TMS320C30 [27) as shown below. The first
instruction defines the number of times to repeat the kernel. The second instruction is the repeat-block instruction
(RPTB). The RPTB instruction allows the iterations ofthe kernel to be performed with zero overhead looping. The kernel
assumes that the error term is stored in register RO. It is
important to note that all of the calculations are performed
in floating-point arithmetic. The MPYF3 is a three-operand
floating-point multiply of the input sample x(i - k), which
is stored in memory by the error term errf. The next step
is a three-operand floating-point add (ADDF3) of the change
in the filtertap to the filter tap in parallel with the store (STF)
of the previously updated filter tap. That is, the store (STF)
is to be performed in parallel withADDF3. Thus the number
of cyles for a fioating-point adaptation is only two.
LDI
N,RC
RPTB
adapt
MPYF3
+ +ARO(l),RO,Rl
ADDF3
'+AR1(1),Rl,R2
STF
R2,'ARl + +(1)
adapt:
; b(k,i) + errf ' x(i - k)
R2
; R2 - b(k-l,i)
Since we have discussed the application of digital filtering, we can now describe several applications in the areas
of telecommunications, graphicslimage processing, highspeed control, instrumentation, and numeric processing,
and then conclude this section with several benchmarks.
If more detail is needed on any of these applications, the
reader is referred to [4].
Te/ecommun{cations Applications
27
High-Speed Modems: The TMS320 can perform numerous functions such a modulation/demodulation, adaptive
equalization, and echo cancellation [21], [22]. For lower
speed modems, such as BeIl212A and V.22 bis modems, the
TMS320C17 provides the most cost-effective Single-chip
solution to these applications. For higher speed modems,
such as the V.32, requiring more processing power and
multiprocessing capabilities, the TMS320C25 and TMS320C30 are the designer'S choice.
Voice Coding: Voice-coding techniques [3], [4], such
as full-duplex 32-kbit/s ADPCM (CCIn G.721), CVSD,
16-kbit/s sub band coders, and LPC, are frequently used in
voice transmission and storage. Arithmetic speed, nor-
high data-transfer rate (ten, million 16-bit words per second). Both devices can be used in closed-loop systems for
control signal conditioning, filtering, high-speed computing, and multichannel multiplexing capabilities. The following demonstrates two typical control applications:
Disk Control: Digital filtering in a closed-loop actuation
mechanism positions the read/write heads over the disk
surface. Supplemented with many general-purpose features, the TMS320 can replace costly bit-slice/custom/analog solutions to perform such tasks as compensation, filtering, fine/coarse tuning, and other signal conditioning
algorithms.
Robotics: Digital signal processing and bit-manipulation
power, coupled with host interface, allow the TMS320C25
to be useful in robotics control [24]. The TMS320C25 can
replace both the digital controllers and analog signal processing hardware for communication to a central host processor and for the performance of numerically intensive
control functions.
Instrumentation
Numeric Processing
replacement for a typical bit-slice solution. The TMS320C30's floating-point precision, high throughput, and
interface flexibility are excellent for this application.
TMS320 Benchmarks
400 ns
FIR filter tap
9.25 kHz
256-tap FIR sample rate
lMS adaptive FIR filter tap 700 ns
256-tap adaptive FIR filter 5.4 kHz
sample rate
Bi-quad filter element (five
multiplies)
Echo canceler (single
100 ns
37 kHz
400 ns
9.5 kHz
2 ps
1 ~s
8 ms
32 ms
60 ns
>60 kHz
180 ns
>20 kHz
360 ns
>64 ms
chip)
SUMMARY
High-Speed Control
28
TMS320 family were covered, and their support tools necessary to develop end-applications were briefly reviewed.
The paper concluded with an overview of digital signal pro-
[14]
[15]
Inc., 1986.
REFERENCES
[1]
[19] S. Rosen, "Electronic computers: A historical survey," Comput. Surv., vol. 1, no. 1, Mar. 1969.
[20] M. Honig and D. Messerschmitt, Adaptive Filters. Dordrecht, The Netherlands: Kluwer, 1984.
(21] R.lucky et al., Principles of Data Communication. New York,
NY: McGrawHill, 1965.
[22]
lock, "A 40 MFlOPS digital signal processor: The first supercomputer on a chip," in Proe. IEEE Int'l Conf. on Acoustics,
Speech, and Signal Processing, Apr. 1987.
[27] TMS320C30 User's Guide. Houston, TX: Texas Instruments
Inc., 1987.
29
30
Panos Papamichalis
Ray Simar, Jr.
Digital Signal Processor Products-Semiconductor Group
Texas Instruments
Reprinted from
IEEE MICRO MAGAZINE
Vol. 8, No.6, December 1988
31
32
The TMS320C30
Floating-Point
Digital Signal Processor
Panos Papamichalis
Ray Simar, Jr.
Texas Instrumellts
33
34
RDV
'"
.5
ia
HOLD
HOLDA
STRB
Rfjj
it
D (31-0)
A (23-0)
RESET
Address
Inlegerl
floating-point
ALU
INT (3-0)
C
a
generators
Control registers
MC/MP
XI
Address
X2/CLKIN
Vee (7-0)
generator
Address
generator 1
Vss (10-0)
VBBP
SUBS
35
/'
Cache
(64 x 32)
I I
RAM
block 0
(1K x 32)
,.1-,
RAM
block 1
(1K x 32)
I I
rb If,
1-
ROM
block
(4K x 32)
.1_ [
PDATA BUS
I I
I I
PADDR BUS ~
IJ
'"
DDATA BUS
'"
.c
:::>
'E"
M
U
M
U
DADDR1 BUS
I
DADDR2 BUS
I
DMADATA BUS ~
DMAADDR BUS Vh
I
CPU
DMA
(PC/IR)
36
...
::I
status register,
index registers,
stack pointer,
interrupt mask and interrupt flag registers, and
repeat-block registers.
In particular, the stack-pointer register points to the
software stack. The user has the flexibility of designating
where the stack resides, and even of changing its location
during the program execution. This feature also makes the
stack of essentially unlimited depth and permits its usage
not only for storing the program counter during subroutine
calls but also for passing arguments to subroutines. Such an
arrangement is particularly convenient in the development
of compilers, and we have used it extensively in the
320C30's optimizing C compiler.
The ALU performs floating-point, integer, and logical
operations. The ALU always stores the result in the register
file, but the input can come either from the register file or
from memory, or it can be an immediate value.
In the case of floating-point arithmetic, the input to the
ALU can originate from either a 40-bit extended-precision
register or a 32-bit memory datum. Registers RO through
R7 store the 40-bit-word result. On the other hand, in
integer arithmetic, both input and output are 32-bit numbers, and the output can move to either the lower 32 bits of
the RO through R7 registers or to any other register in the
register file.
The single-cycle hardware multiplier has been an integral part of DSPs because any real-time application relies
on the fast execution of multiplies. Following the same
distinction as in the previous paragraph on the ALU, the
multiplier performs both floating-point and integer multiplications. The 32-bit inputs to a floating-point multiplication yield a 4O-bit-wide result for storage in one of the
extended-precision registers.
In both the ALU and the multiplier the results of the
operations are automatically normalized, thus handling
any overflows of the mantissa. If there is an exponent
overflow, the result is saturated in the direction of overflow
and the overflow flag is set. Underflows are handled by
setting the result to zero and setting an underflow flag.
ALU
Multiplier
C\I
0::
Cl
Cl
Cl
0:
C\I
Cl
Cl
!C.
'",
Cl
a:
0::
32bit
barrel
shifter
at
*"
37
Software
MemOry}
space '
UI
"
"
.a
~
"0
"0
"0
E
J:
0!!~
<>.
..
J:
f>.
'ij
f>.
38
Integer and floating-point formats. A 32-bit, twoscomplement notation represents the integers. In addition to
this single-precision format, we have a short format, consisting of l6-bit, twos-complement numbers used only for
immediate operands. Every instruction of the 320C30
consists of one 32-bit word.
We use three formats for floating-point numbers: short,
single precision, and extended precision. The single-precision, 32-bit-wide format assigns 24 bits to the mantissa and
8 bits to the exponent. The exponent occupies the 8 most
significant bits, and it is represented in twos-complement
notation, taking values between -128 and 127. The exponent value -128 is the result reserved to represent zero.
The mantissa, placed at the 24 least significant bits of a
32-bit number, is normalized to a number with an absolute
value between 1.0 and 2.0. Since the mantissa is represented in a normalized, twos-complement notation, the
leftmost bit, which corresponds to the sign, and its adjacent
bit will always be the complement of each other. As a
result, only the sign bit is represented, with the most
significant bit suppressed, In other words, the mantissa
contains 24 significant bits plus the sign bit, with the most
significant bit implied.
Addressing modes. The 320C30 supports several addressing modes that allow the user to access data from
memory, registers, and the instruction word. The basic
addressing modes are
register,
direct,
indirect,
short immediate,
long immediate, and
PC relative.
In register mode the operand is placed into a CPU
register that is explicitly specified in an instruction. In
direct mode the data memory address is formed by preceding the 16 least significant bits of the instruction word with
the 8 least significant bits of the data page pointer. To keep
all instructions one word long, we store only the 161east
significant bits from the address in the instruction word; the
rest become the data page pointer. This restriction implies
that in direct addressing the memory space is segmented
into 256 pages of 64K words each.
Table 1.
Addressing modes of the 320C30.
Mode
Example
Operation
Description
Register
Direct
Short
immediate
Long
immediate
PC relative
Indirect
ADDF RO,RI
ADDF @MEM, RI
Addr=MEM
Operand in RO
Operand in MEM
ADDF 3.14,RI
Operand = 3.14
BRLABEL
BGE LABEL
ADDF * +ARO(di),RI
Addr = ARO + di
Indirect
Addr=ARO- di
Indirect
ADDF * + + ARO(di),RI
Indirect
ADDF * - -ARO(di),RI
Indirect
Indirect
Indirect
Indirect
Indirect
Addr=ARO+di
ARO=ARO+di
Addr=ARO-di
ARO=ARO-di
Addr= ARO
ARO=ARO+di
Addr=ARO
ARO=ARO-di
Addr= ARO
ARO = circ(ARO + di)
Addr= ARO
ARO = circ(ARO-di)
Addr= ARO
ARO = B(ARO + IRO)
Branch to LABEL
Branch to LABEL
Predisplacement add
without modification
Predisplacement subtract
without modification
Predisplacement add and
modify
Predisplacement subtract
and modify
Postdisplacement add
and modify
Postdisplacement
subtract and modify
Postdisplacement add
and circular modify
Postdisplacement subtract
and circular modify
Postindex (IRO) add and
bit-reversed modify
di is an integer between 0 and 255 or one of the index registers IRO and IRI.
at the input of the transform are scrambled at output (bitreversed order). To avoid moving the data around to place
them in the proper order. bit-reversed addressing accesses
the data in scrambled order for any subsequent operation.
Circular addressing implements circular buffers. Such
buffers are very convenient for use in digital-filtering
operations. In circular addressing. BK. one of the control
registers, specifies the size of the block. Then. when the
user modifies the contents of an auxiliary register (pointing
within that block) in a circular fashion. the final value is
tested to determine if it is still within the block. If it is not.
it is wrapped around using modulo arithmetic.
The short-immediate mode encodes immediate, 16-bitlong operands of arithmetic operations. The long-immediate mode encodes program control instructions (branch
instructions) for which it is useful to have a 24-bit absolute
address contained in the instruction word. Finally. the PCrelative addressing also applies to program control instructions and uses the difference from the present location of
the PC counter rather than an absolute address. The last two
39
'"c:
ti
~
.E
Fetch
I
I
Decode
Fetch
4
5
Read
Fetch
Decode
I
I
*ARI,RO,RI
RI,*AR3
ADDF
STF
Cycle
Execute
Read
Decode
Fetch
I
I
I
Execute
Read
Decode
Fetch
I
I
I
Execute
Read
Decode
I
I
Execute
Read
40
ADDF3
STF
*ARO,Rl,R2
RO,*ARI
41
Table 2.
Instructions for the 320C30.
Instruction
Load and store
LDE
LDF
LDFcond
LDI
LDIcond
LDM
Description
instructions
Load floating-point exponent
Load floating-point value
Load floating-point value conditionally
Load integer
Load integer conditionally
Load floating-point mantissa
Two-operand instructions
ABSF
Absolute value of a floating-point
number
ABSI
Absolute value of an integer
ADDC t
Add integers with carry
ADDF t
Add floating-point values
ADDI
Add integers
t
AND
Bitwise logical-AND
t
Bitwise logical-AND with complement
ANDN t
ASH
Arithmetic shift
t
CMPF t
Compare floating-point values
Compare integers
CMPI
t
FIX
Convert floating-point value to integer
FLOAT
Convert integer to floating-point value
LSH
Logical shift
t
MPYF t
Multiply floating-point values
MPYI
Multiply integers
t
NEGB
Negate integer with borrow
NEGF
Negate floating-point value
Negate integer
NEGI
Program control instructions
Bcond
Branch conditionally (standard)
BcondD
Branch conditionally (delayed)
BR
Branch unconditionally (standard)
Branch unconditionally (delayed)
BRD
CALL
Call subroutine
CALLcond
Call subroutine conditionally
DBcond
Decrement and branch conditionally
(standard)
Decrement and branch conditionally
DBcondD
(delayed)
Instruction
Description
POP
POPF
PUSH
PUSHF
STF
STI
NORM
Bitwise logical-complement
Bitwise logical-OR
Round floating-point value
Rotate left
Rotate left through carry
Rotate right
Rotate right through carry
Subtract integers with borrow
Subtract integers conditionally
Subtract floating-point values
Subtract integer
Subtract reverse integer with borrow
Subtract reverse floating-point value
Subtract reverse integer
Test bit fields
Bitwise exclusive-OR
IDLE
NOP
RETIcond
RETScond
RPTB
RPTS
SWI
TRAPcond
Trap conditionally
NOT
OR
RND
ROL
ROLC
ROR
RORC
SUBB
SUBC
SUBF
SUBI
SUBRB
SUBRF
SUBRI
TSTB
XOR
42
Applications
Certain features of the 320C30 such as its high speed,
versatile architecture, and rich instruction set, make it easy
to implement very demanding algorithms. The large
memory space makes the device suitable for application
areas such as image processing in which memory addressing is one of the prime considerations. And the C compiler
makes it easy to construct algorithms with complicated
logic.
.
. General nsp algorithms. Almost every OSP applicatIOn needs to perform some kind of filtering, the first
application considered for a DSP device. Digital filters are
categorized as FIR (finite-length impulse response) and
IIR (infinite impulse response) filters,'" or, equivalently,
as filters that have only zeros or both poles and zeros. Each
of these categories can have either fixed or adaptive coefficients.
The 320C30 implements FIR filters very efficiently. For
instance, let an FIR filter have an impulse response h[O],
h[ 11, ... , h[N Xl], and let x[nl represent the input of the
filter at time n. Then, the following equation gives the
output y[n1 with the equation:
h[N - 1] X x[n - N + 1]
43
Typical
Calling Sequence:
load
load
load
load
ARc)
ARl
RC
BK
CALL
FIR
Organization~
Data Memory
Impul se
response
+------------+
Low
address
h (N-l)
h(N-2)
+------------+ +------------.+
Hi gh
+------------+
address
h<O)
x (n-1)
Newest +------------+
input
x(n)
+------------+
x (n-2)
+------------+
x(n-1)
:---+
+------------+
The physical address for the start of the input samples mLlst be on
a boundary wi th the LSBs set to zero according to the length of the
buff er. The poi nter to the input sequence (x) is incremented and
assumed to be moving from an older input to a ne .... er input~ At the
end of the subroutine AR1 will be pointing to the position for the
nei:t input sample.
.
Argument Assi gnments:
Argument
: Function
ARO
AR1
RC
Address of h (N-1)
Address of x (N-1)
; Length of fi 1 ter - 2
: Length of f i 1 ter (N)
---------+----------------------B~~
(N-2)
Prografll sIZe:
6 words
11 +
(N-l)
; ===========""====================""'=="'""'-.;::=-'-=====================::==cc========
FIR
.global
;
FIR
MPYF3
LDF
f i 1 ter
RPTS
MPYF3
ADDF3
::
ADDF
<=
initialize Rl):
h(N-1) * x(n-(N-l
initialize R2.
*ARO++(1),*AR1++(1}'l.,RO
I).O,R2
1
<
-) RO
N)
RC
*AR()++(t) ,*ARl++(1)X,RO
RO,R2,R2
. RO,R2,RO
return sequence
RETS
return
end
.end
44
R2
ARC)
ARt
IRO.
load
load
IRI
BK
RC
CALL
IIR2
Low
+------------+
address I
aiW)
b2(O)
+------------+
+------------+
al (0)
Initial delay
node values
Newest
delay
Final delay
node values
+------------+ +-------.:..----+
d(O,n)
dCO,n-l)
:----+
+_ ... _---------+ +------------+
dCO,n-2): circular
queue
d(O,n-U
oldest
delay
bl (0)
+------------+
bO(O)
+------------+ +------------+
I
d (O,n-2)
d(O,n)
1----+
+------------+ +------------+
Empty
Empty
+------------+ +------------+
+------------+
+------------+ +------------+
deN-1,n)
: d(N-l,n-l> :----+
+------------+ +------------+
+------------+
+------------+
+------------+
I
I d(N-l,n-2):
d(N-l,n)
:----+
: d(N-l,n-1>
a2CN-l)
+------------+
b2 (N-I)
I d(N-l,n-2)
t circular
queue
+---------~--+
+------------+
Empty
Empty
al (N-l)
bl (N-I)
Hi gh
+------------+
address I
bO<N-l)
+------------+
The physical address for the start of each circular queue of delay node
values must be on a boundary with the LS8s set to zero according to thE"
; length of the buffer. The BK <block size) register must contain the
Two features of the 320C30 facilitate the implementation of the FIR filters: parallel multiply/add operations and
circular addressing. The first feature pennits a multiplication and an addition to execute in one machine cycle, while
the second makes a finite buffer of length N sufficient for
the data xl nJ. Figure 7 shows the arrangement of the data
and the assembly code for an FIR filter. Note that the filter
takes one cycle of execution per tap.
The transfer function of the IIR filters contains both
poles and zeros, and its output depends on both the input
and the past output. As a rule, these filters need less
computation than a FIR filter of similar frequency response, but they have the drawback of being sensitive to
coefficient quantization. Most often, the IIR filters are
implemented as a cascade of second-order sections, called
biquads. To implement an IIR filter consisting ofNbiquads,
let al Ii], a2li] be the numerator coefficients of the ith biquad and bO[i], b I Ii], b2111 the denominator coefficients of
=
=
=
y[O.nj x[nj;
for (i=O; i<N; i++){
d[i.nj a2[ij*d[i.n-2j + al[ij*d[i,n-Ij + y[i-I,nj;
y[i,nj b2[ij*d[i,n-2j + bl[ij*d[i,n-Ij +
bO[ij*d[i,nj;
}
y[nj = y[N-I,nj;
45
?"$si Clnment s:
Argument
: FunctIon
R2
ARO
AR1
BI<
IRO
JR1
RC
Program size:
RC
17 words
Execution cycles:
23 + 6N
; ==:::::::;;::0=====:::=========================================,""""=========... ::11=0::::=.,""::1=
.global
I JR2
MPYF3
MPYF3
*ARO, *AR1,RO
*++ARO( 1) , *AR1-- (1) 7., RI
a2 (O)
b2(Q)
MPYF3
*++ARO(l) , *ARt, RO
ADDF3
RO, R2, R2
MPYF3
;
IIR2
I:
*
*
d (O,n-2) -) RO
d(O,n-2) -) R1
:t
ADDF3
*++ARO(l) , *AR1--(Ui!., RO
RO, R2, R2
b1 (0)
d (O,n-1) -) RO
second sum term of d (O,n).
MPYF3
STF
bO(O)
:t
R2,
* d<O,n) -> R2
store d (O,n); point to
d (0,n-2).
RPTB
LOOP
MPYF3
<:= i <
loop for
a2(i)
d (i ,n-2) -) RO
first sum term of y(i-l,n)
:t
ADDF3
..
MPYF3
AODF3
*++ARO(1) , *AR1--(U7., RI
Rl,R2,R2
b2(i)
d(i,n-2) -> Rl
second sum term of y(i-l,n)
..
MPYF3
al ( i )
d (i ,n-1) -> RO
first sum term of dU ,n).
ADDF3
::
MPYF3
ADOF3
*++ARO(l) , *AR1--
STF
MPYF3
*++ARO(I) , R2, R2
(1)
*
*
bl(i)
d(i,n-l) -> RO
second sum term of d (i ,n).
7., RO
RO, R2, R2
;
;
LOOP
flnal
bO
5ummatlon
AOOF
ADOF3
NOP
NOP
RO,R2
R1,R2,RO
return to
i rst b i quad
point to d (O,n-1>
*AR1--(IRll
,*AR1--(1)%
return sequence
RETS
return
end
.end
Figure 8 (confd.)
46
Table 3.
Timing of an FFT on the 320C30.
Number of Radix-2
points
(complex)
FFT timing (ms)
0.167
64
128
0.367
256
0.801
1.740
512
1,024
3.750
Code size
(Words)
55
Radix-4
(complex)
Radix-2
(real)
0.123
3.040
0.075
0.162
0.354
0.771
1.670
176
86
0.624
Table 4.
Program memory and timing
requirements for 320C30 routines.
Application
Inverse of a floating-point
number
Integer division
Double-precision integer
multiplication
Square root
Dot product of two vectors
Matrix times vector
operation
FIR filter
IIR filter (one biquad)
IIR filter (N) 1 biquads)
LMS adaptive filter
LPC lattice filter
Inverse LPC lattice filter
/L-law compression
)L-law expansion
A-law compression
A-law expansion
Words
Cycles
(best easel
worst case)
31
27
31
27/58
24
32
20/24
35
8 + (N -
10
10
5
7
16
9
11
9
16
13
18
15
1)
2 + R(C + 9)
7 + (N - I)
7
19+6N
8 + 3(N - 1)
9 + 5(P - 1)
9 + 3(P - 1)
16
11116
18
14/21
47
JULY 16,
1987
FFT 51 ZE
N
M
SINE
INP,1024
LOG2 (N)
TEXT
INITIALIZE
.WORD
SPACE
FFTSIZ
WORD
LOGFFT
.WORD
. SINTAB
.WORD
INPUT
WORD
FFT.
LOP
LDI
LSH
LDI
LOI
LSH
LOI
LOI
LOI
;
OUTER LOOP
L[JOF':
NOP
LOI
ADDI
LOI
SUBI
FFT
100
N
M
SINE
INP
FFTSIZ
@FFTSIZ,IR1
-2,IR1
O,AR6
@FFTSI Z , I RO
1,IRO
@FFTSIZ,R7
1,AR7
1,AR5
*++AF,6 ( 1 j
>
@INPUT A~';
R/,AF:O,I'~K
Af,/ ,Re
1.RC
AR(I,2 + 2.-Nl
R2=X(I)-X(L)
R!~Y(j)-Y(Ll
RO=R2*SIN AND
K$=Y (I) +Y (L>
J R3""Rl *COS AND
48
II
II
BLK2
AND
II
END
STF
SUBF
MPYF
ADDF
MPYF
STF
ADDF
STF
Rl,R6,RO
*AR2, *ARO 1 R3
R2, *+AR4 (IRl) ,R3
R3,*ARO++(IRO)
RO,R3,RS
R5, *AR2++ (IRO)
STF
R4 t *+AR2
CMPI
BNE
R7,ARl
LSH
LSH
LDI
LSH
1,AR7
1,AR5
R7,IRO
-l,R7
BR
LOOP
R3,*+ARO
Y'!)=Y(!)+Y(L)
RO,R3,R4
R4=Rl*CaS-R2*SIN
R(J=Rl*SIN AND. ~.
R3=X <I )+X (L)
R3=R2*COS AND
X (I) =X (I) +X (L) AND ARO=ARO+2*Nl
INLOP
RS ... R2*COS+Rl*SIN
X (L) aR2*CaS+Rl*SIN I
;
I
INCR AR2
IE=2*IE
NI=N2
N2=N2/2
NEXT FFT STAGE
NOP
.END
Figure 9 (tont'd.)
References
I. K.-S. Lin, G.A. Frantz, and R. Simar, "The TMS320 Family
of Digital Signal Processors," Proc. IEEE. Vol. 75, No.9,
Sept.1987,pp.1143-1159.
2. R. Simar and A. Davis, "The Application of High-Level
Languages to Single-Chip Digital Signal Pr~essors," Proc.
19881nt'l. Con! Acoustics, Speech, and Signal Processing,
Apr. 1988, pp. 1678-1681.
49
50
51
52
Panos Papamichalis
Digital Signal Processor Products-Semiconductor Group
Texas Instruments
53
54
This report describes the implementation of several Fast Fourier Transforms (FFTs)
and related algorithms on the TMS320C30. The TMS320C30 is the first device in the
third generation of 32-bit floating-point Digital Signal Processors (DSPs) in the Texas
Instruments TMS320 family. The algorithms considered here are the complex radix-2 FFT,
the complex radix-4 FFT, the real-valued radix-2 FFT (both forward and inverse
transforms), the Discrete Hartley Transform (DHT), and the Discrete Cosine Transform
(DCT). These transforms have many applications, such as in image processing, sonar,
and radar.
The introduction briefly describes transforms and their implementation on the
TMS320 family of processors. Next, the different kinds of FFTs (including the real FFT),
the closely-related Hartley transform, and the Cosine transform are described and compared. This is followed by a description of the TMS320C30 features that permit efficient
implementations of these algorithms. Then, specific implementations, transforms, and
TMS320C30 C Compiler facts are outlined. Finally, the report discusses some implementation issues, and the appendices list actual TMS320C30 code for performing transforms.
The powerful architecture and instruction set of the TMS320C30 permit flexible
and compact coding of the algorithms in assembly language while preserving close correspondence to a high-level language implementation. The efficiency of the architecture
and the speed of the device make faster realization of real and complex transforms possible. With the availability of a C compiler, these routines can be put in C-callable form
and used as faster versions of FFT C functions.
Introduction
The Fast Fourier Transform (FFT) is an important tool used in Digital Signal Processing (DSP) applications. Its development by Cooley and Tuckey gave impetus to the
establishment of DSP as an independent discipline. The well-structured form of the FFT
has also made it one of the benchmarks in assessing the performance of number-crunching
devices and systems.
In recent years, because of the popularity of this signal-processing tool, there have
been efforts to improve its performance by advances both at the algorithmic level and
in hardware implementation. Researchers have been developing efficient algorithms to
increase the execution speed of FFTs while keeping requirements for memory size low.
On the other hand, developers of VLSI systems are including features in their designs
that improve system performance for applications requiring FFTs. In particular, singlechip programmable DSP devices, currently available or under development, can realize
FFTs with speeds that allow the implementation of very complex systems in realtime.
55
j -
00
x(t) e-jwtdt
(1)
00
determines the frequency content of the signal x (t). In other words, for every frequency,
the Fourier transform X(w) determines the contribution of a sinusoid of that frequency
in the composition of the signal x(t). For computations on a digital computer, the signal
x(t) is sampled at discrete-time instants. If the input signal is digitized, a sequence of numbers
x(n) is available instead of the continuous-time signal x(t). Then, the Fourier transform
takes the form
00
X(dw) =
.E
x(n) e-jwn
(2)
n=-oo
56
x(n) e
_ j27rkn
N
(3)
n=O
When x(n) consists of N points x(O), x(I), . . . , x(N-l), the frequency-domain
representation is given by the set of N points X(k), k=O,I, .. . ,N-I. Equation (3) is often
written in the form
N-l
X(k)
x(n)
wr;:
(4)
n=O
where W ': = e - j 27r:nk / N. The factor WN is sometimes referred to as the twiddle factor.
A detailed description of the DFT can be found in references [1,3,4]. The computational
requirements of the DFT increase rapidly with increasing block size N, having an impact
on the real-time system performance. This problem was alleviated with the development
of special fast algorithms, collectively known as Fast Fourier Transform (FFT).With an
FFT, the computational burden increases much less rapidly with N, and for any given
N, the FFT computational load, measured in terms of required mUltiplications and additions, is smaller than a brute-force computation of the DFT.
The definition of the FFT is identical to the DFT: only the method of computation
differs. To achieve the efficiency of an FFT, it is important that N be a highly composite
number. Typically, the length N of the FFT is a power of 2: N = 2M , and the whole
algorithm breaks down into a repeated application of an elementary transform known as
a butterfly. If N is not a power of 2, the sequence x(n) is appended with enough zeroes
to make the total length a power of2. Again, references [1,3,4] contain a detailed development of the FFT. Reference [2] also discusses the same topic.
57
--_i...,L.--------to
wNk
P+Q w~
--.~
P-Q W ~
-1
+ Q w~
(5)
W~
(6)
P'
Q'
P - Q
and
The quantities P, Q, and P', Q' represent different points in the array being transformed, and they mayor may not occupy adjacent locations in that array. In an in-place
computation, the result P' will overwrite P, and Q' will overwrite Q. W k represents again
N
the twiddle factor, and its exponent is determined by the location of the corresponding
butterfly in the FFT algorithm.
Figure 2 shows an alternate form of the same FFT butterfly.
Although the notation is now less descriptive, it creates a clearer picture when several
butterflies are put together to form an FFT. Using the first notation, Figure 3 is the
flow graph of an 8-point FFT example.
x(O)
X(O)
x(1)
X(4)
x(2)
X(2)
x(3)
X(6)
WO
x(4)
X(1)
WO
x(5)
X(5)
WO
x(6)
N
X(3)
WO
x(7)
X(7)
-1
-1
-1
59
The same procedure can be repeated with all the scrambled numbers not occupying
the position that their index suggests. If the input sequence x(n) is rearranged to appear
in bit-reversed form, the output X(k) appears in the correct order, as shown in Figure 4.
X(O)
x(O)
WO
N
X(1)
x(4)
X(2)
x(2)
WO
N
X(3)
x(6)
X(4)
x(1)
x(5)
WO
N
X(5)
X(6)
x(3)
x(7)
WO
N
X(7)
-1
-1
-1
Figure 4. Alternate Form of 8-Poiut FFT with Decimation in Time. The Input Is in
Bit-Reversed Order and the Output Is in the Correct Order.
Since the only difference between Figures 3 and 4 is a rearrangement of the butterflies, the computational load and the final results are identical. In terms of implementation, this rearrangement means that the nesting of the two innermost loops in the FFT
routine is interchanged.
The butterflies and the FFT configurations presented thus far implement the FFT
with a decimation in time. This terminology essentially describes a way of grouping the
terms of the DFT definition; see Equation (3). An alternative way of grouping the DFT
terms together is called decimation infrequency. Figures 5 and 6 show the same example
of an 8-point FFT: Figure 5 with the input in correct order and the output in bit-reversed
order, and Figure 6 vice-versa, and using the decimation in frequency (DIF).
60
X(O)
x(o)
Wo
N
X(4)
x(1 )
X(2)
x(2)
WO
x(3)
X(6)
X(1 )
x(4)
WO
N
X(5)
x(5)
X(3)
x(6)
WO
x(7)
-1
-1
-1
X(7)
x(o)
X(O)
x(4)
X(1)
x(2)
X(2)
x(6)
X(3)
WO
N
x(1 )
X(4)
wO
N
x(5)
X(5)
WO
N
x(3)
X(6)
WO
N
x(7)
X(7)
-1
-1
-1
61
In radix-4 FFT, each butterfly has 4 inputs and 4 outputs, essentially combining
two stages of a radix-2 algorithm in one. Figure 7 shows this combination graphically.
A
A1
A'
B1
B'
B'
C1
C'
C'
D'
D1
D'
62
Although four radix-2 butterflies are combined into one radix-4 butterfly, the computationalload of the latter is less than four times the load of a radix-2 butterfly. Examples of radix-4, 16-point FFTs are shown in Figures 8 and 9 for decimation in time
and decimation in frequency, respectively.
0
4
2
12
4
5
13
10
10
11
14
12
13
14
11
15
15
63
4
2
12
4
5
13
10
10
11
14
12
13
14
11
15
15
64
A'
B'
C'
C'
B'
0'
0'
(a)
(b)
65
There are eight extended-precision registers, RO-R7, that can be used as accumulators or general-purpose registers, and eight auxiliary registers, ARO-AR7, for
addressing and integer arithmetic. For many applications, these registers are sufficient
for temporary storage of values, and there is no need to use memory locations. This is
the case with the radix-2 FFT algorithm, where no locations are required other than those
for the transformation of incoming data to be transformed. Also, arithmetic using these
registers greatly increases the programming efficiency. The two index registers, IRO and
IR 1, are used for indexing the contents of the auxiliary registers ARO-AR7, thus making
the access of the butterfly legs and the twiddle factors easy.
A powerful structure in the TMS320C30 is the block-repeat capability that has the
form
LABEL
RPTB
LABEL
put instructions here
last instruction
Whatever occurs after the RPTB instruction and up to the LABEL is repeated one
time more than the number included in the repeat counter register, RC. The RC register
must be initialized before entering the block-repeat construct. The net effect is that the
repeated code behaves as if it were straight-line coded (no penalty for looping), with program size equal to the one in looped code. In this way, the FFT butterfly, being the core
of the program, can be implemented in a block-repeat form, thereby saving execution time
while preserving the clarity of the program and conserving program space.
A bit-reversed addressing mode is available to eliminate the need for swapping
memory locations at the beginning or the end of the FFT (depending on the FFT type).
When you use this addressing mode, you access a sequence of data points in bit-reversed
order rather than sequentially, and you can recover the points in the correct order during
retrieval of the data instead of spending extra cycles to accomplish it in software.
66
Table 1. Program Memory Requirements for the Core of the FFT and Hartley
Transforms
Routine Type
Program Size
50 words
170 words
68 words
76 words
Hartley transform
71 words
The numbers in the table correspond only to the core program and do not include
the sine/cosine tables for the twiddle factors, any input/output, or any bit-reversing operations. Note also that they are independent of the FFT data size.
The data memory requirements are, of course, dependent on the FFT size. The maximum length of a complex, radix-2 FFT that can be implemented entirely on the internal
memory of the TMS320C30 is 1024 points. In the present implementation, the 1024-point
radix-4 FFT requires a few more locations (about 7) than are available on-chip.
The code (provided in the appendices) has been written to be independent of the
FFT length. The length N, together with the sine/cosine tables for the twiddle factors,
should be provided separately to maintain the generic nature of the core FFT program.
An example of a file with the sine/cosine tables for a 64-point FFT is given in the Appendix F. Note thatthe FFT size and the number of stages are declared .global in both files
(i.e., the main routine and the file with the table) so that the core program gets the actual
values during linking.
To reduce the storage requirements of a sine/cosine table, a full sine and a cosine
cycle are overlapped. The table stores 5/4 of a full sine wave, with the cosine table starting with a phase delay of 114 cycle from the sine table. This table size is larger than actually needed, and it is selected merely for testing convenience of the algorithms. The
minimum table size for a radix-2 complex FFT includes 112 of a full sine wave, and 112
of a full cosine wave. If these two half waves are combined using the above quarter-cycle
phase delay, the minimum table size for this kind of FFT is 3/4 of a full sine wave. For
instance, for a 1024-point FFT, the table can be the first 768 points of a sine wave, where
a full cycle would be 1024 points. In the case of a radix-4 complex FFT, the minimum
table size should include 3/4 of a sine and 3/4 of a cosine wave. Overlapping these requirements, we get the minimum table size of a radix-4 algorithm to be one full sine wave.
An example of a linking file is also included in Appendix F to show how the different segments are assigned. For a complete description of the assembler and linker, consult
the corresponding manual [6].
An Implementation of FFT, DCT, and Other Transforms on the TMS320C30
67
The timing of the FFT routines was done using the cycle-counting capability of the
TMS320C30 simulator. For the conversion of the number of cycles into seconds, a cycle
time of 60 ns was used. The timing refers only to the core FFT computation, ignoring
read-in and write-out requirements, since such requirements are application-dependent.
Also, no bit reversal is counted (although it may be included in the program), since it
is performed as part of the read-in or read-out. Table 2 gives the timing for the different
FFT routines and for the Hartley transform.
64
128
256
512
1024
1024
Radix-2
Radix-4
Radix-2
Radix-2
Complex
Complex
Real
Real
FFT
FFT
FFT
Inverse FFT
0.165
0.370
0.816
1.784
3.873
2.366
0.123
0.077
0.174
0.387
0.857
1.879
0.085
0.193
0.434
0.964
2.124
0.624
3.040
Hartley
Transform
0.081
0.181
0.403
1.132
2.430
For the complex FFTs, the radix-4 algorithm reduces the execution time by 20-25%
compared to radix-2, depending on the FFT size. The last entry in this table represents
the timing of the radix-2, DIT routine generated at the University of Erlangen [18] and
given in Appendix A. These numbers are typically used for benchmarking.
= R(k) + j
/(k)
(7)
and that the sequence has length N, R(k) and I(k) should satisfy the following relations:
R(k) = R(N-k), k = 1, ... , N12-1
/(k) = -/(N-k), k = 1, ... , N12-1
/(0) = /(NI2) = O.
68
(8)
(9)
(10)
In other words, the real part of the transform is symmetric around zero frequency,
while the imaginary part is antisymmetric. Similar conditions hold if the transform is expressed in terms of magnitude and phase.
The savings are due to the fact that not all points need to be computed. Since the
not-computed points do not need to be saved either, there are also storage savings. An
efficient algorithm for real-valued FFTs is described in [10]. This algorithm was implemented in the present study in such a way that, given the sequence of N real numbers
x(O), x(1), .. . ,x(N-I), the resulting FFT, consisting of complex numbers, is stored as
R(O), R(I), .. . ,R(NI2), I(NI2-I), I(NI2-2), ... ,/(1). R(k) and I(k) represent the real and
imaginary parts of the complex number X(k). Figure 11 shows the memory arrangement
for the FFT. Note that the input to the real FFT should be bit-reversed, but the bit reversal can be done as the data is brought in. With this arrangement, an N-point FFT uses
exactly N memory locations. If the full array X(k) is needed, the following relations should
be used:
X(O) = R(O)
X(k) = R(k) + j I(k), K = 1, ... , NI2-I
X(NI2) = R(NI2)
X(k) = R(N-k) - j I(N-k), k = NI2+ 1, ... , N-I
(11)
(12)
(13)
(14)
x(O)
R(O)
x(1)
R(1 )
x(2)
--....
REAL
BITREVERSAL
--II
FFT
.....
R(N/2)
I(N/2-1)
1(N/2-2)
x(N-2)
x(N-1)
1(1 )
69
H(k)
0, .. . ,N-l, by
(15)
n=O
N-l
x(n)
= _1
N
~
k=O
(16)
where cas(x) = cos(x) + sin(x). The DHT demonstrates a symmetry that is convenient
for implementations: The same program can be used for both the forward and the inverse
transforms, and the result is correct within a scale factor. Also, the real FFT and the DHT
can be derived from each other [12].
70
A radix-2 Hartley transform was implemented on the TMS320C30, and the corresponding code is included in Appendix n. This code follows the structure of the real
FFT in Appendix C. Tables 1 and 2 show the program memory requirements and the
timing for the execution of Hartley transforms of different sizes. The sine/cosine table
sizes are the same as in the case ofa real FFT.
N-I
x(k) = ~
n=O
1)1I"n
(17)
2N
N-I
x(n)
k=O
e(O)
e(k)
= 11 -J 2
= 1, for k
I)1I"n
(18)
2N
'* 0
(19)
(20)
Appendix E shows an implementation of the nCT based on the paper by Lee [14].
The appendix contains the algorithms for both the forward and the inverse transformations
and an example of a table for a 16-point nCT. Note that, because of the structure of the
algorithm, the cosine table needed contains actually the inverses of the cosines (within
a scale factor), and it is not stored in the natural order. Instead, it is generated by the
following C pseudocode:
cos_table[N-2] = cos[pi/4];
cos_table[N-1 ]
2/N;
71
The last entry to the table is not part of the cosine itself; it is a constant that is used
by the algorithm, and it is placed at the end of the cosine table for convenience.
Table 3 shows the timing of the forward and inverse transforms for different transform
lengths. The difference in the timing between the forward and the inverse transforms is
due to the fact that more time was expended to optimize the performance of the inverse
transform. Since four of the smallest butterflies were done simultaneously in the center
program loop, the minimum permissible array size to be transformed is 8.
Forward
Inverse
Size
Transform
Transform
16
64
128
256
512
1024
0.023
0.105
0.230
0.502
1.094
2.378
0.020
0.088
0.193
0.416
0.905
1.982
Table 4. Execution Times in Seconds for a 1024-Point Real FFT. The Numbers Should
Be Compared with 0.001879 s of a 1024-Point Real FFT on the TMS320C30
Machine
Radix-8
Mix-radix
Split-radix
0.3634
0.3902
0.3021
0.2376
0.2948
0.2089
0.2545
0.1825
0.2600
0.2127
0.1672
0.1046
0.1107
0.1101
0.0796
0.0943
0.0811
0.0767
0.0871
0.0975
0.0633
0.2371
0.0539
0.0641
0.0217
0.0243
0.0235
0.1671
0.1846
0.1864
0.1299
0.1527
0.1419
0.0940
0.1184
0.0991
0.0885
0.1110
0.0845
0.0277
0.0319
0.0338
0.0277
0.0316
0.0337
0.0182
0.0171
0.0151
0.0180
0.0173
0.0150
0.2518
0.3365
0.2103
0.2806
0.3897
0.2802
0.7586
1.047
0.6955
0.7476
1.029
0.7033
0.6037
0.6895
0.5660
0.0983
0.1060
0.0946
0.3689
0.4126
0.3390
0.3530
0.4142
0.3297
0.2053
0.2244
0.1416
0.2206
0.2457
0.1326
0.9400
1.248
0.9478
2.6670
3.1600
2.8260
1.5040
2.0800
1.4630
73
74
To minimize or avoid such conflicts, there are some simple steps that the designer
can take. The TMS320C30 has three separate memory areas (one on-chip, one accessed
by the primary bus, and one accessed by the expansion bus) that can be combined. For
instance, the program can be placed on the expansion port and the data on the primary
port. Or the data can first be brought into internal memory and then operated upon.
Alternatively, the program may be relocated to internal memory. A related approach is
to use the cache. All the transforms are implemented as loops that are executed many
times. If you activate the on-chip cache after the first access of the code, the instructions
execute from the cache instead of the external memory.
If there are additional conflicts, they can typically be resolved by some rearrangement
of the code. For instance, consecutively writing to external memory takes two cycles per
write. If, however, a write is followed by some internal operation, then the second cycle
of the write is transparent, and the actual cost is one cycle.
Bit Reversal
The TMS320C30 has a special form of the indirect addressing mode for the bitreversing operation that is required at the beginning or the end of an FFT. Through this
addressing mode, the scrambled data are accessed in their proper order. This addressing
mode works as follows:
Let ARn (n=O .. 7) be the auxiliary register pointing to the array with scrambled
data. The index register IRO contains a. number equal to one-half the size of the FFT.
Then, after every access of the data, ARn is incremented by IRO using the construct
* ARn + + [IRO]8
This causes the contents of ARn to be incremented by the contents of IRO, but if
there is a carry in this incrementing, the carry propagates to the right instead of to the
left. The result is the generation of the addresses in a bit-reversed order. The bit-reversed
addressing mode works correctly if the array with the data is aligned in memory so that
the first memory address is a multiple of the FFT size. This can be achieved if the first
memory address has zeros for the last M bits, where M = iog2N, with N being the FFT
size. For example, in the case of a 1024-point FFT, the last 10 bits of the memory address
of the first datum should be zeros.
In the implementation of the complex FFT, the output is complex even when the
input is real. So, there is a need to consider both the real and the imaginary parts of the
data array. The above description of the bit-reversed addressing mode assumed that the
real and the imaginary parts are stored as separate arrays in the memory. In this case,
each of the arrays (real or imaginary parts) can be accessed as described. However, in
most cases (including this report), the real and imaginary points alternate in the same array.
75
In this arrangement, the following simple modification achieves the same goal: set IRO
equal to N instead of N12, and access the N points of the transform. At every access, the
auxiliary register is pointing to the real part of the FFT. The imaginary part is located
in the next higher location, and it can be easily accessed.
With the bit-reversed addressing mode, the unscrambling of the data can take place
when the FFT result is accessed for further processing or for 110. It is possible, though,
that certain applications demand the reordering of the data in the same array. Such a
rearrangement can be done very simply for a complex FFT with the following code.
@FFrSIZ,RC
1,RC
@FFrSIZ,IRO
@INPUT,ARO
@INPUT,AR1
: RC = FFr SIZE
; RC SHOULD BE ONE LESS THAN DESIRED #
; IRO = FFr SIZE
*
RPTB
CMPI
BGE
LDF
II
LDF
STF
II
STF
LDF
II
LDF
STF
II
STF
CONT NOP
BITRV NOP
BITRV
AR1,ARO
; EXCHANGE LOCATIONS- ONLY
CONT
IF AROAR1
*ARO,RO
EXCHANGE REAL PARTS
*AR1,R1
RO,*AR1
R1, *ARO
* +ARO,RD
EXCHANGE IMAGINARY PARTS
* +AR1,R1
RO, * + AR1
R1,* +ARO
*ARO + + [2]
*AR1 + + [IRO]B
Note that ARt is pointing to the bit-reversed version of the address contained in
ARO. For real-valued FFT, or for FFTs that store the real and the imaginary parts in
separate arrays, the real-FFT routine in Appendix C contains a modified example of the
above code.
Use ofDMA
If the signal to be transformed arrives as a continuous stream of data, the DMA
could be used to collect the new data while the data already collected are processed. In
this case, the data source address of the DMA points to the memory location corresponding to a serial port, or to another port associated with an external device. The destination
is a memory space designated for storage.
76
There are two ways to use such buffers. One possibility is to designate one buffer
as the temporary storage and the other buffer as the working area. When the storage buffer
receives the necessary amount of data, the data is transferred to the working area, and
the DMA starts refilling the storage buffer. Alternatively, the two buffers are considered
equivalent: when the processor finishes processing and outputting the data from one and
the DMA has filled the other, the two buffers switch functions; i.e., the DMA starts filling
the first buffer while the CPU is processing the data in the buffer just filled.
Test Vector
For testing purposes, a vector with 64 (quasi-random) data points and the
corresponding FFT values is given in Appendix F. In this way, if any of the routines is
implemented, the test vectors can be used to verify the correct functionality of the routines.
Together with the test vectors, Appendix C gives a sine/cosine table for a 64-point
transform, and the linking file for such a transform.
Summary
This report examined implementations of fast transforms on the Texas Instruments
TMS320C3x floating-point devices. The transforms considered were several forms of the
FFT, the Discrete Hartley Transform, and the Discrete Cosine Transform. Because of
the powerful architecture of the device, the implementation was done easily and efficiently.
It was shown that a TMS32OC30 executes the FFTs several times faster than large computers
such as VAX and SUN workstations. With the availability of the C compiler, these routines
can be put in C-callable form and be used to compute the corresponding transforms
efficiently.
77
Appendices
Appendices A to F contain the TMS320C30 assembly language programs for the
different algorithms considered. The contents of the appendices are as follows:
Appendix A: Radix-2 Complex FFT.
composed of
AI: Generic Program to Do a Looped-Code Radix-2 FFT
Computation on the TMS320C30.
A2: ffL2 - Radix-2 Complex FFT to Be Called as a C
Function.
A3: Complex, Radix-2 DIT FFT - R2DIT.ASM.
A4: Complex, Radix-2 DIT FFT - R2DITB.ASM.
A5: TWIDIKBR.ASM - Table with Twiddle Factors for a FFT
up to a Length of 1024 Complex Points.
Appendix B: Radix-4 Complex FFT.
composed of
BI: Generic Program to Do a Looped-Code Radix-4 FFT on the
TMS320C30.
B2: fft_4 - Radix-4 Complex FFT to Be Called as a C
Function.
Appendix C: Radix-2 Real FFT.
composed of
CI: Generic Program to Do a Radix-2 Real FFT Computation
on the TMS320C30.
C2: fft~l - Radix-2 Real FFT to Be Called as a C Function.
C3: Generic Program to Do a Radix-2 Real Inverse FFT
Computation on the TMS320C30.
Appendix D: Discrete Hartley Transform.
composed of
DI: Generic Program to Do a Radix-2 Hartley Transform on the
TMS320C30.
Appendix E:
composed of
EI:
E2:
E3:
E4:
78
Acknowledgements
Mr. Raimund Meyer and Mr. Karl Schwarz (Lehrstuhl fur Nachrichtentechnik,
University of Erlangen) provided the fast routines of Appendix A to do l024-point, radix-2,
DIT FFT. Mr. Paul Wilhelm of the University of Washington provided the routines for
the Fast Cosine Transform (FCT) together with the related explanations and the test vector
in Appendix E. Their contributions are gratefully acknowledged.
79
References
[1] Burrus, C. S., and Parks, T.W. DFTIFFTand Convolution Algorithms, John Wiley
and Sons, New York, 1985.
[2] Lin, K. -S., Ed. Digital Signal Processing Applications with the TMS320 Family,
Prentice-Hall, Englewood Cliffs, New Jersey, 1987.
[3] Oppenheim, A. V. and Schafer R.W. Digita.l Signal Processing, Prentice-Hall,Inc.,
Englewood Cliffs, New Jersey, 1975.
[4] Rabiner, L. W., and Gold, B. Theory and Application of Digital Signal Processing,
Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1975.
[5] Burrus, C.S. "Unscrambling for Fast DSP Algorithms," IEEE Transactions on
Acoustics, Speech, and Signal Processing, Vol. ASSP-36, No.7, pp. 1086-1087,
July 1988.
[6] Papamichalis, Panos E., and Burrus, C.S."Conversion of Digit-Reversed to BitReversed Order in FFT Algorithms," Proceedings of 1989 IEEE International
Conference on Acoustics, Speech, and Signal Processing, May 1989.
[7] Third-Generation TMS320 User's Guide, Texas Instruments, Inc., Dallas, Texas,
August 1988.
[8] Papamichalis, Panos E., and Simar, Ray Jr. "The TMS320C30 Floating-Point Digital
Signal Processor," IEEE Micro, Vol. 8, No.6, pp. 13-29, Decemberl988.
[9] TMS320C30AssemblyLanguage Tools User's Guide, Texas Instruments Inc., Dallas,
Texas, July 1987.
[10] Sorensen, H.V., Jones, D.L., Heideman, M.T., and Burrus, C.S.- "Real-Valued Fast
f/ourier Transform Algorithms", IEEE Transactions on Acoustics, Speech, and Signal
Processing, Vol. ASSP-35, No.6, pp. 849-863, June 1987.
[11] Bracewell, R.N. "The Fast Hartley Transform," Proceedings of IEEE, Vol. 72,
No.8, pp. 1010-1018, August 1984.
[12] Sorensen, H.V., Jones, D.L., Burrus, C.S., and Heideman, M.T. "On Computing
the Discrete Hartley Transform," IEEE Transactions on Acoustics, Speech, and Signal
Processing, Vol. ASSP-33, No. 4,pp. 1231-1238, October 1985.
[13] Ahmed, N., Natarajan, T., and Rao, K.R. "Discrete Cosine Transform," IEEE
Transactions on Computers, Vol. C-23, pp. 90-93, January 1974.
[14] B. G. Lee, "FCT - A Fast Cosine Transform," Proceedings of 1984 IEEE
International Conference on Acoustics, Speech, and Signal Processing, pp.
28A.3.1-28A.3.4, March 1984.
[15] TMS320C30 C Compiler Reference Guide, Texas Instruments Inc., Dallas, Texas,
December 1988.
80
[16] Sorensen, H.V., Heideman, M.T., and Burrus, C.S. "On Computing the Split-Radix
FFT," IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol.
ASSP-34, No.1, pp. 152-156, February 1986.
[17] Sorensen, H.V.and Burrus, C.S. "Computer Dependency of FFT Algorithms",
Proceedings of ASILOMAR, 1987.
[18] Schuessler, H.W., Meyer, R., and Schwarz, K. "FFT Implementation on DSP
Chips-Theory and Practice," Proposal for the 1990 IEEE International Conference
on Acoustics, Speech, and Signal Processing.
81
82
83
00
ADDI
LDI
SUBI
R7,ARO,ARl
AR7,RC
I,RC
>
"CI
"CI
FIST LOG'
THE PROGRAM IS TIl<EN FRc.1 HI' BURRUS L PARKS B1Xl<. P. III. TIE lCOII'lEXI
DATA RESIlE IN INTERNAl remy. TIE Cl)1PUTATION IS DCK IN-PLACE, BUT TIE
RESULT IS MOVED TO IiNlHR PEMORY SECTION TO DEMONSTRATE THE B1T-R!:VERSED
ADDRESSING. THE TWIDDLE FACTffiS ARE Slf'PLiED IN A TABLE PUT IN A .DATA
;ECTJON. THIS DATA IS InUIED IN A SEPARATE FILE TO PRESERVE THE GElRIC
NATURE OF THE _AM. FCIl THE SAPE PLmlSE, THE SIZE DF TIE FFT N AND
LOG21NI ARE DEFItD IN A .GlOBL DIRECTIVE AND SPECIFIED DURING LINKING.
::...
;:,
~
'tj
~
~
;:,
'"is
6'
;:,
.s;,
IN?
.GLOBL
FFT
.GlOBL
.GlOBL
.GlOBL
M
SINE
,
,
,
:
.USECT
.BSS
"IN", 1024
OUTP,I024
.'"-3
WORD
FFT
l:l
SPACE
100
(j
;:,
I:l
;:,
FFTSIZ
LOGFFT
SINTAn
INPUT
OUTPUT
WORD
WORD
WORD
WOOD
SINE
IN?
ruTP
fFT:
LOP
FFTSIZ
LOI
LSH
LDI
LDI
LSi<
LDI
LOI
tFFTSIZ,IRl
-2,IRI
0, ARb
tFFTSI Z, IRO
I,IRO
tFFTSIZ,R7
l,AR7
LOI
1,AR5
~
<::>
""<::>
;:,
S-
'"
10m
CMPI
B10
NOP
LDI
"
"
"
"
"
H+AR6( 1)
@INI'JT , ARO
RO=l1IltllU
RI=l1IJ-XIU
R2=YllltYIU
R3=Y1II-YIU
Y1II=R2 AND ...
YIU=RJ
: XII I=RO AND ...
XIU=RI AND ARO,Z = ARO,2 t 2t'NI
LDI
LDI
ADDI
LOI
ADDI
ADDI
ADDI
LDI
SUBI
LDF
I-"
("j~
=
a ....
3
"CI ""i
a.~
.... ""i
END
=(JQQ
2,Ml
@SINTAB,AR4
ARS,AR4
ARI,ARO
2,ARI
@It-f'UT,ARO
R7,ARO,ARl
AR7,RC
I,RC
tAR4,Rb
RPTB
SUBF
SUBF
MPYF
AODF
MPYF
STF
SUBF
MPYF
ADDF
MPYF
STF
ADDF
STF
STF
BLK2
tAR2, *ARO, R2
t+AR2,I+ARO,Rl
Rl,Rb,RO
HAR2, HARO,R3
Rl, <tAR41 IRI I ,R3
R3,HAAQ
RO,R3,R4
Rl,Rb,RO
<AR2, tARO, R3
Rl, <tAR41 IRII, R3
R3,IAAO++(IRO)
RO,R3,R5
R5, <AR2ttIIROI
R4,HAR2
CMPI
R7,ARI
IILOP
BNE
.>
~
@lOGFFT , ARb
BLK2
LOOP:
1M2, "ARO, R3
R2,4MO--
....=
,
,
,
,
,
0
0
BLKI
tARO, *AR2, RO
tAR2++, fARO++, R1
*AR2, *ARO, R2
SECOND LOOP
"HER LOOP
tv
[3
"
IIt.OP:
INITIALIZE
STF
STF
tl
S'...."
..
BLKI
TEXT
.'"-3
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RPTB
ADDF
SUBF
ADDF
SUBF
STF
STF
Q.
,
,
,
,
;
,
,
,
,
,
,
,
,
R2=l1IJ-XIU
RI=YIJ I-YIU
RO=R2<SIN AND ...
R3=YllltYIU
R3=Rl<COS AND ...
YlJIYlJltYIU
R4=RI<COS-Rl<SIN
RO=R1+SIN AND ...
R3=XlIJtXIU
R3=R2tCOS AND
X1II.11IItXIU AND _Ot2<NI
R5=R2tCOStR1+SIN
XIU=R2tCOStR1+SIN, INCR AR2 AND...
YIU=RltCOS-fl2<SIN
""i
= =3
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="Q
1-30
~Q
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I
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is
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=ii
.'-l
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LOI
SUBI
LOI
LOI
LDI
LDI
@FFTSlZ,Re
I,Re
@FFTSlZ,IRO
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to.J1PIJT,ARI
RPTB
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STF
~
..,
"
8!TRY
HAROtll,RO
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RO,HARlIll
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SELF
!Ill
SELF
.'-l
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c
~
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So
~
~
~
o
C
00
VI
, N2=N2/2
, 111 FFT
ST~
~.
I~
IE=2flE
, NI=H2
L~
LDF
.END
, RC=N
, RC SIIlllI IE !IE LESS THAN lESIRED
, IRO=SIZE ~ FFT~
00
0-
... NAI'E:
ffU --- RADIX-2.C!l'If'LEX FFT TO BE CAlLD AS A C RKTlON.
FP
SYtO'SIS:
INT ffUIN,~, DATAl
INT N
FFT SIZE: No2"~
NlI1IlER {F STAGES = UlG2(NI
INT ~
ARRAY WITH I~ AND OOTPUT OATA
FLOAT 'DATA
::..
:::
DESCRIPTION:
GNRIC FlKTlON TO 00 A RADIX-2 FfT CM'UTATIOO ON TIE 32OC3O.
Tft: DATA rHlAY IS 2'N-U}(;, WITH REAL AND IMAGINARY VALUES ALTERNATHI3.
THE _
IS BASED 00 THE FORTRAN _
IN Tft: lltIlRUS AND PARKS
BOOK, P. 111.
:::
is'
g.
:::
<5;,
.'-3
t.:::?
FLOAT
VALUE(5N/41
\:l
\:l..
Sf.
....~
.,
~
:::
~
C
'"C
:::
_fiL2:
tv
00
.~or-d
PUSH
LDI
MH
PUSti'
PUSHF
PUSH
PUSH
PUSH
PUSH
LOI
STI
Lal
STI
LDI
STI
= sin! (5+N/4-11*2tpi/N)
THE VALUES VALUEI, VALUE2, ETC., ARE Tft: SAllE WAVE VALUES. FOR AN
N-P\JINT FFT, HRE ARE N+N/4 VALUES FOR A FLU AND A IlUARTER PERIOD {F
THE SINE WAVE. IN THIS WAY, A FULL SINE AND COSINE PERIOD ARE AVAILABlE
IS/.f'ERlt1POSEDI.
>
"C
"C
=
....
Q.
~
~
_sine
:::
FP
SP,FP
R4
RS
R6
R7
AR4
AR5
ARb
AR7
t-FP(21,RO
; ~ ARGUMENTS TO LOCATIONS
; Tft: NMES I N THE PROOW1
RO,!f'FTSIZ
.-FPi3I, RO
RD. !LOGFfT
=
....
.... C
I
:;:d
==
r':l
Q.
....
~
I
N
~TQHNG
~
~
+---------+
-FP(41
-FP131
-FP(11
-FP(11
-FPIOI
DATA
N
: RETlIIN AOOR
ruJ FP
+------+
REGISTERS USED: RD, RI, R2, R3, R4, R5, Rb, R7, ARC, ARI, AR2, AR4, AR5
ARb, AR7, IRO, IRI, RS, RE, fit
AUTHOR: PANOS E. P~MICHALIS
TEXAS INSTRUIENTS
!FFTSIZ ,IRI
-1.IRI
LD!
1,AA5
O,AAb
!FFTSIZ.IRO
I.IRO
@fFTSIZ,R7
I,AR7
HHHffftUfHHnH**ffHff-HHHUHtttHHHHU.UHHHHHft-HIf.UfH
LOOP:
....
0=
~
=
~
(J.ITER LOOP
OCTOOCR 13, 1987
RO.!INPUT
LDI
LSH
LDI
LDI
LSH
LDI
LDI
~
0
"C
f-FP(41,RO
Sf.
~
FFTSIZ.I
LOGFFT,I
Itf'UT,1
_Slne
TEXT
SINTAB
:::
. ass
PUSH
(j
_ffU
INITlALlZE C FUtUIOO
THE COMPlITATlOli IS OONE IN PlACE, AND Tft: ORIGINAL DATA IS [STROYED.
BIT REVrnSAL IS Itf?LEI1ENTED AT THE END (F THE FOCTlON. IF THIS IS t{)T
NECESSARY, THIS PART CAN BE ClMNTED OJT.
GLOBAL
DATA
_swe
FLOAT
.'-3
AA3
.BSS
.SSS
"'<:S
"::!
.set
GLOB!.
GLOB!.
Q.
NaP
H+AR6(1)
LDI
ADDI
LDI
SUBI
@INPUT.ARO
R7.ARD,AR2
AR7, R(
1,RC
=
=
~
~
;:,
FIST LOW
RPTB
AIlIF
SUBf
ADIIF
SUBf
STF
STF
SIF
STF
"i:5
is
gO
ILK!
"
END:
YILI~3
XIII~O
AND ...
XfLI~1 AND ARO,2
ARO,2 + 2+NI
END
,:--l
INLOP:
C)
So
'"...
~
~
LDI
LDI
ADDI
LDI
ADDI
ADDI
ADDI
LDI
SUBI
LDF
2,ARI
tsINTAB,AR4
AR5,AR4
ARI,ARO
2,ARI
~ltflJT ,ARO
RI,ARO,AR2
ARI,RC
I,RC
+AR4,R6
So
'"
~
~
N
C
o
C
I1LK2
"
RPTB
SUBf
SUBf
II'YF
ADDF
IIPYF
STF
SUBf
ItPYF
ADDF
IIPYF
STF
ADDF
STF
STF
CIIPI
BLK2
tAR2, tARO, R2
HAR2, '+MO,Rl
R2,R6,RO
,
,
R2~XIII-XILI
RI~YIII-YILl
,~tSIN
AND ...
R~YIII+YILI
f+AR2, t-tARO,R3
RI, HAR4IIRII,R3
R3,HMO
RO,R3,R4
RI,R6,RO
tAR2,tMO,R3
R2, HAR41 IRII,R3
R3,tARO++llROI
RO,R3,R5
R5, +AR2++1 IROI
R4, HAR2
~/2
CONT
BITRV
LDI
SUBI
LDI
LDI
LDI
~FTSIl,RC
I,RC
~FTSIl,
IRO
IltflJT,ARO
!INPUT,ARI
RPTB
CMPI
IIGE
LIF
LDF
STF
STF
LDF
LDF
STF
STF
B!TRV
ARO,ARI
CONT
*ARO,RO
tARI,RI
ROt "'ARl
Rl,fARO
II(p
H+ARO(2)
NOP
tARI++llROIB
t+ARQ(1)
,RO
HAA1(t),Rl
RO,t+ARlIll
RI, t+AROI I I
SECOND LOOP
'"
NI~
RI,IRO
-1,R7
LOW
@l.OGFfT,AR6
Cl'l'1
BZD
o
(j
, ~XIII+XILl
, RI~XIII-XILl
, ~YIII+YILl
, R3=YIII-YILl
, YIII~2 AND,
~
,:--l
I::>..
ILKI
tMO, tAA2, RO
fAR2tt, tMO++, Rl
tAR2, tARO, R2
1M2, fAAO, R3
R2,+AROR3, tAA2ROt fMQH( lROJ
RI, tAA2++ I lRO I
LDI
LSH
DR
~I+COS
/MI ...
Y1I1~YIII+YILl
,
,
R~I tCOS-R2tSIN
,
,
~tCOS+RI+SIN
~ltSIN
AND ...
R3=X III +X III
, R3=R2tCOS AND ...
XIII~XIII+XILI
AND
XILI~tCOS+R1tSIN,
~ARO+2tNI
YILI~RI tCOS-R2+SIN
lINE
RI,ARI
INLOP
LSH
I,AR7
LSH
1,AR5
IE~2tIE
POP
POP
POP
POP
POPF
POPF
POP
POP
PIP
R!:TS
AR7
AR6
AR5
AR4
R7
R6
R5
R4
FP
00
00
R2DlT,ASII
THIS _
GENERIC _
IIOJIlES
19,07,89
!?
"<::j
[
i:;
'
~
.!"1
i:::l
<l
.!"1
$:l
;:,
$:l..
s....,
'"
$:j
;:,
~
<:l
'"
~INIIDI
'"
COEFFICIENT
RUoNIO)) = COSI2*PItO/321
-!(WNIO)) = SINI2*PIt01321
R{WN(4)) = COSI2*PI*4/321
-!(WNI4Il = SINI2*PI*41321
=1
=0
= 0,707
= 0.707
12
13
FIRST 1110 PASSES IIIlE REALIZED AS A FlU! BUTTERFLY LIXJ' SINCE TIE
rt.t.TIPLlESIIIlE TRIVIAL. THE rt.t.TIPLIER IS DIU USED FOR A LOAD IN
PARAlLEL WITH IW ADIIF IR SUBF.
14
R{WNI3IJ
-!(WNI3))
R{WNI7Il
-!(WNI7I)
= 0,831
= 0.550
= O,I9:i
= 0.981
15
= COSI21P!J3/321
= SINI2IPI*3/321
= COS I21PI>7I32 I
= SINI2*PI*7/321
229 WOOOS
512 IIMIIS
ttffttftHtftfftU-ttfHHffHHffHfHffHIHHflHfHflfllfHfHffHfHlfIHI
f
A~AGE
CYCLES/BUTTERFLY
7,275
TOTAL BUTTERFLYCYCLES
= 37249
INITIALIZATION OVERHEAD
= 2181 = 5,55, (F TOTAL TItE
TOTAL NIJ1BER OF INSTRUCTION CYClES = 39429
TOTAL TIME FOR A 1024 POINT FFT
2.36 os IEXCLUDING BIT
j AI/
/ \
/
RE~I
DR + J BI --- I
cos -
/
\ +
j SIN I -------------------- DR' + j BI'
HUtHtHftHHIHnHHfHltftfHfHHtfftttftHHltlHHffHHfHfHltftfH
=~
cos
TR
TI = DR * SIN - Bl *
81 f SIN
cos
AR'= AA + TR
AI'=AI-TI
DR'= AR - TR
81/= AI + Tl
oc
J
~
a
.~
WHEN GENERATED FOR A FFT LENGTH IIF 1024, TIE TABLE IS FOR ALL
AVAILABLE FFT IIF LESS OR EIllW. LENGTH,
HtlHHHHHHffHHHfHHffHtHHHUHHHffHHHfHHtHHHHHHHft
s.
FILES'
TIE TWIDDLE FACTMS IIIlE SHRED IN BIT1If.IIERSED IRIEl AND WITH A TAa.E
LENGTH IF N/2 IN = FFTLENGTHI,
EX1<'I'LE' SOOWN FIR N=32, WNlnl = COSI2IPItn/NI - j>SINI21PItn/NI
ADIRESS
;:,
F!l.L~ING
ftfftHHftftfHHfHtHHfHfHffHftHHfHffHfHtHfHHffffHff-HfffHftf
3
I
.~
>
~
;:,
.,lobil
.globil
.globil
.globl!
.global
.global
_global
"
;:,
.BSS
111'.2048
.BSS
OOTP,2048
"i:5
.;:!
~
~.
-~
t:1
C)
-~
I:>
;:,
..,'~"
~
I:>
;:,
~
c:::;
FFTSIZ
FG4Il2
FG4"3
FGSt12
FG2
FG2I13
LOOm
SINTAB
SINT"I
SINTP2
INPUT
INPUTP2
(UJTPUT
'"
0C
00
\0
SUBf
SINE
INPUT IlECTCll lENGTH = 2N IIEPENDS
IJj NI
OOTPUT IlECTCll lENGTH = 2N 1 _
IJj HI
.lIiord
,word
N'lIERT-2
INIERT -3
.lIIord
.word
~TCHEL-2
.lIIord
fWolB
fWolB-3
."ord
.word
.lIIord
,lIIord
.word
.1II0rd
,word
.lIIord
FFT:
I.lf'
LOI
LDI
LOI
ADDI
ADDI
ADDI
LOI
LOI
LDI
LOI
LSH
LOI
SUBI
SIIE
SIIE-I
SIIE+2
INP
111'+2
OOTP
AR3,ARb
2.IRI
-I,IRO
lRO,RC
2,RC
"
"
SUIIf
ADIJ'
STF
SUIIf
"
STF
ADIF
II'YF
"
SlIIIF
"
"
FFTSIZ
fFG2,IOO
fSIHTAB,AR7
IINPUT,IIRO
lRO,IIRO,ARI
IRO,ARI,AR2
lRO,AR2,AR3
ARO,AR4
ARI,ARS
ADIJ'
II'YF
"
AIIIJ'
STF
SlIIIF
STF
ADIF
1M2,<ARO,R4
1M2, tAROtt ,RS
IMI, tAR3, Rb
tARl ++. IM3++ I R7
Rb,R4,RO
tAR3++,1M7,RI
Rb,R4,RJ
RI,tARI,RO
RO,.fAR4++
RI,lMltt,RI
RJ,tAR5++
RI,RS,R2
t+AR2,1M7,RI
RI,RS,RJ
RI,tllRO,R2
R2,lM2ttIlRII
Rt, tMO+-t I R6
RJ,lMbtt
RO,R2,R4
R4=AR+CR
RS=AR-CR
Rb=M+IIR
R7=M-IIR
AR'=RO=R4+Rb
RI=OI, I1R'=RJ=R4-Rb
; RO=BI +01, AR' =RO
; RI = 51 - DI , BR' = R3
;CR'=R2=R5+RI
; RI=CI, M'=RJ=RS-RI
; R2=AI +CI, CR' =R2
; Rb=AI -CI, M' =RJ
; AI' = R4 = R2 + RO
RPTB
II'YF
::
ARO AA + Al
ARI SR + HI
AA2 CR ... CI ... CR' t CI~
M3:DR+OI
AR4 : AR' + AI'
ARS , SR' + HI'
ARb : M' + 01'
AR7 : FIRST TWIDIl FACTCll = I
S-
ADIJ'
SUBF
ADIJ'
~TCIL
.tixt
FILL PIPELllE
N
IfW.B
N'lIERT
J:
::
SUIIf
II'YF
ADIF
ADIF
STF
SUBf
"
"
LDAD PAGE POIHTER
lRO = N/2 = IJ'FSET BETWEEN INPUTS
AR7 POINTS TO TWIDOLE FACTCll I
IIRO POINTS TO AR
ARI POINTS TO IIR
AR2 POIHTS TO CR
AR3 POINTS TO M
AR4 POIHTS TO AR'
ARS POINTS TO I1R'
ARb POINTS TO M'
ADMESS OFFSET
lRO = H/4 = lUUIER OF R4-BUTTERflIES
::
::
::
STF
SlIIIF
ADIJ'
STF
SUIIf
STF
AIIIJ'
II'YF
SUIIf
ADIF
STF
SUIIf
:1
STF
ADIF
II'YF
::
SUIIf
"
STF
"
STF
ADIF
SUIIf
IlKI
1M2-, 1M7, RO
RO,R2,R2
IMI tt, tAR7, RI
R7,Rb,RJ
RO,<ARO,R4
R4,1M4tt
RO, _ARO++,R5
R2,tAR5++
R7,Rb,R7
RI,tAR3,Rb
R7,tAR6++
RI, tM3tt, R7
R3, IM2tt
Rb,R4,RO
tAR3tt, 1M7, RI
Rb,R4,R3
RI,tARI,OO
RO,1M4tt
RI,lMltt,RI
R3, 1M5++
RI,RS,R2
ttAR2, 1M7,RI
RI,RS,R3
RI,<ARO,R2
R2, IM2ttllRIl
RI,_,Rb
R3,tM6++
; RO = CR , IBI' = R2 = R2 - ROI
; RI = IIR , ICI' = RJ = Rb + R71
; R4 = AR+ CR , IAI' = R41
; R5 = AR - CR , IBI' = R21
; 101' = R7 = Rb - R71
; Rb = M + BR , 101' = R71
: R7 = M - BR , ICI' = R31
;AR'=OO=R4+Rb
; RI=DI, BR' =R3=R4-Rb
; 00 = BI + DI , AR' = 00
; RI = BI - DI , I1R' = R3
;CR'=R2=R5+RI
; RI = CI , M' = R3 = RS - RI
;R2=AI+CI,CR'=R2
; Rb=AI -CI, M' =R3
8LKI
ADIIf
RO,R2,R4
; AI' = R4 = R2 + RO
nEAR PIPELINE
SUIlf
ADIIf
STF
STF
SUIIf
STF
STF
"
RO,R2,R2
R7,Rb,R3
R4,IM4
R2,tAR5
R7,Rb,R7
R7,IMb
R3,'-AR2
R2,IM3++
AR5,RC
FIRST BUTTERFLY-TYPE;
; BI' = R2 = R2 - RO
; CI' = R3 = Rb + R7
; AI' = R4 , SI' = R2
TR = BR cos + BI SIN
TI=BR'SIN-BI'1lIS
AR"= AR + TR
AI'= AI - TI
BR'= AR - TR
BI'= AI + TI
; DI' = R7 = Rb - R7
; DI' = R7 , CI' = R3
;:,
STF
llll
'tj
"
::l
~
;:,
is
~.
;:,
.Q,
STLH
tl
(j
~
I:l
;:,
I:l..
S.
~
...
\:l
;:,
::
llll
llll
SUBI
llll
fFG2,IRI
IRO,AR5
1,AR5
I,ARb
LDI
llll
llll
LDI
ADDI
llll
LSI!
LSI!
LSI!
LSH
!SINTAB,AR7
O,AR4
@INPUT,ARO
ARO,AR2
IRQ,ARO,ARJ
AR3,ARI
I,ARb
-2,AR5
1,AR5
-I,IRQ
LSH
ADDI
-I,IRI
I,IRI
L!F
L!F
IMI++,Rb
tAR7,R7
tARt++, tAR7--, RO
RO,RI,R3
'ARI++,R7,RI
R3, tARO,R2
tARO++,R3,RS
;RS=AR+TR,BR'=R2
FILL PIPELINE
'"
;:,
S.
~
"
"
a
C
"
"
"
"
"
IIFLYI
"
L!F
If'YF
ADIIf
MPYF
I1PYF
ADDF
If'VF
SUIIf
ADIIf
H+AR7,Rb
IMI-,Rb,RI
H+AR4,RO,R3
IMI,R7,RO
; RI = BIt cos , R2 = AR - TR
IIfLY!
t+AR!, RO, R5
ADDF
SUIIf
STF
ADIIf
If'YF
SUIlf
If'YF
STF
ADIIf
STF
RS, tAR2++
RI,RO,R2
IMI,R7,RO
R2,'ARO,R3
R2, 'MOH ,R4
R3, IM3++
RQ,RS,R3
tARltt,Rb,RO
R3, 'ARO,R2
IMI++,R7,RI
R4, IM2++
IMO++, R3, RS
R2,IM3++
"
::
c:;
~
N
GRLI'PE
~
c:;
"
RPTB
If'YF
STF
SUIIf
If'YF
"
"
"
"
SUIIf
ADOF
STF
SUIIf
STF
NOP
If'YF
STF
If'YF
If'YF
SUIIf
I1PYF
SUBF
ADIIf
STF
llll
RI,RO,R2
R2, tARO,R3
; R2 = TI = RQ - RI
; R3 = AI + TI , AR' = RS
RS,IM2++
RQ,RI,R3
IMI++,Rb,RI
R3, tARO,R2
IMO++,R3,RS
R2, IM3++
AR5,RC
; R4 = AI - TI , BI' = R3
; AOOOfSS UPDATE
; RI = BI t cos , AI' = R4
; RQ = BR SIN
; R3 = TR = RI - RQ , RQ = BR cos
; RI = BI SIN, R2 = AR - TR
;RS=AR+TR,BR'=R2
~
~
LDI
LDI
LDI
LDI
"(5
SECOND BUTTERFLY-TYPE:
;;J
~
IS
~.
;:
I. BUTTERFLY' 0('()
ADDF
SUBF
ADDF
SUBF
f*+.HHUHUfHHHHHHHHtHHfHHfHUHffHfHfUH+HHHHHHTHH
RPTB
BFLY2
:--J
MPYF
STF
ADlIF
MPYF
ADDF
SUBF
STF
WBF
MPYF
SUBF
MPYF
STF
ADDF
STF
f+ARl,R7,R5
"'-
~
..,'"
~
"
s,
c
;:
~
'"
tv
aa
BfLY2
"
*ARQ++ R3. R5
R2. fAR3++
.ARO, .ARI,R2
tAAt ++, fARO ... , R3
tARO,'ARI,RO
fAAl++,*A/lO++,Rl
1IR'=R2=IIR+OO
OO'=R3=AR-OO
AI' = RO = AI + BI
BI' = RI = AI - BI
2, BUTTERFLY' ."()
RS, tAA2++
RI,RO,R2
tARI,Rb,RO
R2, IAIlO,R3
R2,IARO+t ,R4
R3, tAR3++
RO,R5,R3
*ARl++,R7,RO
R3, .ARD,R2
fARl++,R6,Rl
R4,IAR2+t
LMIl OUTPUT
POINTER TO TWIDlLE FACTOR
OISTiVU IIETIEN TWO GRIlPS
FILL PIPELINE
:--J
("J
IIRI,1IR3
ts1NTP2,1IR7
5,IRO
fFG8I12,RC
; (R2 = TI = RO + RII
, RO = 00 I SIN, (R3 = AI + TIl
; (RI = AI - TI , BI' = R31
;TR=R3=I15-RO
; RO=OO.COS, R2=AR-TR
ADDF
SUBF
ADDF
SUBF
STF
STF
STF
STF
fARO, IAIlI,Rb
; IIR' = Rb = AR + 00
<ARIH,*ARO++,R7
; 00' = R7 = AR - 00
.ARO,IAIlI,RI
; AI' = R4 = AI < BI
tARIHIlROI,IAROHIIROI,RS; BI' = 115 = AI - BI
R2,IAR2++
; (AR' = R21
R3,IM3+t
; IBW = R31
RO,tAR2++
; (AI' =RO)
RI, 1AIl3H
; (81' = Rli
STF
R6,tAR2++
; ARf
R7, tAR3H
R4,-tAA2++(JRO)
115, 1AIl3++IIROI
; 00' = R7
; AI' = R4
; BI' = 115
STF
, STF
STF
= Rb
3. BUTTERFLY: .rM/4
CLEAR PIPELINE
AOOF
ADIIF
STF
CMPI
BHED
SUBF
STF
L!IF
STF
N(f>
Rl,RO,~l
R2, <ARD,R3
RS, *AR2++
ARb,AR4
GIlUPPE
R2, .fARO++! IRt) ,R4
ADIIF
SUBF
ADDF
SUBF
R2=TI=RO'RI
R3=AI+TI
AR'=R5
ADLf
LIF
LOF
SUBF
STF
STF
STF
R7 = cos
AI' = R4
BRANCH HERE
I,IRO
snn
AR'
AI'
BI'
00'
= 115
= Rl
= Rb
= RT
= IIR
= AI
= AI
= AR
+ BI
- 00
+ 00
- BI
4. BUTTERFLY' 1<'1114
, 00 FOLLOWING 3 INSTRUCTIONS
, RI = AI - TI , BI' = R3
tARo... , '+ARl, R5
IARl,fARO,R4
IftRl++,IARO--,Rb
tARl t+, 1AIl0++, R7
HARI,H+ARO,R3
; AR' = R3 = AR + SI
+-ART,RI
; RI = IFoo INNER LW'I
IAIlI++,RO
; RO = 00 (FOR INlIER LOO"I
IAIlIHIIROI,IARO++,R2; 00' = R2 = IIR - BI
R5,IIIR2++
(AR' = 1151
R7,tAR3++
100' = RTI
R6,fM3H
(81' =Rbl
5. TO M. BUTTERFLY:
APTB
BF2ND
LDF
STF
LIF
STF
-AR7++,R7
RI, tAR2++
tAR7++,Rb
R2,tAR3++
\0
LDI
LDI
ADD!
~INPlJT,ARO
ARO,1IR2
IRO,ARO,IIRI
UPPER Itf'UT
Lf'PER OUTPUT
UlER Itf'UT
"
"
\0
tv
"
rl'VF
STF
ADlF
rl'YF
ADDF
SUBF
STF
ADDF
rtPVF
SUHF
;.,.
;::
~
':j
"
"
;:;:
'"
;::
"
Ei
"
"
.'"-3
"
tI
"
.'"-3
"
;::
C)
1:>
;::
;:,.
a
s'..."
"
"
R2, fARO++,R4
R3, t-AR3++
, (R4 = AI - TI , BI'
RO,RS,R3
,R3=TRoRO'RS
; RO = DR + SIN, R2 = AR - TR
II'VF
STF
SUHF
II'YF
ADDF
SUHF
"3,
c:;
"
SUHF
'"
sc:;
"
"
'"
"
~
~
tv
00
"
"
,R3=TR=RO+RS
,RO=DR'SIN, R2=AR-TR
SUHF
II'YF
STF
ADDF
STF
II'VF
STF
ADDF
II'YF
ADDF
SUBF
STF
SUBF
rtPVF
~l++,Rb,RO
R3,+ARO,R2
tAR I ++1 IROI ,R7,RI
RI, tAR2++
tARO++, R3, R3
R2. tAR3++
SUBF
rl'VF
ADlF
R3, 'ARO,R2
tARI++( IROI ,Rb, RI
tARO++, R3, R3
, RI = 01 SIN, R3 = AR + TR
R31
+tARI,R6,RS
RS,tAR2++
RI,RO,R2
tARI,R7,RO
R2, .ARO,R3
STF
ADDF
I1PVF
SUBF
rl'YF
STF
ADDF
STF
"
HF2END
"
a.EAR PIPELINE
, (R4 = AI - TI , BI'
rtPYF
STF
SUBF
rwYF
ADDF
STF
SUBF
rtPVF
;::
, (R2 = TI = RO + Rll
, RO = DR COS , (R3 = AI + TIl
R3,.ARO,R2
tARI++,R7,RI
R4,tAR2++(IROI
+ARO++, R3, RS
R2,tAR3++
"
fARl++,Rb,RO
rtPYF
STF
ADIF
STF
1:>
;::
f+ARI,Rb,RS
R3, tAR2++
RI,RO,R2
'ARl,R7,RO
R2,+ARO,R3
R2, 'ARO++(JROI ,RI
R3,tM3++ilROI
RO,RS,R3
"
"
::
,RS=AR+TR,DR'=R2
, RS
BI + SIN, (AR'
RSI
R2, fM3++
RI,tAR2++
Rl,RO,R2
R2, +ARO,R3
RJ,I-M2++
R2, +ARO,R4
R3,tAR3
R4,+AR2
LDI
lOI
lOI
lOI
LDI
lOI
lOI
R31
tINPtiT,ARO
ARO,AR2
tINPtiTP2,ARI
ARI,AR3
ts I NTP2, AR7
3,IRO
@FG4r12,RC
FILL PIPELINE
,R3=AR+TR,DR'=R2
I. BUTTERFLY' ."0
f+ARI,R7,RS
R3, 'lM2++
RI,RO,R2
tARI,Rb,RO
R2, .ARO,R3
R2, +ARO++I IROI, R4
R3, tM3++{lRO)
RO,RS,R3
t-Ml++,R7,RO
R3,+ARO,R2
tARl++,Rb,Rl
R4,+AR2++IIROI
fAAO++,R3,RS
, RS = AR + TR , DR' = R2
, 1R2 = TI = RO - RII
, RO = DR + SIN, 1R3
, DR' = R2 , AI'
R4
,R2=TI=RO+Rl
, R3 = AI + TI , AR' = R3
, RI = AI - TI , 01'
R3
, AI' = R4
LAST STIa
, (R2 = TI = RO - RII
, RO = DR + COS , (R3 = AI + TIl
0
STF
STF
ADDF
ADIF
STF
SUBF
STF
STF
DDF
SUBF
ADDF
SUHF
AI + TIl
; UPPER II~UT
; UPPER ClJTPUT
,LMR IIf'UT
, LMR ClJTPUT
, POINTER TO TlUDIH FACTORS
, GRP OFFSET
,AR'oR6=AR+DR
tARO, tAR I ,Rb
,BR'=R7=AR-DR
fAA 1++ *ARO++ R7
, AI' = R4 = AI + BI
tARO, tARI, R4
tARI++1 IROI, tARO++l IROI,RS , BI' = RS = AI - 01
2. BUTTERFLY: w"tt/4
ADDF
LDF
,R3oTR=RS-RO
,RO=DR'COS, R2=AR-TR
::
LDF
SUHF
STF
STF
STF
R2, IM3++
,AR'=R3=AR+BI
, RI = 0 IFOO INf'ER LOiJ'I
, RO 0 DR IFOR IIH:R LOiJ'I
tMl++,RO
tAR1++( IRO). fARO++ ,R2 , DR' = R2 = AR - BI
, IAR' = Rbi
Rb, tUt2++
, IDR' = R71
R7,+AR3++
RS, iM3++(IROI
, IBI' = RSI
f+ARI,+ARO,R3
<-AR7,RI
3. TO M. BUTTERFLY:
f+ARI,R7,RS
RS, tAR2++
RI,RO,R2
+ARI,R6,RO
R2, +ARO,R3
R2, fARO++,R4
R3, tAR3++
RO,RS,R3
tARl++,R7,RO
,R3=TR=RS-RO
,ROoDR+COS, R2=AR-TR
, 1R2 = TI = RO + Ril
, RO = DR SIN, 1R3 = AI + TIl
0
R31
::
::
"
LDF
STF
LDF
STF
rl'YF
STF
ADDF
rtPYF
+AR7++,R7
RI, +AR2++IIROI
+AR7++,Rb
R2, +AR3++
f+ARI,Rb,RS
R3,+AR2++
RI,RO,R2
tARI,R7,RO
, R7 = COS , IAI'
R41
;:s
II
~
'G
..
II
SUIIF
..
..
..
..
..
..
If>YF
SIF
ADIF
STF
!:i
~.
~
t:l
(")
-....,
I:l
;:s
!:l..
So
ADIF
SUIIF
SIF
ADIF
rlf'YF
If>YF
SIF
SUIIF
If>YF
ADIF
SUlF
SIF
SUIIF
If>YF
SUIIF
lFLEND
...'"
~
~
So
..
..
SIF
SIF
ADIF
; R5"::: BI
ADIF
R3,I-M2++
SUIIF
R2, <ARO,R4
R3,1AR3
R4,tAR2
END IF
BIT REVERSAl
a
C
..
..
BITRV
LOI
LOI
LOI
LOI
LOI
SUBI
I!FHSIl,IRO
2,IRI
@INPUT,ARO
!OUTPUT, ARI
I!FFTSIl,RC
2,RC
LDF
Rf'TB
BlTRY
ttAROlll,RO
IN
~++IIROlb,Rl
SIF
RO, _1 (I I
ttAROUl ,RO
RI,IMl++lIRIl
tARO++(JROlb,RI
RO,_11l1
LDF
SIF
LDF
STF
NIP
NIP
NIP
NIP
RI,IMI
SELF
BR
_I, R7, R5
R3,1M2tt
RI,RO,R2
IMI,R6,RO
R2,<ARO,R3
R2, tAROttilROl, R4
R3,1M3tt (JROI
RO,R5,R3
IMltt,R7,RO
R3,<ARO,R2
tARltt(JROI,R6,RI
tARO++ ,R3,R3
STF
END:
,R3=TR=RO+R5
, RO = BR SIN, R2 = AR - TR
R2,_
R2,lAR3tt
R4,1M2++(JROI
RI,RO,R2
R2,<ARO,R3
SIF
STF
II
~
N
IARO++,R3,R3
SIF
, (R4 = AI - TI , BI' = R31
:I
, 1R2 = TI = RO - Rll
, RO = BR SIN, 1R3 = AI + TIl
, IR4 = AI - TI , BI' = R31
,R3=TR=RO-R5
,RO=BRt.COS, R2=AR-TR
, RI = BI t SIN, R3 = AR + TR
Il.EAR PIPELINE
'"
\0
If>YF
ADIF
R2,<ARO,R3
R2, fMOttl IROI,R4
R3,IAR3++(JROI
RO,R5,R3
IMltt,R6,RO
R3,'ARO,R2
IMltt(JROI,R7,RI
R4,1AR2++( IROI
,R2=T1=RO+RI
,R3=AI+T1,AR'=R3
, R4 = AI - TI , BI' = R3
, AI'= R4
.tnd
SELF
'2
APPENIIIlM
COIfl.EX, RADIX-2 DIT FFT
R2DITB.ASIt
THE TWIDIl.E FACTOOS ARE STORED IN BIT REVERSED ORDER AND WITH A TABLE
LOOTH IF N/2 (N = FFTlfNGTHI.
;:::
3'
"i:5
ADDRESS
"
12
13
14
15
FIRST Till PASSES ARE RAl.IZED AS A FlUl BUTTERFLY LIXP Situ TIE
I1lI.TlPLIES ARE TRIVI~. TIE I1lI.TlPLIER IS ONLY USED FOO A LOAD IN
PARALLEL WITH AN ADDF 00 SUBF
IIIN
"-l
i::l
(J
I:l
IIIORY SIZE :
I:l..
PROO
DATA
;:::
S.
...,
'"
I:l
;:::
~
<::i
~
~
s.
'"
~
w
ac
COEFFICIENT
R{WNIO)) = COSI2.PltO/32)
-I(WNIO)) = SINI2tPltO/32)
R{ljNI4)) = COSI2tPl.4/32)
-I(WNI4)) = SINI2tPl'4/321
R(Wlmll
-I(WNI3))
R{1IH17Il
-I(WNl7Il
= COS(2'P!t3/32)
= SIN(2tPl'3/321
= COSI2'PIt7/321
= SINI2tPl'7/32)
= 0.831
= 0.550
= 0.195
= 0.981
~L
231 WOODS
512 WOODS
fHftIHHfffHffHfHUHffHfff+ffH4HfHIIHUffHfftfffHHf.fHffHfo+H.
4
8
8.25
AVERAGE CYCLES/BUTTERFLY
7.475
TOT~ BUTTERFLYCYCLES
= 38272
INITIALIIATIOO OVERIAD
= 2185 = 5.4 Z DF TOT~ TIlE
TOT~ NlIIIER IF INSTROCTIOO CYCLES = 40457
TOTAL TIlE FOR A 1024 POINT m
2.42 .5 IINCLUDIti BIT
REVERSIL)
fHHffH-+ ...... H .. HfoHHHfHIt. .HHHffHttH.HHHHHH-tHH.... fHfHHff
c::I.o
=1
=0
= 0.707
= 0.707
~TERED.
=
....
c
tfHtHHHHHfHffHnHHHfHHtHfHHfHtfHHtfHffHffHHHffHlfHff
:-l
- j*SINC2tPIt-n/N)
'i
~
24.07.89
E;
= COS(2*PItn/N)
\ I
I \
/
I
TR
= BR
COS + SI
* SIN
TI = BR
SIN - BI
AR'= AR
TR
AI'= AI - TI
SR'= AR - TR
Bl'= Al + TI
\
\ +
cos
'H+UHffHHfflU.HfHfHHflltfHHHHHffHIHffHtHIIH'IIHHHHHHt
'"
r;
....c::I.o
~
~
::3
~I
>
~
::..
;::
FFT
H
IfW.B
FILL PIPW
Ei
.global
.global
,glob.1
.global
,glob.1
.global
.global
"SIN!:
;::
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ltf',2048
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OOTP,2048
Sl
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.text
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;:!
~
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NVIERT
NACHTL
ADDF
SUBF
I"'UT I'ECToo LENGTH = IN IW'ENDS
ON HI
OOlI'UT I'ECTIll LEIf3TH = IN 1!EP9IDS
ON HI
"
"
FFTSIZ
"
,!IIord
.word
.word
FG4M2
FG4"3
FGBM2
..
,word
NVIERT-2
NVIERT -3
NACHT[L-2
I:l..
FG2
.word
~B
"
(j
_"-l
;::
a
..,
S~
~
$:I
;::
~
~
FG2I13
LooFFT
SINTAB
SINT"I
SINTP2
INPUT
INPUTP2
OUTPUT
wm
'"
.word
ttiAUl-3
.lIIord
"
,!IIord
.word
,word
,word
.liIord
.word
.\IIord
"
SINE
SINE-l
SINE'2
Iii'
IhP+2
WTP
WTP.l
S~
APTB
MPYF
"
"
..
..
"
c:>
0c:>
\0
UI
FFT:
W'
LDI
LDI
LDI
ADDI
ADDI
ADDI
LOI
LOI
LDI
LDI
LSH
LDI
SUBI
FFTSIZ
1FG2,IRO
!SINTAB,AIl7
@IIf'UT,1IRO
lRO,AIlO,AIlI
IRO,AIlI,AR2
lRO,AR2,AR3
AIlO,AIl4
ARl,AR5
AR3,AIlb
2,IRI
-1,IRO
lRO,RC
2,RC
SUBF
ADLl'
STF
SUBF
STF
ADDF
1AR2, <MO, R4
1AR2, .ARO++ , RS
<Ml,<M3,R6
tAR1++, *AR3++,R7
Rb,R4,RO
fAR3tt, -tAR7, Rl
Rb,R4,R3
RI,'IIRI,RO
RO, fAR4++
Rt, fARt ++, Rt
RJ,IARS++
Rl,R5,R2
ttAR2,tM7,Rl
Rl,R5,R3
Rl,'IIRO,R2
R2,<M2++IlRII
Rt, IMO++, Rb
R4=AIl'CR
RS=AIl-CR
Rb=M:+BR
R7 = III - IIR
AIl'=RO=R4.R6
RI = DI , IIR' = R3 = R4 - R6
; RO=BI'Dl, All' =RO
; RI = BI - DI , IIR' = R3
; CR' = R2 = RS Rl
; RI = CI , 00' = R3 = R5 - RI
; R2 = Al
CI , CR' = R2
; R6 = AI - CI , Ill' = R3
R3,IARb++
~~,R2,R4
; AI' = R4 = Rl RO
AIlO'AIl'AI
AIlI , IIR' BI
AR2 : CR .. CI + CR~ + CI I
AIl3 : III DI
AIl4 : All' AI'
AIlS : IIR' BI'
IIRb : DR' Dl'
AIl7 , FIRST TWIDDLE FACToo = I
;::
ADDF
SUBF
ADIF
I1PYF
SUBF
ADLl'
STF
SUBF
STF
ADLl'
II'YF
"
"
"
..
SUBF
MPYF
ADDF
ADLl'
STF
SUBF
STF
SUBF
ADLl'
STF
SUBF
STF
ADLl'
MPYF
SUBF
ADDF
STF
SUBF
STF
ADDF
.
..
MPYF
SUBF
ADLl'
STF
SUBF
BLKI
fAFU--. tAR7 ,RO
RO,Rl,Rl
IARlt+,fM7,Rl
R7,R6,R3
RO, 'IIRO,R4
R4,tAR4++
; RO = CR , IBI' = R2 = Rl - ROI
; RI = BR , ICI' = R3 = R6 R71
; R4 = All CR , IAI' = R41
RO, IARO++, R5
R2,IARS++
R7,R6,R7
RI,'AIl3,Rb
, IDI' = R7 = Rb - R71
, R6 = III IIR , IDI' = R7l
R7, IMb++
Rt, fAR3++, R7
R3, tAR2++
,R7=Ill-IIR,ICI'=R31
Rb,R4,RO
tAR3++, <M7 ,RI
R6,R4,R3
Rl,+AIll,RO
RO, <MI++
RI, fARl++,Rl
R3, fAR5t+
Rl,RS,R2
; All' = RO = RI + R6
, RI = DI , IIR' = R3 = RI - Rb
; RO = BI DI , All'
= RO
, Rl = BI - Dl , IIR' = R3
; CR/ :; R2 :: R5 + RI
, RI = CI , 00' = R3 = R5 - Rl
; Rl = AI CI , CR' = Rl
,R6=AI-CI, Ill' =R3
I:
STF
IlJCI
ADIF
Rl,W6++
RO,R2,R4
FIRST IlITTERflY-TYPE:
a.EAR PIPEl.INE
SUIIF
STF
STF
::
~
::s
SUIIF
SIF
::
STF
LDI
LDI
SUBI
LDI
is
SllfE
t:l
(J
."-'l
$:l..
c:>
.,So
'I>
..
!RPPE
M,_
112,_
R7,R6,R7
R7,<AR6
Rl,<-AR2
~
c::s
LDI
LDI
LDI
LDI
ADDI
LDI
LSH
LSH
LSH
LSH
tsINTAB,AR7
O,AR4
111I'UT,ARO
ARO,AR2
IRO,ARO,ARJ
ARJ,ARI
I,AR6
-2,AR5
1,AR5
-I,IRO
LSH
ADDI
-I,IRI
I,IRI
LDF
LDF
WI++,R6
<AR7,R7
tv
LDF
..
.
..
..
If'YF
ADIF
If'YF
If'YF
If'YF
SUIIF
ADIF
STF
::
1FG2,IRI
IRO,AR5
1,AR5
1,AR6
FILL PIPEl.INE
'"
So
'I>
TR = BR
TI = BR
AR'= AR
AI'= AI
BR'= AR
BI'= AI
"~
5"
::s_
RO,II2,II2
R7,R6,Rl
f++AR7,R6
WI-,R6,Rl
++W4,RO,Rl
Wl,R7,RO
Wl++,W7-,RO
RO,RI,R3
Wl++,R7,RI
Rl,<ARO,II2
_,Rl,RS
112,_
AR5,RC
LDI
, AI' = R4 = R2 + RO
::
::
,
,
,
,
,
,
,
,
,
,
TR
II
II
..
!FlYI
RPTB
!FlY!
If'YF
_1,R6,R5
R5,iM2++
RI,RO,R2
WI,R7,RO
R2,'MO,R3
STF
SUIIF
If'YF
ADIF
SUBF
SIF
ADIF
If'YF
SUIIF
If'YF
STF
STF
Rl,<AR3++
RO,R5,Rl
WI++,R6,RO
R3,'ARO,R2
WI++,R7,RI
R4,<AR2++
WO++,Rl,R5
112,_
SIN
tAR'
R5J
, 1112 = TI = RO - RII
; RO =lit f COS , (R3:1 AI + TI)
, IR4 = AI - TI , BI' = Rl)
;R3=TR=RO+R5
,RO=BRISIN,R2=AR-TR
, RI = BI I COS , IAI' R4)
,R5=AR+TR,BR'=R2
::
.
.
II
II
II
STF
SUBF
SIF
HOP
If'YF
SIF
If'YF
If'YF
SUBF
If'YF
SUIIF
SIF
LDI
RI,RO,R2
II2,<ARO,Rl
R5,<AR2++
112, IARO++IIRII ,R4
Rl, <AR3++IIRII
WI++IIRII
WI-,R7,RI
R4, <AR2++IIRII
WI,R6,RO
tARl++,'M7++,RO
RO,Rl,Rl
Wl++,R6,Rl
Rl,<ARO,II2
_,Rl,R5
R2,IAR3++
AR5,RC
SECOND IIJTTERFLY-TYPE:
TR=BllCOS-BRISIN
TI=BIISIN+BRICOS
AIl'= AR +TR
,RS=AR+TR,BR'=R2
R2,fARO++,R4
; R5 = BI
AI'= AI - TI
BR': AR - TR
,R2=TI=RO-RI
,Rl=AI+TI, AR' =R5
, R4 AI - TI , BI' = Rl
, ADalESS lPDATE
, RI BI I COS , AI' R4
,RO=BRISIN
, Rl = TR = RI - RO , RO = BR I COS
,Rl=BItSIN,R2=AR-TR
,R5=AR+TR,BR'=R2
SlIIIF
~
8['= AI I TJ
;::
RPT9
IIfLY2
If'YF
STF
AJIlF
If'YF
HARI,R7,AS
AS,lAR2ff
Rl,RO,R2
fARI,R6,RO
R2, tARO,R3
R2,fMO++,R4
R3,tAR3ff
RO,AS,R3
fAR1+l, R7, RO
R3,.MO,R2
fARl ff ,R6,Rl
R4,lAR2ff
fAROff ,R3,AS
R2,fAR3ff
ADlf
;;;-
::
!il
...S-.
Q
I:
"
AIlIlF
SlIIIF
"
STF
;::
~
tl
<"'l
,:--l
SlIIIF
If'YF
SlIIIF
"
If'YF
STF
ADlf
STF
II
IIfLY2
II
I:>
CLEAR PIPELIlE
ADlf
AJIlF
STF
O'f[
~
~
....
BlED
~
c::;
""
Q
;::
So
~
~
N
<::>
Q
<::>
, AS = 9[
: 1R2 = TJ = RO I Rll
, RO = BR f SIN, (R3 = AI I TIl
;:
,TR=R3=AS-RO
,RO=BRtCOS,R2=AR-TR
"
, Rl = 91
"
SUIIf
"
STF
"
STF
LIf'
NOP
END
, 91' = RI A[ - 91
STF
STF
STF
STF
STF
STF
STF
STF
AIlIlF
SUIIf
Rl,RO,R2
R2, tARO,R3
R5,IAR2++
AR6,AR4
GfilPPE
R2,tIIRO++URll,R4
R3, tAR3ffURll
fHAR7,R7
R4, IM2++( IRll
fARlIIURIJ
;R2=TJ=ROIRI
,R3=Alln
; AR' = RS
SUBF
, AR' = AS = AR I 91
,AI'=R4=A[-BR
, BI' = Rb = AI I BR
;BR'=R7=AR-91
4, BUTTERfLY; W"ft/4
, 00 Rl.I.~INl 3 INSTROCTJONS
, R4 = AI - n , 8[' = R3
;R7=COS
; A[' = R4
; BRAIli IRE
,AR'=Rb=ARIBR
: BR' = R7 = AR - BR
, AI' = R4 = AI I 91
tARO, fARI,R4
fARIIII IROI ,tIIRO++ I IROI ,AS , 91' = AS = A[ - 91
, (AR' = R21
R2,tAR2++
, IBR' = R31
R3,fAR3ff
, (A!' = ROI
RO,tM2++
, (91' = Rll
Rl,fAR3ff
R6, fM2++
,AR'=Rb
, BR' = R7
R7, fAR3H
R4,IAR2IHIROI
,AI'=R4
AS, tAR3ff( [ROI
, 9[' = AS
tARO, fARI,R6
3. IlUTTERfLY: W"ft/4
,AS=ARITR, BR'=R2
ADlf
"
LIf'
LIf'
SUIIf
"
STF
STF
STF
,
HARl,tIlARO,R3
t-AR7,RI
;
,
fARlff,RO
fARlffUROI, tAROtl, R2
R5,fAR2++
,
R7,fAR3ff
;
R6,*M3++
;
AR' = R3 = AR I B[
RI = 0 IFOR IIftR UXI'I
RO = BR IFOR lItER LOOPI
;BR'=R2=AR-91
IAR' = RSI
IBR' = Rll
191' = RbI
O'fl
aNZ
4,IRO
STLfE
lOl
LD[
lOl
lO[
!INPUT,ARO
ARO,AR2
[RIl,ARO,ARI
ARI,AR3
IS INTP2, ARl
S,IRIl
;
,
,
;
;
,
lPPER [NPUT
lPPER OOTl'\JT
L~ [NPUT
L~ OOTPUT
PO[NTER TO TW[Dll.E FACTOR
DISTANCE IIETIEEN TIIIJ OROOPS
!FGIlIt2,RC
1. BUTTERFLY'
ADlf
SUIIf
ADlf
LDF
fAR7ff,Rl
R4,IAR2ff
fAR7ff,Rb
R2,fAR3ff
HARI,R6,AS
R3,fAR2ff
RI,RO,R2
fARI,R7,RO
R2,tARO,R3
R2,.ARQ++<IROI,R4
R3, tAR3ffUROI
RO,AS,RJ
fARl++,R6,RO
R3,tARO,R2
fARlff,R7,RI
R4,iAR2++UROI
"
STF
If'YF
STF
ADlf
If'YF
"
0('()
; AR' = R2 = AR + BR
,BR'=R3=AR-BR
,AI' = RO = AI + 91
IIf2END
STF
"
RPT9
"
"
FILL PIPELINE
\0
-...I
SUIIf
ADlf
SUIIf
ADIf'
"
fARI++,tIIRO++,RI
2, IlUTTERfLY: lO"O
"
"
LDF
AIlIlF
SUIIf
STF
ADDF
If'YF
SlIIIF
If'YF
STF
; (R2 = TJ = RO I Rll
; RO = BR t COS , (R3 = A[ I TIl
; IR4 = A[ - Tl , B[' = R31
:R3=TR=RO+R5
, RO = BR f SIN, R2 = AR - TR
, Rl = BI
10
00
AIlIF
:1
STF
II'I'F
STF
SlIIF
II'I'F
ADIF
SlIIF
STF
II
;l..
;:
~
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W
~
is
II'I'F
::
SlIIF
II'I'F
STF
n
r:
STF
II'I'F
g'
::
I:
II'I'F
ADIF
If
STF
STF
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SUBF
SUBF
II'I'F
tl
::
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:I
AIlIF
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(')
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II'I'F
I:l
S.
C
S-
...<1>
~
s::\
;:
II'YF
::
STF
AIlIF
II'I'F
"
SUBF
~
<:i
BF2ElCI
"
::
S<1>
Q
C
SlIIF
II'I'F
ADIF
,R5ollR+TR,IIR'=R2
t+ARI,Rt.,R5
R5,tIIR2++
RI,RO,R2
tllRl,R7,RO
R2,tMO,R3
R2, tARO++,R4
R3,_
RO,R5,R3
tllRl++,Rt.,RO
R3,tMO,R2
tllRl++t1ROI,R7,RL
R4,tAR2++
tARO++,R3,R3
R2,_
t+ARI'R7,R5
R3,tAR2++
RI,RO,R2
tllRl,R6,RO
R2,tMO,R3
R2, tIIRO++lIROI ,R4
R3,_tlROI
RO,R5,R3
tllRl++,R7,RO
R3,IARO,R2
tllRl++,R6,RI
R4, tAR2++tlROI
tIIRO++ , R3, R5
R2,_
t+ARI,R7,R5
R5,tAR2++
RI,RO,R2 ,
tllRl,R6,RO
R2,tMO,R3
R2, tARO++ ,R4
R3,tAR3++
RO,R5,R3
tllRl++,R7,RO
R3,tMO,R2
tllRl++tlROI,R6,RI
tMO++,R3,R3
"
::
STF
STF
AOOF
AIlIF
STF
SlIIF
"
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
R3,'M3
R4,t11R2
, AI' = R4
IINPUT,ARO
lOOTPUT, AR2
IINPUTP2,1IR1
1OOlP1,AR3
ISINTP2;1iR7
IFFTSIZ,IRO
3,IRI
, IJ'PER IIf'UT
;
,
;
,
,
IFtl4II2,fIC
ADIF
SUBF
SUBF
AOOF
UBF
"
"
,R5=Bllros,IIIR'=R51
LDF
LDF
ADIF
STF
STF
STF
IIR' = R3 = IIR - BI
RI = 0 IFOR IMlER LOOPI
RO = IIR tFOR IMlER LOOP)
,1IR'=R2=IIR+BI
tllR' = 1161
IAI' = R51
tllR' R71
PTB
BFLEND
17 CYCLES IF FFT SIZE (1024 IU: TO TI USE OF INTERNAL IEIDlY FOR BIT
1If\.RSAl, 21 CYCLES IF m SIZE = 1024 IU: TO TI USE OF EXTEANAI. IEItORY
FOR BIT IIf\.RSAl
LDF
"
STF
"
STF
KPYF
STF
AOOF
LDF
, IIR' = R2 , AI' = R4
II'I'F
,R2=T1=RO+RI
,R3=AI+T1,IIR'=R3
SlIIF
ADOF
STF
AOOF
I R4 = AI - TI , BI' = R3
,
t+ARI,tMO,R3
,
t-AR7,RI
tllRl++,RO
,
tARl ++tlRII, IAROt+, R2
R6,I~++(IRO)b
,
,
R5,tIIR3++tlROlb
,
R7,1AR2++tlROlb
3. TO K. BUTTERFLY:
,tR2=T1=RO+RII
, RO = IIR I SIN, tR3 = AI + TIl
, RI = BI I SIN, R3 = IIR + TR
2, WfTERFLY: 0"11/4
"
R2,tAR3++
R4,tAR2++
RI,RO,R2
R2,tMO,R3
R3,tIIR2++
R2,tMO,R4
STF
STF
CLEAR PlPELIIE
STF
SlIIF
II'I'F
tMO++,R3,R5
R2,_
"
"
II'I'F
tllR7++,R7
R4, tllR3++IIROIB
tllR7++,R6
R2, tAR2++IIROIB
ttIlRI,R6,R5
R3, tllR2++IIROIB
RI,RO,R2
tllRI,R7,RO
R2,tMO,R3
R2, iARO++tIRII,R4
R3, tllR3++IIROIB
RO,R5,R3
tARl++,A6,AO
, R7 = ros , tlBI'
=R4))
;::
~
"t:l
;:'l
Ei
::;<.
<Q.,
~
_'-l
tl
(J
~
::,
"
"
"
"
"
;::
~
<:>
"
"
'"
<:>
;::
~
~
<::::>
0<::::>
R2,IAR2++(lROIB
R4, tM3tt<1ROIB
RI,RO,R2
R2,IMO,R3
R3,IAIl2
R2,IMO,R4
R3, tM3++<1ROIB
R4,IAIl3
I'I'VF
ADIF
rl'VF
WBF
STF
ADlIF
WBF
STF
ADIF
STF
STF
END IF FFT
END:
S'I>
tv
STF
"
""t
~
::,
;::
.tMI,R7,RS
R3, tM2++<1ROIB
RI,RO,R2 "tMI,R.,RO
R2,IMO,R3
R2, IARO++<1Rll ,R4
R3, tM3++<1ROIB
RO,RS,FtJ
*ARl++,R7,RO
R3,IMO,R2
tMl++IIRII,Rb,RI
R3, tMO++, R3
; RI = BI I
cos ,
IBI' = R41
; IR2 = 11 = RO - RII
, RO = III I SIN, IAI' = R3 = Al - TIl
; IBI' = R4 = Al Tl , AI' = R31
,R3=TR=RO-RS
, RO = III I COS , All' = R2 = All + TR
, Rl = BI SIN, BIt' = R3 = All - TR
CLEAR PIPELINE
I:>...
C)
S'I>
rf>YF
STF
SIIBF
rl'VF
SIIBF
SIIBF
BFLEND
"
R3,IMO,R2
tMI++IlRlI,R7,RI
R4, tM3ttilROIB
R3, fARO++ ,R3
R2, tM2++<1ROIB
ADIF
STF
"
"
ADIF
rl'YF
STF
WBF
STF
NlP
NlP
N(f>
NlP
SELF
III
.end
SELF
;R2=Tl=RO+Rl
, AI' = R3 = Al - Tl , Ill' = R3
, Bl' = R4 = Al + 11 , AI' = R3
, BI' = R4
:g>
HH. .HHH*nHfHfUHHHUHfHfffHffHHHfHHHfHHfftfffHffH-IftH
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TITLE: llIlD1KBR.ASII
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= Idlol
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til
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101
HfHHffHfHlffUHUIHHHHHffffffHHHHHfHfffffffHftHfHHfHHI
GCNERIC _
TIIS320C30.
THE TWIDCl..E FACTalS ARE SlPPLIED IN A TAILE PUT IN A .DATA SECTl(w, THIS
DATA IS IN:lUlD IN A SEPARaTE FILE TO PRESERVE TIE OENERIC NAME IF THE
PROORA/t. FOR THE SAlE PlIlPOSE, THE SIZE IF TIE FFT NAND LOO4IN) ARE
!FINED IN A .Il.OIIL DlRECTlE AND SPECIFIED MlNO LIN<INO,
~
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go
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g
So
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f:2
N
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N
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SINE
TEItP
STORE
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'IN',1024
.WORD
FFT
100
,WORD
.WORD
$+2
.IDlD
WORD
WORD
WORD
"SINE
.ass
.ass
.ass
ass
.ass
.ass
FFTSIZ, I
LOGFFT,I
SINTAII,I
INPUT,I
STAGE,I
RPTCNT, I
IEINDX,I
FFTSIZ
.""""==
!STeIlE,ARI
tAROH,RO
STl
RO. fARt++
IARO++.RO
RO, tAR1++
(WE
I'EIOOY TO TIE
~~
('D
('D
~;
LOI
'AROH,RO
STI
RO,fAR1++
LOI
'ARO,RO
STl
RO,'AIlI
LOP
LOI
LOI
LOI
LOI
STl
FFTSI2
IFFTSIZ.RO
IfFTSIZ,IRO
IFFTSIZ,IRI
O,AR7
AR7,tSTAGE
LSH
LSH
LOI
STl
I,IRO
-2,IRI
I,AR7
AIl7, IRPTCNT
LSH
STl
ADDI
STl
SUBI
LSH
-2,RO
AR7,@IEINDX
2,RO
, INITIAliZE IE INlX
RO,M
, JT=RO/2'2
2,RO
I,RO
, RO=N2
== ::!.
oof')
, WI1ANIl TO LOAD DATA PAGE POINTER
IIf>
FFl SIZE
L004IFFTSIZl
SINE/COSINE TABLE BASE
AREA WITH INPUT DATA TO PROCESS
FFT STAGE
REPEAT COJlTER
IE INlX Fell SINE/COSINE
ADDF
ADDF
S"
~
~
('D
9-
!INPUT,ARO
RO,ARO,ARI
RO,ARI,AR2
RO,AR2,AR3
!RPTCNT,RC
I,RC
(WE
FIST LOOP
RPTB
ADIF
=9
"C
OUTER LOOP
LDI
ADDI
ADDI
ADDI
LOI
SUBI
~~
==
~(JQ
~.,
LOOP:
, BEGllfoIlNO IF TEIf' STORAGE AREA
tTEIIP,ARO
.SPACE
.BSS
TEll'
~g
SEcoo-\.OOP mNT
JT mNTER IN _ , P. 117
IAI INlX IN _ , P. 117
NlI'IIIER
INITIAlIZE
...
~
.GLOIIL
.il.OIIL
.GLOIIL
.1l.01IL
TEXT
~
~
~
c::;
fHHUHHfIHHH:lHHfUIHHHHUffHHHftH*UHHHfftftHfH*HfHfH
LOP
LOI
LOI
LOI
STl
LDI
LPCNT,I
JT,I
IAI,I
FfT:
THE PRiJGRAII IS TAKEN FRIl1 THE IIlIlRUS AND PARKS 1100(, P. 117. TIE ctH'I.EX
DATA RESIl IN INTERNIi..~, AND THE IXfI'UTATl(W IS IIIH: IN-PLJ:E,
.ass
.ass
ass
APPENDIX BI
IILKI
*+ARO, f+AA2.Rl
t+AR3, 'tARI, R3
Rl,RI,R6
=
Ii'
~
J:..
't3
;:
"
"";::is'
"
LDF
LDF
ADDF
ADIF
STF
ADIF
SUBF
;::
<Q.,
STF
SUBF
SUBF
SUBF
STF
SUBF
ADIF
STF
STF
5tH
ADIF
STF
STF
"
."-'l
"
i::1
(J
."-'l
!:l
"
;::
!:l.
0
S.
""...
I1LKI
"
LDI
ADDI
CI1PI
BID
STI
~
C
tv
C
a
C
IJ,)
RPTB
1,AR7
AR7,fIAI
2,AR7
AR7,@LPCNT
LDI
ADDI
LDI
LDI
ADDI
ADDI
STI
ADDI
2,ARb
I!LPCHT ,ARb
@LPCNT,ARO
@IA1,AR7
fIElHOX,AR7
@1tf'UT,ARO
AR7,@IAI
RO,ARO,ARI
AR6, I!LPCHT
, IA2=IAI+IAH
, 1A3=1A2+IAH
"
ItPYF
ADDF
ItPYF
STF
If'YF
SUBF
IIPVF
"
STF
R6,++M3
; Y(l3)=R4*C03-R2+S13
If'IF
ADDF
STF
R4, 'ARb,R7
R7,R6
Rb, tAR3++IIRO)
, R7oR4tSI3
, R6=R2tC03+R4tSI3
, XI!3)oR2tC03+R4'SI3
'"
"
ADDF
ADDF
SUBF
SUBF
ADIF
ADDF
N'YF
STF
ADIF
SUBF
SUBF
! ~!
! '!
"
"
END
LOI
STI
LDI
STI
I1LK2
HAR2, ttARO,RJ
nAR3 ....Ml,R5
RS,R3,R6
HAR2,*tMO,R4
R5,R3
IAR2, fMO,R1
tAR3,tARI,R5
R3, HAR5I1RIl, R6
Rb, .tARO
RS,RI,R7
.AR2 , tARO ,R2
RS,R1
RI,tAR5,R7
R7, tARo++ I lRO)
R),R.
HAR3, f+ARl, RS
RI, ..AR5(JRIl ,R7
Rb, .tARl
R3,*M5.R6
R7,R6
RS,R2,RI
R5,R2
tAR3, tARl ,115
RS,R4,R3
RS,R4
R3, HAR41 IRI), R6
Rb,tAR1++(IRO)
RI,tAR4,R7
R7,Rb
RI, ttAR4IIRIl ,Rb
Rb,ttAR2
R3, tAR4,R7
R7,Rb
R4, .tARbllRll ,Rb
Rb,tM2++(IRO)
R2, tARb,R7
R7,Rb
R2,.tARbIlRll,R6
ADIF
!STAGE,AR)
1,AR7
@LOGFFT,AR7
AR7,@5TAGE
@IAI,AR7
@IAI,AR4
@5INTAB,AR4
AR4,AR7,AR5
I,AIr.i
AR7,AR5,AR6
I,ARb
seCOND LOOP
, Ci.IlRENT m STAGE
If'YF
STF
SUBF
SUBF
If'YF
STF
If'YF
ADIF
ADDF
SUBF
SUBF
~JBF
"
INLCP:
ADIF
If'YF
STF
If'VF
SUBF
sn
; X<I2)::ft?-R3
; X(J3)~+R3
LDI
LDI
ADDI
ADDI
SUBI
ADD!
SUBI
S.
""
~
R4=YII)-Y(J2)
YlIloRl<fi3
RloRl-R3
R5=XII2)
R7=mll
R3=XiIIl+X(13)
, RI=IIIl+XII2)
, VllIloRl-RJ
,_I<fi3
, R2=XII l-X ([2)
, XII)oRl<fi3
, RloRl-R3
, R6=XI11 l-X1!3)
, -fl3=VIIIl-V<l3)
, XllI)oRl-R3
, R5=R4-R6
, R4=R4+R6
, m2)oR4-R6
, VII3)oR4+R6
, R5=R2-R3 '"
, R20R2<fi3 '"
:::i
;::
'"
g
*+M2,f+ARO,R4
R6, ttARO
RJ,RI
tAR2,R5
t+ARI,R7
tAR3, tAR I ,R3
R5,tARO,RI
RI, ttARl
R3,RI,R6
115, tARO,R2
R6, tARO++<lRO)
RJ,RI
1M3, fM1,Rb
R7, ttAR3, RJ
RI, tARl++<lRO)
R6,R4,RS
R6,R4
RS, t-+AR2
R4, t+AR3
RJ,R2,RS
R3,R2
115, tAR2++1 lRO)
R2,tAR3++IIRO)
SUBF
STF
SUBF
;::
N'VF
"
, IA1=IAI+IE
: IXIIl,VII)) POINTBl
, IXIIIl,VIII)) POINTBl
ADD!
RO,ARl,AR2
; U(I2),Y<I2)) POINTER
ADDI
LDI
SUBI
Clf'1
BlD
RO,AR2,ARJ
!RPTCNT,RC
I,Re
@JT,ARb
SPCL
, 1I(I3),VI13)) POINTER
, RC SIIJlU) !If M LESS THAN IESlREO
IF LPCNT=JT, GO TO
Sl'ECIAl OOTTERFLV
BLK2
STF
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
R3=V<ll+VII2)
R5=VI1Il+V(13)
R6=R3+RS
R4=VII)-YI12)
R3=R3-RS
RI=IIIl+XII2)
R5=XIIIl+XII3)
R6=R3tC02
YII)oR3+RS
R7oR1+RS
R2=XIIl-XII2)
RloRl-RS
R7oRltSI2
lI11oRl+RS
R6=R3tC02-RI'SI2
R5=YIII)-YI13)
R7oRltC02
VI1I)oR3tC02-flltSI2
R6=R3'SI2
R6=R1tC02+R3tSI2
R10R2+RS
, R20R2-RS
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
-i
aPl
II
8ft
ILf'CNT,RO
III.OP
COO
STI
lOl
LSH
ADDI
STI
SUBl
IRI,M4
-I,M4
tSINTAB,M4
RP18
IILJ(3
AIlIF
SIIF
AIlIF
SIIF
-II'YF
AIlIF
II'YF
S1f
SIIF
II'YF
S1f
AIIF
II'YF
S1f
STF
IM2,_,RI
tM2,_,R2
<+IIR2,<+MO;Rl
<+IIR2,_,R4
tM3,tMI,RS
RI,RS,Rt.
RS,RI
<+M3,_I,RS
RS,Rl,R7
RS,Rl
Rl,_
RI,IARO++IlROI
tMl,tMI,RI
<+M3,_I,Rl
R6,ftM:l
R7,tMl++IlROI
Rl,R2,RS
R2,Rl,R2
RI,R4,Rl
RI,R4
RS,Rl,RI
tM4,RI
RS,Rl
_,Rl
RI .. <+11R2
R4,R2,RI
_,RI
Rl,tM2++IIROI
R4,R2
_,R2
RI,<+M3
R2,tM3++IIROI
aPl
l1'li
ILf'CNT,RO
III.OP
LDI
LDI
LSH
1RPTCNT,M7
IIEINDX,AR6
2,AR7
STI
LSH
AR7,WTOO
2,AR6
SI'CI.
i..SH
; POINT TO SIN(451
; CllEATE COSINE INIIEl M4>C021
8ft
AR6,tlEltill
RO,IRO
-3,RO
2,RO
RO,IJT
2,RO
I,RO
LOOP
; NI'IQ
; JT'lQI2+2
; N2=H2/4
;:,;
't:i
:=
SlIIF
'"S;:,;
AIXF
SIIF
AIXF
g"
.a.
~
t::I
stF
:l
::
AIlIF
SIIF
SlIF
AIlIF
SlIF
S-
'".,
..
..
IILJ(3
II
S-
'"
~
~
Q
C
S1f
SIIF
SIIF
S1f
STF
coo
RI=XIII+1tI21
R2-11l1-X 1121
R3=YIII+YII2I
R4aYIII-Y1121
RS=XCIII+Xml
R6oA5-RI
RI=RI+RS
RSoYIIII+Y1131
R7=RH5
R3=R3+RS
YIIIXIII=RI+RS
RI.11II1-X 1131
R3=YCIII-yml
YCIIloR5-ftl
; XCIII>113-R5
; R50R2+R3
; R2=-R2+R3 !!!
; 1l3oR4-R1
I R4=R4tRl
; RI>113-R5
; RloRltC021
; R3=R3+RS
; R3=R3tC02I
; YII21-(Rl-RSltC02l
;Rl~'11
; RI=RltC021
; XII2I-(R3+RSltC02l
; R2-R2+R4 !!!
; R2=-R2tC021 ! ! !
; Y(I3)-(R4-R2ltC02l !!'
; X(3)-(R4+R2)tC021 III
END:
I!
SITRV
;:
SELF
LDI
SUBI
lOl
LDI
LDI
LOP
lOr
tFFTSlZ,Re
I,Re
ImSlZ,lRO
2,IAI
tlNPUT,ARO
STIR
tSTlR,AftI
RP18
BITRV
_(II,RO
tARO++IlROIB,RI
RO,_IUI
RI, IMI ++IIRII
L!F
LDF
STF
STF
8ft
END
SELF
:Re=N
; Re SIWJI BE ONE LESS THAN IESIRED
; IRO=SIZE IF FFT=N
;::
~
'i:l
~
~
is
=:t.
,:--l
t::I
(J
,:--l
~
;::
I:l...
.,S'"
tw1E: ffU -
lESCRIPTl(Jj:
GENERIC FlKTI(Jj TO 00 A RADIH m COI'UTATl(Jj (Jj TNE TIIS320C30.
TNE DATA ARRAY IS2tNo-l(JjG, WITH REAL AN) llIAGINMY VALIS AlTERNATlMl. TNE _
IS BASED (Jj TNE FIIHRAN _
IN TNE lUlRUS
AN) PMKS BOO<, p, 117,
,globoI
= sin(Ot2lpilNI
.floit
.floit
'l'lht.1
.'float
vi,lue(5N/41
vllut2 ;: 5il'l(1'2Ipi/N)
;::
S-
'"
~
N
C
Q
C
TI VALlES vII ... l, .11 2, ETC., ARE TNE SINE WA\ VAlIS. FCIl AN
N-POINT m,' THERE ARE N+N/4 VALlES FCIl A All ANII A QlWlTER PERIOD
OF THE SINE WA\. IN THIS WAY, A FLU SINE AND alSlNE PERIOD ARE
AYAILAIU IStftRllI'OSElIl.
STACK STIUTLII lI'IJN TI ClU:
+--------+
-fP141
DATA
-fP131
ft
-fP121
N
: fIETIRj AOCIl
-fP1ll
-fPIOI
OLDFP
+-------.
REGISTERS USED: RO, RI, H2, Rl, R4, R5, R6, R7, MO, ARI, ARl, ARl, AR4,
Nr.>, M6, M7, IRO, IR1, RS, RE, RC
AR3
.[Loa.
GUll.
.IFT_4
_SINE
,BSS
.BSS
.BSS
FFTSlZ,1
LOGFFT,I
Itf'UT,1
>
'C
'C
,ENTAY POINT FCIl EIECUTI(Jj
, AOCIlESS OF SINE TAIU
SINTAB
.!IIord
t:=
~::;
PUSHF
PUSHF
PUSH
PUSH
PUSH
PUSH
Rb
LOI
ST!
LOI
ST!
LOI
STl
<-FP121,RO
RO,IfFTSlZ
.-FPI3I,RO
RO,@lOGFFT
R4
R5
~
~
I
'~
n
0
LOI
LOI
LDI
LOI
STl
IfFTSlZ,RO
IfFTSIl,IRO
IfFTSIl,IRI
O,AR7
AR7,!!STAGE
LSH
LSI!
LOI
STl
I,IRO
-2,IRI
I,AR7
AR7,IRPTOO
"e.
~
f-FP(41,RO
RO,!Itf'UT
STAGE,!
RPTCNT ,I
IEINDI,!
LPCNT,!
JT,!
IA1,1
=~
..
R7
AR4
AR5
ARb
AR7
.BSS
.BSS
.BSS
.BSS
.BSS
.BSS
ac I~
e -
INITIAlIZE C FlJI:Tl(Jj
FP
SP,FP
_SINE
PUSH
LOI
PUSH
PUSH
..=
~
.sine
dati
.sine
.SET
TEXT
_ffU:
IN CIlDER TO HA\ THE FINAL RESllT IN BIT-R\RSED CIlDER, TI TWO
ftID!l IIRAIDES OF THE RADIX-4 IIUTTEflfLY ARE INTERCHIIHGfD IIIJIIMl
STCIlAGE. NOTE THIS DIFFERENCE WIN COII'ARIMl WITH THE PROGRAII (Jj
p, 117. TI CM'UTATl(Jj IS OONE IfH>LACE, ANI! TNE CIlIGlNAL DATA IS
lESTRDYED. BIT IIE\RSAL IS IIflEIIENTED AT THE END OF THE FlKT!(Jj.
IF THIS IS NOT NECESSARY, THIS PART CAN IE ClXXENTED OOT. THE
SINE/COSlNE'TAIU FCIl TNE TWID!l FACTCIlS IS EIPECTED TO IE StPPLIED
IIIJIII) LUt< TlIE, ANIIIT SHWl) HA\ TI FI1WIIMl FCIlMT:
;::
<::>
SYIO'SIS:
int
I:j
~
c
fP
Ii'PEIIIIl B2
, FFT STAGE I
, REPEAT al.WTER
: IE INtEl FCIl SINE/alSllE
, SECINH.IXP al.WT
, JT COltITER IN _ , P. 117
, IAI INtEl IN PROORAII, P. 117
t:=
~
!.
~
~
rIl
~
LSII
STI
AIIII
STI
SUBI
LSII
-2,RO
M7,tlEIlIX
2,RO
RO,M
2,RO
I,RO
INITIALIIE IE INDEX
I JT=RO/2+2
I
RO=II2
IIJTER LOOP
::
1i'
'i;i
;;;l!I
<10
::
is
g"
ADIF
ADIF
ADIF
.~
t1
SUB'
STF
SUB'
:J
::
So
<10
~
0
is
So
<10
tv
Q
C
STF
ADIF
::
....
~
s::;
LDF
LDF
ADIF
ADIF
tINPUT,ARO
RO,ARO,IIRI
RO,IIRI,IIR2
RO,IIR2,IIR3
IRPTCNl,RC
I,RC
I
I
I
I
ARO
IIRI
IIR2
IIR3
POINTS
POINTS
POINTS
POINTS
TO
TO
TO
TO
RC SID.lII lIE
XCII
XliII
X1121
11131
(IE
FIST LOOP
RPTB
..
J:
..
IlJ(I
SUB'
STF
SUB'
SUB'
SUB'
STF
SUB'
AIIIF
STF
STF
SUB'
ADDF
STF
STF
IlJ(I
_ , t+IIR2,Rl
I
I
;
;
;
;
;
;
I
;
;
;
I
I
I
;
;
;
;
;
;
;
;
;
;
Rl=YUI+YII2I
R3=YIIII+Y( 131
_1+R3
R4=YCII-YU21
YIII=RI+R3
Rl=RI-R3'
R5=X1I21
R7=YIIlI
R3-XIIlItXII3I
RI=XIII+1II21
YIIII=RI-R3
_1+R3
R2=XIII-!II2I,
XCII=RI+R3
Rl=Rl-R3
R6=X III I-! 1131
-R3=YIIlI-YU31
XlIlI=RI-R3
R5=R4-R6
R4=R4+R6
YU21=R4-R6
YU31=R4+R6
R5=R2-R3 ! ! !
R2=R2+R3 !! !
XU2}=R2-R3 !!!
LDI
ADDI
LDI
LDI
ADDI
ADDI
STJ
ADDI
STJ
ADDI
ADDI
LDI
SUBI
Cl'PI
BiD
LDI
LDI
ADDI
ADDI
SUBI
ADDI
SIIII
2,ARl>
IlKNT,IIR6
ILPCNT,ARO
IIAl,M7
IIEIf()X,1IR7
IINPUT,ARO
1IR7,tIAI
RO,ARO,IIRI
ARl>,tLPCNT
RO,lIRl,lIR2
RO,IIR2,IIR3
IRPTCNl,RC
I,RC
M,ARl>
5I'CL
IIAl,M7
tlAl,IIR4
ISINTAB,IIR4
1IR4,1IR7,AR5
1,AR5
1IR7,AR5,1IR6
1,ARl>
I
I
IAl=IAl+IE
CXCII, YIIII POINTER
(XIIII,YUIlI POINTER
I
I
I
I
tsTAGE,M7
1,M7
ILOOFFT,M7
END
1IR7,ISTAGE
'"
STAGE
IlJ(2
ADIF
ftAR2.I+MO,R3
++IIR3,I+llRl,R5
R5,R3,R6
t+IIR2, _ , R4
ADIF
..
..
RPTB
ADDF
ADDF
SUB'
SUBF
ADDF
..
; aReIT
SECOND LOOP
; X(3)=R2+R3 !!!
I,M7
1IR7,tIAI
2,M7
M7,1LPCNT
11t.(J>:
LOOP'
LDI
ADDI
ADDI
ADDI
LDI
SIIII
LDI
STJ
LDI
STJ
IIPYF
STF
ADDF
SUBF
SUBF
IIPYF
STF
SUB'
SU8F
IIPYF
STF
IIPYF
ADDF
R5,R3
+IIR2,_,Rl
+AR3, +ARI,R5
R3, ++AR5I1RIl, R6
R6,t+ARO
R5,Rl,R7
tllR2,+ARO,R2
R5,Rl
RI,'AR5,R7
R7,tllRO++llROI
R7,R6
ttM3, HAR1, R5
Rl,'+AR5I1RIl,R7
R6,t+AR1
R3,'AR5,R6
R7,R6
; R3=YIII+YII21
I R5=YIIlItY(131
I -
; R4=YUI-Y(121
; R3=R3-R5
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Rl=XCII+1II21
R5=XIIII+XII3I
_3+CD2
YCII=R3+R5
R7=Rl+R5
R2=XIII-! 1121
Rl=Rl-RS
R7=Rl+SI2
XIII=RI+R5
R6=R3+CD2-Rl'SI2
R5=YIlIl-YIl3I
R7=Rl'C02
Y(IlI=R3+CD2-RI+sI2
R6=R3'SI2
_ I +CD2+R3'SI2
:::
AD!}"
SUBF
SUBF
~
"i::l
'""
;:;
:::
IS
"
:::to
C
:::
~
"
."'-l
tl
"
(j
_"'-l
i:l
:::
i:l..
(;)
"
lJL)(2
S....'"
SIJBF
ADIJ"
l'I'YF
STF
l'I'YF
SIJBF
I1PYF
STF
I1PYF
AD[/'
l'I'YF
STF
l'I'YF
SIJBF
I1PYF
STF
l'I'YF
ADDF
STF
Cl'I'I
BP
BR
RS,R2,RI
RS,R2
>AR3, >ARI,RS
RS,R4,R3
RS,R4
R3, ++AR4IIRII ,Rb
Rb,>ARI+t(IROI
RI,>AR4,R7
R7,Rb
RI, ++AR411RIl ,Rb
Rb, .+AR2
R3, >AR4,R7
R7,R6
R4, ++ARbllRl I ,Rb
Rb, 'AR2++IIROI
R2, +ARb,R7
R7,R6
R2, ++ARbIIRIl ,Rb
R6,HAR3
R4, 'ARb,R7
R7,Rb
Rb, IAR3++( IRQ)
I!I.PCNT,RO
Irt..OP
CONT
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RI=R2+RS
R2=R2-R5
RS=XIIIl-l{!31
R3=R4-RS
R4=R4+RS
Rb=R3+C01
XIIIl=RI'C02+R3'SI2
R7=RI'SII
Rb=R3*COI-RlfSIl
Rb=RI+CDl
YII21=R3'C01-Rl'SII
R7=R3'SIl
Rb=RlfC01f.R3tSII
Rb=R4'CQ3
XI121=RI,COI+R3'SI1
R7=R2'S13
Rb=R4'CQ3-R2'SI3
Rb=R2'CQ3
y(!31=R4'CQ3-R2'SI3
R7=R4'SI3
Rb=R2fC03+R4+SI3
XI131=R2+C03+R4'SI3
~
C
'"C
:::
S-
'"
LOI
LSH
ADD!
"
BLK3
"
CONT
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RI=XI!)+l{!21
R2=XII1-X1121
R3=YIlI+YI121
R4=YIIJ-Y1121
RS=XIIIl+l{!31
Rb=RS-ll1
RI=RI+RS
RS=YIIII+YII31
R7=R3-RS
R3=R3+RS
YIlI=R3+R5
XI!I=RI+RS
RI=XIlII-X(j3J
R3=YIIII-YI131
Rb,HARl
Y(I1I=R5-Rl
R7,>ARJ++IIR()1
R3,R2,RS
R2,R3,R2
Rl,R4,R3
Rl,R4
; XIIII=R3-RS
; RS=R2+R3
CONT
; R2=-R2+R3 !!!
BITRV
AODF
AD[/'
SUE<!'
AD!}"
AD[/'
AD[/'
STF
STF
SUBf
SUBF
-...I
END:
BLKJ
[(I
>AR2,>ARO,RI
1AR2, -IARQ, R2
HARZ, HMO,R3
HAR2, HARO,R4
1M3, *ARt ,RS
RI,R5,Rb
RS,RI
HARJ, ++ARI, R5
RS,R3,R7
RS,R3
R3, HMO
RI, -tM{)t+( IROl
.AR3,>AR1,RI
HAR3, ++ARt, R3
SUBF
; POINT TO SINI4S1
; CREATE COSI~ INDEX AR4=C021
AlJ[/'
SUBF
STF
STF
AD!}"
SlJBF
SlJBF
ADDF
: R3=R4-ll1
; R4=R4+Rl
RS,R3,RI
.AR4,RI
RS,R3
LDI
LOI
LSH
@APTCNT,AR7
@IEINDX,ARb
2,AR7
STI
LSH
ST!
LOI
lSH
AR7, !RPICHI
2, ARb
ARb,mINDX
RO,IRO
-3,RO
ADDI
2,RD
*AR4,R3
RI, f+AR2
R4,R2,RI
.AR4,RI
R3, *AR2++( lRO)
RI=R3-RS
RI=RI>C021
R3=R3+RS
R3=R3>C021
YII2I=IR3-RSI'C021
,,,
RI=R2-ll4
RI=R1+C021
X1121=IR3+RSI+C021
R2--R2+R4 ",
R2=R2+C021 ",
y(!31=-IR4-R21+C021
1Il3)=IR4+R21'C021
I~MENT
,,,
~XT
TIlE
RPTB
SUBF
tv
0
IRI,AR4
-1,AR4
@SINTAB,AR4
I!I.PCNT, RO
I,,-OP
STF
SIIBF
l'I'YF
STF
AD!}"
I1PYF
STF
STF
Cl'I'I
BFD
I1PYF
AD[/'
I1PYF
i:l
:::
R4,R2
.AR4,R2
RI, 'tAR3
R2. +AR3++IlROI
;
;
;
;
;
;
;
;
;
;
;
;
SUBF
STI
RO,M
SUBI
LSH
BR
2,RD
; JT=N2I2+2
I,RO
LOOP
; N2=N2/4
~XT
FH STAI
!fFTSIZ,Re
I.Re
!fFTSlZ,IRO
@INPUT,ARD
@INI'UT,ARI
RPTa
eMPI
BGE
L!}"
LDF
BlTRV
ARO,ARI
CONT
'MO,RO
>ARI,RI
RO, *ARI
Rl,fMO
STF
STF
"
; IE=4'IE
; NI=N2
LDF
LDF
srF
SIF
NOP
NOP
HARQ( 1)
Re=N
Re SIO.lD BE OOE LESS 1fW< DESIRED ,
lRO=SIZE Of FFT=N
,RO
HARHlI,Rl
RO,HARt(l)
RI,t+AROI11
f+tAf(O(Zl
'ARI++llROIB
108
109
CllPI
BGE
LLf
Pl'PENDlX CI
GENERIC PROORAII TO 00 A RADlX-2 RfAL FFT COIf'UTATION ON TlE TI1S32OC30
THE PROGRAM IS TAKEN FROM HE PPI'ER BY SORENSEN ET AL, cUE 1987 ISSUE
OF THE TRIV<SACTIONS ON !\SSP,
..
LLf
STF
..
CONT
STF
tfl'
tfl'
BITRV
THE lREALI DATA RESIlE IN INTERNAL ~Y. TlE COMPUTATION IS lXJiE
IN-I'lACE. HE BIT REVERSAL IS lIOI AT TIE BEGINNItIJ Lf HE PROJRII/1.
~
;:
~
~
~
;:
AlJTti(IR:
i:i
~.
INP
\:j
<'l
.GLO~.
FFT
N
.GLOBL
; LOO2(NI
.GLOBL
SINE
.USECT
.BSS
"IN",I024
OOTP, 1024
s::,
;::
INITIALIZE
wORD
:::..
So
~
....
;::
~
0
'"
FFTSIZ
LOGfFT
SINTAB
INPUT
OUTPUT
FFT:
0
;::
~
~
t:i
a
C
BLKI
:=
=-
~.
tINPUT,M~
lRO,RC
I,RC
BLKI
HARO, *ARO++, RO
tARO,*-ARO,Rl
RO,*-AAO
RI,lIARO++
, R(FXlll+X(J+11
, RI-X(! I-X(J+()
; xn )=X( I 1+x{I+lI
, X(!+II-X(1)-X!l+()
fFT
SPACE
100
WOOO
WORD
WORD
WORD
.WOOO
SINE
INP
ClJTP
LOP
@INPUT,ARO
2,IRO
eFFTSIZ,RC
-2,RC
I,RC
..
.
..
BLK2
NEGf
STf
STf
STF
BLK2
, R(FX(1)+XII+21
HARO{ IRO), *MO++( IRO),RO
tARO, .-AAOIIROI,RI ; RI-XIII-XII+21
, R(F-m+31
t+AAO,RO
; X(I)=X(J)+X{i+2J
RO, '-AROI lROI
, m+21-m )-X (J+21
Rl,*r:iKl++(JRQI
, x(!+31--Xll+31
RO, HARO
FfTSIZ
LDI
SUBI
LDI
LSH
LDI
LOI
I!fFTSIZ.RC
I,Re
eFFTSlZ ,IRO
-I,IRO
@INPUT,AAO
@INPUT.ARI
RPTS
Sl1RV
LOOF
; RC=N
; Re SHOOLD BE ONE LESS THAN lIESlRED I
LOI
LSH
LOI
LOI
LOI
LSH
LSH
LSH
eFFTSIZ,IRO
-2,IRO
I,R4
; lRO-INDEX FOR E
; R5 IIlLDS TIE ClIlRENT STAGE NltIlIER
: R40N4
2,R3
, R30Ia
-I,IRO
I,R4
1,R3
, EoE/2
; N4=2ftt4
3,R5
, N2020m
LOI
LDI
ADDI
LOI
tINPUT,AR5
lRO,AAO
@SINTAB,AAO
R4,IRI
~~
:3 :=
..,
~
aa~....
"0
.... Q..,
..,
:=trQ
Q
-9
:=
:
r~
Q
~~
a:: Q
00=
~~
==
O~
=~
So
N
C
SEPTEMBER 8, 1987
"0
"0
~
TEXT
.'"-l
::?
\:i
RPTB
ADDF
SUBF
STF
STF
PAN~;
(;LOft
~
.'"-l
LDl
LDI
SUBI
= N/2.
E. PAPAMICtlAlIS
TEXAS INSTRlJMENTS
>
LENGTH- 00 lIUTTERFLIES
'G
MI,AAO
CONT
'MO,RO
lIARl,RI
RO,lIARl
Rl,*MO
tMO++
tAR1 H( 1ROIB
~
~
!.
~
~
;:
N(p
~
:!
is
~.
~
tI
"
(J
a
S.
...'"
~
s::i
;:
~
<::i
"
<::i
f:::i
tv
C
a
C
LOF
ADOF
SUBF
STF
NEGF
'IIRS++IIRII,RO
HIIRSIIRII,RO,RI
RO, mARSIlRI I ,RO
RI,HIRSIlRlI
RO
Ht-M5(1RU,Rt
RO,'M5
RI,'IIRS
,
,
,
,
,
,
,
,
STF
STF
LOI
LSH
LDI
SUBI
@FFTSII,IRI
-2,IRI
R4,Re
l,Re
RPTB
It'YF
If'YF
I'I'YF
ROOF
It'YF
SlJBF
ILK3
>AR3,>+ARQIIRII,RO
fAA4, 'ARO,R1
>AR4,"AROIIRII,RI
RO,RI,R2
'AR3,>ARO++lIROI,RO
RO,RI,RO
>AR2,RO,RI
'AR2,RO,RI
Rl.fAR3++
>ARI,HZ,AI
RI,>AR4R2,tARI,RI
Rl,IAR1++
RI, 'AR2-
SUBF
;:
'"
ADDF
"
STF
"
STF
"
BLK3
ROOF
SUBF
STF
STF
SUBI
ADDI
Cl'l'I
SLID
ADDI
MlP
HOP
!INPUT,ARS
R4.11RS
@FFTSII,1IRS
INLOP
!ItflJT,1IRS
ADOI
Cl'l'1
BLE
I,RS
!LIXHT,RS
LOOP
N(p
I()p
MlP
RO=XUI
RI=XUI+XIl+N21
RO=-XIlIHIl+N21
XIlI=XIIi+XIl+N21
RO=XIl I-XI I +H21
RI=-XII+N4+N21
XIl+N21=XIII-XII+N21
XII+N4+N21=-KIl+N4+N21
INNERIIOST LOOP
I:>
;:
I:>..
S.
IIRS,ARI
I,ARI
ARI,AR3
R3,AR3
AR3,AR2
2,AR2
R3.M2,AR4
NEGF
"
."-l
LDI
ADOI
LOI
ADDI
LDI
SUBI
ADOI
Tl~S
,RO=XII31'COS
, RI=XII41'SIN
, RI=XI141.COS
, R2=XtI31'COS+XI141'SIN
, RO=X!l3I'SIN
; RO=-X(l3)ISINtX(J4)'COS !!!
; Rl=-XII21+RO I!!
: Rl=X(J2I+RO !!'
; X( I31=-X021+RO ! I!
, RI=XII1I<il2
; X(l4)=X(J2>+RO !! I
, RI=l(lIHl2
, XIlIl=XilIl+R2
, XII21=XIlIl-R2
, IIRS=I+NI
, LOOP BACK TO TI INNER LOOP
END
BR
,END
END
FP
/\'PENDIK C2
NAI1E:
.BSS
lnt PI
~BER OF STAGES = LOO21NI
floit Idata.
MAAY WITH IIf'UT AND 0U1l'IJT IiITA
is
5'
::
[(SCRIPTION:
GNERIC Fl))C!ION TO JJO A RADIK-2 FFT CMUTATION ON THE T11S32OO).
THE IiITA MAAY IS tHONG. WITH ONLY REAl. DATA. THE OUTPUT IS STORfD
IN TIE SME LOCATIONS WITH REAL AND IIIAGINARY POINTS RAND I AS
Fo..LOIIS: RIOI. Rill RINI2I. IINI2-lI 1111
II
::
s:l..
= c.os( (N/4)t2*pi/NI
-FP(4)
-FP<3l
-FP(2)
-FPIIl
-FP(O)
'"
<:::S
::
S.
""
+--------------+
DATA
"
N
: RETLIlN ADffi
0..0 FP
"
t--------------+
"
a
C
_SINE
FP
SP,FP
PUSH
R4
RS
AR4
AR5
LDI
STI
LDI
STI
LDI
STI
+-fPI21.RO
RO.@FFTSIZ
+-fPI31.RO
RO.tLCXJ'FT
+-FPI41.RO
RO.@INPUT
LDI
SUBI
LDI
LSH
LDI
LOI
IfFTSIZ.RC
I.RC
IfFTSIZ.IRO
-I.IRO
@IIf'UT.ARO
tINPUT.ARI
IIPTB
ClIPI
BITRV
ARI.ARO
CONT
oARO.RO
+ARI.RI
RO.+ARI
RI.oARO
oARO++
.AR1++IIROIB
BGE
tv
C
UfUU'U'.HUfffffU,ffffffffffffff.'HUH,fHfUfffH fffffU'HU'HH
=
....
~
~
CONT
BITRV
LDf
LDf
STF
STF
IU'
IU'
LDI
LDI
SUBI
!INPUT.ARO
IRO.RC
I.RC
a; RC=N
; RC SIO.UI IE ONE L<:SS THAN IlESIRED I
; IRO=HALF TIE SIZE OF FFT=NI2
~
~
t-3
.....
Q
=
tD
-atD
~
=
=
n
til
L<:NGTH-TWO BUTTERFLIES
OCTOBER 13. 1987
~
~
REGISTERS USEO: RO. RI. R2. R3. R4. RS. ARO. ARI, ARl. AR4. AR5; IRO.
IRI, RS. RE. RC
.n
TIE VALLS v.luel TO v.I"INI41 ARE THE FIRST QUARTER OF THE SINE
PERIOD AND; v.I"INI4+1I TO v.lu.INI2) ARE THE FIRST QUARTER OF THE
COSltE PERIOD.
~
1:1
::
~
<:::S
= siniOI2f pi/NI
"".,
=
;;:l'
FFTSIZ.I
LCXJ'FT.I
IIPUT.I
= sinlllltpl/NJ
.fluat value{NI2)
<:)
PUSH
PUSH
PUSH
PUSH
_sine
.floit vahe1
.float vilue-2
.word
LDI
,dita
_sine
s:l
S.
..FFT _RL:
INITIALIZE C FtKTlON
tl
,:-i
SINTAB
>
i
"I:S
TEXT
::
..FFTJI!.
_SItE
ass
.o..OIIl
.BSS
SYNCf'SIS:
M3
.0..011..
SET
.....
....~
Q
;:
rr
'::l
~
::!
~
ilK!
ti
RPTS
ADOF
SUSF
STF
STF
lUI
HARO AROt+ ,RO
fARO, f-MO,Rl
RO,f~ARO
Rl,lIARQtt
;
;
;
;
RQ=XtII+xtl+11
RI=Xtl I-Xtl +1 I
XtII=XtlltXtl+11
Xtltll=ltIHtl+11
LDI
LDI
lDI
lSH
SUSI
@INPUT,ARQ
2,IRQ
tFFTSII,RC
-2,Re
I,Re
i::l
RPTB
ADOF
."-3
SUBF
NEGF
IIlK2
I+AROIIROI, 'AROt+IIROI, RO
; RO=XtlI+Xtl+21
'ARQ, f-MOtlROI ,RI ; RI=XtlI-XII+21
++ARO,RO
; RQ=-Xtl+31
RQ, f-ARQ tl RO I
; XIII=XtlI+1iI+21
Rl,fMQH(IRO)
; Xtl+21=XIIHtl+21
RO, HMO
; Xllt31=-Xtl+31
<Q.,
~
\)
;:
$:l..
..
IIlK2
..
S~
$:l
;:
~
<:j
lOOP
g'"
~
INlOP
tv
C
a
C
LDI
lSH
lDI
LDI
LDI
lSH
lSf!
lSH
tFFTSII,lRO
-2,IRO
3,RS
I,R4
2,R3
-I,IRQ
I,R4
I,RJ
;
;
;
;
;
;
;
IRQ=INDEX F~ E
R5 nos TI CLIlRENT STAG NLI1IIER
R4=N4
R3=N2
E=E/2
N4=2fN4
R2=2tN2
S-
'"
...'"
~
STF
STF
STF
lDI
lDI
ADDI
lDI
!INPUT,AR5
IRO,ARO
ISINTAB,ARO
R4,IRI
LDI
ADDI
lDI
ADDI
LDI
SUBI
ADDI
AR5,ARI
I,ARI
ARI,AR3
RJ,AR3
AR3,AR2
2,AR2
R3,AR2,AR4
LOF
-IM5++(lRU ,RO
RO=X(J)
ADDF
SUEIF
STF
NEGF
ftAR5IIRII,RQ,RI
RO, f ..AR5( IRI I ,RO
RI, f-AR5tlRI I
RQ
RI=Xt I I+XtltN21
RQ=-Xtl 1+11 1+N21
XtIl =XI! 1+1iI+N21
RQ= Xtll-l tl tN2 I
NEGF
STF
STF
l++iIR5tIRll,RI
RQ,+i1R5
RI,t-AR5
RI=-Xtl+N4+N21
Xt ItN2I=Xtll-XtltN21
Xtl +N4tN2I=-Xtl +N4+N21
INtJmOSTLOCf>
g'
$:l
..
LDI
LSH
lDI
SUSI
IFFTSll,IRI
-2,IRI
R4,Re
2,Re
RPTB
It'YF
It'YF
It'YF
ADOF
II'YF
1lK3
tM3,ftARQtlRII,RQ ;
fAA4, .ARQ;RI
;
'AR4, ftARQt IRI I,RI ;
RQ,RI,R2
;
'AR3,tAAOt+IIRQI,RQ;
RQ,RI,RQ
;
fAR2,RQ,RI
;
fAR2,RQ,RI
;
SUIIf
.
..
..
1lK3
SUEIF
ADOF
STF
AOOF
STF
SUBF
STF
STF
SUBI
ADOI
CI1PI
!l.ED
ADDI
HOP
fa'
ADDI
C!l'1
!I.E
RQ=Xt!3lfCOS
RI=Xtl41'SIN
RI=xtl41'COS
R2=ltI3ItCO$+ltl4l'SIN
RQ=XI!3I'SIN
RO=-XIl3)*S]N+X(l4}tCOS !! I
Rl=-XlI2)+RO !!!
RI=X I 121+RQ .. ,
Rl,fM3H
; XIJ31=-X(2)+RO !!!
fARI,R2,RI
RI, 'AR4R2,fAAI,RI
Rl,lARl++
RI, iAR2--
;
;
;
;
;
!INPUT,AR5
R3,AR5
IFFTSIl,AR5
IILDP
!INPUT,AR5
RI=11ll 1+R2
X(J41=XII2HRO !!!
RI=XllIH12
ltlll=ltl1l+R2
XI121=XIllI-R2
; AR5=ltNl
; LW' BACK TO TI IHR LW'
1,R5
eUGFT,R5
lOOP
RESTORE TI REGISTER
POP
POP
POP
POP
POP
RETS
AR5
AR4
R5
R4
FP
V~UES
AND RETlIlN
--
LID'
APPENJUC3
GENERIC I'ROGIWI TO 00 AlWIIX-2 REIl. INIIERSE FFT CM'UTATlIII III TI
INl.IP
TIIS32OC3O.
TI lREIl.I DATA RESIlE IN INTERIW. tEItORY. TI COIf'UTATlIII IS In
IN-f'I.M:E. TI BIT REVERSIiL IS In AT TI IIEGlrtllNl IF TI I'ROGIWI. TI
1tf'UT DATA ARE SraD IN TI FOLLOIIINl 0RlER:
li'
'15
~
11tf'UT.AR5
lRO.1IRO
ISINTAB.IIRO
R4.IRI
LDI
ADDI,
LDI
ADDI
U11
SUBI
ADDI
AR5.ARI
I.ARI
ARI.AR3
Rl.AR3
ARl.AR2
2.AR2
Rl.AR2.AR4
NIP
AIIIF
SUIIF
t++IIR5URlI
, POINT TO IIl+N41
t-AR51 IRlI.f+IIR5URI I.RO
t+AR5URI I. f-ARSURI I.RI
RO.f-ARSURlI
, IUI=IUI+XIl+N21
RI ....AR5URlI
, IU+N2I-IIII-lU+N21
tAR5.RO
2.0.RO
RO. f-ARSURlI
, IU+N4I=2tIU+N41
t++IIR5URlI.RI
-2.0.RI
RI.fAR5++URlI
, XU+N4+N2I~XIl+N4+N2lf2
STF
STF
is
~TIDI:
g"
PANOS PIIPMIClW.IS
TEIAS INSTRtIIEIITS
.a,
.Ill.OBL
. 1ll.OBL
.1ll.OBL
.1ll.OBL
"
SIIE
tl
.BSS
INP.I024
,:-l
.TEIT
INITIALIZE
IFFT
N
LIF
NPYF
..
STF
LIF
NPYF
STF
1lK3
tAR2.tARI.RI
tAR2. tARI.RO
RI.f+llROIlRlI.RO
RO.tARI++
tAR3. tAR4.R2
tAR3._.R6
R2.fARO.R6
R6.tAR2R6.RO
R2.f+llROIIRlI.R6
RO,IAR3++
RI. tARO++I lROI.RO
R6.RO
RO.tAR4-
RPTB
SUIIF
ADIF
.IOIIRII
.1oIIRII
.1oIIRII
.1oIIRII
N
"
SINE
IMP
UIP
FFTSIZ
g
So
"'
~
N
NPYF
'FFTSIZ
LOOFFT
SINTAB
1tf'UT
IFFH
U11
U11
U11
LSH
LDI
LSH
I.IRO
3.R5
IFFTSIZ.Rl
-1.Rl
IfFTSIZ.R4
-2.R4
STF
ADIF
SUIF
::
NPYF
STF
::
SUIIF
NPYF
STF
1lK3
NPYF
ADIF
STF
ac
::
, lRO=INlEX FOR E
, R5 IILDS TI CIIlRENT STAlE IUIIIER
, R3oilII2=N2
, R4=NII4=N4
SUBI
CNPI
BLTO
ADlII
IrtlER LID'
LDI
ADDI
t'D
I'C t'D
== :I.
;-n
::.~
8ri5
=9
..
=
:s
t'D
2.Re
IFFT
n~
=
a :s
: 1"-
100
IFFTSIZ.IRI
-2.IRI
R4.RC
SPACE
.Q
U11
LSH
U11
SUBI
,WORD
So
INNERIIOST LID'
U11
U11
ADDI
U11
, RI=T1"IUlI-11121
RO=T1tCOS
1111 1=1111 1+11121
R2=T2=III3I+XIl41
, R6=T2tSIN
, 11121=XIl41-l1131
R6=T2tCOS
IU31=T1tCOS-T2tSIN
RO=T1tSIN
, XIl41=T1fSIN+T2tCDS
11tf'UT.1IR5
IfFTSlZ. AR5
Irt.OP
11tf'UT.AR5
lRO.ARO
ISINTAB. ARO
~o
::::=
00=
~~
==
Q~
=~
f
~
;:s
ADDI
~
~
I,RS
ILOIFFT,RS
L(IJ>
1,IRO
-1,R4
-1,R3
Cll'1
IlD
LSI!
LSH
LSI!
S!
go
lAST PASS
(F
"
E=E12
"
_12
N2=N212
11 MIN L(IJ>
;:s
tl
("')
!-i
s::..
I:i
~
C
"
"
STF
BLK2
I:
..VI
II'VF
STF
UF
Rl=XIII+XU+21
Rl'XIII-XII+21
XIII=XIII+XU+21
XII+21=X!Il-X1I+21
; Rl=2.OtXCI+1I
; XII+1I=2.OtXII+1I
; Rl=-2.OtXCI+31
; XCI+31=-2.0tXCI+31
; RO=XII+4+21
LENGTH-Till MTERFLIES
""
~
ADDF
SUBF
STF
STF
UF
.~
t+MOUROI,RO
BLK2
RO,fIIR(}++(IROI,Rl
RO,t-AROIlROI,Rl
Rl,'-ARO(IRO)
Rl,tARO++
t-ARO,RI
2,O,Rl
Rl,t-AROIIROI
tARO++,Rl
-2,O,Rl
Rl,t-ARO
t+AROIlROl,RO
UF
II'IF
So
UF
:1
~
g
tINPIIT,ARO
2,IRO
tFFTSIZ,Re
-2,Re
I,Re
IIPTB
!:>
;:s
a
So
..,""
LOI
LDI
LOI
LSH
SUBI
BLKI
I:
LOI
LDI
LSI!
51111
@INPIIT,ARO
IFFTSIZ,Re
-1,Re
I,Re
IIPTB
ADDF
SUIIF
STF
STF
BLKI
t+AAO, tARO++ , RO
tARO, t-ARO, Rl
RO,t-ARO
Rl,tMOt+
;
;
;
;
RO=XIIl+XH+1I
Rl=X!II-XII+1I
XIII=X!Il+XCI+11
X11+1 l=XII l-X1I+1 1
IFFTSIZ,Re
I,Re
IFFTSIZ,IRO
-1,IRO
IIPTB
BITRV
ARl,ARO
Cll'1
; RC=N
; Re SIO..UI BE
(J,(
; lRO=HALF 11 SIZE
m=N12
IUfltJT,MO
@INPIIT,ARI
IIIi:
UF
UF
STF
STF
ClJjT
BITRV
10'
to'
END
III
.END
CIJjT
tARO,RO
tMl,Rl
RO,IARI
Rl,tARO
tMl>++
tARl++IIROIB
; IF ARO<Ml
END
116
117
UF
STF
STF
"
APPENDIX Dl
00
TI TlIS32OC30,
"
10'
10'
~T
BITR'!
lOl
lOl
SlIiII
THE TWIDDLE FACTORS ARE stfPLIED IN A TAlilE PUT IN A .DATA SECTION. THIS
DATA IS IIQUDEO IN A SEPARATE FILE TO PRESERVE TIE GENERIC NATLIIf OF TIE
PIlOGRAl1. FOR TIE SM PURPOSE, THE SIZE OF TI FHT N AND LlmlNI ARE
DEFINED IN A .GLOBL DIRECTIVE AND SPECIFIED OOUtIJ Llrt<IOO. TIE LENGTH OF
THE TABLE IS NI4 t NI4 = N/2.
;:,:
~
;:!
'is"
:::to
.il..0!Il
;:,:
..:;,
~
:-J
tl
.GLOBL
.GLO!Il
.GLOBL
.BSS
FHT
N
RPTB
AIU
SlIIIF
STF
STF
"
"
SINE
;
;
;
;
INP,1024
~tQlY
TEXT
INITIALIZE
I:l
;:,:
I:l..
WORD
FHT
"
SPACE
100
"
'"....
I:l
;:,:
..;,
~
'"
~
FHTSIZ
LOGFHT
SINTAB
INPUT
WORD
INP
FHT<
LOP
FHTSIZ
WORD
WORD
WORD
N
C
RPTB
CMPI
BHRY
ARl,ARO
CONT
tARO,RO
'"
a
C
Q.
~.
.~
@INPUT,ARO
lRO,RC
1,RC
I-"
BLKl
HARO, tARO++, RO
tARO, t-ARO, Rl
RO,HIRO
Rl, tARO++
;
;
;
;
RO=Xllltl(J+1I
Rl=XU)-lU+1)
XU)=xtI)+xII+1I
XII+II=xtII-XU+1I
lOl
lOl
lOl
LSH
SlIiII
@INPUT,ARO
2,IRO
eFHTSIZ,RC
-2,RC
1,RC
RPTB
AIU
SlIIIF
STF
UF
AODF
STF
SlIIIF
STF
STF
BLK2
; RO=XIJ)+XIL2)
HAROI lRO), 'ARO++I lROI, RO
f'ARO,*-MO(IROI,Rl ; Rl=XIJI-XIL2)
; X(JI=X(JI+x(L2)
RO, HIROURO)
; RO=XIL4)
HARO,RO
; Rl=XIL3)+XIL41
RO, t-ARO,Rl
; XIL2I=IIJI-XIL2)
RI, tARO++
; Rl=XIL31-XIL4)
RO,H.ROURO),Rl
; XIL3)=IIL3)tXIL4)
Rl, H.ROURO)
; XIL4)=XIL3l-XIL4)
Rl,tARO++
=
-=
.,..
~
=-~
~ '"1
~r':)
~::p
~ci5
N'"1
~a
~=Q
~
t=
Q.
~.
I
~IN
S-
"
BLK2
"SINE
LDI
SUBI
LOI
LSH
LDI
lOl
;:,:
(j
--.,
BLKI
AUTHOR; PANOS PAPAIIICHALIS
TEXAS INSTRlINTS
;:,:
"t:S
LENGTH-TIll WTTERFLIES
tARl,Rl
RO, 'ARI
Rl , tARO
tARO++
tARl++URO)B
; RC=N
; RC SIIllD BE ONE LESS TIWI DESIRED
LOOP
eFHTSIZ,IRO
-2,IRO
3,R5
1,R4
2,R3
-l,IRO
1,R4
1,R3
;
;
;
;
;
;
;
lRO=INDEX FOO E
R5 f.DS TIE ClIlRENT STAGE tuIBER
R4=N4
RJoII2
E=E/2
N4=2'N4
N2=21N2
~
'"1
~
'-<i
'"1
=
~
[IJ
BGE
LDF
; XCHANGE LOCIITI~
IF ARO<ARI
(H.y
INlOP
lOl
lOl
ADDI
LDI
@INPUT,AR5
lRO,ARO
tsINTAB,ARO
R4,IRl
'"1
:3
:l:..
;::
LDI
AIIDI
LDI
ADDI
LDI
SUBI
ADDI
!?
'ti
i1!
'"is
'
;::
.s;,
LDF
AIIDF
SUBF
STF
.~
"
"
STF
LDF
AIIDF
"
STF
STF
t"l
.'-3
i:l
;::
SUBF
i:l..
!:\
;::
~
'l
"
S.
~
c;:,
a
c;:,
RI,'-IIR5!1RlI
RO
RO,f1iR5
f+AR5!1RlI ,RO
RO,'-IIR5IIRlI,RI
RO, '-AR51 IRII ,RI
RI,'-IIR5!1RlI
RI, .fIiR5lIRli
LDI
LSH
LDI
SUBI
@FHTSIZ,IRI
-2,IRI
R4,Re
2,Re
RPTB
If'YF
If'YF
If'YF
ADDF
If'YF
AIIDF
STF
AIIDF
STF
SUBF
STF
STF
IlK3
tAR3,f+AIlO!lRlI,RO
fAR4,fMO,Rl
tAR4, f+AIlOI IRII ,RI
RO,RI,R2
tAR3,'ARO++IIROI,RO
RI,RO,RO
RO,'AR2,RI
fAR2,RO,RI
RI,'AR4-tARI,R2,RI
RI,'AR2-R2,tARI,RI
Rl,*ARl++
RI, tAR3++
SUBI
ADDI
Clf'I
IlTD
ADDI
fINPUT,ARS
R"J,1IR5
@FHTSIZ,1IR5
INLOP
fIIf'UT,1IR5
SUBF
SUBF
'"
tAR5++IIRlI,RO
<+IIR5!1RII,RO,RI
RO,u-tAR5(IRl),RO
"
"
::
BLK3
Ia
N(p
.....
.....
I,C)
AIIDI
Clf'I
1,R5
KOO'HT,RS
END
IIl
LOCI'
III
END
,END
; AR3 POINTS TO XIL31=XlU+N21
; AR2 POINTS TO XIL2I=XlJ-I+I+1121
; AR4 POINTS TO X!L41=11L2+1121
;
;
;
;
;
;
;
;
;
;
;
RO=IIJI
RI=XlJI+IIL21
RO=-XlJ)+IIL2)
IIJ)=XlJI+IIL2)
RO=IIJHIL21
IIL2)=XIJHIL2)
RO=llL41
RI=XIL31+IIL41
RI=IIL31-lIL4)
XIL31=IIL31+IIL41
IIL41=X!L3HIL41
INNI'III1OST LOCI'
~
..,'"
'l
;::
NEGF
IIR5,ARI
I,ARI
ARI,AR3
RJ,AR3
AR3,AR2
2,AR2
RJ,AR2,AR4
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RO=XIL31.COS
RI=XIL41.SIN
RI=IIL411COS
R2=IIL3IICOS+XIL4lfSIN=T1
RO=IIL31.SIN
RO=IIL31'SIN-1II41ICOS=T2
RI=IIL2H2
RI=IIL2)+T2
XIL41=IIL21-T2
RI=XlL1I+T1
XIL2)=XIL21+T2
RI=IIUHI
XlU)=IIL1l+T1
XIL31=XlUHI
; AR5=I+NI
; LOCI' BACK TO TI lIfER LOCI'
120
121
t-l
t-l
OOTSllLLOOP.
ftlllllU.lD'l
IIPf'ENIIX EI
A FAST COSIIE TRAIISFORII
!lASED IJI TIE ALGaUM OOTLIIED IIY IIYElNl GI LEE IN HIS ARTIQ.E, FCT - A
FAST COSIIE TRANSFORII, PUllLISIEII IN 11 PROCEEDINGS IF 11 IEEE INTER-
LEE'S AU~IUM HAS BEEN IIIDIFIED TG ALLIJI NATlRIL OIlER T1~ _IN
COO'FICIENTS RATHER THAN 11 LESS _
INPUT SUGGESTED IN HIS ARTIQ.E.
~
'e
...
is
C
;:s
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0.5224986
1.7224471
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0.7881546
0.5097956
2.5629154
0.6013449
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0.7071068
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128
APPENDIX E4
DATA FILE
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FILE TO BE LINKED WITH TIE SWlCf COlE All A M-1'OINT. RADIX-4
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0.773010
0.707107
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0.555570
0.471397
0.38U83
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{
text: {}
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IN 809800h : { 12fopt.obj(IN) }
.bss 809COOh: {}
}
135
136
Doublelength Floating-Point
Arithmetic on the TMS320C30
AI. Lovrich
137
138
Short floating-point format, used to represent immediate operands, consisting of a 4-bit exponent and a 12-bit mantissa.
Single-precision format, used for regular floating-point value representation, consisting of an 8-bit exponent and a 24-bit mantissa.
139
f
Figure 1. Single-Precision Floating-Point Format of the TMS320C30
Operations are performed with an implied binary point between bits 23 and 22. When
the implied most-significant nonsign bit is made explicit, it is located to the immediate
left of the binary point after the sign bit. We show the implied bit explicitly throughout
this application report for clarity. The floating-point number x is expressed as follows:
x
if
if
if
s = 0;
s = 1;
e = -128, s = 0, andf= 0
The range and precision available with the TMS320C30 single-precision floatingpoint format are illustrated by the following values:
Most Positive:
Least Positive:
Least Negative:
Most Negative:
x
x
x
x
=
=
=
=
+3.4028234 x 10+ 38
+5.8774717 X 10- 39
-5.8774724 X 10- 39
-3.4028236 X 10+ 38
140
the most significant portion of the floating-point operation, while zz represents the least
significant portion of the floating-point operation.
As an example, consider the result of the exact addition of two floating-point numbers
x and y that are expressed in the single-precision format of the TMS320C30:
x = 217FFFFFh
Y = OC7FFFFFh
= 233
= 233
X
X
As can be seen in this example, most of the precision available for y will not be
available to carry out the addition. Maintaining full precision for floating-point addition
requires extra mantissa bits beyond the 24 bits available on the DSP. Since the need for
such precision is rare, software methods are used to represent the result of the operation
as a floating-point number pair (z,zz). In our example, the exact result is represented as
follows:
z = 234 X 01.000 0000 0000 0000 0000 00l1b
zz = 209 X 01.111 1111 1111 1111 1111 1000b
The corresponding hexadecimal representation of (z,zz) is shown below:
z = 22000003h
zz = 097FFFF8h
Some definitions are basic to the development of concepts in this report. First is
the definition of the floating-point operations over a system R. The system contains all
the possible floating-point numbers that the single-precision format of the TMS320C30
can represent. All the floating-point arithmetic is carried out in base 2. Therefore, R can
be represented as follows on the TMS320C30:
141
multiplier on the TMS32OC30 saves the upper 40 bits of the mantissa in one of the extendedprecision registers [1] and drops the least significant byte of the result. By this definition,
the floating-point multiplication on the TMS320C30 is faithful. Since the algorithms require the floating-point result to be in single-precision format, the floating-pointmultiplication on the DSP must therefore be followed by a second truncation step. Saving the contents
of the extended-precision register to a memory location or masking off the low 8 bits results
in truncation.
A floating-point operation is optimal if for all x and y, the result of fl(x * y) is an element
of R nearest to (x * y). In other words, the round-off error should not exceed one-half
of the last remaining bit position. This is commonly referred to as rounding.
The results of floating-point operations on the TMS320C30 are stored in the extendedprecision registers [1]. The extended-precision register adds 8 bits of precision to the
floating-point arithmetic result. Execution of the RND (round) instruction forces the result
of the floating-point arithmetic to be optimal. When you round the result of the addition
or subtraction operations on the TMS320C30, these floating-point operations become
optimal.
Z+zz=x+y
(2)
142
=y-
(z - x)
(3)
(4)
In particular, Ixl > Iyl must be valid for Equation (4) to be valid. Implementation
of Equation (4) on the TMS320C30 always generates the exact correction term zz if the
result of floating-point addition operation is made optimal. This requirement guarantees
that the result of single-precision floating-point add and subtract belongs to system R. By
swapping the x and y values 'when Ixl < IYI, the condition for obtaining an exact result
is met.
The algorithm requires that x and y be normalized. Normalization guarantees that
the floating-point number has only one sign bit, and that sign bit is followed by nonsign
bits [1]. Floating-point addition on the TMS320C30 assumes that the operands are normalized.
The TMS320C30 assembly code for obtaining the doublelength sum of two
singlelength floating-point numbers x and y is shown in Appendix A. First, the values
for x and yare interchanged when Ixl < Iyl. When you add x and y values, the number
with the smaller exponent, y, is shifted repeatedly until the exponents of x and yare equal
and their mantissas are aligned. We have now calculated the singlelength number,z, that
satisfies Equation (2). Since the floating-point addition on the TMS320C30 is made optimal by rounding, the extra precision is, in effect, dropped. The extra precision value,
zz, is obtained by implementing Equation (4). Figure 2 is a graphical representation of
the implemented algorithm. The figure also shows the relationship between doublelength
number pair (z,zz) and singlelength floating-point numbers and their representation on
the TMS320C30.
143
FaA'
-e(X~
I I
e(y)
24
f(x)
'I
f(y)
x+y
z
zz
f2(normalized)
Doublelength Addition .
A natural extension of exact singlelength addition and subtraction is its application
to doublelength arithmetic. Figure 3 shows an algorithm for implementing doublelength
addition on the DSP. Using this algorithm, you can add two doublelength numbers (x,xx)
and (y ,yy) and represent the result as a doublelength number (z,zz).
The algorithm requires forming a doublelength number (r,rr) that represents an exact addition of x and y. Generating a second number, s = rr + yy) + xx), results in
a number pair (r,s) that approximates the addition of (x,xx) and (y,yy). Finally, an exact
addition of rand s generates a doublelength number (z,zz) that has the same value as (x,xx)
+ (y,yy).
To obtain exact results for addition and subtraction, subtraction and addition must
be optimal; this is guaranteed by following each subtraction or addition instruction on
.
the DSP with a round instruction.
144
r = x + y;
if (abs(x) >abs(y
s = x - r
else
s =y - r
z = r + s;
. zz = r - z + s;
+ y + yy + xx;
+ x + xx + yy;
(5)
145
;
;
;
;
hy
ty
= Y=y-
P + p;
hy;
p = hx X hy;
q = hx X ty + tx X hy;
z = P + q;
zz = p - z + q + tx X ty;
Figure 4. Exact Singlelength Product
Doublelength Multiplication
The doublelength multiplication algorithm, shown in Figure 5, relies on the
singlelength algorithm discussed earlier. The algorithm generates a nearly doublelength
approximation of the output result (c,cc). Note that the exact singlelength mUltiplication
routine is used for this approximation. Exact addition is used to generate a doublelength
floating-point number that is the closest approximation to the actual result.
The doublelength product program implementation uses the TMS320C30 stack
capabilities to save some intermediate variables. These programs are written to be used
as callable functions or macros in your program. In either case, the stack pointer must
be set to a valid memory segment for proper code execution.
; Calculate the doublelength product of (x,xx) and (y,yy)
; the result being a nearly doublelength number (z,zz).
; Program uses exact singlelength multiplication, mult12 (.).
mult12 (x, y, c, cc);
cc = x X yy + xx X Y + cc;
z = c + cc;
zz = c - z + cc;
Figure 5. Exact Doublelength Product
146
xx - c
yy) / y;
147
Error Analysis
This section discusses and determines an upper bound for the error generated in
forming a doublelength result. The value of the doublelength number (z,zz) is equal to
z + zz. Singlelength addition, subtraction, and multiplication results are always exact.
In doublelength addition, any error introduced in the end result is generated by calculating
the zz term. An upper bound error magnitude has been calculated in Reference [2] and
is shown in Equation (6) as follows:
Iy +yyll x
2 2 - 2t
= IZI x
(6)
22-2t
where t = 24 for this system. This gives an upper bound of Izi X 2-46 , or approximately Izl x 1.42 x 10- 14 . This translates to a theorical accuracy greater than 13 decimal
places. Table 1 shows an example of doublelength addition using the exact addition
algorithm previously described. The numbers in the left column represent TMS320C30
hexadecimal notation for the floating-point results, and (z,zz) is the decimal equivalent
of the doublelength output result. Appendix B shows a listing of C programs (exact) that
convert from TMS320C30 hexadecimal notation to decimal notation.
Table 1. Exact Singlelength Arithmetic Examples
Singlelength Addition
x
= 217FFFFFh
= OC7FFFFFh
= 22000003h
zz
= 097FFFF8h
= FC7C8923h
= OA29A7E5h
= OA29ABD8h
zz
= EFA46000h
148
= OF7FFFFFh
= 21FFFFFFh
= 30800000h
zz
= 18800002h
= FC7CB923h
= OA29A7E5h
= 07277BF7h
zz
= EBA714FOh
(DS~
The doublelength product, quotient, and square-root algorithms all have a small
relative error. The upperbound error magnitude for each is given in Equations (7) through
(9).
IExl=(lx+xxl x Iy+yyl) x 11 x 2- 48
(7)
IE + I =(Ix +xxl
(8)
(9)
149
x
xx
y
yy
Z
zz
x
xx
y
yy
Z
zz
=
=
=
=
=
=
=
=
=
=
=
=
22000000h
097FFFFEh
21000001h
097FFFFEh
43000002h
(Z,ZZ)
1.47573996570139475 x 10 20 (Exact)
1.47573996570139427 x 1020 (DSP)
2A7FFFFCh
22000003h
097FFFF8h
OA29ABD8h
EFA46000h
2C29ABDDh
(z,zz)
23319450552284.2434 (Exact)
23319450552284.1250 (DSP)
13907DC2h
Doublelength Quotient
x
xx
y
yy
z
zz
x
xx
y
yy
Z
zz
=
=
=
=
=
=
=
=
=
=
=
=
43000002h
2A7FFFFCh
2C29ABDDh
13907DC2h
1641205Ah
(Z,ZZ)
FC24BE20h
6328365.08044074177 (Exact)
6328365.08044075966 (DSP)
22000000h
097FFFFEh
21000001h
097FFFFEh
007FFFFDh
(z,zz)
1.99999964237223082 (Exact)
1.99999964237217398 (DSP)
D3400000h
x
xx
Z
zz
x
xx
Z
zz
150
=
=
=
=
=
=
=
=
2C2BDDOOh
3907DC2h
61451A4h
(Z,ZZ)
FB39EF11h
4860114.04539400958 (Exact)
4860114.04539400712 (DSP)
21000001h
097FFFFEh
103504F5h
F7BC0784h
(Z,ZZ)
92681.9110722252960 (Exact)
92681.9110722253099 (DSP)
Note that the results were obtained using the programs shown in Appendix B. The
C programs were created and compiled on a 80386-based microcomputer running under
MS-DOS 3.3.
Set up a local frame by saving the old frame pointer on the stack.
Assign the new frame pointer to the current value of stack pointer.
Allocate the frame.
Save any dedicated registers that the function modifies.
Execute function code.
Store a scalar value in RO.
Deallocate the frame.
Lastly, restore the old frame pointer [4].
The following code segment shows the singlelength addition routine modified to be
in C-callable form. Note that registers R4 through R7 and AR4 through AR7 are dedicated
registers used by the compiler. These registers must be saved as floating-point values.
single
fp
x
y
z
zz
.set
.set
.set
.set
.set
.set
OFFh
ar3
rO
r1
r2
r3
151
w
x1
y1
.set
.set
.set
.global
.width
.text
r4
r2
r3
_add12:
push
pushf
push
Idi
Idi
Idi
absf
absf
cmpf
Idflt
Idflt
dflt
fp
r4
r4
sp,fp
* -fp[2],rO
* - fp[3],r1
x,x1
y,y1
y1,x1
x,x1
y,x
x1,y
; Save old fp
addf3
rnd
subf3
rnd
subf3
rnd
pop
popf
pop
retsu
.end
x,y,z
z
x,z,w
w
w,y,zz
zz
r4
r4
fp
;z=x+y
96
_add12:
; Form w = z - x
; zz
= y - [y - w]
; Restore fp
Conclusion
This report presented an implementation of extended-precision arithmetic routines
for the TMS320C30 DSP. The programs presented include singlelength floating-point addition, subtraction, and multiplication, which produce exact doublelength results.
Doublelength floating-point addition, subtraction, multiplication, division, and square root
were also presented. The doublelength floating-point routines all had a small relative error that appeared in the correction term zz. However, it has been shown that the accuracy
of the doublelength floating-point result is at least 13 decimal digits. Table 3 is a summary
of information about the routines contained in Appendices A and B. Execution times shown
152
in the table are given only for the routines in Appendix A. These times do not include
the call and return if the routine is implemented as a called function. They also do not
include any context saves and restores that may be required.
Table 3. Summary Information
Routine
Mnemonic
Appendix
Code Size
Execution
(Words)
(Cycles)
Singlelength Add
_add12
A1
12
12
Doublelength Add
_dbladd
A2
25
25
Singlelength Multiply
-"1ult12
A3
35
35
Doublelength Multiply
_mult2
A4
51
51
Doublelength Divide
_div2
A5
115
115
_sqrt2
A6
163
163
C30DBL
B1
C30DBL2
B2
References
[1.]
[2.]
[3.]
[4.]
[5.]
[6.]
Third-Generation TMS320 User's Guide (literature number SPRU031), Texas Instruments, Inc., 1988.
Dekker, T.J., "A Floating-Point Technique for Extending the Available Precision",
Numer. Math. 18, 1971, pp 224-242.
Linnainmaa, S., "Software for Doubled-Precision Floating-Point Computations",
ACM Transactions on Mathematical Software, Vol. 7, No.3, Sept. 1981, pp
272-283.
TMS320C30 C Compiler (literature number SPRU034), Texas Instruments, Inc.,
1988.
Kernigan, B.W. and Ritchie, D.M., The C Programming Language, 2nd Revision,
Prentice-Hall, Englewood Cliffs, New Jersey, 1978.
Kochan, S.G., Programming in C, Second Edition, Howard K. Sams, Indianapolis,
Indiana, 1988.
153
Appendix A
154
;::
<::!~
~~
~
2
S
~
~.
()Q
HHHfHHHHfIIIIIIIIIlIIIIIIIHfHfHfHHHHfH..
Entry Conditions:
Upon entry (rO,1'1l contains Ix,y)
Exit Conditionsl
Upon exit 11'2,1'31 conti-ins Iz,zz),
Registers Affected:
rO, 1'1, r2, 1'3, 1'4
Revision: Original
Execution n.t: 12 cycles
H*tHHHH+HHHJ:HfHfffHfHfHHffHffHfHfHff
single
::I.
.set
.set
;;!
...-.
~
<"\
~
~
.set
.9101>01
zz
xl
yl
.set
.set
.set
Offh
..iddl2
e:=
,0
,I
,2
.>
,3
,4
.Sit
,2
.set
. text
,3
...
=
rLJ.
_iddI2.
~
~
N
C
x,xl
absf
ibsf
capl
Idflt
y,yl
yl,xl
1df1t
y,'
Idllt
xl,y
iddl3
rod
x,y,z
5ubf3
X,Z,III
x,xl
; :xl ) 1'1: ?
; if not, exchuge x " y
.end
....
VI
VI
III,Y,ll
zz
t""
-=-=~
(JQ
Iz=x+y
,od
(JQ
5ubf3
,od
retsu
>
"=
"=
;fol'."=z-x
>
Q.
;zz=y-~
AUHIOIl: AI Lovrici1
rexa~;
2/21/89
In~;trumenls,
Inc.
neqi~;ter5
AffeGtecl:
rN, r 1, r2, r3, r4, rh, rf}, r7
* Hev i s ion: Or i ~J i na I
* ~::xecu1ion time: 2~) Gycles
**** ***'Ie *** ******(lhl,,,ld
'" ********** **** *** **** **** **** *** ****
.~ll
xx
y
yy
z
lZ
x1
yl
obal
set
set
set
set
set
set
set
set
set
se t
rN
rl
r2
1<3
r4
15
rG
(!
r6
r7
.Iexl
clbI a(ld:
absl
absf
011p"t
I (If I I
I elf! t
I clf I I
I ell I t
I (If 11
I elf It
x,x1
xx, y1
ancl (y,yy)
vy. xx
x1, y
y1, yy
x, y, r
rnc1
subf3
rncl
adell3
!""ncJ
adelt
rnd
aelelf
rnd
subf3
I"nd
acldf3
rnd
retsu
.end
y,x
adell3
adelf'3
I"nd
156
><,x'l
y, y1
y1, x1
+ y
,x.:;
y, s, s
r +
yy, s
r + y .f yy
xx, s
r.f
r, lZ
YY
xx
r + s
s, r ,1
7.
77
"l..l.
S, 17,7'1
2/
Z + S
zz
subf3
f
~.
~~.
::...
;:;.
::!.
Al.JTt('R:
Entry Conditions:
Upon entry (rO,rlJ contains (x,y)
Exit Conditions:
Upon exit (rO,rH contains (Z,IZ),
Registers Affected:
rO, rl, r2, r3, r4, r5, NI, r7
Revision: Original
Execution TiH: 3S Cycles
~.
single
~
N
C
o
C
,gl.bal
...1
set
. set
, .. I
x
Ix
q
by
Iy
zz
.Ieop
set
.set
.5et
.set
set
.set
.set
.set
.text
.....:J
"",hy,p
;p=hXfhy
; fJl.> is faithful
.pyl3
andn
"py13
andn
addl3
rnd
subl3
rnd
addl
rnd
.pyl3
rO
rl
r7
single, te.p
tx,hy,q
single,q
q, te.p,q
;telp=hxfty
; f1(*) is fi.ithful
;q=txfhy
; f1 (f) is faithful
; q=hXfty+txfhy
p,q,z
>
;z=p+q
~
~
I'D
z
l,p,ZZ
zz
q,zz
zz
txt ty, te.p
andn
single, hap
addl3
rnd
ZZ, hiP, zz
;zz=p-z
I."p,x,p
; p
single,p
; f1(.) is fiithful
subf3
PIX, hx
Ihx=x-p
rnd
hx
addl3
rnd
"",p,""
hx
;hx=x-p+p
s.bl3
rnd
hx,x, tx
I tx =x-bx
"py13
te.p,y,p
single,p
; p = Y I constant
; fHI) is faithful
p,y,hy
hy
hy,p,hy
hy
,hy=y-p
= x cons tint
.=
Q..
;zz=p-z+q
;telp=txfty
; flit) is faithful
; zz=P-Z+q+tXfty
zz
..
=
'J.l
rttsu
(JCl
,data
I'D
.11.al
'constant, teap
rnd
addl3
rnd
singJe,p
conshntl
Idl
.pyl3
andn
subf3
Ul
.... 1112
om
rO
rl
r2
r3
r4
,5
r5
r6
.... 1112'
indn
"py13
ando
addl3
rnd
HfHHfHftHHHHHfHfHHHHffHfHHHffH+tHf
;:;.
,Iy=y-hy
AI Lovrich 2/21189
~;:;.
:!J
~
hy,y,ly
Iy
rnd
.end
4097
; constant
=2"'124-2412)+1
-==I'D
(JCl
-.=.
""d
Ix
;hy=y-p+p
u;
00
HHffHHIHtfHfHffHHfHffHflfHHfffHffHUHf
FlKTlOOIEF , -"ult2
Al LOYl"'ich
212118'1
Texas InstruHots, Inc.
Entry Conditions:
Upon entry (1'0,1'1> conhins (x,y),
and (1"2,1'3) contains (xx,yy).
Exit Conditions:
Upon exit (1'0,1'1) contiins (z,zz),
Registers Affected:
rO, 1'1, 1'2, 1"3, 1'4, 1'5, 1'6, 1'7
!f
So
~
::l'.
;:.
~~.
~
:I.
So
~
::l'.
'"
'c:>"'
;:.
So
'"
a
C
,hx=x-p
rnd
addl3
rnd
p,x,hx
hx
hx,p,hx
hx
subf3
rnd
hX,x,tx
tx
;tx=x-hx
opyl3
tup,y,p
; p =Y f constant
andn
singlt,p
subl3
rnd
addl3
rnd
p,y,hy
hy
hY,p,hy
hy
addl
rod
constant
tup,cc
1 CC=X*YY+XX*Y+CC
"
addl3
rnd
;hx=x-p+p
CC,C,1
;z=c+cc
.. zz=c-z+cc
Algorithl used:
lult12tx, y, c, cel;
cc=x*yy+xx.y+cq
Revision; Original
Execution TiIH': 51 cycles
HHHfHfffHflllllllll.llllllllllllffHHHffHffHf
....1t2
,global
single
Offh
.set
.set
rO
r1
y
.set
p
r2
.set
r3
hx
.Stt
r~
set
Ix
q
r5
.set
r5
hy
.set
ty
.set
r'
.set
rO
r1
zz
.set
xx
.set
r2
yy
r3
.set
r~
.set
cc
.set
r'
t ..pO
.set
r'
.set
r7
tellP
.ttxt
...ult20
; teapO = ~yy
apyl3
x,yy, teapO
udn
single, teapO
; teap = ylxx
y,xx, teap
lIPyl3
single,teap
andn
; tHP = xfyy + ylxx
te.pO. teap
addl
leap
rnd
; (xiyy + y1xx)
telp
pushl
breik:
I ault12(x, y, e, cd
I cc=xlyt+xxfy+ec
subf3
IZ=C+CC
zz=c-z+cq
Iconstant, tnp
teap,X, p
; p =X
single,p
AI.JTtI(fi:
z = c ... ee;
;;:
<:l"
~
Idl
apyl3
ando
subf3
hy,y,ty
,hy=y-p
;hy=y-p+p
,tY'y-hy
rnd
ty
hx,hy,p
singie,p
lIjIyl3
indn
Ipyl3
ando
addl3
rnd
apyl3
andn
addl3
rnd
; ttlp = tx I ty
subf3
e, p,ee
;ee=p-e
rnd
addl
rnd
addl
rnd
cc
;p=hxfny
;zz=c-z
;zz=c-z+cc
retsu
(t>
data
.end
>
"C
"C
4097
; conshnt
= 2"(24-2412)+1
=
e:
>
~
~
;tttp=hXfty
-6(t>
;q=txlhy
;q=hxlty+txlhy
t"'4
-=-=
(t>
(JCI
;e=p+q
;ee=p-c+q
cc
teap,ee
cc
; ec=p-c+q+txfty
teap
; XIy + ytxx
I restore variables
popl
Z,C,tZ
zz
zl,ee,zz
zz
constant:
.float
apyf3
andn
q,ee
subl3
rnd
addl3
rnd
--
=
...
"C
;:
HHIIIIIIIIIIIIIIIIIIIIIUII"IUllllfHHfHffHffH
I
0<>
15
g.
0<>
~
S
I
I
I
AlgoritM used:
IlUltl2(c, Y. u, uu);
::I.
S-
I
I
cc = I,x- u- uu +xx-c
Z = C + ee;
%z=c-z+cq
~.
a
C
globol
.5tt
_div2
Offh
rO
rl
r2
r3
r4
r4
r5
r5
r6
rO
rl
r2
r3
r7
r3
rl
r2
r3
set
.5.t
zz
.5tt
y
p
.s.t
.s.t
.5It
hx
.5.t
Ix
yl
.Stt
hy
ty
.stt
.5et
,set
.5et
zz
.5.t
set
xx
yy
tt.p
ttopl
teap2
...t
set
.s.t
... t
.s.t
.5.t
cc
u
uu
VI
pushf
rO
iSh
-24,rO
popf
f
xx
Sive x
; Now Rl
x[O]
:I
opyf3
.. dn
rO,r1,r2
singlf,r2
; R2
subrf
2.0,r2
r2
; R2 = 2.0 -
r2.rO
lin91e,rO
; Rl
rO.rl,r2
sing1t,r2
2.0,r2
; R2 = V
andn
Sivt
24,rO
rO
rO
1.0" 2H(;-1).
:I
udn
subr;
rnd
opyf
indn
I:
I:
Y f x[OJ
x[1]
V f x[O]
I:
x[OJ
(2.0 - v
f x[O])
x[tJ
; R2 = 2.0 -
V f
x[1]
r2
r2,rO
singl rO
~
~
6-
~
...
<
rnd
lIIIyf
save yy
rO
1,rO
~.
rtfgi
subi
uh
push
f
Q..
opyf
yy
xx
rl
pop
the RI = -127 - I = -128. Thus x[Ol = 0 ond this _ill (iuse tho olgoritha
tfxt
1.0
rl
_div2'
pushf
1"1,1"3
pushf
yy) I y;
pushf
ldf
..bsf
tHffHtHftfHHHHffHfHHflllllllllllllllllffHU
single
inv_f:
Rtvision: Original
<)
c=x/y;
'"
'"
to
Regist.rs Affected:
1'0, 1'1, 1'2. 1'3, 1'4, 1'5, r6, 1'7
S-
Entry Conditions:
Upon entry 11'0,1'0 contains Ix,y),
and (r2,r3) contains Cxx,yy),
Exi t Conditions:
Upon exit (1'0,1'11 contains (Z,lZ),
...
;:s
; SlY' Y
Icx/y;
"
S-
pushl
8l
"pyf
lAdn
subr
,nd
lI'yf
iOdo
1"0,1'1,1'2
li0911,1'2
2.0,,2
,2
;R2=vlx[21
1'2,1'0
;- Rl = x[3] = x[2]
o,yf
iOcin
;R2:cv
.nd
lI'yl
1"0,1'1,1'2
Sillglt,rO
2.0.,2
.2
1'2,1'0
iOdn
singl.,tO
ldl
opyl3
udn
leonstant, tap
.. bf3
rnd
oddf3
,nd
p.x,hx
I hx-x"p_
hx
hx.p.""
hx
I hx=x-p.p
bI3
.nd
hx,x, tx
Ix
;tx=x-hx
opyl3
top,y,p
singt."
; P . y I eGnstlRt
lndn
bI3
,nd
oddl3
.nd
p.y.hy
hy
hy.p.hy
hy
Ihy'y-p
bI3
.nd
hy.y.ty
ty
IIY'y-hy
opyl3
!\x,hy,p
singl."
I p-""'hy
;I.... hx.ty
; -R2 =.2.0 ..
x[2]
(2~O
subrf
; R2
x[31
=2.0 -- v
x[31
I::
1:3~
~S~
~.
~
~.
~
::I.
S;:
~.
"l
g
S'1>
N
C
Q
C
lI'yl
iOdo
Jubrf
.nd
lI'yl
iO'"
addf
.nd
Noll tho CUt .1 v
..,I
1'0,1'1,1'2
singll,r2
1.02
.2
1'0,1'2
lingll,1'2
.2 0
; R2 = v x[41 = 1.0.. 01 .. =) I
rO 1
<0 i.
hlndl,d.
Idl
ldln
1'1,1'2
.33
1'2,1'1
Idl
rl,t.
; MVt lly
o,yl
tncin
I IUlU2le, y, u, uu)
lI'yl3
Indn
lingl., ttlp
lI'yf3
.. dn
Iddl3
rod
lx.hY,q
singl',q
q, t ..... q
q
lI'y13
III'"
; rtstor. y
; rtstort x
; SlY. x
yl,x
singlt,x
Ie;,; x I
stv. vt.rilblts
puohl
phl
lndn
x
yl
; SlY' e
; SlY' lly
Ihy'y-p+p
;q-tx'hy
lqahxtty+txfhy
I rtstort vlritb1ts
popl
popl
pu.hl
I P x constant
- v x[2])
singl.,rO
1
t ..... x.P
singl",
Iddl3
rod
tty)
.vbl3
rod
oddl
.nd
tx, ty,ttlp
.t..,-tx.ty
singlt, ttIP
P.,q,u
;up+q
U,p,UU
tUUp-u
VI
q,uu
v.
I uup-u+q
popl
popl
popl
subl3
end
subf
rnd
popl
oddl
rnd
popl
.pyl
indo
S-
i\'
i\'
JJ
S.
~
~.
~
S
subf
...
S.
rod
opyf
indn
yl
c
restore lIy
res tOte ,
t p
testort x
U, tNP,CC
(c=x-u
cc
UU,CC
;cc=x-u-uu
cc
hap
ttllP,CC
; restore xx
; cc =x - u -
YU
+ xx
cc
ttlp
c, ttlp
single, tMP
tUp, ec
; restore yy
; c yy
; cc=x-u-uu+xx-c*Y)
cc
=( x -
yl,ec
single,cc
; cc
(,Ce,l
IZ=C+C'
l,C,ZZ.
;zz=c-z
u - uu
xx -
:::So
;:
IZ=C+CC
oddl3
rod
ri'
S.
zz=c-z+cc
subf
rnd
aW
rnd
rehu
'"
~
~
Q
C
-0'1
zz
ce,ll
; ZI
=C -
+ CC
zz
dati.
cOIls-h.ot;
.floit
.end
4091
; conshnt-
= 2"(24-24121+1
C f
yy ) I Y
....
flll:TllII IEF
pu.hf
",yf
..d.
pushf
pop
uh
.sqrt2
li/liiii. Al ltYricb
2121189
EAtry Conditio.s
Upon try (rO,rU cooloi (x, xx).
Exi t Conditiensl
(ztu),
Rlglsl.r. Afftcl.d'
rOt 1'1, .1'2, ,.3, r4, rS, 1'6, 1'7
IHIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIHH
~
;:
Revisionl Drigi....1
Extculio. n ... 163 Cycl
.globtl
sinlle
...t
y
p
hx
Ix
q
by
tt
ot
.Ht
.Ht
.Ht
.Ht
If
... t
OQ
S~
~.
I
cl'
a"
.Ht
.HI
zz
xx
t..,
S;:
cc
::I.
"'
g'"'
::to
.
cI
nogi
h
push
popf
"'
tv
C
Q
C
C
I
:II
O.25,rO
singl.,rQ
single,r2
.o,r2
I r2 (v/2) [0]
zz
lIIyf
..2,1'1
singl',r1
.o,r2
I r2 (v/2) tIl
.1Il
singlt,r2
; r2' 1.5 - (v/2) 1Il 1Il
r2,rl
singl',rl
I rl [21
= .[n
subrf
1.5,r2
r2
r2,rl
singl.,r!
; rl
rl,rl,r2
singl.,r2
rO,r2
lingl.,r2
; r2 x[3]
r.d
IIIYf
Inda
IIIYf
Indn
lIIyf
..d.
.[2]
singl.,r2
I r2
= x[31
= (v/2)
x(3]
[3]
t""
~
(;I.l
i!
~
rl,rl,r2
sin'gl.,r2
.o,r2
[2]
1:1"
1.5,r2
r2
= (v/2)
=
&
.1Il
lIIyf
.. d
indn
xx
.[01
; r2
IIIYf
Indn
1.5,r2
r2
I r2 111
rnd
IIIYf
.[0]
,.1,rl,r2
lingl.,r2
Indn
sub"f
; Slye y.
= I.S
Indn
lIIyf
rO,r3
5ing1.,r2
=-....
~
&odn
lIIyf
andn
>
"=
"=
1:1
I r2 = x[O]
5ubrf
letr.ct tH ..p....t of v.
pu.hf
rl,rl,r2
rnd
.0
retslt
rl
24,rl
rl
rl
"pyf
lIIyf
..d
sqrtlx)
ldf
",yf
..d.
_.qrt2
Offb
rO
rl
r2
r3
r4
r5
r5
r6
rO
rl
rl
r7
r2
r3
.sqrt2t
S-
...t
.Nt
.Nt
...t
...t
.HI
.Nt
.Ht
.to.t
~
~
rO
rl
-25,1'1
Gent"t. v/2.
z .e+ce,
zzc-z+cc,
I
UII),
cc ( x - u - uu + xx ) 10.:11 I CI
;:
;- SlVI Ie
Algorilla u..d'
c ill 541"tex),
IUtt12ec, c, u.
2.0.rO
singl.lrQ
x[31
::::
<:l~
~
;:
S-
S"
<><>
;0
g"
~
:::So
'"
tv
[3
C
0'1
W
single,r1
opyf
,..1,1'1,1'2
single,r2
rO,r2
5iogle,I'2
1.5,,2
,2
; 1'2
1'2,1'1
; 1'1
andn
<::>
S-
andn
subrf
rod
apyf
i::l
'~"
"I'yf
~.
1'2,1'1
andn
<><>
SS!
1.5,r'2
,2
rod
opyf
subl'f
tl
<::>
andn
Idf
single, 1'1
rl,rO
apyf
1'3,rO
andn
5i091e,1'0
= (v/2)
opyf3
andn
opyf3
indo
oddf
rod
Idf
I"p,q
1 q=hxfty+txfhy
x[4]
11.5 - (vl2l*d41tx
.pyf3
Indo
.ddf3
rod
tX,ty,ttap
;telp=tx+ty
single, teap
p,q,u
u
lu=p+q
subf3
u,p,Uu
;uu=p-u
= sqrtlxl
rod
oddf
rod
oddf
,nd
; save c
x,y
singl',q
I"
Slve variables
pushf
;ttlp=hx+ty
;q=tx*hy
x(4] f x(4)
=x(5]
uu
;uu=p-u+q
q,uu
uu
, uu=p-u+q+txfty
telp,-tltI
uu
.. cc =.!
X - U - Uti
+ xx I
popf
popf
subf3
'nd
subf
'nd
popf
addf
,nd
telp
teap,cc
cc
; restore xx
;cc=x-u-uu+xx
push!
pushf
cc
; sa~e cc
; save c
0.5 / c
It:onstant, hip
hlp,x,p
; p = x * constant
single,p
5ubf3
,nd
oddf
,nd
p,x,hx
hx
p,hx
hx
;hx=x-p
subf3
,nd
hx,x,tx
Ix
;tx=x-hx
lIflyf3
andn
tup,y,p
single,p
; p
subf3
,nd
oddf3
,nd
p,y,hy
hy
hY,p,hy
,hy=y-p
hy
subf3
,nd
hy,y,ly
Iy
,Iy=y-hy
lPyf3
andn
hx,hy,p
single,p
,p=hx1hy
;hx=x-p+p
= y " constant
,hy=y-p+p
hip
u, hap,cc
; r.storf C
; rutorf x
;cc=x-u
cc
uU,ce
;cc=x-u-uu
cc
r2,r3
,2
; v is
.2
.1
uh
-24,.1
of y
rl,r2,rO
single,rO
; Rl -=
1.0,rO
rO
rl,rO
singlt,rO
rO,.1
; RO [5] (.[4]*(I.o-(VOX[4llU+>[4]
rl,r2
y ..
x[4]
->
.pyf
tndo
subrf
d
opy!
Indn
add!
I:
1.0 01
negi
.1
iSh
1,.1
24,.1
posh
popf
.1
.1
Jlbi
i
l;;"
d
opyl
Indo
~
So
opyf
..do
1~
~.
~
::!.
So
I
g
So
<1>
Q
c
subrf
opyl
..do
rl,r2,rO
iinglt,rO
2.0,rO
rO
rO,.1
single,r'
rl.,2,"0
singl.,rO
2.0,rO
rO
rO,.1
ntgf
Idl
Idln
opyf3
..d.
sub.f
<0 is
rO,r2
.. restore YII'ilblu
popf
popf
opyf
indo
opyl
indo
; RI 2.0 - v I .[0]
; RO x[IJ = x[O] I (2.0 - v I x[Oll
t p
cc
0.5,ce
singl.,cc
r2,tc
; restore c
; restore cc
; cc ( x - u - au + )0(
; cc
=( x -
singl',ee
,RI=.lx[IJ
I=C+C(
; Rl: 2.0 -
V t
xU]
oddl3
.nd
t.I"ce,l
; z=c+cc
I, tap,ll
I ZZC-Z
zzc-z+cc
,RI=v l .[2]
2.0,rO
rO
; RI = 2.0 - v I .[2]
d
opyf
..d.
to,r!
siftJ 1t,rl
opyl
..d.
sllb.f
d
.,yl
rl,r2,rO
,RI =vo.[3]
2.0,.0
..d.
liD.I.,rt
5ubf
.nd
oddl
.nd
zz
CC,IZ
; zzc-z+cc
zz
!'thu
s11l91.,rO
.ellto
constant:
; RI-2.0-vI.[3]
I RO [41 [3] I (2.0 - * .[3ll
float
d
4'm
0.5
u - uu + xx ) .. 0.5 I c
single,rt
rO
rO,.1
IFYF
hlndltd.
r2,rO
r3,r3
; Rl-v*x[Ol
rl,r2,rO
Jingl.,tO
opyf
..d.
slIbrf
I.
, const.. t 2"(24-24/2)+1
Appendix B
165
166
r
~
!So
I
long
long
int
long
~.
...
::to.
~
;:
~
r;'
~
So
'"
if (operation = 1) z = x + Y;
if (operation ZIi: 2) z = x - y;
if (operation lIZ 3) z x I YI
if (operation = 4) z = x / YI
if (opetltion = 5) z II sqrt(x);
printfC-\nz II 1.1Slg, z),
f.::i
N
a
<::>
z=x+Y;
printff-'nz := 1.18L1-~ z);
printfC-\n\nTypt 0 to txU, ehe continue: -It
scanf
.ill
,-lit,
) IIIAn. (i != O}I
)
I'D
=
a
represent it lS O /
(=
t:=
""""
-127) return(O);
t::'=
OIJQ
I'D
=
="~
;-~
if Csignl .antiSSl
II
=
..0,=
o tIllJQ
, I'D
if (Mntiua. = OxOl000000H
exp++;
HntiS5I = 0x00900000,
return(Rntissa);
}
~~
I'D (')
I
exp += 127;
Mntissa = <M.ntissl "0x007fffff) I (Sign 8) : (exp
~OO
I'D .. '
-...ntisH;
<::>
/f fxp=-l28 corresponds to O.
i=l;
dol
printfC-Type h.o C30 hex nuab.r5:\n-)1
printfl -x = .);
sClAH-XX,b1);
printfCy = .);
scanf('XX','YIl;
xl = c30tot(xl);
x = (long doublelilln ..t fltlxlll;
yl = c3Otoelyll,
y = (long double)(flfloat f)('Y1l I;
dol
p,;ntft'Addlll, SUbl21, lIpyl31, D;v141, Sq,t1511 "I;
scuf(Xd-, '.ptrdion);
) wIli It (operation" :: operation)Sh
"CI
z,
double x, Y.
int xl, yl;
i, operation;
int c30toe(1ong inU;
if (exp
sign = x II 0x00800000;
exp = x
24;
MinD
t-oo'
AU_bel'S
23)1
=
l!3,
~
til
.. ,
~
~
SO
...i.n
I
long doubl. x, Y.
I ... int Xl, yl, xxi. yyl,
ilt it ope....ti..n;
10., i.t c30t.. n.., I.tl,
j-l,
I,
s.
:?J
~
~.
dol
p.i.tflMelIII. MI2I ..,,131. 010141. Sq.tISII '1,
1ClIf1'1d' .......U.. I,
(optrltio.<1 n optNtion)5);
) "il,
::...
if I.....ti .... II
if C.....ti -21
if C.....ti.... 31
if I.....U.... 4'
If lo....ti .... 51
l!'
::I.
S.
long int
ptintfll\u
II.
Lla.,I,
s.
.cull'U' .'YII,
xl c30tMlxll,
x non, d....I.II.lfl ..t '11"111;
yl c30tHlyll,
y' non, .....I.II.UI ..t 'II'YIIII
Z&x+Y1
"
Q
c
bp;
I: . . . .
ntissil
;
!'~
g.~
;':19
,=
l~g.
g' 7'
Fil'
~.~
t'I)
E.
.'
III
if I...ti ...
= 0.0100000011
exp++1
antiss.
0x008000001
if (exp
z),
prilltf(IZ )1
=
~
x,
sign. x 0x0Q800000.
exp-x241
I
Z =x )'l
z'x-YI
z x "YI
I x / YI
Z Iq.tlxl,
output in hex/
print"'x '},
J:
In'
dol
.cutfl'U,bll,
prhUC'xx '1;
IcUf(-U;' ,bxU,
prittfC'y I),
....fIU.'YII,
priAtfC' " II,
.clllfIU.,"11,
xl c30tHlxll,
xxi c30tHlxxll,
yl c30tHlyll,
yyl c30tHlyyll,
X' non, doubl.II'UI ..t '11..111
no., d.... I.II.lfl ..t 111...111,
y' non, doubl.II.lfl ..t 'II'YIII
non, _1.II'lfl ..t '11,"111,
>
>127)
scufC I U,lrxl),
printfClu III
~,
... =
=
~
51
gO
William Hobl
Digital Signal Processor Products-Semiconductor Group
Texas Instruments
169
170
Introduction
In the general class of orthogonal transforms, there exists one in particular, the
discrete cosine transform (DCT), that has recently gained wide popularity in signal processing. The DCT has found applications in such areas as data compression, pattern recognition, and Weiner fIltering, primarily becauseofits close comparison to the Karhunen-Loeve
Transform (KLT) with respect to rate distortion criteria [1]. Although the KLT is considered to be optimal, there is no fast algorithm to compute it. Since there is no fast KLT
algorithm, the DCT is an attractive alternative.
For image coding, the DCT works well because of the high correlation among adjacent data samples (pixel values). Because of this correlation, the DCT provides near optimal reduction while retaining high image quality. In a comparative study [2], the DCT
was shown to outperform the Fourier, Hartley, and cas-cas transforms for image com~
pression, providing even more motivation for finding fast implementations.
A number of algorithms have been developed, most notably those of HOll [3] and
Lee [4], which generate higher-order DCTs from lower-order ones. This paper presents
two 8 X 8 DCT routines, one for the TMS320C25 and another for the TMS320C30, based
upon the routine in [3].
171
Zk =
- ex(k) N-I
E
~
N
n=O
Xn
cos
(7r (2n+
I)k)
k = 0, I, . . . ,N - I
2N
(Ia)
xn
N.-I
E ex(k)Zk cos (7r (2n+
~
N k=O
2N
I)k) k = 0, I, . . . ,N - I
(Ib)
~T(N)X'
(2)
where x and z are column vectors denoting the input and output data sequences, and T(N)
is the DCT matrix of order N. Actually, expanding the matrix (neglecting the factor of
172
Zo
Z2
ex
(3
-ex
ex
-ex
-(j
-(3
(3
-(j
Xo
X2
(3)
-(3
where
0(
and 0
= sin (~).
expressed as
Zo
Xo
Z4
0(
-0(
0(
-0(
0(
-0(
0(
-0(
x2
Z2
(3
-0
-(3
(3
-0 -(3
x4
Z6
(3
-0
-(3
(3
-0 -(3
x6
Zl
)..
P.
-p
-'Y
-}..
-p.
'Y
x7
Z5
P.
-'Y
}..
-p.
-p
'Y
-}..
X5
Z3
'Y
-}..
P.
-'Y
}..
-p.
-p
X3
Z7
'Y
}..
P.
-p
-'Y
-}..
-p.
Xl
where}..
cos
(~), 'Y =
cos
(4)
the input is no longer in natural order but has been rearranged according to the permutation
matrix P and the relation
x = Px,
(5)
where
An 8x 8
173
Upon examination, the matrix T(N) in (4), which is the matrix T(N) with the rows and
columns rearranged, can be described more compactly as
. T
(~)
15
(~)
T(N;
(6)
since the upper half of the 8-point DCT is exactly the 4-point DCT matrix previously
generated. Using the results obtained in [3], the relationship between
T
15 (~)
and
(~) is a given as
(7)
where
K
= RLRt,
R being the matrix that performs a bit reversal on the input data; L is the lower triangular
matrix
and Q
diag [ cos
-1
-2
-1
-2
-2
-2
-1
-2
-2
-2
-2
-2
-1
-2
-2
2 -2
(n
is now in bit-reversed order. Signal flow graphs for 2-point, 4-point, and 8-point DCTs
are shown in Figure 1, with the multipliers defined as in (4).
174
Zo
Zo
Xo
"
Zo
Xo
Z2
X,
X2
Za
a
X,
"
"
Z,
Z2
Z,
X3
-1
Z,
2:1 MUX
"
Za
2-ptDCT
1:2DEMUX
(b) 4--Point
(a) 2-Point
Zo
Xo
.z,
X,
Z2
X2
Zo
Xa
..
X.
"
"
Zo
Z,
"
"
Z3
I'
X.
"
"
Z,
"
Z2
Zo
Z.
-tJ
X.
-y
"
4-ptDCT
X7
Z7
2:1 MUX
1:2DEMUX
(e) 8-Point
Figure 1. Signal Flow Graphs for 2-Point, 4-Point, and 8-Point DCTs
The structure of the algorithm looks very much like that of a Fast Fourier Transform
(FFT). since the most fundamental computation is a 2-point butterfly. This routine is actua1ly
a generalized case of the Cooley-Tukey FFT algorithm with the addition of the recursion
at the end. If the equations for the signal flow graph are written explicitly. the recursive
nature of the DCT becomes clear; for a 4-point DCT. we have
Zo
Z2
= Zoo
= Z2.
Z1
= z],
Z3 = 2Z3 - Z],
175
Zo =
Z4
Z2
Z6
Z1
Z3
zs
Z7
ZO,
= Z4,
= Z2,
= Z6,
= Z],
= 2Z3
- Z],
= 2zs - Z3,
= 2Z7 - zs
transform is obtained by completely reversing the direction of the signal flow graph; i.e.,
performing the bit-reversal first, then the recursions and the butterflies, and finally, the
data permutation.
For the two-dimensional case of interest, the OCT can be described in the form
z(k,I)
1 (,)
= -2
x(m,n)
= 1N
(11" (2m+
l)k) cos
2N
(11"
(11" {2n+
2N
1)0 (8a)
(8b)
where a (k) = ~ for k = 0, unity otherwise. Like the FFT, the OCT kernel is
separable, allowing the transform to be performed in two steps, first along the rows and
thenthe columns.
176
zo
Zl
A-
'Y
P,
-p
-p,
Z2
fj
-0
-fj
-fj
-0
fj
X2
A-
-'Y
X3
-a -a
X4
A- -p,
x5
Xo
-'Y -A-
Xl
Z3
'Y
-p
-A-
-p,
p,
Z4
-a
-a
Z5
p,
-A-
'Y
-'Y
-p
Z6
-fj
fj
-0
-0
fj
-fj
X6
Z7
-p,
'Y
-A-
A-
-'Y
p,
-p
X7
where A- = cos
(~),
'Y = cos
(R)' p,
(7)
= sin (~)
16 .
The algorithm described above has been shown to be numerically stable for fixedpoint processors; however, to prevent serious data errors, truncation and roundoff must
be accounted for. A roundoff technique similar to the one in [6], is used to prescale the
matrix coefficients by (2 15 - 1). This product is then loaded into the accumulator with
a one-bit left shift, effectively dividing it by 215. After a mUltiplication is performed, the
32-bit value in the accumulator must be rounded to sixteen bits, where bits 13,14, and
15 are used to determine the value of the sixteenth bit. The TMS320C25 performs this
operation in a single instruction by adding 3000h to the accumulator product with a onebit left shift, as outlined in the code shown in Figure 2.
177
*
*
*
DCTINI
*
*
*
T2
LDPK
RSXM
SPM
LRLK
RPTK
BLKP
LRLK
RPTK
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IDATA,* +
AR1,RNDOFF
10
EDATA,*+
SIGN-EXTENSION MODE
LEFT SHIFT 1 BIT
COEFFICIENTS
VARIABLES
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LAR
LARK
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MPY
ZAC
RPTK
MAC
*+,AR2
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AR3,7
* + ,AR2
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LTA
MPY
ADD
SACH
BANZ
* + ,AR1
C10
RNDOFF
*0+,AR3
t2,*-,AR2
6
C11, * +
178
After the multiplications are computed, the results are stored in another array area
in transposed order; thus, a separate routine for transposing the matrix is not needed. Once
the rows are transformed, the pointers for the input and output matrices are exchanged.
When the procedure is repeated, the output is stored as rows, completing the transform.
Appendix A contains a complete program listing for the forward transform on the
TMS320C25. To perform an inverse nCT, the table of cosine coefficients should be
replaced with those used for an inverse transform.
*
BITREV
II
II
II
II
LDF
LDF
STF
STF
LDF
LDF
STF
STF
*ARO,RO
*-AR2,R1
R1,*ARO
RO,*-AR2
*AR1,RO
*-AR3,R1
R1, *AR1
RO,*-AR3
179
Because of the amount of data shuffling that occurs, an eight-word scratch-pad vector
has been created with four permanent pointers set up at every other memory location.
This allows access to each element in the vector (by predecrement or preincrement
addressing) without requiring constant alteration of one or two pointer locations. Although
there is no overhead for looping on the TMS320C30, straight-line coding is used as much
as possible to increase performance.
You can transpose the DCT matrix in the same way as in the TMS320C25
implementation: namely, store the transformed row vector as a column vector in another
matrix and interchange the input and output pointers.
The complete routines for the forward and inverse transforms are given in Appendix B.
Results
The execution times and memory requirements for the two routines are given in
Table 1. For the TMS320C30 implementation, the forward transform contains the scale
so the transform is not unitary. When the signal flow is reversed,
factor of
1,
instructions accumulate and thetime required to perform the inverse transform actually
increases (see Table 1). This increase occurs because certain multiplications cannot be
performed in parallel with another instruction. The two times are identical on a TMS32OC25
because it uses a matrix routine to compute the transform.
Table 1. Execution Times and Memory Requirements
Device
Memory Required
Program
TMS320C25
TMS320C30
Time Required
'Data
(f'S)
232 words*
203 words
257.3 (forward)
232 words
203 words
257.3 (inverse)
148 words**
136 words
155 words
136 words
99.4 (forward)
107.9 (inverse)
180
Summary
Two routines for a two-dimensional Discrete Cosine Transform are presented: one
for the TMS320C25 and one for the TMS320C30, with a development of the algorithm
given for clarification. This report also discussed the similarities of the DCT to the CooleyTukey FFT algorithm and arithmetic shortcuts which can reduce the DCT's execution
time. Although these implementations use the most recent formulation, there is still room
for investigation into more efficient methods. Another approach that might prove fruitful
is to deal with the entire 8 x 8 array all at once, as suggested by Haque [7], rather than
transforming the array by rows and columns. However, both routines given in the
appendices provide fast, numerically stable solutions for applications requiring the DCT.
Acknowledgements
The author thanks Steve Ford for supplying the original code for the TMS320C25
implementation. Francois Charlot helped in modifying the code for the TMS320C25, as
well as in preparing this manuscript. Daniel Chen improved the performance of the code
for both the TMS320C25 and the TMS320C30.
References
[1] Ahmed, N., Natarajan, T., and Rao, K.R. "Discrete Cosine Transform," IEEE
Transactions on Computing, vol. C-23, pp. 90-93, January 1974.
[2] Perkins, M. "A Comparison of the Hartley, Cas-Cas, Fourier, and Discrete
Cosine Transforms for Image Coding," IEEE Transactions on Computing, yol.
36, pp. 758-760, June 1988.
[3] Hou, H.S. "A Fast Recursive Algorithm for Computing the Discrete Cosine
Transform," IEEE Transactions on ASSP, vol. ASSP-35, No. 10,
pp. 1455-1461, October 1987.
[4] Lee, B.G. "FCT - A Fast Cosine Transform," Proceedings of 1984 Conference
on ASSP, pp. 28.A.3.1-28.A.3.4, March 1984.
[5] Jayant, N.S., and Noll, P. Digital Coding of Waveforms, New York, PrenticeHall, 1984.
[6] Srinivasan, S., Jain, A.K., and Chin, T.M. "Cosine Transform Block Codec for
Images Using the TMS3201O," Proceedings of IEEE ISCAS '86, Cat. No.
86CH2255-8, vol. 1, pp. 299-302.
[7] Haque, M.A. "A Two-Dimensional Fast Cosine Tranform," IEEE Transactions
on ASSP, vol. ASSP-33, pp. 1532-1539, December 1985.
181
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0.980785280403
0.555570233019
-0.195090322016
-0.831469612303
0.923879532511
-0. 382683432365
0.707106781188
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.global
.data.
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.end
COUAB
0.707106781188
0.923879532511
-0.382683432365
-0. 19509032L"Q16
-0.831469612303
0.980785280403
0.555570233019
ALPHA
BETA
-DELTA
-NU
-GAIi1A
LAMBDA
MU
Sen Kuo
Northern Illinois University
Chein Chen
Digital Signal Processor Products-Semiconductor Group
Texas Instruments
191
192
Introduction
A filter selects or controls the characteristics of the signal it produces by conditioning the incoming signal. The coefficients of the filter determine its characteristics and output
a priori in many cases. Often, a specific output is desired, but the coefficients of the filter
cannot be determined at the outset. An example is an echo canceller; the desired output
cancels the echo signal (an output result of zero when there is no other input signal). In
this case, the coefficients cannot be determined initially since they depend on changing
line or transmission conditions. For applications such as this, it is necessary to rely on
adaptive filtering techniques.
An adaptive filter is a filter containing coefficients that are updated by an adaptive
algorithm to optimize the filter's response to a desired performance criterion. In general,
adaptive filters consist of two distinct parts: a filter, whose structure is designed to perform a desired processing function; and an adaptive algorithm, for adjusting the coefficients of that filter to improve its performance, as illustrated in Figure 1. The incoming
signal, x(n), is weighted in a digital filter to produce an output, yen). The adaptive algorithm
adjusts the weights in the filter to minimize the error, e(n), between the filter output, yen),
and the desired response of the filter, den). Because of their robust performance in the
unknown and time-variant environment, adaptive filters have been widely used from
telecommunications to control.
din) - - - - - - - - - - - - - - - ,
1-....__ .In)
FILTER
STRUCTURE
I - - - -....-~.........yln)
ADAPTIVE
FILTER
193
Adaptive filters can be used in various applications with different input and output
configurations. In many applications requiring real-time operation, such as adaptive prediction, channel equalization, echo cancellation, and noise cancellation, an adaptive filter
implementation based on a programmable digital signal processor (DSP) has many advantages over other approaches such as a hard-wired adaptive filter. Not only are power,
space, and manufacturing requirements greatly reduced, but also programmability provides flexibility for system upgrade and software improvement.
The early research on adaptive filters was concerned with adaptive antennas [1] and
adaptive equalization of digital transmission systems [2]. Much of the reported research
on the adaptive filter has been based on Widrow's well-known Least Mean Square (LMS)
algorithm, because the LMS algorithm is relatively simple to design and implement, and
it is well-understood and well-suited for many applications. All the filter structures and
update algorithms discussed in this application report are Finite Impulse Response (FIR)
filter structures and LMS-type algorithms. However, for a particular application, adaptive filters can be implemented in a variety of structures and adaptation algorithms [1,
3 through 9]. These structures and algorithms generally trade increased complexity for
improved performance. An interactive software package to evaluate the performance of
adaptive filters has also been developed [10].
The complexity of an adaptive filter implementation is usually measured in terms
of its multiplication rate and storage requirement. However, the data flow and data
manipulation capabilities of a DSP are also major factors in implementing adaptive filter
systems. Parallel hardware multiplier, pipeline architecture, and fast on-chip memory size
are major features of most DSPs [11, 12] and can make filter implementation more efficient.
Two such devices, the TMS320C25 and TMS320C30 from Texas Instruments [13,
14], have been chosen as the processors for fixed-point and floating-point arithmetic. They
combine the power, high speed, flexibility, and an architecture optimized for adaptive
signal processing. The instruction execution time is 80 ns for the TMS320C25 and only
60 ns for the TMS320C30. Most instructions execute in a single cycle, and the architectures of both processors make it possible to execute more than one operation per instruction. For example, in one instruction, the TMS320C25 processor can generate an instruction
address and fetch that instruction, decode the instruction, perform one or two data moves
(if the second data is from program memory), update one address pointe~, and perform
one or two computations (multiplication and accumulation). These processors are
designed for real-time tasks in telecommunications, speech processing, image processing, and high-speed control, etc.
194
To direct the present research toward realistic real-time applications, three adaptive
structures were implemented:
1. Transversal
2. Symmetric transversal
3. Lattice
Each structure utilizes five different update algorithms:
1.
2.
3.
4.
5.
LMS
Normalized LMS
Leaky LMS
Sign-error LMS
Sign-sign LMS
Each structure with its adaptation algorithms is implemented using the TMS320C25
with fixed-point arithmetic and the TMS320C30 with floating-point arithmetic. The processor assembly code is included in the Appendix for each implementation. The assembly
code for each .structure and adaptation strategy can be readily modified by the reader to
fit his/her applications and could be incorporated into a C function library as callable
routines.
In this application report, the applications of adaptive ftlters, such as adaptive prediction, adaptive eqUalization, adaptive echo cancellation, and adaptive noise cancellation
are presented first. Next, the implementation of the three filter structures and five adap-,
tive algorithms with the TMS320C25 and TMS320C30 is described. This is followed by
the practical considerations on the implementation of these adaptive ftlters. The remainder
of the application report covers coding options, such as the routine libraries that support
both assembly and C languages.
Adaptive Prediction
Adaptive prediction [16 through 18] is illustrated in Figure 2. In the general application of adaptive prediction, the signals are x(n) - delayed version of original signal,
d(n) - original input signal, y(n) - predicted signal, and e(n) - prediction error or
residual.
Implementation of Adaptive Filters with the TMS320C25 or the TMS320C30
195
dln)--......- - - - - - - - - - - - ,
1--.......... eln)
DELAY
xln)
ADAPTIVE
FILTER
yIn)
a2* u(n-2)
+ ...... +
am* u(n-m)
v(n)
where at. a2, .... , am are the AR parameters. Thus, the present value of the process u(n)
equals a finite linear combination of past values of the process plus an error term v(n).
This adaptive AR model provides a practical means to measure the instantaneous frequency of input signal. The adaptive predictor can also be used to detect and enhance a narrow
band signal embedded in broad band noise. This Adaptive Line Enhancer (ALE) provides
at its output yen) a sinusoid with an enhanced signal-to-noise ratio, while the sinusoidal
components are reduced at the error output e(n).
Adaptive Equalization
Figure 3 shows another model known as adaptive equalization [2, 9, 15]. The signals
in the adaptive equalization model are defined as x(n) - received signal (filtered version
of transmitted signal) plus channel noise, den) - detected data signal (data mode) or pseudo
random number (training mode), yen) - equalized signal used to detect received data,
and e(n) - residual intersymbol interference plus noise.
196
DATA
, . . - - - - - - , MODE
yIn)
xln)
TRAINING
MODE , - - - - - - - ,
PSEUDO
RANDOM
NUMBER
GENERATOR
ADAPTIVE
FILTER
SLICER
+
dIn)
r--------I
HYBRID I
,,
,,
,,,
,,
,
xln) ----~~----+---9---__1Ir--
ADAPTIVE
FILTER
ECHO
PATH
yIn)
+
eln) ....-41---4
,..__'1--_
,
NEAR-END
SIGNAL
I
'
IL.. _ _ _ _ _ _ _ _ _ I'
Figure 4. Block Diagram of an Echo Canceller
Implementation of Adaptive Filters with the TMS320C25 or the TMS320C30
197
The adaptive echo cancellers are used in practical applications of cancelling echoes
for long-distance telephone voice communication, full-duplex voiceband data modems,
and high-performance audio-conferencing systems. To overcome the echo problem, echo
cancellers are installed at both ends of the network. The cancellation is achieved by
estimating the echo and subtracting it from the return signal.
SIGNAL
SOURCE
"'-..---1" e(n)
xln)
NOISE SOURCE
ADAPTIVE
FILTER
yIn)
Application Summary
The above list of applications is not exhaustive and is limited primarily to applications within the field of telecommunications. Adaptive filtering has been used extensively
in the context of many other fields including, but not limited to, instantaneous frequency
tracking, intrusion detection, acoustic Doppler extraction, on-line system identification,
geophysical signal processing, biomedical sign~ processing, the elimination of radar clutter,
beamforming, sonar processing, active sound cancellation, and adaptive control.
198
(1)
i=O
where ~(n)=[x(n) x(n-l) ... x(n-N+l)]T is the input vector, ~(n)=[wo(n) wl(n) ...
wN-l(n)]T is the weight vector, T denotes transpose, n is the time index, and N is the
order of filter. This example is in the form of a finite impulse response filter as well as
the convolution (inner product) of two vectors ~(n) and ~(n). The implementation of Equation (1) is illustrated using the following C program:
y[n] = 0.;
for (i = 0; i < N; i + +) [
y[n] + = wn[i]*xn[i];
[
where wn [i] denotes wi(n) and xn[i] represents x(n -i).
199
xln-2)
xln -1)
x(n)
xln-N+ 1)
Z-1
Z-1
Z-1
PFC
Weights
80
Data Buffer
B1
ARn
Data Bus
Program
Bus
T(16)
MULTIPLER
P(32)
ACC(32)
200
The MACD instruction enables complete multiply/accumulate, data move, and pointer
update operations to be completed in a single instruction cycle (80 ns) if fIlter coefficients
are stored in on-chip RAM or ROM or in off-chip program memory with zero wait states.
Since the adaptive weights wj(n) need to be updated in every iteration, the fIlter coefficients must be stored in RAM. The implementation of the inner product in Equation (1)
can be made even more efficient with a repeat instruction, RPTK. An N-weight transversal fIlter can be implemented as follows [23]:
LARP
. LRLK
RPTK
MACD
ARn
ARn,LASTAP
N-l
COEFFP,*-
(A)
Where ARn is an auxiliary address register that points to x(n - N + 1), and the Prefetch
Counter (PFC) points to the last weight wN -1 (n) indicated by COEFFP. When the MACD
instruction is repeated, the coefficient address is transferred to the PFC and is incremented
by_ one during its operation. Therefore, the components of weight vector 'y!::(n) are stored
in BO as
Low Address
PFC - - - -
w1(n)
HIgh Address
The MACD in repeat mode will also copy data pointed to by ARn, to the next higher
on-chip RAM location. The buffer memories of transversal fIlter are therefore stored as
Low Address
x(n)
x(n-1)
....
x(n-N+2)
ARn ____
x(n-N+1)
HIgh Address
201
The architecture ofTMS320C30 [14] is quite different from TI's second generation
processors. Instead of using program/data memory, it provides two data address buses
to do the data memory manipulations. This feature allows two .data memory addresses
to be generated at the same time. Hence, parallel data store, load, or one data store with
one data load can be done simultaneously. Such capabilities make the programming much
easier and more flexible. Since the hardware multiplier and arithmetic logic unit (ALU)
of TMS320C30 are separated, with proper operand arrangement, the processor can do
one multiplication and one addition or subtraction at the same time. With these two combined features, the TMS320C30 can execute several other parallel instructions. These
parallel instructions can be found in Section 11 of the Third-Generation TMS320 User's
Guide [14]. Associating with single repeat instruction RPTS, an inner product in Equation (1) can be implemented as follows:
II
MPYF3
RPTS
MPYF3
ADDF3
ADDF3
; w[O].x[O]
; Repeat N -1 times
; y[] = w[].x[]
; Include last product
where auxiliary registers ARO and ARI point to x and w arrays. The addition in the parallel
instruction sums the previous values of Rl and R2. Therefore, Rl is initialized with the
first product prior to the repeat instruction RPTS.
Note that the implementation above does not move the data in the x array like MACD
does in TMS320C25. For filter delay taps, the TMS320C30 uses a circular buffer method
to implement the delay line. This method reserves a certain size of memory for the buffer
and uses a pointer to indicate the beginning of the buffer. Instead of moving data to next
memory location, the pointer is updated to point to the previous memory location.
Therefore, from the new beginning of the buffer, it has the effect of the tapped delay line.
When the value of the pointer exceeds the end of the buffer, it will be circled around
to the other end of the buffer. It works just like joining two ends of the buffer together
as a necklace. Thus, new data is within the circular queue, pointed to by ARO, replacing
202
the oldest value. However, from an adaptive filter point of view, data doesn't have to
be moved at this point yet.
TMS320C30 has a 32-bit floating point multiplier and the result from the multiplier is
put and accumulated into a 40-bit extended precision register. If the input from AID converter is equal to or less than 16 bits, there is no roundoff noise after multiplication.
Theoretically, the TMS320C30 can implement a very high order of adaptive filter.
However, for the most efficient implementation, the limitation of filter order is 2K because
the TMS320C30 external data write requires at least two cycles. If the filter coefficients
are put in somewhere other than internal data RAM, the instruction cycles will be increased.
(2)
den) -yen),
where den) is the desired signal and yen) is the filter output. The input vector ~(n) and
e(n) are used to update the adaptive filter coefficients according to a criterion that is to
be minimized. The criterion employed in this section is the mean-square error (MSE)E:
E
= E[e2 (n)]
(3)
where E [.] denotes the expectation operator. Ify(n) from Equation (1) is substituted into
Equation (2), then Equation (3) can be expressed as
E
E[d2 (n)]
~T(n)R~(n)
- 2
~T(n)
(4)
where R = E[x(n)x T(n)] is the N x N autocorrelation matrix, which indicates the sampleto-sample correlation within a signal, and ~ = E [den) ~(n)] is the N x 1 cross-correlation
vector, which indicates the correlation between the desired signal d(n)and the input signal
vector ~(n).
The optimum solution w*
rived by solving the equation
= [wo* Wl*
OE
----= 0
o~(n)
(5)
~6)
203
If the R matrix has full rank (i.e., R-1 exists), the optimum weights are obtained by
~*
R-1 ~
(7)
In Linear Predictive Coding (LPC) of a speech signal, the input speech is divided
into short segments, the quantities of Rand .Q are estimated, and the optimal weights corresponding to each segment are computed. This procedure is called a block-by-block dataadaptive algorithm [24].
A widely used LMS algorithm is an alternative algorithm that adapts the weights
on a sample-by-sample basis. Since.this method can avoid the complicated computation
of R -1 and .Q, this algorithm is a practical method for finding close approximate solutions
to Equation (7) in real time. The LMS algorithm is the steepest descent method in which
the next weight vector w(n + 1) is increased by a change proportional to the negative gradient of mean-square-error performance surface in Equation (7)
~(n+ 1) = ~(n)
(8)
- u'V (n)
where u is the adaptation step size that controls the stability and the convergence rate.
For the LMS algorithm, the gradient at the nth iteration, 'V (n), is estimated by assuming
squared error e2 (n) as an estimate of the MSE in Equation (3). Thus, the expression for
the gradient estimate can be simplified to
o[e2(n)]
o~(n)
- 2 e(n)
~(n)
(9)
Substitution of this instantaneous gradient estimate into Equation (8) yields the
Widrow-Hoff LMS algorithm
,
~(n +
(10)
204
~(n)
will
(11)
where Amax is the largest eigenvalue of the matrix R. Amax can be bounded by
N-l
= N r(O)
(12)
r (0)
i=O
For adaptive signal processing applications, the most important practical consideration is the speed of convergence, which determines the ability of the filter to track nonstationary signals. Generally speaking, weight vector convergence is attained only when the
slowest weight has converged. The time constant of the slowest mode is [1]
t
=---UAmin
(13)
This indicates that the time constant for weight convergence is inversely proportional to u and also depends on the eigenvalues of the autocorrelation matrix of the input.
With the disparate eigenvalues, i.e., Amax> > Amin, the setting time is limited by the
slowest mode, Amin. Figure 8 shows the relaxation of the mean square error from its initial value EO toward the optimal value Emin.
Adaptation based on a gradient estimate results in noise in the weight vector, therefore
a loss in performance. This noise in the adaptive process causes the steady state weight
vector to vary randomly about the optimum weight vector. The accuracy of weight vector
in steady state is measured by excess mean square error (excess'MSE = E [E - Emin])'
The excess MSE in the LMS algorithm [1] is
excess MSE = u Tr[R] Emin
(14)
205
10- 3
w,
Initial Wo = 0.2.
- 1.0
30.00
22.50
15.00
7.50
.00
64.75
128.50
192.25
256.00
Iteration
206
Since u*e(n) is constant for N weights update, the error signal e(n) is first multiplied
by u to get ue(n). This constant can be computed first and then multiplied by x(n) to update w(n). An implementation method of the LMS algorithm in Equation (10) is illustrated
as
ue(n) = u*e[n];
for (i=O; i<N; i++) [
wn[i] + = uen * xn[i];
TMS320C25 Implementation
The TMS320C25 provides two powerful instructions (ZALR and MPYA) to perform the update example in Equation (10).
ZALR loads a data memory value into the high-order half of the accumulator while rounding the value by setting bit 15 of the accumulator
to one and setting bits 0-14 of the accumulator to zero. The rounding is
necessary because it can reduce the roundoff noise from multiplication.
Assuming that ue(n) is stored in T and the address pointer is pointing to AR3, the
adaptation of each weight is shown in the following instruction sequence:
LRLK ARl,N -1
LRLK AR2,COEFFD
LRLK AR3,LASTAP+ 1
MPY
. ADAP ZALR
MPYA
SACH
BANZ
*-,AR2
* ,AR3
*-,AR2
*+,O,ARI
ADAP,*-,AR2
;
;
;
;
;
;
;
;
;
;
;
;
;
For each iteration, N instruction cycles are needed to perform Equation (1), 6N instruction cycles are needed to perform weight updates in Equation (10), and the total number
of instruction cycles needed is 7N + 28. An example of a TMS32OC25 program implementing a LMS transversal fIlter is presented in Appendix AI. Note that BANZ needs three
instruction cycles to execute. This can be avoided by using straight line code, which requires 4N + 33 instruction cycles [25].
Implementation of Adaptive Filters with the TMS320C25 or the TMS320C30
207
TMS320C30 Implementation
Although the TMS32OC30 doesn't provide any specific instruction for adaptive filter
coefficients up<iate, it still can achieve the weight updating in two instructions because
of its powerful architecture. The TMS320C30 has a repeat block instruction RPTB, which
allows a block of instructions to be repeated a number of times without any penalty for
looping. A single repeat mode, RM, in the status register, ST, and three registers - repeat
start address (RS), repeat end address (RE), and repeat counter (RC) - control the block
repeat. When RM is set, the PC repeats the instructions between RS and RE a number
of times, which is determined by the value of RC. The repeat modes repeat a block of
code at least once in a typical operation. The repeat counter should be loaded with one
less than the desired number of repetitions. Assuming the error signal e(n) in Equation
(10) is stored in R7, the adaptation of filter coefficients is shown as follows:
MPYF3
LDI
RPTB
MPYF3
IIADDF3
LMS
STF
MPYF3
IIADDF3
STF
ADDF3
STF
*ARO+ +(1)%,R7,Rl
order-3,RC
LMS
*ARO+ +(1)%,R7,Rl
*ARl,Rl,R2
R2, *ARI + +(1)%
; Rl = u*e(n)*x(n)
; Initialize repeat counter
; Do i = 0, N-3
; Compute u*e(n)*x(n -i -1)
; Compute wi(n) + u*e(n)*x(n -i)
; Store wi(n+l)
*ARO,R7,Rl
*ARl,RI,R2
R2, *ARI + +(1)%
*ARl,Rl,R2
R2, *ARI + +(1)%
; For i = N-2
; Store wN-2(n+l)
; Include last w
; Store wN-l(n+l)
where auxiliary register ARO and ARI point to x and w arrays. Rl is updated before loop
since the accumulation in the parallel instruction uses the previous value in Rl. In order
to update x array pointer to the new beginning of the data buffer for next iteration (i.e.,
perform the data move), one of the loop instruction set has been taken out of loop and
modified by eliminating the incrementation of ARO.
To perform an N -weight adaptive LMS transversal filter on TMS320C30 requires
3N + 15 instruction cycles. There are N and 2N instruction cycles to perform Equations
(1) and (10), respectively. The TMS32OC30 example program is given in Appendix A2.
The LMS algorithm considerably reduces the computational requirements by using
a simplified mean square error estimator (an estimate of the gradient). This algorithm has
proved useful and effective in many applications. However, it has several limitations in
performance such as the slow initial convergence, the undesirable dependence of its convergence rate on input signal statistics, and an excess mean square error still in existence
after convergence.
208
______ _
xln)-.......... Z-1
___---
Z-1
z-1
I-------<~
yIn)
y(n)
(ISa)
i=O
where N is an even number. Note that, for fixed-point processors, the addition in the
brackets may introduce overflow because the input signals x(n -i) and x(n - N +i + 1) are
in the range of -1 and 1 - 2 -15. This problem can be solved by shifting x(n) to the right
one bit. The update of the weight vector is
wj(n+I) = wj(n) + ue(n)[x(n-l) + x(n-N+i+I)]
(ISb)
209
for i=O,I, ... ,(NI2-1), which requires N/2 multiplications and N additions. Theoretically, this symmetric structure can also reduce computational complexity since such filters
require only half the multiplications of the general transversal filter. However, it is true
only for the TMS320C30 processor. When a filter is implemented on the TMS320C25,
the transversal structure is more efficient than the symmetric transversal structure due
to the pipeline multiplication and accumulation instruction MACD, which is optimized
to implement convolution in Equation (1).
TMS320C25 Implementation
For TMS320C25, in order to implement the instructions MAC, ZALR, and MPYA,
we can trade memory requirements for computation saving by defining
z(n-i) = x(n-i) + x(n-N+i+l) , i=O,I, ... ,N/2- 1
(16a)
y(n) =
wj(n) z(n-i)
(16b)
i=O
Wj(n+ 1) = wj(n) + u e(n) z(n-i) , i=O,I, ... ,N/2- 1
(16c)
SYM
LARK
LRLK
LRLK
LRLK
LARP
LAC
ADD
SACL
BANZ
AR1, N/2-1
AR2,LAST-X
AR3,FIRST-X
AR4,FIRST-Z
AR3
*+,O,AR2
*-,O,AR4
*+,O,ARI
SYM,*-,AR3
;
;
;
;
Counter
Point to
Point to
Point to
= N/2 -1
x(n-N+l)
x(n)
z(n)
The instruction sequence to implement the LMS algorithm in Equations (1) and(lO)
can be used to implement Equations (16b) and (16c), except using MAC instead ofMACD
in Program (A). Therefore, N instruction cycles are needed to shift data in x(n), 3N instruction cycles are needed to implement Equation (16a), N/2 for Equation (16b), and
3N for Equation (16c). The total number of instruction cycles required to implement the
symmetric transversal filter with the LMS algorithm is 7 .5N + 38. Where 7.5N is an integer because N is chosen as an even number. The O.5N instruction cycles come from
Equation (15a) since symmetric transversal structure folds the filter taps into half of the
order N (see Figure 9). The maximum filter length for most efficient code, 256, is the
210
same as for the FIR filter. The use of the additional data memory can be obtained from
the reduced data memory requirement for weights of the symmetric transversal filter. The
complete TMS320C2S program is given in Appendix Bl.
Note that instead of storing buffer locations x(n) contiguously, then using DMOV
to shift data in the buffer memory (requiring N cycles) at the end of each iteration, we
can use a circular buffer with pointers pointing to x(n) and x(n - N + 1). Since pointer updating requires several instruction cycles, compared with N cycles using DMOV to update the buffer memory contents, the circular buffer technique is more efficient ifN is large.
TMS320C30 Implementation
As mentioned above, the TMS320C30 uses a circular buffer instead of data move
technique. Therefore, it does not have to implement tapped delay line separately as
TMS320C2S. Equations (I) and (16a) can be combined and implemented in the same loop.
The advantage of this is that a parallel instruction reduces the number of the instruction
cycles. The implementation is shown as follows:
II
INNER
II
LDF
LDI
RPTB
ADDF3
MPYF3
STF
ADDF3
0.0,R2
;
order/2-2,RC
;
INNER
;
*AR4++(1)%,*ARS--(I)%,Rl;
Rl,*ARI+ +(I),R3
;
Rl, *AR2+ +(1)
;
R3,R2,R2
;
ADDF3
MPYF3
STF
ADDF3
Clear R2
Set up loop counter
Do i = 0, N/2 -2
z(i) = x(n-i) + x(n+N-i)
R3 = w[] * z[]
Store z(i)
Accumulate the result for y
where AR4 and ARS point to x[O] and x[N-l]. ARI and AR2 point to wand z array,
respectively. IRO contains value of N/2 -1. The same instruction codes of weight update
of transversal filter can be used in symmetric transversal structure by changing the x array pointer to the z array pointer. Appendix B2 presents an example program. The total
number of instructions needed is 2.SN + IS, which is less than that of the transversal
structure.
211
fo(n)
= bo(n) =
(17a)
x(n)
(17b)
(17c)
where fm(n) represents the forward prediction error, bm(n) represents the backward prediction error, km(n) is the reflection coefficients, m is the stage index, and M is the number
of cascaded stages. The lattice structure has the advantage of being order-recursive. This
property allows adding or deleting of stages from the lattice without affecting the existing
stages.
r--~-., fm(n)
xln)
Stage
Stage
Stage
- - - -.... bmln)
Stage m
.---------------,I
f m -1 In)
-i------.,--___t...
Z-1
212
(19a)
(19b)
(20)
O<=m<=M
where the LMS algorithm is used to update the coefficients of the regression filter. For
noise cancellation application, em(n) corresponds to the output e(n) in Figure 5. For applications such as adaptive line enhancer and channel equalizer, filter output yen) is obtained as
M
yen)
(21)
gm(n) bm(n)
m=O
fo(n)
f,(n)
Stage
xln)
boln)
b,ln)
fm(n)
Stage
Stage
bm(n)
: 9,(n)
dIn)
)-1--'----- ..... - - - - - f I I I f
yIn)
213
TMS320C2SITMS32OC30 Implementation
There are five memory locations-fm(n), bm(n) , bm(n-l), km(n) , and gm(n)required for each stage. The limitation of on-chip data RAM is 544 words for the
TMS320C25 and 2K words for the TMS320C30. A maximum of 102 stages can therefore
be implemented on a single TMS320C25 for the highest throughput. Here, another ad.vantage of TMS32OC30 architecture design is shown. Since the operands of the mathematic
operations can be either memory or register on the TMS320C30, and there is no need
to preserve the values of fm array for the next iteration (refer to Equations (17) and (18,
the fm array can be replaced by an extended precision register. Thus, for the most efficient codes, the stage limitation of lattice structure for TMS320C30 is 512, or one-fourth
of the 2K on-chip RAM.
Lattice structures have superior convergence properties relative to transversal structures and good stability properties; e.g., low sensitivity to coefficient quantization, low
roundoff noise, and the ability to check stability by inspection. The disadvantages of lattice filter algorithms are that they are numerically complex and require mathematical
sophistication to thoroughly understand their derivations. Furthermore, as shown in Appendixes Cl and C2, lattice structures cannot take advantage of the TMS320C25 and
TMS320C30's pipeline architecture to achieve high throughput. The total number of instruction cycles needed is 33M +32 for TMS320C25 and 14M +4 for TMS320C30.
214
=aI
var(n)
(22)
and
~(n
+ 1)
= ~(n)
u(n)e(n)~(n)
(23)
where a is a convergence parameter, and var(n) is an estimate of the input average power
at time n using the recursive equation
var(n) =(1 - b) var(n -1)
b x2 (n)
(24)
AR3
AR3,FRSTAP
ERRF
VAR
VAR,SHIFT
ERRF ,SHIFT
VAR
ACC = var(n-I)
ACC = (I-b) var(n -1)
ACC = (I-b) var(n -1) + b x2(n)
Store var(n)
215
TMS320C30 can be found in the user's guide for each device [13, 14]. Since the power
of input signal is always positive, those codes can be simplified to save computation time.
Since the power estimation in Equation (24) and step size normalization in Equation (22)
are performed once for each sample x(n), the computation increase can be ignored when
N is large. As shown in Appendixes Dl and D2, the total number of instruction cycles
needed for the normalized LMS algorithm (7N +57 for the TMS320C25 and 3N +47 for
the TMS32OC30) is slightly higher than for the LMS algorithm (7N + 34 and 3N + 15)
when N is large.
where
1) =
~(n)
sign[e(n)]
+ u sign[e(n)]
~(n)
(25)
1 , if e(n) ;;::: 0
- 1 , if e(n) < 0
216
The programs in Appendixes El and E2 implement a transversal filter with signerror LMS algorithm in looped code. The total number of instruction cycles needed for
this algorithm using the TMS320C25 is 7N +26, which is slightly less than for the LMS
algorithm's 7N +28. Computing u*e(n) takes 5 instruction cycles. The sign-error LMS
algorithm determines the sign of the u by checking the sign of e(n), which takes only 3
instruction cycles. The total number of instruction cycles needed for the sign-error LMS
algorithm using the TMS320C30 is 3N + 16, which is slightly higher than for the LMS
algorithm. This occurs because the TMS320C30 takes only one instruction cycle to compute u*e(n) and two instruction cycles to determine the sign of the u.
Secondly, the sign-data LMS algorithm is
~(n +
1) =
~(n)
+ u e(n)
sign[~
(n)]
(26)
(27)
which requires no multiplications at all and is used in the CCITT standard for ADPCM
transmission. As we can see from the above equations, the number of mUltiplications is .
reduced. This simplified LMS algorithm looks promising and is designed for VLSI or
discrete IC implementation to save multiplications.
The sign-sign LMS algorithm can be implemented as
for (i=0; i<N; H+) [
if (e[n] > = 0.) [
if (xn[i] >= 0.)
wn[i] + = u;
else
wn[i] - = u; J
else [
if (xn[i] > = 0.)
wn[i]-= u;
217
else
wn[i] +
= u; J J
ARl,N-l
AR2,COEFFD
AR3,LASTAP+l
*-,O,AR2
ERR
ERRF
LAC
ERRF
XORK
MU,15
ADD
SACH
BANZ
*,15
*+,l,AR1
ADAP,*-,AR3
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Set up counter
Point to wi(n)
Point to x(n-i)
Load x(n-i)
XOR with e(n)
Save sign bit, sign = 0 if same signs
Sign = 1 if different signs
Sign extension to ACCH,
ACCH = 0 If ERRF > = 0
ACCH = OFFFFh if ERRF < 0
Take one's complement of m
If sign = 1
Weight update
Save new weight
The one's complement of u is used instead of -u, because they are only slightly
different and the step size does not require the exact number. The weight update with
this technique requires lON instruction cycles and FIR filtering requires Ninstruction cycles
so that the total number of instruction cycles needed is lIN + 21. The complete TMS32OC25
assembly program is given in Appendix Fl.
To determine whether a positive or negative u should be used without branching
is trickier in the TMS320C30. Fortunately, the extended precision registers ofTMS320C30
interpret the 32 most-significant bits of the 40-bit data as the floating-point number and
the 32 least-significant bits of the 40-bit data as an integer. When a floating-point number
218
changes its sign, its exponent remains the same. Therefore, the sign of step size u can
be determined by using XOR logic on its mantissa. The following code shows how the
sign-sign LMS algorithm is implemented on the TMS320C30.
II
SSLMS
II
=
=
=
=
=
=
ASH
XOR3
LDF
ASH
XOR3
ADDF3
-31,R7
RO,R7,R5
*ARO+ +(1)%,R6
-31,R6
R5,R6,R4
*AR1,R4,R3
;
;
;
;
;
;
R7
R5
R6
R6
R4
R3
LDI
RPTB
LDF
STF
ASH
XOR3
ADDF3
order-3,RC
SSLMS
*ARO+ +(1)%,R6
R3, *AR1 + +(1)%
-31,R6
R5,R6,R4
*ARl,R4,R3
;
;
;
;
;
;
;
LDF
STF
ASH
XOR3
ADDF3
STF
*ARO,R6
R3,*AR1++(1)%
-31,R6
R5,R6,R4
*AR1,R4,R3
R3, *AR1 + +(1)%
;
;
;
;
;
;
Sign[e(n)]
Sign[e(n)] * u
x(n)
Sign[x(n -i)]
Sign[x(n -i)]*Sign[e(n)] * u
wi(n) + R4
Here, RO, R4, and R5 contain the value of u before updating. ARO and ARl point
to x array and w array, respectively. R7 contains the value of error signal e(n). The complete program is given in Appendix F2. The total number of instruction cycles is 5N + 16,
which is much higher than LMS algorithm.
The sign-sign LMS algorithm is developed to reduce the multiplication requirement
of the LMS algorithm. Since DSPs provide the hardware multiplier as a standard feature,
this modification does not provide any advantage when implementing this algorithm on
the DSPs. On the contrary, it causes some disadvantages since decision instructions will
destroy the instruction pipeline. If you use the XOR logic operation in order to avoid using the decision instructions, the complexity of the program will be increased and the total
number of instruction cycles will be greater than the regular LMS algorithm.
219
based upon adding a small forcing function, which tends to bias each filter weight toward
zero. The leaky LMS algorithm has the form
~(n +
1) = r
~(n)
+ u e(n)
(28a)
~(n)
1) =
~(n)
- c
~(n)
+ u e(n)
~(n)
(28b)
In order to achieve the highest throughput by using ZALR and MPYA, cw(n) can
be implemented by shifting wj(n) right by m bits where 2- m is close to c. Since the length
of the accumulator is 32 bits and the high word (bits 16 to 31) is used for updating w(n),
shifting right m bits of wj(n) can be implemented by loading wj(n) and shifting left
16 - m bits. The sequence of TMS320C25 instructions to implement Equation (28b) is
shown as
LRLK
LRLK
LRLK
LT
MPY
ADAPT ZALR
MPYA
SUB
SACH
BANZ
ARl,N-l
AR2,COEFFD
AR3,LASTAP+ 1
ERRF
*-,AR2
*,AR3
*-,AR2
*,LEAKY
*+,O,ARI
ADAPT,*-,AR2
;
;
;
;
Set up counter
Point to wj(n)
Point to x(n - i)
T = ERRF =u*e(n)
; LEAKY=16-m
For each iteration, 7N instruction cycles are needed to perform the adaptation process (6N for the LMS algorithm). The total number of instruction cycles needed is 8N +28
(see Appendix Gl for the complete program). The leaky factor r has the same effect as
adding a white noise to the input. This technique not only can solve adaptive weights
overflow problem, but also can be beneficial in an insufficient spectral excitation and stalling
situation [5].
The method used above is especially for the TMS320C25, which has a free shift
feature. Since TMS320C30 is a floating-point processor, r can simply multiply to filter
coefficient. However, in order to reduce the instruction cycles, this mUltiplication can
combine with another instruction to be a parallel instruction inside the loop. The following code shows how to rearrange the instructions from the LMS algorithm to include this
multiplication without an extra instruction cycle.
220
II
II
LLMS
II
II
II
II
MPYF
MPYF3
MPYF3
ADDF3
LDI
RPTB
MPYF3
ADDF3
MPYF3
STF
@u_r,R7
*ARO+ +(I)%,R7,Rl
*ARO+ +(1)%,R7,Rl
*ARl,Rl,R2
order-4,RC
LLMS
*AR2,R2,RO
*+ARl(I),Rl,R2
*ARO++(1)%,R7,Rl
RO, *ARI + +(1)%
;
;
;
;
;
;
;
;
;
;
MPYF3
ADDF3
MPYF3
STF
MPYF3
ADDF3
*AR2,R2,RO
* + ARl(I),Rl,R2
*ARO,R7,Rl
RO,*ARl++(I)%
*AR2,R2,RO
*+ARl(1),Rl,R2
;
;
;
;
;
;
MPYF3
STF
STF
*AR2,R2,RO
RO,*ARI + +(1)%
RO,*ARI + +(1)%
II
R7 = e(n)*u/r
Rl = e(n)*u*x(n)/r
Rl = e(n)*u*x(n-l)/r
R2 = wa(n) + e(n)*u*x(n)/r
Initialize repeat counter
do i = 0, N-4
RO = r*wj(n) + e(n)*u*x(n-i)
R2 = Wj+l(n) + e(n)*u*x(nz-i-l)/r
Rl= e(n)*u*x(n-i-2)/r
Store wj(n + 1)
RO = r*wN-3(n) + e(n)*u*x(n-N+3)
R2 = wN-2(n) + e(n)*u*x(n-N+2)/r
Rl = e(n)*u*x(n - N + 1)/r
Store wN-3(n+l)
RO = r*wj(n) + e(n)*u*x(n-N+2)
R2 = wN-l(n) +
e(n)*u*x(n - N + 1)/r
; RO = r*wj(n) + e(n)*u*x(n - N + 1)
; Store wN-2(n+l)
; Update last W
Auxiliary registers ARO and ARI point to x and Warrays. AR2 points to the memory
location that contains value r. R7 contains the value of error signal e(n). Rl and R2 are
updated before the loop because the parallel instructions inside the loop use the previous
values in Rl and R2. Note that Rl is updated twice before the loop because the updating
of R2 requires the previous value of Rl. In order to update x array pointer to the new
beginning of the data buffer for next iteration, two of the loop instruction sets have been
taken out ofloop and modified by eliminating the incrementation of ARO. The TMS320C30
assembly program of an adaptive transversal fIlter with the leakage LMS algorithm is listed
in Appendix G2 as an example. The total number of instruction cycles for this algorithm
is 3N + 15, which is the same as the LMS algorithm. This example shows the power and
flexibility of the TMS320C30.
221
Implementation Considerations
The adaptive filter structures and algorithms discussed previously were derived on
the basis of infinite precision arithmetic. When implementing these structures and algorithms
on a fixed integer machine, there is a limitation on the accuracy of these filters due to
the fact that the DSP operates with a finite number of bits. Thus, designers must pay attention to the effects of finite word length. In general, these effects are input quantization,
roundoff in the arithmetic operation, dynamic range constraints, and quantization of filter
coefficients. These effects can either cause deviations from the original design criteria
or create an effective noise at the filter output. These problems have been investigated
extensively, and techniques to solve these problems have been developed [28, 29].
The effects of finite precision in adaptive filters is an active research area, and some
significant results have been reported [30 through 32]. There are three categories of finite
word length effects in adaptive filters:
Design Issues (design of the optimum step size u that minimizes system
noise).
(29)
i=O
and
wj(n + 1)
wj(n)
(30)
where x(n -i) is the input sequence and wj(n) are the filter coefficients.
If the input sequence and filter coefficients are properly normalized so that their
values lie between -1 and 1 using Q15 format, no error is introduced into the addition.
However, the sum of two numbers may become larger than one. This is known as overflow.
The TMS320C25 provides four features that can be applied to handle overflow management [13]:
222
A.
B.
C.
D.
< 1/
(31)
Iwj{n) I
i=O
where Xmax denotes the maximum of the absolute value of the input. The right shifter
of the TMS320C25, which operates with no cycle overhead, can be applied to implement
scaling to prevent overflow of multiply-accumulate operations in Equation (29). By setting the PM bits of status register STl to 11 using the SPM or LSTl instructions, the
P register output is right-shifted 6 places. This allows up to 128 accumulations without
the possibility of an overflow. SFR instruction can also be used to right shift one bit of
the accumulator when it is near overflow.
Another effective technique to prevent overflow in the computation of Equation (29)
is using saturation arithmetic. As illustrated in Figure 12, if the result of an addition
overflows, the output is clamped at the maximum value. If saturation arithmetic is used,
it is common practice [28] to permit the amplitude of x(n -i) to be larger than the upper
bound given in Equation (31). Saturation of the filter represents a distortion, and the choice
of scaling on the input depends on how often such distortion is permissible. The saturation arithmetic on the TMS320C25 is controlled by the OVM bit of status register STO
and can be changed by the SOVM (set overflow mode), ROVM (reset overflow mode),
or LST (load status register).
output
1-2- 15
-1
: 1-2- 15
--------1-------.. . .
input
223
Filter coefficients are updated using Equation (30). As illustrated in Figure 13, a
new technique presented in reference 31 uses the scaling factor a to prevent filter's coefficients overflow during the weight updating operation. Suppose you use a = 2-ffi. A right
shift by m bits implements multiplication by a, while a left shift by m bits implements
the scaling factor 1Ia. Usually, the required value of a is not expected to be very small
and depends on the application. Since a scales the desired signal, it does not affect the
rate of convergence.
dIn) - - . . . , . . . . - - - -......
J----.~
xln)---t_.....
FILTER
STRUCTURE
1/8
eln)
yIn)
ADAPTIVE
ALGORITHM
o=
2- b ,
(32)
(b = 15), is called the width of quantization since the numbers are quantized in steps of o.
The products of the multiplications of data by coefficients within the filter must be
rounded or truncated to store in memory or a CPU register. lAs shown in Figure 14, the
roundoff error can be modeled as the white noise injected into the filter by each rounding
operation. This white noise has a uniform distribution over a quantization interval and
for rounding
- 112 0 < e
224
~112
(33a)
and
(33b)
where
x----t. .[:----t4..,
.
E
t - - -........... y
= Rounding Ix
8]
=x
225
Design Issues
The performance of digital adaptive algorithms differs from infinite precision adaptive algorithms. The finite precision LMS algorithm is given as
~(n
+ 1)
~(n)
Q[u*e(n)*~(n)]
(34)
where Q [.] denotes the operation of fixed point quantization. Whenever any correction
term u*e(n)*x(n -i) in the update of the weight vector in Equation (34) is too small, the
quantized value of that term is zero, and the corresponding weight wj(n) remains unchanged. The condition for the ith component of the vector w(n) not to be updated when the
algorithm is implemented with the TMS320C25 is
I u e(n)
x(n-i)
I <012
(35a)
2exp * 0/2
(35b)
(36b)
where ax 2is the power of input signal x(n) and fmin is the minimum mean squared error
at steady state.
In the Leaky LMS Algorithm section, it was mentioned that the exce.ss MSE given
in Equation (14) is minimized by using small u. However, this may result in a large quantization error since the most significant term in the total output quantization error is [31]
226
Noe2
(37)
2 a2 u
The optimum step size uo reflects a compromise between these conflicting goals.
The value of uo is shown to be too small to allow the adaptive algorithm to converge completely and also to give a slow convergence. In practice, u > uo is used for faster convergence. Hence, the excess MSE becomes larger, and the roundoff noise can typically
be neglected when compared with the excess mean square error.
Finally, recall Equations (11) and (12). The step size u has an upper limit to guarantee
the stability and convergence. Therefore, the adaptive algorithm requires
1
O<u<----
(38)
Nox 2
On the other hand, the step size u also has a lower limit. The optimum uo, which
minimizes the sum of the excess MSE and roundoff noise, is smaller than Umin, i.e., too
small to allow the adaptive weight to converge. For an algorithm implemented on the
TMS320C25, the word-length of 16 bits is fixed, and the minimum step-size that can be
used is given in Equation (36). The most important design issue is to find .the best u to satisfy
Umin
<
< ----
Nol
(39)
Therefore, in order to make the condition in Equation (39) valid, the initial values
of filter coefficients are better close to zero for the floating-point processor if the situation
in unknown.
Software Development
The TMS320C25 and TMS320C30 combine the high performance and the special
features needed in adaptive signal processing applications. The processors are supported
by a full set of software and hardware development tools. The software development tools
include an assembler, a linker, a simulator, and a C compiler. The most universal software development tool available is a macro assembler. However, the assembly language
programming for nsp can be tedious and costly. For adaptive filter applications, an
assembly language programmer must have knowledge of adaptive signal processing. The
challenge lies in compressing a great deal of complex code into the fairly small space and
most efficient code dictated by the real-time applications typical of adaptive signal processing.
227
Recently, C compilers for the processors were developed to make DSP programming easier, quicker, and less costly compared with the work associated with programming in assembly language. Due to the general characteristics of a compiler, the code
it generates is not the most efficient. Since the program efficiency consideration is important for adaptive filter implementation, the code generated from the C compiler has to
. be modified before implementing. Thus, two alternative ways, besides writing an assembly
program, to implement adaptive signal processing on DSP are presented. First is the
automatic adaptive filter code generator [12], which can be found on Texas Instruments
TMS320 Bulletin Board Service (BBS), and second are the adaptive filter function libraries
that support assembly and C programming languages.
In this report, two adaptive filter libraries have been developed: one can be called
from an assembly main program; the other can be called from the C main program. Note
that, for the TMS320C25 only, certain data memory locations have been reserved for storing
the ne.cessary filter coefficients, previous delayed signal, etc. In other words, these data
memories are used as global variables.
The foilowing example is the TMS320C25 assembly main routine, which performs
an adaptive line enhancement by calling the LMS algorithm subroutine. The filter order
is 64, delay is equal to one, and the convergence factor u is 0.01.
*
*
228
ORDER:
MU:
PAGEO:
.equ
.equ
.equ
20
327
*
*
**
XO:
XN:
WN:
.usect
.usect
.usect
*
ONE:
U:
ERR:
Y:
.usect
.usect
.usect
.usect
.usect
.usect
D:
ERRF:
**
*
"buffer" ,ORDER-l
"buffer" ,1
"coeffs" ,ORDER
, 'parameters' , , 1
, 'parameters' , , 1
, 'parameters' , , 1
, 'parameters' , , 1
, 'parameters' , , 1
"parameters" , 1
INITIALIZATION
START
LDPK
SPM
SSXM
LRLK
LACK
SACL
LALK
SACL
PAGEO
1
AR7,XO
1
ONE
MU
U
;
;
;
;
;
Set DP = 0
Set PM equal to 1
Set sign extension mode
AR7 point to > 300
Initialize ONE = 1
************************************************************************
************************************************************************
INPUT:
IN
D,PA2
CALL
LMS
; Call subroutine
OUT
Y,PA2
LAC
LARP
SACL
B
.end
D
AR7
*
*
OUTPUT:
*
INPUT
229
The symbols, such as ORDER, U, ONE, D, LMS, Y, and ERR, are defined and
referred to for the purpose of modular programming. The uninitialized sections specified
by the directive .usect can be placed in any location of memory according to the linker
command file. Note that MACD instruction requires the sources of the operands on program memory and data memory separately, and CNFP instruction configures RAM block
oas program memory. Therefore, the coeffs section has to be in data RAM block 0, and
the buffer has to be in RAM block 1. Appendix HI contains the adaptive transversal filter
with LMS algorithm subroutine using the TMS320C2S, and Appendix H2 contains an
example of a linker command file.
*
N
mu
*
begin
230
$
N,BK
@xIL-addr
@xIL-addr,ARO
@wIL-addr,ARI
O.O,RO
N-1
RO,*ARO+ +(1)%
;
;
;
;
;
Set
Set
Set
Set
RO
up circular buffer
data page
pointer for x[]
pointer for w[]
= 0.0
; x[] = O.
IlsTF
LDI
LDI
; w[] = O.
; Set pointer for input ports
; Set pointer for output ports
nput:
LDF
IILDF
STF
STF
*AR6,R7
*+AR6(1),R6
R7,@d
R6,*ARO
;
;
;
;
*
*
*
*
CALL LMS30
OUTPUT y(n) AND e(n) SIGNALS
LDF
BD
LDF
STF
STF
@y,R6
input
@e,R7
R6,*AR7
R7,*+AR7(1)
;
;
;
;
;
Input d(n)
Input x(n)
Insert d(n)
Insert x(n) to buffer
Get y(n)
Delay branch
Get e(n)
Send out y(n)
Send out e(n)
*
DEFINE CONSTANTS
*
*
.usect "buffer" ,N
n
.usect "coeffs" ,N
wn
.usect "vars",1
iIL-addr
out_addr .usect "vars",1
xIL-addr .usect "vars",1
wIL-addr .usect "vars",1
.usect "vars" ,1
u
.usect "vars",1
order
.usect "vars",1
d
.usect "vars",1
y
.usect "vars" ,1
e
" .cinit"
. sect
cinit
. word 6,iIL-addr
.word 0804000h
.word 0804002h
.word xn
. word wn
Implementation of Adaptive Filters with the TMS320C25 or the TMS320C30
231
.float
.word
.end
mu
N-2
In the above example, data memory order is initialized to N - 2 for computation convenience. The linker command files and the subroutine that implements the LMS transversal filter can be found in Appendixes H4 and H5.
C Function Libraries
The TMS32OC25 and TMS32OC30 C language compilers provide bigh-Ievellanguage
support for these processors. The compilers allow application developers without an extensive knowledge of the device's architecture and instruction set to generate assembly
code for the device. Also, since C programs are not device-specific, it is a relatively
straightforward task to port existing C programs from other systems.
To allow fast development of efficient programs for adaptive signal processing applications, C function libraries have been developed. These libraries include functions for
adaptive transversal, symmetric transversal, and lattice structures.
232
**-
SUBK
SACL
LAC
SACL
LAC
SACL
LAC
LRLK
SACL
1
ORDER
*U
*D
*-,O,A-R3
AR3,FRSTAP
*
; ORDER = N - 1
; Getting and storing the mu
; Getting and storing the D
; Insert the newest sample
ARl
AR2,*-,AR2
y
*,O,ARl
AR2,*,AR2
ERR
*,O,ARI
Therefore, the parameters should be entered in the order given above. If there are
other parameters, they should be inserted right after the convergence factor mu. The leaky
LMS algorithm subroutine is given as an example.
llms(n,mu,r ,d,x,&y ,&e}
the r is defined in Equation (28a). Note that the values of the AR registers, which will
be used in subroutine, and the status registers must be saved at the beginning of the
subroutine and restored right before returning to calling routine. An example of a C-callable
program is given in Appendix 11. Memory locations 0200h to 0200h + N -1 and 0300h
to 0300h + N -1 are reserved for filter coefficients and buffers, respectively. N denotes
the filter order.
TMS320C30 C Subroutine
As previously mentioned, the TMS320C30 architecture has features designed for
a high-level language compiler. Note that the callable word is dropped in this section title
because the TMS320C30 is so flexible that the restrictions for the TMS320C25 no longer
exist. Since the memory locations of filter buffers and coefficients are determined by the
parameters that pass from the calling routine, the same subroutine can be used in different
places. However, the only restriction is that the memory locations of filter buffers must
align to the circular addressing boundary [14]. The features of TMS320C30 architecture
that make a major contribution toward these improvements are dual data address buses,
software stack, and flexible addressing mode. The parameters passed to subroutine are
pushed into the stack. Therefore, after returning from the subroutine, the stack pointer,
SP, must be updated to point to the location where SP pointed before pushing the parameters
Implementation of Adaptive Filters with the TMS320C25 or the TMS320C30
233
into the stack. "However, this will be done by the C compiler. The usage example of the
C function subroutine is given as follows:
tlms(n,u,d,&w,&x,&y,&e) where
n - Filter order
u - Step size
d - Desired signal
&w - Filter coefficients
&x - Input signal buffers
&y - Addr of output signal
&e - Addr of error signal
The example below shows how the C subroutine receives and manipulates the
parameters passed from the caller program and how the result is returned to the caller
routine.
FP
*
*
*
*
AR3
FP"
SP,FP
*-FP(2),R4
; Get filter order
"*-FP(6),ARO ; Get pointer for x(]
*--FP(5),ARl ; Get pointer for w(]
IlsTF
LDI
STF
MPYF
POP
*-FP(2),AR2
R2, * +FP(1),R7
R2, *AR2
*-FP(3),AR2
R7, *AR2
* + FP(2),R7
FP
;
;
;
;
;
;
Note that AR3 is used as the frame pointer in TMS320C30 C compiler. Appendix
12 contains the complete LMS transversal filter example subroutine program.
234
on the TMS320C25. Figure 15 illustrates the flowchart of this procedure. Since the implementation on TMS320C30 is done only by the simulator, the last stage, real-time testing,
is not implemented.
Algorithm Analysis
and C Program
Implementation
J
.~
Re-write C Program
to Emulate
DSP Sequence
~
Implement in DSP
Program and Testing
by DSP Simulator
Real-Time
Testing
+
Figure 15. Adaptive Filter Implementation Procedure
In the first stage, algorithm design and study is performed on a personal computer.
Once the algorithm is understood, the filter is implemented using a high-level C program
with double precision coefficients and arithmetic. This filter is considered an ideal filter.
In the second stage, the C program is rewritten in a way that emulates the same
sequence of operations with the same parameters and state variables that will be implemented
in the processors. This program then serves as a detailed outline for the DSP assembly
language program or can be compiled using TMS320C25 or TMS320C30 C compiler.
The effects of numerical errors can be measured directly by means of the technique shown
in Figure 16, where H(z) is the ideal filter implemented in the first stage and H'(z) is
a real filter. Optimization is performed to minimize the quantization error and produce
stable implementation.
235
H(z)
+
10(n)12
x(n)
ME
n=1
e 2 ln)
H(z)
236
PERSONAL
COMPUTER
TEK2235
SCOPE
FG504
FUNCTION
GENERATOR
HP3561A
DYNAMIC
SIGNAL
ANALYZER
1:
+
.......-
PRECISION
NOISE
GENERATOR
HP PLOTTER
x(n)........,-.------------,
d(n)
+
~-~~e(n)
x(n-1)
Adaptive
Filter
1 - - - 0 - - - - _ Enhanced
yIn)
Output
237
oscilloscope and signal analyzer, the significant SNR improvement, convergence speed,
ability to track nonstationary signals, and long-term stability of the adaptive predictor are
observed.
RANGE: 17 dBV
1/15
115dBV
STATUS: PAUSED
A:MAG
Amplitude
6dB/DIV
-33
START: 0 Hz
BW: 47.742 Hz
STOP: 5,000 Hz
,238
RANGE: 13 dBV
1/15
STATUS: PAUSED
A:MAG
15 dBV
Time
Amplitude
6 dB/DIV
-33
START:
0 Hz
BW: 47.742 Hz
Summary
Three adaptive structures and six update algorithms are implemented with the
TMS320C25 and TMS320C30. Applications of adaptive filters and implementation considerations have been discussed. Two subroutine libraries that support both C language
and assembly language for two processors were developed. These routines can be readily
incorporated into TMS320C25 or TMS320C30 users' application programs.
The advancements in the TMS320C25 and TMS320C30 devices have made the implementation of sophisticated adaptive algorithms oriented toward performing real-time
processing tasks feasible. Many adaptive signal processing algorithms are readily available
and capable of solving real-time problems when implemented on the DSP. These programs provide an efficient way to implement the widely used structures and algorithms
on the TMS320C25 and TMS320C30, based on assembly-language programming. They
are also extremely useful for choosing an algorithm for a given application. The performances of adaptive structures and algorithms that have been implemented using the
TMS320C25 and TMS320C30 have been summarized in Tables 1 and 2.
239
LMS
TMS320C25
Instruction Cycles
7N+28
33
Leaky
Instruction Cycles
8N+28
LMS
34
Sign-Data
Instruction Cycles
11N +26
Transversal
LMS
41
Structure
Sign-Error
Instruction Cycles
7N+26
LMS
30
Sign-Sign
Instruction Cycles
11 N + 21
LMS
30
Normalized
Instruction Cycles
7N+S7
LMS
47
Instruction Cycles
7.SN+38
LMS
50
Leaky
Instruction Cycles
8N+38
Symmetric
Transversal
Structure
LMS
51
Sign-Data
Instruction Cycles
9.SN+36
LMS
58
Sign-Error
Instruction Cycles
7.5N+36
LMS
47
Sign-Sign
Instruction Cycles
9.5N+31
LMS
47
Normalized
Instruction "Cycles
7.5N +69
LMS
66
Instruction Cycles
33N+32
LMS
63
Leaky
Instruction Cycles
35N+32
Lattice
LMS
65
Structure
Sign-Error
Instruction" Cycles
36N+32
LMS
65
Normalized
Instruction Cycles
90N+34
92
LMS
"
240
Instruction Cycles,
3N+ 15
17
Leaky
Instruction Cycles
3N+ 15
LMS
19
Sign-Data
Instruction Cycles
5N+ 16
Transversal
LMS
24
Structure
Sign-Error
Instruction Cycles
3N+ 16
LMS
18
Sign-Sign
Instruction Cycles
5N+ 16
LMS
24
Normalized
Instruction Cycles
3N+47
LMS
49
Instruction Cycles
2.5N+15
LMS
Symmetric
Transversal
Structure
23
Leaky
Instruction Cycles
2.5N + 19
LMS
26
Sign-Data
Instruction Cycles
3.5N+ 18
LMS
30
Sign-Error
Instruction Cycles
2.5N + 18
LMS
24
Sign-Sign
Instruction Cycles
3.5N + 17
LMS
30
Normalized
Instruction Cycles
2.5N+50
LMS
56
Instruction Cycles
14N+9
LMS
20
Leaky
Instruction Cycles
16N+9
Lattice
LMS
22
Structure
Sign-Error
Instruction Cycles
16N+9
LMS
22
Normalized
Instruction Cycles
67N+9
LMS
73
241
References
[1] B. Widrow and S. Stearns, Adaptive Signal Processing, Prentice-Hall, 1985.
[2] R. Lucky, J. Salz, and E. Weldon, Principles of Data Communications, McGrawHill, 1968.
[3] S. Haykin, Adaptive Filter Theory, Prentice-Hall, 1986.
[4] M. Honig and D. Messerschmit, Adaptive Filters: Structures, Algorithms, and Applications, Kluwer Academic, 1984.
[5] J.R. Treichler, C.R. Johnson, and M.G. Larimore, Theory and Design of Adaptive
Filters, Wiley, 1987.
[6] T. Alexander, Adaptive Signal Processing, Springer-Verlag, 1986.
[7] G. Goodwin and K. Sin, Adaptive Filtering Prediction and Control, Prentice-Hall,
1984.
[8] M. Bellanger, Adaptive Digital Filters and Signal Analysis, Marcel Dekker, 1987.
[9] J. Proakis, Digital Communications, McGraw-Hill, 1983.
[10] C. Chen and S. Kuo, "An Interactive Software Package for Adaptive Signal Processing on an ffiM Person Computer," 19th Pittsburgh Conference on Modeling and
Simulation, May 1988.
[11] S. Kuo, G. Ranganathan, P. Gupta, and C. Chen, "Design and Implementation of
Adaptive Filters," IEEE 19881nternational Conference on Circuits and Systems, June
1988.
[12] S. Kuo, G. Ma, and C. Chen, "An Advanced DSP Code Generator for Adaptive
Filters," 1988 ASSP DSP workshop, Sept. 1988.
[13] Texas Instruments, Second-Generation TMS320 User's Guide, 1987.
[14] Texas Instruments, Third-Generation TMS320 User's Guide, 1988.
[15] S. Qureshi, "Adaptive Equalization," Invited Paper, Proceedings of the IEEE, Sept.
1985.
[16] L. Rabiner and R. Schafer, Digital Processing of Speech Signals, Prentice-Hall, 1978.
[17] N. Jayant and P. Noll, Digital Coding of Waveforms: Principles and Applications
to Speech and Video, Prentice-Hall, 1984.
[18] J. Makhoul, "Linear Prediction: A Tutorial Review," Proceedings ofthe IEEE, April
1975.
[19] C. Cowan and P. Grant, Adaptive Filters, Prentice-Hall, 1985.
[20] C. Gritton and D. Lin, "Echo Cancellation Algorithms," IEEE ASSP Magazine,
April 1984.
[21] D. Messerschmitt, et al, "Digital Voice Echo Canceller with a TMS32020," in Digital
Signal Processing Applications with the TMS320 Family, Prentice-Hall, 1986.
[22] B. Widrow, et al, "Adaptive Noise Cancelling: Principles and Applications," Proceedings of the IEEE, December 1975.
[23] A. Lovrich and R. Simar, "Implementation of FIRIIIR Filter with the
TMS3201O/TMS32020," in Digital Signal Processing Applications with the TMS320
Family, Texas Instruments, 1986.
242.
243
CI
C2
DI
D2
EI
E2
FI
F2
GI
G2
HI
H2
H3
H4
H5
Ii
12.
244
Title
Transversal Structure with LMS Algorithm Using the TMS320C25
Transversal Structure with LMS Algorithm Using the TMS320C30
Symmetric Transversal Structure with LMS Algorithm Using the
TMS320C25
Symmetric Transversal Structure with LMS Algorithm Using the
TMS320C30
Lattice Structure with LMS Algorithm Using the TMS320C25
Lattice Structure with LMS Algorithm Using the TMS320C30
Transversal Structure with Normalized LMS Algorithm Using the
TMS320C25
Transversal Structure with Normalized LMS Algorithm Using the
TMS320C30
Transversal Structure with Sign-Error LMS Algorithm Using the
TMS320C25
Transversal Structure with Sign-Error LMS Algorithm Using the
TMS320C30
Transversal Structure with Sign-Sign LMS Algorithm Using the TMS320C25
Transversal Structure with Sign-Sign LMS Algorithm Using the TMS320C30
Transversal Structure with Leaky LMS Algorithm Using the TMS320C25
Transversal Structure with Leaky LMS Algorithm Using the TMS320C30
Assembly Subroutine of Transversal Structure with LMS Algorithm Using
the TMS320C25
Linker Command File for Assembly Main Program Calling a TMS320C25
Adaptive LMS Transversal Filter Subroutine
TMS320C30 Adaptive Filter Initialization Program
Assembly Subroutine of Transversal Structure with LMS Algorithm Using
the TMS320C30
Linker Command/file for Assembly Main Program Calling the TMS320C30
Adaptive LMS Transversal Filter Subroutine
C Subroutine of Transversal Structure with LMS Algorithm Using the
TMS320C25
C Subroutine of Transversal Structure with LMS Algorithm Using the
TMS320C30
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P = U ERRln) f Xln-k)
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not bun set up. User has to lodify the Rin routine for specific
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text
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= 0.01.
Note: This source progru is the generic version; I/O configuration has
not betn set up. User has to .odify the !Nin routine for specific
application.
Initial condition:
!) ptf status bit should be equi.l to 01.
2) sxn stitus bit should be set to logic 1.
3) Tt.. current (P Ida.ta IItllOry page pointer) should bt pige O.
4) Data lIt.ory U should be "]27.
5) The 81 " BD1 pointer 1M3 " M4) should be exchanged every
iteration. For enap1e,
For odd iteration: AR3 -) 81
AR4 -} 81
l.IIRf'
AR3
l.AAI(
ARI.IlIIlER-I
M2,FI
lRlK
l.RI.J(
l.RI.J(
l.RI.J(
l.RI.J(
W~
~~
('1~
N="
AR3.BI
AR4.BDI
ARS,GI
AR6.KI
Vt~
a:
INITIAlIZE TI BI AlII Fl
00
lAC
SACL
SOlCL
-.O,M2
I,O,AR3
"1
INITIIIlIZATJI*
LT
II'Y
....= .r,;.
(JQ
fffffHfHHfffffHHHfHHHHfH
= SU1
d~
HfffHffffffffffHfffffffHfffffH
Kiln+U = Kiln) +
Q.
('1
bi-l!n:-l)
Ul
Bl=
8Dl:
* fi-Hnl
AR4 -} 001
tv
'coeffs"~CER
I-
i=O
eoeffs ,au:ER
coeffs .~+1
64
yin) = SIJ'I yUn)
.uSlet
.usect
D:
>
"CI
"CI
bi-Hnl :-:
;;"!
64
.usect
-i
-iZi-i-}ISlMI--} . ----iZi-i-}ISlMJ--)bilnJ
bOtn) :-:
.equ
n:
1(1:
fki-J :
:-:
Ftbruuy, 1989
fki-l
xln)-:
.leO :
Clltin~hung
fHHUHfl,III IIIIIII.fHH+HfHHHHHHHHUHHtHHHfl4ff'HHH
IEFII PARAIETERS
is
.s;,
ehtn,
'us'
fHH.fH.......ufHfHf-HH.HHtH.HHffHHfHHHf......ffH
',ARS
1.M2
PAC
SACH
IG
ADIII
SACH
E,
T = BI
P=BIIGI
ACe =81 f Gl
Initialize YIOI = B1 f 01
ra = -181 I Gil
ra = Dlnl - 81 GI
Initialize EIOI = Din) - 81 _ G1
... *
252
u:~
j~
~
~
ii!.
..
L30 I Adaptive lattice Structure Filter IIIith"UIS Algorithl
. using the 1l1S32OC3O
::l
Algorithll
1;;"'
"";osis
bi-1(n-l)
~:;;.
k=O
64
64
yin) = SlJI yiCn) =ilIt biCn)fG;iCn)
i=l
i=l
""~
kHn+l) = Kilnl + IU
GHn+1)
""
~
~
c:>
""
~
I [
I
filnlfbi-Hn-l) + bUnlffi-Hnl ]
tiln)
* biln)
i=I,2, 64
=0.04.
; R3
copy
idipfltr.int l
OOTPUT y(nl
..
BD
SUBF
fHffHfllfffHfffHHffHHHfffHHHffHtHH
ord.r
.5.t
.s.t
64
0.04
STF
:I STF
LDI
II LDI
; Filter ord.r
; St.p siz
begin
c:>
a
c:>
01'<ier f 2,BK
f:kn-iddr
Ikruddr,MO
Ibn_iddr,lIRl
f! .....ddr,AR2
order-,IRO
O.O,RO
ordtr*2-1
RO, tIIROttl lIX
RO,tllRltt(!lX
IIRI,IRO,1IR4
liruddr, AR6
f:out-l.ddr,M1
ItOI'd
LDF
II LlIF
tIIR6,R7
ft/IR6ll ) ,R5
; Input dIn)
I Input xln}
.lIIOl'd
;
,
;
;
;
Set
Stt
Set
Set
Set
up Circular
d.ti page
pointtr for
pointer for
pointer for
buff.r
Ul
b[]
gEl
, RO = 0.0
, kll = 0.0 .nd gIl = 0.0
, bll = 0.0 ODd bd[] = 0.0
input:
f
kn
gn
bn
in_iddrouLaddr
kn-iddr
bn...ddr
gO-lddr
cinit
.UStct
.usect
.usect
.usect
.usect
.usect
used
.usect
.usect
.Stct
.lIIord
.lIIord
.word
.lIIord
.fl ..t
.tnd
....=
.
Q.
~
~
N
~~
a.
.........
= ....
[Il
(JQ
DeIlY bl'lnch
Tik. out liSt tel'll
Stnd out ylnl
Send out e(n)
Upditt k[] pointer
Updit. g[] pointer
t")
~
;'00
.....
""I
1-3=
~~
00E;
~~
~~
~=:
~=-
DEFIIf: cmsTANTS
.t.xt
.5.t
LDI
UP
LDI
LDI
LDI
LDI
LDF
Rl'TS
STF
Ii STF
ADDI
LDI
LDI
"C
"C
.(nl SIGNALS
input
R4,R6
R6,tAR7
R7,ttllR7<l1
fARO-UROI,RS
tAR2-UROI, R7
>
= kFi-l
fHffHlfHffHHfHffffllllllllllllllll tHH
~
N
N
UI
W
SUBF
ordtr-l,RC
lattice
tARO,RS,R3
R7, tllRltt( m,RO
R3,tllR4,R3
I.,RO
RO,tAR2,RO
R3,.ARl
R5,tllRl,Rl
RO, tAR2tt( II
tARO, tM4,RO
RO,RS
RS,fllR4tt(IlX,RO
RI,RO
lu,RO
RO,tIIRO,RO
R3,tAR2,R4
RO, fAROtt1l1
R4,R6
R4,R7
BI f 01
Insert Bl
E=D-BItGI
fHffHHHffftfHHHHHfHHtlllllllllllllllllllllHHHffHfl
VI
<:l
....
S-
+ IU
S.
SS-
=Giln)
Rl'TB
Pl'YF3
1I'YF3
SUBF3
"
II'YF
ADDF3
I I STF
Pl'YF3
II STF
II'YF3
SUBF
rfYF3
ADIF
II'YF
ADIF3
Pl'YF3
II STF
ADIF
;OS
RS,tAR2,R6
RS,tllRl
R6,R7
SUBF
un
5'
rfYF3
" STF
cotffs",ord.r
coeffs ,order
buffer".2i'order
vin-,i
vars.l
vats-,i
-val's, 1
wrs-,1
vars l ,l
.cinit
6.irLaddr
O804OOOh
l
080400211
kn
bn
gn
ou
=~
00
-=....>
(JQ
""I
.....
e=-
,htl.
'1JQ5'
tH-tHHH+ftfHHIHHtH-IfH+H++fHfHffHHHHffHH*HtHffHH
u.s
yarU) = (1.-r)
Where
vu(K-l) + r
x(nl
lJIRP
LRLK
k=O,l,2, 63
SPH
x(nl
lilt
M3
M3,XO
=
=~
ADD
ACe = (1-r)
oct = (1-1')
SACH
VM
Stort
~.
;;.
;;.
DEFIlE PARAlTERS
~ER:
SHIFT:
PAGEO:
...,<::>
.equ
.equ
.equ
..
I:>
D:
USfct
.used
.usect
RESERVE ADIR:SSES
.ustct
"buFfu" ,M[R-l
"buffer- ,I
"coeffs.,flUR
F~
VM(n-ll
VM(n-i) ... r
PIlRAlETERS
par-utters,1
"'1
* X(n)
X(n)
W~Hn)
CNFP
If'YK
LAC
1JE,15
LRlJ(
FIR
to 07fffh.
IIPTK
I1ACIJ
CNFD
APr;;
SACH
M3,XN
~-1
lIItOfdOOh, t-
CllIIPUTE 11 ERROO
; ACe = - Vln)
D
ERR
lPDATE 11 IoEIGHTS
10:
IN:
lit:
~;;
=--<
=~
d\ll
"'1
[IJ
lEG
ADm
SACH
b4
7
ACe = VMln-li
Initial condition:
1> PI1 status bit should be equal to 01.
2) SI~ status bit should be set to 1.
>~
rjQ~
o "'1
~
ERIIF
VM
VM,SHIFT
ERIIF,SHIFT
SUB
Note: This source progru is the generic version; 110 configuration has
not been set up. User has to .odify the Rin routine for specific
app 1ication.
Q
I:>
ZIUi
:3l
~
N
~.
SQRA
~.
'"
. text
."
;;.
ERRF:
VAA:
parae hrs,1
~
;:..
Q
v,
pa.rueters ,1
parueters,1
"parueters, 1
parueters",!
N
I:>
.usect
.used
.used
usect
u:
ko()
i.
pariHters.,l
M
63
'"
.used
.usect
HffffttHfffHH"tH""'.....HHf
Algorithll:
!?
'tl
Y:
ERR:
OOE:
LT
ERR
; T = ERRln)
; P ::: U f ERR(n)
1JE,15
rt'Y
pr;;
ADD
IUllli.I!E COOERGE
ABS
RPTK
SUBC
BIT
FACT~
14
VM
ERR, 0
e.
:r rJ1::t
. . . .....=
IJ'Q
=-~
~e;
s=~
rJ1~
~
....
N .....
Q=(lZ
NO
Vie
e.
N'
~
=~
rJ1
:?
~
'i5
BBZ
'
~Y
ADAPT
::...
'i5
:::to
:::J
;:;
;t
:
So
~
~
~
N
C
Q
v,
....c
So
~
~
~
N
C
ac
N
Ul
Ul
SAel
LARl<
LRIJ(
LRLK
LT
.s;,
NEXT
lEG
IEXT
FINISH
; ERRF
ERRF
ARt,ORDER-t
U .. :ERR(rd: I VAR
Set up counter
AR2,~
AA3, IN+1
Em
IALR
MPYA
"-,M2
',M3
1-,M2
SACH
H,O,ARI
BANI
.end
=-
; Store ERRF
P = U * ERR(n) .. X(n-k)
lQad ACCH !!11th A(k,nl &- round
W(k,n+ll = W(k,n) + P
p = U f ERRfnl .. X(n-k)
Store W(k,o+1)
tv
ItfftHftHffHltHflHHHttHftHfffffHffHtfHftffotflfffHfl
VI
0\
If'YF
If'YF
~
I'PYF
Algor-ittll:
b3
yin) = SltI .Ik)>xln-k) k=O.1.2 ..... b3
k=O
Vitln)
= rlvarln-l)
tin)
=dIn)
- yin)
wlk)
=!IIlk)
::t
!;
c
.s;,
PFYF3
:: ADIF
STF
RPTS
u~(n)tx(n-k)/var(n) k=O,I,2, 63
=64
ind -au
copy
btgin
\.It
(;)
.,
...
64
0.01
1.0
0.996
0.004
; Filhr,ordtr
; Step 5Ut
; Input signil powr
..
STF
STF
tARO++(Ul,tMl++(1)l,Rl
R6,R3
R3,tvu
; Rutore varin)
ordtr"2
Rl.R7
, .In)
= din)
- yin)
t.xt
... t
LDI
LIf'
LDI
LDI
LIF
Rl'TS
STF
I I STF
LDJ
LDI
~
II ~
STF
R2,tM7
R7,ttM7(1)
, 1.0 - olp"
_,R7
_Ml),Rb
Rb,<ARO
Input din)
Inpul xln)
Inmt xlnl to buff..
x[l = 0
.[1 = 0
Stt pointtr for iftput ports
Sft poinhr lor output ports
""r-:....
II"""""
~ ~
.,
=- ::a=
-s
=:
~
-
...-4
""1
rn
~ Qj
~. -
= =1
,Cooput. IIvarlnl
; min) = 0 2.
(JQ
~
~
......J
'"'"":I
a:
=
n
=
....
~
PUSH
POPF
Rl
-24,Rl
Rl
1.R2
24,Rl
Rl
Rl
II'YF
SUIIIF
If'YF
Rl,~.RO
2.0.RO
RO.Rl
, RO = v x[0]
, RO = 2.0 - v x[OI
, Rl = x[l] = x[O] 12.0 - v x[OII
I'fYF
SUIIIF
II'YF
R2,Rl.RO
2.0,RO
RO,Rl
; RO =V f xU]
, RO = 2.0 - v x[l]
, R2 " x[2] = x[1l 12.0 - v x[l])
~
Q..
II'YF
SUIIIF
If'YF
Rl.~.RO
, RO =v X[2]
, RO = 2.0 - v' x[2]
, R2 =x[3] = x[2] 12.0 - v x[21)
!;;ioI
2.0.RO
RO.Rl
If'YF
Rl.~,RO
, RO = v x[31
IEGI
SUBI
"dtr.II(
","_oddr
fxruddr.MO
..._oddr,ARI
O.O.RO
order-!
RO,tfIROt+llII
RO.tflRl++1III
lin~4dr 1Mb
loul_oddr;AR7
1--4
"'-'
r.I'J.
ASIi
.set
.set
.Stt
.5Ot
.5.t
PIJSW
v..>
~
....
SUBF
Q..
, Rl = 0.0
HfiffffHHHfHHtHlftHHfUHHMftHHH
...
O.O.Rl
'odoplltr.int'
"C
vuln-lI
tfffffHfHffHfHIfHffHfHHHHfIHHHtH
:
~
HfftHffHfHHHfHfffHHHfHffHHfHftHftHf
~
order
:::;-.u
~
pollltr
'"
olph.
;t
alphol
So
=t
::;.
~
; R3
>
If'YF3
>MO++II)I.tflRl++IIII.RI
:: ADIf3
Rl,R2.R2
; yin) = fII[].X[]
ADtf
Rl,R2
; Include liSt result
.
calPUTE ERROR SIGHAl .Inl
=0.01.
;:s
it.I::.
; R6 =x2
, Rb = IH) xl
+ l1-rlfXln)fx(n)
R6,-R6
"'_I.Rb
~~
lvat ,R3
ASIi
00 ::.a
W ....
(1
.,
W 0
~
..
!.
....
~
~
00
,.
;;li~
"'""
~i
!h
i~ ih
~.,
~~&
rhi ri
~i ~~
257
00
.title
1TSE25'
ERR:
.useet
HHtHHftHHllllllllllllllllHHfIHIHHtHHfflHfHHfHtHlfH
(1:
U:
.useet
.useet
ERRF:
NEGMU:
parueters",l
Rpal"ueters,1
parueters".1
"paruettrs,1
parueters R ,I
.useet
.ustet
>
"CI
*ff.l"HHHffHHHH~
Algorithll
IflflftfllfHIHit*HHHHfHHHH
63
ylnl 5lII.lkltxln-lc1 k=O,1,2, ,63
k=O
"
~.
01 llit.
Q
c
/GIll sh.uld be
NEG
ADDH
BGEI
LT
-m.
ACe - Ylnl
ACe Dlnl - Ylnl
; T register = -U
ADAPT
qu
qu
lEFllE AIDlSSES
64
.usect
.IStct
.usect
[f
-buffer- ,MlR-l
-buffer-, 1
-coeffs- ,(Ji[R
I);
VI
.USlct
usect
ARI,ORDER-I
; Set up counter
LRU<
l.Rl.K
II'Y
AR2,1fj
AR3,XN+1
IALR
II'YA
SACH
BANI
t+,O,ARI
ADAPT, ...., AR2
10=
INI
"U
lARK
.... ,AR2
1,M3
.... ,AR2
-parueters\1
-paI'ueters -.1
FINISH
.end
rIQ~
Q .,
:1.
~
~tIl
e="~.,~
....
T register = U
D
NEXT
/GIll
>.
til _
~;
ERROR
[f
1I'IIATE TI !.EIGHTS
lEFllE PiIRAITERS
Ifj+OfdOOh, ....
LT
HtHHff+lfHHHHtffllllllllllllllllllllllHHH
PAlEO'
~.
~
MCD
SACH
NEXT
!JURI
if
_.y
ONE, 15
AR3,XN
tJlIEl-1
tfj
Configure eo is progr... lHIIory
Clear the P register
Using rounding
Point to the oldest saple
Repeat N tiMS
Estiaate YCn)
Configure eo a5 data IBOry
RPTK
ClCK Tl SIGN
v.
II'YK
CNFD
APAC
Initial condition:
U PII stdus bit should be equal to 01.
21 SX" st.tus bit sh.uld be Stt t. I.
3} The current IF (dda ory ~ge pointer) should be page O.
4} Dlta ... ry CIE should be 1.
51 llit ....ry U should be m.
~
::;-
AR3
LAC
~.
LARP
CNFP
LRU<
>= 0
<0
FIR
~
::t...
ESTlMTE TI SIGNN. Y
is'
So
So
~
. text
= .,00
(JCI~
~=
="n
tD
~E;
=::tD
00 ~.
~~
N="
=00
n
....
N(JCI
UI=
00
s::to
::...
~.
for k=O.l,2, 63
olkl olk) + ulxln-k) if tl,) )= 0.0
olk) olk) - Ulxln-k) if 01,) ( 0.0
Where
::::~
WI'
tv
<::>
~
STF
-= 0.01.
.set
et
ASH
ildilpfltr.int l
b4
0.01
SEUtS
.Sft
begin
LDI
UI'
LDI
LDI
UF
RPTS
~
~
..
<::>
a
<::>
input:
STF
STF
LDI
LDI
UF
UF
order , 8K
txn..oddr
lxn..lddr.ARO
lIon...ddr.MI
O.O.RO
order-t
RO. tMO++lllI
RO.1M1++11l1
liruddr,AR6
lout..a.ddr ,Nfl
,xll'O
; .11 0
; Set .pointer for input ports
; Set pointer for output ports
".R4
;R4=.u
".R5
_.R7
t+ARl>lll R6
R6.1MO
IORJ
tFtF3
LOt
RPTB
1f'YF3
AOOF3
STF
If'VF3
.. ADW3
BD
STF
ADIF3
STF
I
R2. tAR7
R7,t+M7U)
-31.R7
,
R4.R7.R5
,
offtRQ++CUJ.,R5,Rl;
order-3, Re
;
SEUtS
xn
Mn
.usect
.useet
"bufftr-,order
cotffs"lordfr
iLaddr
.useet
yus",1
out-ddr
. used
.used
"vars'''.
xJ\_addr
Im_addr
u
Get Signltln)]
R5 =S[tln)] U
Rl = S[e(n)) " U .. xCn)
Initialize reptit counter
00 i O. N-3
Rl S[tln)] U I xln-i-[)
R2 oHn) + S[tln)] U I xln-j)
oHn+[) oiln) + S[eln)]lulxln-j)
For i = N - 2
tMO++I1lI.R5.Rl;
IMI.RI.R2
;
R2.1M1++11l%
,
1MO.R5.RI
,
IMI.RI.R2
input
; Delay brancb
R2,tAR1++(1)1
; lIIiln+U = .itn} + S[.Cn)]tut')(Cn-i)
IMI.RI.R2
R2.1M1++11l%
, Update ).. t 0
IEFIIE COISTANTS
~
tfj
N
>.1-3
Q
rJ
:I. =
r ;:g
vars,'
vlrs,.
virs",l
tIl
~ ~
til
(lei
....
..,
53-
t/.}
==
==
1-3 ..,
;.
~ ~
~
00
tc>
~
N=-00=:
(is
==
(".N ~.
I
tr1
a
.,
; Input xCn)
.used
,used
. sect
.lIIord
word
word
0804002h
-.lIIord
l1li1
00
,R5'"
cinit
UF
II UF
STF
....
fllfHfltHHHfffffHHflfHHfIHHHfIHHf
tU
tv
R2.R7
HfHHlfHHffHfffHHHfHHHHfHflKlHf
order
SUBf
.copy
>
"C
"C
; yIn) =oll.xll
f IRelucit last fesult
tHHfHfHffHfHfffHHHtHHfHlHHHHHfffH
....
So
~
10
=64 and au
Rl.R2.R211U
Rl,R2
Q
v,
:: STF
RPTS
tMO++IIlI.1M1++IIlI.RI
ord,,-2
tMO++lIll.1M1++1Il%.RI
II'YF3
0.0.R2 II
;; ADW3
ADIF
; R2
=0.0
UF
63
So
So
~
_3
A)gorilh,"
~.
; bput dCn)
.float
.end
.,
",cinit"
5, iru.ddr
08040(l()h
.u
'TSS25'
.titl.
IHHHfHtlllllllllllllllllHHHffHlftHHfHHlfHHlHtHfflfHf
1):
.useet
pvueters.l
U:
ERRF:
ustet
useet
paruetfrs ,1
,aruettl's- ,I
ffUHfIfHUHfHfffflffHffHlHf
UIIIP
"
!it
~
..,c
~
~
Q.
API
SET !P 11 POINTERS
lARK
l.RI.K
lRlK
ARI.ORIEl-!
AR2.111
ARJ.XN+I
Set up counter
Point to the coefficients
Point to the dila supJe
ERR
OOJERI
PAGEO'
.equ.
.equ
!PIlATE 11 IoEIGHTS
ADAPT
64
.usect
.usect
.usect
buffer .0UR-1
buffer ,1
coeffs".(JUER
.usect
.useet
.ustd
api.rueters 11
pitueters ,1
-"rueters,1
LAC
1-, O,M2
ACe = Xln-k)
lOR
ERR
ERRF
IORK
111.15
ADD
SACH
1,15
Upd.te Wlkl
SACL
LAC
FINISH
BANZ
.tnd
..... . . =
ERRF
".I.ARI
ADIIPT ..... ARJ
="tIl
=~
....
= 00
~~
~
til
.....
~~
1-3"1
HfIIHIHflIHfHfHHIHflHIHHIIHIHfIHIHH
IEFIIE PARAITERS
>~
~1-3
S; "1
CICI
/G
So
<1>
!x.15
ARJ.XN
ORDER-I
IoN+OfdOOb ....
CN'D
LAC
l.RI.K
SACH
=0.01.
Initial condition:
~.
I!ACIl
....=
ARJ
If>\')(
RPTK
FIR
,pplication.
IU
)= 0
<0
Note: This source progru is the generic version; 110 configuration hiS
not been set up. User has to aodify the Hin routine for specific
So
<1>
CN'P
For k = 0.1.2 63
lII(k) = w(k) + u if e(nlfx(n-kl
wlk) =1110:1 - u iF e{n)~(n-Ic)
ESTiIlATE 11 SIGNAl. Y
I
s.So
text
63
yIn I = 5U1 .lkl",ln-kl k=O.1.2 63
k=O
:g>
ft.,fHfHfIIH.tHtHHfHHHHH
~~
OO::;;!
~
N ....
....
==-
(100
N ....
fJlCICI
=
....
=
I
00
CICI
00
fHHHfHlIHffHIHHHtHIHHHftHfflHHffHffHHfHtHH
g"
y(n)
~
~
~.
...,,.. 11ft
"'
~
N
9...
<
0.0
UIF
ASH
=M and .u =0.01.
XOR3
LUI
Ii'TB
.lHllHfHHHlIIIIIIIIII I.IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIH
order
copy
,Sft
ai.ckpf1tr. iDt'
64
..
,set
0.01
text
.s.t
LUI
LII'
LUI
LUI
UIF
UIF
UIF
UIF
begin
So
"'
IIPTS
STF
Ii STF
~
N
C
UIF
Ii STF
_'IS
order,.
l>auddr
I>auddr,lIRO
""'-oddr,MI
I.,RO
;
;
;
;
u,
",RS
O.O,RO
; RO
order-l
lin_ldclr,M6
h.t...ddr,M7
UIF
_,R7
_U),R6
R6,eIIRO
LIIF
II STF
ASH
lID
Set
circulir buffer
s.t dAti pige
stt p.inter for x(]
Set pointer for !f(]
;RO=IIU
; R4=1U
RO,IAAQ++(lJX
RO,IMI++(lJX
XORJ
AIlDF3
STF
-3I,R7
RO,R7,RS
IAAQ++(l)X,R6
-3I,R6
RS,R6,R4
IMI,R4,R3
:g
~
~
R7
RS
=Signle(nll
=Sign[e(n)l
I-
R6 = x(nl
R6 = Sign[x(n-Ul
R4 =Signlx(n-illeSignl.(nll
R3 =IIIHn) + R4
;RS=.u
Input d(nl
Input xC D)
Insert xen) to buffer
II'Yf3
IAAQ++U IX, R6
R3,IMI++(l)X
-31,R6
RS,R6,R4
IMI,R4,R3
eIIRO,R6
R3,IMI++UIX
-3I,R6
input
RS,R6,R4
IMI,R4,R3
R3, eARI++( 111
N-3
Update oN-2(n+1I
Get the sign of dati
Delay brinch
Decide the sign of u
Coop.t. oN-l(n+1I
Store list ,,(n+l)
.,
-=
e
.... 11:1
="t'I.l
~
('t)
O~
....t'I.l
11:1
Ji~
~~
~=
a::~
....
....
'J).~
~
N-
=="
.useet
'buffer',ordtr
r':l'J).
.usect
.useet
.useet
.useet
used
.usect
sect
'eotHs' ,order
vats.,1
'vars',l
'Yl.rs,1
=~
irt..addr
ouLaddr
xl'I-i.ddr
u
cinit
!ford
lIIord
=0.0
IAAQ++UlX,IMI++(lJX,RI
=0,
riQ~
xn
...rd
; R2
Do i
>~
IiII'I
Ial-i.ddr
O.O,R2
SSUIS
=0.0
xll =0
oil = 0
s.t pointer for input ports
Set pointer for oatput ports
input:
UIF
order-3,RC
IEFIIoE caeTANTS
ASH
XORJ
ADIIF3
SSUtS
",R4
LDI
LDI
Ii UIF
STF
R2,R7
R2,<M7
R7,_7(l)
ASH
XORJ
>= 0.0
ADIF.l
;;"!
So
So
SUBF
STF
II STF
for k=O,1,2., 63
o(tl = oCt) + ., if x(n-(cllt(n)
1iI(k) ;; .. Ck} - u, if xCriJftCn)
I,
ordtr-2
COtPUTE ERROR SIGfW. .(nl AND IlJTPUT y(nl AND .(nl SIGfW.S
63
StII .. (U~ln-k) PO,1,2, ,63
PO
s.
II'Yf3
II ADIF.l
ADIIF
Algor-jth.:
is
R1'TS
.tnd
vars.,1
-Yf.rs-,1
-.cinUS,iruddr
O804OOOh
OS04OO2h
01'4
xn
.lford
.float
IIIn
.u
'J).
t.
title
~Tl25~
fH*H+f.H+tHH+ffHHHHtfffHf .....fHHHHHHHHftHtffHHHf
u:
.USfct
ERRF:
.used
-c>-
pirueters, 1
Rpuuehrs,1
fffffHlHHHIffflflHffHff+ff+H
"'CI
("t)
"'-tfHffHfIHffflfHlfHHHHHf
.-
Algorithl:
Q..
~.
yin)
= SltI .Ikilxln-k)
eel'll
= dlnl
k=O
'"G
ff~
"'hue
'
Iff
~.
:31
~
tv
..."
...
<:l
IIMfdOOh....
~-1
'-EG
AD()l
SACH
IlIDER:
LEAKY:
PAGEO:
,equ
ACe =- Vln)
D '
ERR
, ERRln) = Din) - Yin)
lPDATE TI IEIGHTS
.equ
.equ
AMOT
II
S;
= :=;
lARK
MI,ORDER-l
; Set up counter
LRLK
AA2.~
LRLK
AR3, XN+l
LT
I'I'V
ERRF
.... AR2
ZALR
I,M3
rFYA
+-,M2
SUB
f,~
coeffs",ORlER
SAO-!
I+,O,ARI
AlW'T ..... AR2
BAN!
ERR:
; - '"l
-buffer ,I
():
(JQ
....
-buffer\auR-l
tv
'"l
OPE, IS
ERIIF
.used
FINISH
til
ADD
SACH
.unct
.uud
pi.raeters ,I
puHfters ,I
puUtttrs ,I
"pt,rilltters ,I
ro
rJJ.
XO:
.usect
.used
.usect
.used
, T = ERRln)
, p = U ERRln)
IN:
WN:
ERR
U
LT
I'I'Y
b4
7
=
~
~~
DEFII PIlRAlTERS
~
C
AR3,XN
RPTK
I1IICll
POC
D:
V:
ac
L.RI..J(
~
......
~TI~
HfffHfHffHHHfftHHHHHfHHHftfHfHHfH
it
~
0
CfE,15
~
SACH
CWD
1?
FIR
Initial condition:
U Pft status bit should be equil to 01.
21 SXI'! status bit should be set to 1.
3) The current If (data Iflory pige pointer) should be pige O.
So:.
k~.1.2 63
Note: nis source progl'u is tl'tt generic version; JlO configurltion has
not been set up. User hu to lodify the Rio routine for sped fie
a.pplication.
~
::....
~
- yin)
is
~
CHFP
I'PYK
lAC
k=O.1.2..... b3
end
, P = U ERRln) I Xln-k)
; Load ~ lIIith A<k,n) &: round
: WO::,n+1) = "'(k,n} + P
: p = U ERfHn) f X(n-kl
: ACe = R I W(I::,n) + P
; Store W(k,n t 1)
Cl=-
N
tJI ~
to
~
~
~
~
~
~
00
>
riQ'
C
'"l
~
:;
:?
'i::j
;:
~
SUBF
b3
fin)
= din)
!}
lillie)
= r*wlkl
~.
1a
<S
s..
'"
~
N
0
=64,
=0.995
and
begin
...
s..
'"
~
~
N
"
.hxt
.set
LOI
LIP
LOI
LOI
LOI
LDF
RPTS
STF
STF
LOI
LOI
ordfr,BK
bn_addrl
txn-iddr, ARO
hln_addr, ARt
ir _addr ,M2
O.O,RO
order-l
RO, 'ARO++llIX
RO,tARlHllll
t!:in_addr ,ARb
@ouLaddr,M7
'ARb,R7
.+ARbill ,Rb
Rb, tARO
; Input din)
; Input x(n)
; Insert x(n) to buffer
;
;
;
;
,
Set
Set
Set
Set
data page
pointer for x[]
pointer for 'II[)
pointer for I'
RO = 0.0
,x[J=O
, .u = 0
; Set pointer for input ports
; Set pointer for output ports
input:
LIF
I I LDF
STF
= 0.01.
LUIS
V,
N
0\
IU
.copy
"a.dapfltr.int"
fffHHlfHffHfflffHlffffHHfHf,*Hfflfflf
PERFIHI ADAPTIVE FILTER
fHfHHHlllfffHHHfHffllfflfHlfflfllHlf
order
. set
64
lIIu_leaky
.Sft
0.01005
; au I leaky
leaky
.set
0.995
<;)
00
tl'YF
tl'YF3
tl'YF3
" ADIF3
LOI
RPTB
tl'YF3
I I AOIF3
tl'YF3
" STF
tl'VF3
" ADIF3
tl'YF3
" STF
iO
tl'VF3
ADDF3
"
tl'VF3
" STF
STF
IHHHHHlfHIHfffffffHIHIHHflHHlffHHIH
, ylnl = w[J.x[]
: include list result
>
"'0
'0
R2,R7
R2, 'AR7
R7,t+AR7111
=
.....
~
~
- yin)
'"2l
STF
II STF
<Q.,
:....
RI,R2,R2
RI,R2
COMPUTE ERROO SIGNI<. .Inl AND OOTPUT ylnl AND .Inl SIGNI<.S
AlgorithD:
...-.is
;:;:-
I I ADIF3
ADDF
LIF
0.0,R2
; R2 = 0.0
tl'VF3
RPTS
tl'YF3
@u_r,R7
; R7
_IlIX,R7,RI ; Rl
.1IROt+l1lX,R7,Rl ; Rt
tARl,Rl,R2
; R2
order-4,RC
LUIS
'AR2,R2,RO
t+AR1I11,RI,R2
tAROt+! 114, R7, Rl
RO, fARt ++( lIX
'AR2,R2,RO
HM1(U,Rl,R2
tARO,R7,RI
RO,'AR1++11II
input
tAR2,R2,RO
<+AR11l1,Rl,R2
'AR2,R2,RO
RO,tARl++1l1%
RO,fARl++(l)X
1l:F1J COOSTANTS
xn
'"in_addr
ouLaddr
xn_addr
IIIn_addr
'-'
r
r_addr
cinit
.usect
.usect
.usect
.used
.used
. used
.usect
.lJsect
.used
.sect
.word
. ord
.ord
.ord
.word
.float
. float
.word
.end
buffer",ordu
coeffs",order
vars",l
N vars ',l
vars,1
virs",l
vars",l
virs,1
'vars",1
. cinit"
7,in_addr
II8II4OOOh
0S040II2h
xn
.n
au_leaky
leaky
C".l
N
=tlnllu/r
= e{n)tulx(nl/r
= e(nlfu*xln-ll/r
=-.0(0) t eln)fulx(nl!t
; Initialize repeat counter
; Do i = 0, N-4
; RO = rfwi(n) t e(nJtufx(n-i)
; R2 = wi+1(n) .. elnlfulxln-i-1)/r
; Rt = eln)fulxln-i-2)/r
; store .i In+l)
; RO = rftM-3(n) + eln)fufx(n-N+3)
; R2 = ...2In) + e(n)fufx(n-H+2)/r
; RI =fln)fulx(n--H+UIr
; Store ~3{n+J)
; Delay branch
; RO = rltili(n) + e(n)t-ufxln-N+2)
; R2 = IIIN-Un) + e(n)lufx(n--N+lI/r
; RO = rf"i(n) + e(n)lufx(n-N+1l
; Stort ,,*"2(n+1)
; Update last .,
--3
""l
=
CIl
d~
CIl
'"l
= -~
.... CIl
(JQ
rJ1
.....
::r .....
~ ""l
--3~
~=
rJ1~
id~
=
..
n
.....
(.H::r
=~
~
=
~
rJ1
->....
(JQ
""I
.....
::r
9
'w.s'
.titl.
tHHfffIHIHffHfffHUnHHIHtflttHHH.u...nftffUtHUffffH
text
lARP
SAA
SAA
SAA
CNFP
/tPYI(
UIS
RPTK
0
OlE, 15
M3.IN
(lUEl-I
MCD
~fdOOh.l-
LAC
11-1
yin} = SU1 .lk}IXln-k} kOO.I,2,oo.,N-I
kOO
LRlJ(
FIR
'G
::!
~
tin) = din)
~ y(n)~
IIIlkJ = wlkJ
g.
;:s
::...
~
~
p.s.
'HfHfffHfttttH+'HunIHftHfHHHHfHftHH
Q
v,
a
c
ADAPT
l.ARI(
LRI.J(
LRlJ(
SACtI
LT
/tPY
Pri::
ADD
S~
S~
SACtI
BANZ
UIS,IlRlER,U.D.M. Y.ERR.IN.1oN
SA\'f2:
SAVE3:
ERRf'
.UStct
.usect
.USfct
.usect
Plruttus,l
~rueters, I
plrUtters , 1
Rptrueters , 1
fHtfHttHtfHfHHf+HHHtHfHf
ESTl11ATE Tl
SI~
....=
~
t"'I.==
~
~~
~
, ACe = - Yin}
D
>9
-C'"
IJQ-
~OO
ERR
, T =ERRln)
, P = U < ERRln}
=-=
9 ~
OlE, IS
ERRf
0[11
ARt,ORIEl-!
AR2,1oN
M3.IN+I
ERRf
; Set up counter
f~,AR2
<,M3
... ,AR2
n,O,ARl
ADAPT ..... AR2
S.
........
==
IJQ
..... 0
=-~
~ ~
~""I
~=
OO~
~-<
N~
Q""I
LAR
LAR
LAR
LT
II'Y
ZILR
II'YA
Q..
00[11
Ll'DATE Tl IoEIGHTS
Initial conditions:
1) Ottl. Hlory M should be equi) to 1.
21 Diti It.ort U should bt equa.l to ttJ (QIS forlNtl.
3) Pt1 status bit should be equal to 01.
41 SIt'I sh,tu5 bit should be set to logic 1.
5) 0'hI stitus bit shourd be set to 1.
6) Tht current DP (dlta ItRiory pig'. pointer) should bt plge O.
~.
.,
; Estiaate Yin)
; Configure SO u aita, ory
Pl'ri::
SACH
ERR
"'CI
"'CI
; Reput N tiltS
af'D
16
ADIIl
SACH
>
Note: This subroutine perforls Adaptive Fi lter using the utS Algoritha.
There ire SOM initial conditions to Htt before cilling it.
<::>
;
;
;
;
;
;
;
;
COIIPUTE Tl ERRIll
is
M3
ARI.SAIIOI
AR2.SA'1f2
M3.SAllC:3
FINISH RET
.end
ARI.SA\I
AR2,SA'1f2
M3.SAVE3
n~
N-
til 00
.....
"'I
=
.....
=
!")
""I
.........~
=-
is
..
>
;~
~
-
~'< ~-
..........
~~ h~
265
,.idth
132
';;l
!a
g'
~
~
~'
~
;;:;
;;
:
So
H**HfffHff*f+HHHftHffHHHffflofHHHHflfHfHHHHH
STAClCSIZE .set
FP
.set
RESET
sect
.word
stack
stacLaddr
ini Laddr
stack
UP
LDI
<:>
....
Cll'1
So
LDI
BZD
LDI
LDI
SUBI
BEQ
c:>
a
c:>
SI',FP
IIO AUTOINITJALIZATJIJI
Q
v.
; Address of stack
; Address of init tables
do_init:
iniLi.ddr
tin; Laddr ,ARO
-I,ARO
done
_,RI
done
_,ARI
_,RO
I,RI
>
"'0
"'0
t'D
=
....
~
begin
.end
.ffi
a:
~
.word
.liIord
stacLa.ddr
@sh.cLiddr,SP
_,RO
I,RI
cinit
_,RO
done:
BR
RO,tARI++
RO,RI
do_init
_,AR
rJ1
vectors
adip_ini t
.useet
,text
LDI
LDI
c:>
LJIP
40h
M3
STI
:: LDI
LDI
BNZD
LDI
LDI
SUBI
fH-IfHffHI-H++HHfffftHHfHffHHfHfHHIHHH+HHHtff
=
=
(1
W
>
~
~
'S.
....
<
('D
~
....
Get page of stored address
LOid the i.ddress into SP
And into FP too
=-
('D
"1
-=
9"
....
....
e:..
....
IS
.o...
~
(JCl
RPTS
Rl
; Block copy
"1
:::to
el
= SUI1wlkltx(n-kl
yIn)
tIn)
= din)
111(1;:)
~.
Where
'"i::l
k=O,l,2, .. ,N-l
= .. 00:)
IH:
- yin)
RPTB
= Nand
IIU
= 0.01.
Initial condition:
;;;
;t
:
So
Chen, Chein-Chung
~rctl,
1989
.global
L/'tS30,u,d,y,e,order
U*lfffffffUUUfflfffl**IIHfHHI**flfHfHtffff
fHHHflHfflffffffl**HffffHfHHfHffHffffHff
. text
.set
PUSH
PUSI'
PUSIF
UlS30
el
....
So
'"
PUSH
PUSI'
PIP
PlPF
POPF
POP
Cl
a
:=
"
=fin)
_(IIX,RJ,RI
= tin) f u f xln)
lorder ,Re
Initialize repeat counter
I,Re
UIS
; Do i = 0, N-3
1ARO++IIIX,R3,RI ; Rl = tIn) f U f xln-i-li
; R2 = ~i(nl + tin) I u * xln-il
'ARI,RI,R2
R2,fARl++(1J~
; ~i(nt1) =IIIHn) + tin) I U f xln-il
IARO;RJ,RI
; for i =N - 2
tARl,RI,R2
R2, 1AR1++(IIX
; lIIi(n+1) =SjilnJ + eln) f u .. xln-i)
tARl,RI,R2
R2,tARl++CIIX
; Update last til
RJ
RJ
R2
Rl
Rl
s;;o
:=
.&;:..
t""I
~~
00'"
~
>5!
-C'"
(JQ-
~
00
_0
-=:
=-C'"
5!
""l
(JQ
dO
'" S.So
So
-0
=-~
~
~~
00'"
~-<
N~
Q""l
, RJ
= 0.0
O.O,RJ
If'VF3
_Ill!, tARl++llIX,RI
@Order
'ARO++IIIX, tARl++IIIX,RI
RI,R3,RJ
, y(nl = o[J.x[J
RI,R3
; Include list result
If'VF3
AD1F3
ADDF
R3
Rl
~""l
Rl
Rl
R2
R3
R3
1.DF
RPTS
.end
IU,R3
POPF
RETS
UIS
If'VF3
" ADlIF3
STF
If'VF3
:: AD1F3
STF
AD1F3
STF
UfffHfHfffHffHfnffHfffffHfffHlfffffHHHf
>
"t:l
"t:l
If'VF
If'VF3
!.DI
SUBI
k=O
<Q.,
D
v,
Store- yin)
.Inl = dlnl - ylnl
Store tin)
Q..
N-l
;::
RJ,@y
@d,R3
RJ,@<
Algorith.:
is
'"
STF
SUIIRF
STF
fHfH+HH*******HtHHHH****HHHHHHHH-tH*,*",**HHff
~~
~
Qoo
""l
=:
~
=:
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272
A Collection of Functions
for the TMS320C30
Gary Sitton
Gaslight Software
273
274
Introduction
This report presents a collection of efficient machine language programs for advanced
applications with the TMS320C30. These programs provide basic math and transcendental functions. Other routines include vector functions, FFTs and linear algebra.
Library Overview
The set of programs fall into six categories:
I.
II.
III.
IV.
V.
VI.
xd - indicates that the relative accuracy of the implemented function is x decimal digits.
* - program name prefix stands for M or R.
M - selects the memory based parameter entry point.
R - selectthe register based parameter entry point.
X - indicates the extended precision program
version.
275
II.
A.
IV.
276
-computes
-computes
-computes
-computes
-computes
-computes
-computes
-computes
III.
SIN
COS
EXP
LN
ATAN
SQRT
FPINV
FDIV
SINX
COSX
EXPX
LNX
ATANX
SQRTX
FPINVX
FDlVX
FMULTX
-computes
-computes
-computes
-computes
-computes
-computes
-computes
-computes
-computes
ILOG2
B.
C.
IMULT
IDiV
*CORMULT
B.
*CONMULT
C.
*CBITREV
D.
*FMIEEE
-in-place computation of the complex vector product of two complex arrays using the complex conjugate of the second array.
-in-place computation of the complex vector product of two complex arrays.
-in-place bit reverse permutation on a complex array with separate real and imaginary arrays.
-in-place fast conversion of an IEEE array to a
TMS320C30 array.
A Collection of Functions for the TMS320C30
V.
VI.
E.
*TOIEEE
F.
G.
H.
*VECMULT
*CONMOV
*VECMOV
CFFFT2
B.
CIFFT2
*SOLUTN
B.
*SOLUTNX
-Solves a well conditioned system of linear equations with any number of dependent variable sets.
Uses no (diagonal) pivoting with normal-precision
floating-point math.
-Solves a well conditioned system of linear equations with any number of dependent variable sets.
Uses no (diagonal) pivoting with extendedprecision floating-point math.
277
The extended-precision versions of the programs in this report may be slower than
their normal precision counterparts. When using extended-precision results in RO from
category II programs, note that the results may be stored in memory with or without rounding. A more accurate normal-precision result will generally be obtained by rounding. You
should never round before using an extended-precision result as input to another extendedprecision program unless special circumstances exist. Note that truncation, not rounding,
will occur if an extended-precision register is moved to any 32-bit register or any memory
location. This will generally cause loss of accuracy in the amount of the value of the least
significant bit of the mantissa.
Program Utilization
Since all programs in this collection are intended to be invoked by a CALL instruction, you must have the stack pointer (SP register) appropriately set to an available memory
area, preferably in internal RAM. Programs in categories I and II save and restore the
data page register DP by using the stack area pointed to by SP. Programs in category
III do not alter or use the DP register at all. The programs in categories IV through VI
alter but do not restore the DP register.
All ofthe programs in categories I through III, except for ILOG2, are implemented
as straight line code. You may wish to disable the instruction cache while these programs
are being executing. This will cause no loss .of execution speed and will avoid flushing
out potentially reusable instructions in the cache. It is beneficial to have the cache enabled
when using most of the remaining programs (categories IV through VI) as they generally
contain multi-instruction loops.
Programs in categories IV through VI allow input through externally defined variables
addresses. The .global references indicate these addresses, where the input variable values
and/or addresses are located. The starting address of these memory locations is given by
the external variable $PARAMS. All of the addresses are assumed to be in the same
TMS320C30 memory page as $PARAMS. If this is not the case, the addresses or the
programs should be changed assure that the DP register gets set properly.
Programs in categories IV and VI also allow the use of registers to hold input
parameters. The exact registers to be used are found in the program source listings. When
using the register input entry point, refer to the program using the R prefix on the program name, e.g. RSOLUTN. The memory based parameter input entry uses the M prefix,
e.g. MSOLUTN. The .global references to the R prefix entry points may be deleted if
they are not needed.
278
Polynomial Approximations
The polynomial approximation method is fundamentally very simple. A limited part
of a function is approximated by a polynomial of some order sufficient to obtain the desired
accuracy. The polynomial is generally a series of the form:
n
Pen, x) =
E [a[i]xiJ,
(1)
i=O
where x is the independent variable, n the polynomial order (a fixed integer), and a[i]
is a set of n + I fixed coefficients.
The desired function, say f(x), is then approximated by a particular Pen, x) such that:
f(x) = Pen, x)
(2)
where xl and xu are the limits of the domain of x, and e(x) or e(x)/f(x) is the error function which has been usually minimized in the min-max (equi-ripple) sense. This is done
by selecting an appropriate means of calculating the coefficients a[i].
Various techniques and schemes are used in the selection of:
See Hastings [2] for an excellenttutorial on this numerical methodology. All of the
polynomial approximations used in here were obtained from the National Bureau of Standards reference edited by Abramowitz and Stegun [3].
279
+ h)
g(x)
(3)
where rex, h) is the remainder of the series (which can be assumed to be small), and g'(x)
is the derivative of the function g(x). Leaving off the remainder in (3) we get, in terms
of incremental values of x, the approximation:
to be quadratic, i.e. the error in the approximation at each iteration is proportional to the
square of the error in the previous iteration. Minimally, this requires a sufficiently close
starting value for x[O] and the condition that ig'(x)i > 0 for all iterated values of x.
= lIx[i] - c = 0,
(6)
which is solved when lIx = c or x = lIc. Taking the derivative of (6) and substituting
into (5) and simplifying gives us:
x[i + 1]
x[i][2 - cx[iD,
(7)
280
g(x[iD = x[ij2 - c = 0,
(8)
which is solved when x2 = c or x = sqrt(c). The solution for (8) leads to the classic square
root formula:
x[i+l] = 0.5[c/x[i] + x[iJ},
but this equation uses division. However, the iteration from f(x)
be shown to be:
x[i + 1] = x[iJ[1.5 - c'x[ij2},
(9)
where c' = c/2 = 0.5c. Though (10) needs no division, the final desired result must be
transformed by an extra multiplication by the input c because:
sqrt(c) = c[1/sqrt(c)J.
(11)
Formula (10) will also converge, in the precision doubling fashion of the NewtonRaphson iteration, given a suitable close starting value for x[O] and the use of sufficiently
accurate arithmetic. Note that the extended-precision version routines FPINVX and SQRTX
both use an extra iteration (for a total of 4) to achieve the needed 32-bit accuracy for the
40-bit format.
The initial guess x[O], for the iterations of l!sqrt(c) and 1/c, may be obtained using
an interesting approximation. A TMS320C30 floating-point number c = (1 + m)2e, where
o ~ m < 1 and -127 ~ e ~ 127. The extra 1, added to the fractional mantissa m,
is the implied bit. Then we can write the inverse of cas:
1/c = 1/(1 + m)2- e .
(12)
m)
1 - m/2,
(13)
which is exact at the end points: m = 0 and m = 1. Then the approximation for the
reciprocal would be:
lIc
(1 - ml2)2- e .
(14)
281
It turns out that this approximation can be achieved in a single logical operation.
If you compute the unlikely value of c' = c XOR OFF7FFFFFFFh, you would complement all bits in c except the sign bit. Including the implied bit and taking the effect of
one's complement arithmetic into account results in a final value of:
c'
= [1 +
(1 - m)]2-(e +
1),
(15)
(1 -mI)2- e
(16)
lIc.
c' gives about 3 bits of precision, which is an excellent seed x[O] for the lIc iteration.
Using e/2, you have a start for the lIsqrt(c) iteration as well.
sin(x) = x
1:
[a[2i]x2i]
xe(x) ,
(16)
i=O
where Ixl ~ Pi/2 and Ixe(x)I ~ 2(10- 9). Instead of using another power series for cos(x),
you can use the fact that:
cos(x) = sin(x
(17)
Pi/2).
The series given by (16) is only accurate in the 1st and 4th quadrants, i.e. Ixl ~
Pi/2. Sin(x) in the other two quadrants is found from:
sin(x)
(18)
sin(Pi - x).
The case for x < 0 is expediently handled by using Ix I for all calculations except
for the final multiply by x in (16).
Exponential Functions
The EXP and EXPX (exponential) routines use an approximation (see Section 4.2.45,
p. 71, in [3]). The expansion is of the form
exp(x)
1: [a[i]xi]
e(x),
(19)
i=O
where 0 ~ x ~ In(2) and le(x)1 ~ 2(10- 10). The series for 2Y is found by substituting
y = x/ln(2) since:
exp(x) = exp(ln(2)y) = 2Y.
282
(20)
A Collection of Functions for the TMS320C30
2y =
[b[i]yiJ
+ e(x) ,
(21)
i=O
where b[i] = a[i](ln(2)i). See the coefficients in the EXP routine.
Values of exp(x) for x outside the convergent range are found by two means. First
for x < 0, note the relationship:
exp( -x)
(22)
lIexp(x),
which does require an inverse (see the FPINV and FPINVX routines). For y > 1, let
y = n + f where n = 1, 2, ... and S f < 1. By substituting y in (20), you get
(23)
In(1
+ x) =
[a[i]xiJ
+ e(x) ,
(24)
i=1
where S x S 1 and ie(x)i s 3(10- 8). The expansion for In(y) can be used if the
transformation y = x - I is applied.
Values ofln(x) for x outside the convergent range are found in the following way.
First, make the substitution x = f(2n) for 1 S f < 2 and n = 0, 1, ... ,and then write:
log2(x)
log2(f2n)
+ log2(f),
(25)
where log2(x) is the log base 2 of x. Using the relationship that log2(x) = hi(x)/ln(2),
you get the equation
In(x) = In(f)
+ nln(2).
(26)
Arctangent Functions
The ATAN and ATANX (arc or inverse tangent) routines use the approximation
from section 4.4.49, p. 81 in [3]. The series with only even terms for atan(x)/x is transformed to
8
atan(x) = x
[a[2i]x2iJ
+ xe(x) ,
(27)
i=O
A Collection of Functions for the TMS320C30
283
where -1 ~ x ~ 1 and Ixe(x)I ~ 2(10- 8). Values for atan(x) for x outside the convergent range are obtained by noting the following identity:
atan(x)
(28)
= b(l/c).
(29)
(30)
The last term in (30) is always less than the 32-bit precision in the mantissa of the
final result. Therefore, you need only to compute the first two terms in the product xc.
Also, note that all the indicated products in (30) may be computed using a normal-precision
native TMS320C30 multiply as long as the terms are collected in extended-precision
registers. The additions are also done using the native TMS320C30 add as it is implemented
in extended-precision.
284
(au)(bu)2 32
(31)
where the powers of two indicated are accomplished by shifts. Note that each product
in (31) must be represented as a 32-bit integer. The adds in the sum must be done with
care to facilitate the carry between the two final 32-bit components of the product.
Integer Divide
The IDIV routine is a modified version of the program DIVI in the TMS320C3x
User's Guide [1]. It has been modified to return the absolute value of the remainder of
the integer division. The remainder was originally computed, but was discarded during
the extraction process for the quotient. A few more instructions allow the extraction of
both the quotient and remainder from the result of the SUBC process. The program IDIV
may be used for the computation of the modulo function. The output of IDIV is the pair
[q, Irll = alb, with the property:
o~
r = (a modulo b) < a,
(32)
= bq + r, for positive
285
+-
c1[k]conj(c2[k]), k = 1, ... , n,
(33)
where +- means replaces. Each complex array is assumed to be stored as two separate
arrays, i.e. (c1] = (xl, yl] and (c2] = (x2, y2]. In cartesian complex representation, (33)
becom~s
(xl
iyl)
+-
(xl
iyl)(x2 - iy2) ,
(34)
where i represents the imaginary constant sqrt( - 1). Separating the real and imaginary
parts, we have:
xl
+-
xlx2
+ yly2, yl
+-
ylx2 - y2xl
(35)
This operation can be used for the frequency domain correlation of two FFTs to implement time domain correlation.
On the other hand, the array routine *CONMULT computes the point-by-point complex multiply oftwo complex arrays. If the arrays are cl and c2, and are each oflength
n, then
c1[k]
+-
cl[k](c2[k]), k
1, ... ,n,
(36)
iyl)
+-
(xl
iyl)(x2
iy2).
(37)
+-
xlx2 - yly2, yl
+-
ylx2
y2xl.
(38)
This operation can be useq for the frequency domain convolution of two FFTs to implement digital filtering.
286
Vector Primitives
The array routines *VECMULT, *CONMOV, and *VECMOVare a useful suite
of efficient programs for simple array operations. The first routine, *VECMULT, performs the simple operation x[k] ~ x[k]c which is a scalar-vector multiply useful in uniformly scaling an array by a constant c. You can use this for scaling arrays after an inverse
FFT by choosing c = lin. The next routine, *CONMOV, performs the operation
x[k] ~ c which is useful in filling or initializing any portion of an array to a single constant c. The last routine, *VECMOV performs the simple operation x[k] ~ y[k] , an array
move, and is, therefore, generally useful.
FFT Routines
This category contains the two complementary radix 2 complex FFT programs
CFFFT2 and CIFFI'2. These programs differ from previously available TMS320C30 FFT
programs in that they operate on complex arrays which are stored as two separate and
independent real arrays. Both routines do the FFTs in-place and do no index permutations
or constant scaling (multiplication). Also these programs require only a 3/4 cycle external, pre-computed sine table. As with previous FFT programs, these, too, have a special
multiply-less butterfly loop for the occurrence of unity twiddle or complex rotation factors.
287
The routine CFFFr2 is a DIF radix 2 complex forward FFT program and thus
assumes a normally indexed pair of input arrays. The output array is bit-reverse permuted
and normally must be unscrambled to be of any use (see *CBITREV). The routine CIFFT2
is a DIT radix 2 inverse FFT program and thus assumes a bit-reverse indexed pair of
input arrays. A normally indexed complex frequency spectrum must be bit-reverse scrambled before using CIFFT2 (again, see *CBITREV). On the other hand, the output from
this inverse FFT is in normal indexed order, but lacks the traditional scaling by the factor
of lin. Therefore, back-to-back calls of CFFFT2 and CIFFT2 will return the original
complex array (in proper order) but multiplied by a factor of n. Consult the handbook
by Burrus and Parks [4] for additional FFT algorithm details.
+
+
A[l, 2]x[2]
A[2, 2]x[2]
A[n, 2]x[2]
+ ... +
+ ... +
A[1, n]x[n]
A[2, n]x[n]
= y[1],
=
(39)
y[2],
damental problem in linear algebra, then, is to find the solution vector x. In fact, you
may desire to find the m different solutions to m sets of linear equations which share the
same coefficient matrix A, i.e. Ax[k] = y[k], for k = 1, . . . , m.
288
You can solve the general problem just stated by using *SOLUTN, or with more
accuracy with *SOLUTNX. This is done by constructing a tableau B (table of coefficients)
which is simply the coefficient matrix A (in row major storage format) with the negative
of the y vector(s) appended (:) as m extra columns to A. Thus you would have B = A
: -y, as your problem, where B is a n by n+m matrix and typically m = 1. Thus, for
the common case of m = 1, the input array B can be written as:
A[1, 1], A[1, 2], ... , A[1, n], -y[I],
A[2, 1], A[2, 2], ... , A[2, n], -y[2],
(40)
2.
The maximum absolute value of the elements in A must be approximately unity. This is necessary to assure that no pivot element is encountered which is
smaller in magnitude than 10- 8 for *SOLUTN, and 10- 10 for *SOLUTNX.
This restriction monitors the system condition and assures an adequately accurate solution, but the fmal solution should always be verified by substitution. This is done by inspecting the elements of the error vector e = Ax Y computed by using the solution x, and the original A and y.
289
Summary
This report presented a set of routines that can be used in digital signal processing
applications. The appendix contains the source code of these routines. This source code
can also be obtained from the Texas Instruments Electronic Bulletin Board (713) 274-2323.
If there are comments or corrections, please contact the author of this report:
Mr. Gary Sitton
Gas Light Software
5211 Yarwell
Houston, TX 77096
Tel (713) 729-1257
References
(1)
(2)
(3)
(4)
Burrus, C.S. and Parks, T.W., "DFT/FFT and Convolution Algorithms", John
Wiley and Sons, New York N.Y., 1985.
(5)
Press, W.H., Flannery, B.P., Teukolsy, S.A., and Vettering, W.T., Numerical
Recipes in C - The Art of Scientific Programming, Cambridge University Press, Cambridge England, 1988.
290
Appendix
Program Librar'y
$MATH. ASM
II.
$MATHX.ASM
II 1. $MATH I. ASM
IV.
$VECTOR.ASM
V.
$FFT2.ASM
VI.
$LINALG.ASM
<5'
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<
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<
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fffffHfHUHHHHHfHHffHfHffHffHfHffHffHfHf
.GLOBL SIN
.GLOBL ECOS
INTERNAL CONSTANTS
~
~
B.
Q
.FLOAT 0.636619n2
; 2/PI
COF
.FLOAT
FLOAT
.FLDAT
.FLOAT
.FLOAT
.FLOAT
; CI (PII21
1.570790327
-0.0459640968 ;C3
0.07969260878 ;C5
-0.00468166687 ; C7
0.00016025884 ;C9
-0.000003433338; ell
;OS
ACOF
.IIJRD
COF
..,
CON
So
ACOO
.IIJRD
;OS
.Q.,
~
;OS
~
SHFT
; AIlMESS OF COEFFS.
too
'"
C
Q
C
CON
; ADDRESS OF COOSTS.
TEXT
~
tv
START OF SIN _
SIN:
PUSH
UP
; ROUND X
; R4 {= X
LDF
rf'YF
FIX
FLOAT
SUBF
NEGF
ADDI
AND
TSTB
RO
RO,RI
!NORM.RI
RI,IRO
IRO,R2
R2,RI,RO
RO,R3
I,IRO
3,IRO
2,IRO
R3,RO
@ACON,ARO
HRRO(IROI,RO
RO,R3
@ACOF,ARO
DP
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RO {= :x:
RI {= RND IX:
RI {= Xt2lPI
IRO <= INTEGER GUADRANt Q
R2 {= FLOATING IlUADRANT Q
RO <= X, -I ( X < I
R3 <= -X
lRO <= Q + I
IRO <= TADLE INDEX
LOOK AT 2ND LSS
IF I THEN RO (= -X
ARI -) CONST. TABLE
FINAL IlAPPING, RO <= 1 + C
R3 <= -I
RRO -} CCfFF. TADLE
UNSAVE DP
.DATA
NORM
RO
RO,R4
ECOS:
LDFNZ
LDI
ADDF
NEGF
LDI
POP
::t.
RND
LDF
If'
@ACOF
;SAVEDP
; LOAD DATR PAGE POINTER
rlPYF
RND
RO,RO,R2
R2
; R2 (= X....2
; ROUND X..2
rlPYF
ADDF
*ARO-,R2,Rl
*ARO--,Rl
; RI <= X"2tCl1
; Rl <= C9 + Rl
rfVF
ADDF
R2,Rl
<ARO--,Rl
II'VF
R2,Rl
*ARo--,RI
ADDF
RI
R2,RI
*ARO-,Rl
ROUND BEFORE
Rl {= X"2'(C5 + RIl
Rl <= C3 + RI
AND
rlPVF
RDDF
Rl
R2,Rl
tRRO.RI
ROUND BEFORE
ADDF
RHO
MPVF
;:..
12~
Q
'
~
~
;:::
'
'"
'C'
....
~
~
~
R4,R4
R3,RO
pop
!!UD
R2
R2
RNO
RHO
MPVF
RO
RI
RI,flO
TEST ORIGINAl X
IF X ( 0 THEN RO (= -x
R2 (= RETWN ADDRESS
RETURN (DELAYEDI
RIJLIill BEFORE
ROUND BEFORE
RI (= hlCI + RII
ffffHfftfHfHHfHHHfHffff****HH******fHIHtfHH
PROORAI1: COS
COSINE FUNCTION: RO
(=
COStROI.
*********H"**I*II**I,,**********************************
tv
.GLOBL COS
.GLOBl ECOS
TEXT
PUSH
LDP
DP
; SAVE DP
~ACOF
BRD
RND
ADDF
LDF
ECOS
RO
@SHFT,RO
RO,R4
\0
W
tv
nHfffl**uuun***UHfHftfHfHtHfltfffIHHHffHf
*
*
*
PROGRAN; EXP
WRITTEN BY: ()AAY A. SITTON
GAS LIGHT SOFTWARE
HOUSTON, TEXAS
MARCH 1989.
PUSH
II'
LDP
ffC7
RO
RO,R2
RO,RI
R2,RI
@ENRI1,RI
RI,R3
R3,RO
RO,RI
R3
24,R3
R3
R3
ffC7,ARO
lIP
RND
IGF
LOF
LDFN
II'VF
FIX
FLDAT
SUBF
IGl
LSH
PUSH
POPF
LOI
POP
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
SAVE II'
LOAD DATA PAGE POINTER
ROUND X
R2 <. -x
RI <. x
IF X <0 THEN RI <. IX;
RI <. X IWLNI21
R3 <. I INTEGER IF X
RO <. FLT. PT. I
RI (. FRACTION OF :XI, 0
R3 <. -I
MOVE -I TO EXP.
SAVE AS INT.
R3 (. FLT. PT. 2*'-1
ARO - >CEFF. TABLE
UNSAVE II'
<.
X( I
HHff*********HHH*tfflf***********HfHHIH*********
AND
NPYF
ADDF
.ARO--,RO
; ROUND BEFORE *
; RO (. X+C7
; RO <. Cb + RO
MPVF
ADOF
RI,RO
'ARO-,RO
NPYF
ADDF
RI,RO
'ARO--,RO
; RO (= XHC5 t- RO)
; RO (. (4 + RO
NPYF
ADDF
RI,RO
*ARO-,RO
RND
NPYF
ADDF
RO
RI,RO
.ARD-,RO
; RO
RND
NPYF
ADDF
RO
RI.RO
1AR0--,RO
; ROUND BEFORE
; RO <. l'lC2 + ROI
; RO <. CI + RO
RND
MPYF
RO
RI,RO
; ROUND BEFORE *
; RO <. X*ICI + ROI
RI
.ARQ--, RI, RO
INTERNAl CONSTANTS
;..
DATA
~
~
ENRM
<Q.,
~
;:
C7
.FLOAT
FLOAT
FLOAT
FLOAT
.FLOAT
.FLOAT
.FLOAT
.FLoAT
1.0000000000
-().693147180
0.240226%9
-0.055503654
0.009615978
-0.001328240
0.000147491
-0.000010863
17
.OIJRD
C7
'"l
::to
<::>
;:
...
S~
aa
CO
CI
C2
C3
C4
C5
C6
C7
; ROUND BEFORE *
; RO <. 11(C3 + ROI
(=
C2 + RO
LDF
TEXT
tv
; I/LNI21
;:
'0'">'
FLOAT 1.442695041
BND
ADDF
RND
II'YF
RETS
R2,R2
FPINV
tARO,RO
RO
R3,RO
;
;
;
;
;
TEST ORIGINAl -X
IF -X <0 THEN RO (. Ill, IDaAYEDI
RO (= 2H-X = CO + RO
ROUND BEFORE *
RO <. 2*'-11 + XI
;::::
f**H**HHfHUfHHHHHffH-IHHHH*HH++Hf*HHH
PROORIII1: tR
'"B.
<:l
;:s
.s;,
~
;:s
B.
'0'"....>
S.
'"
PUSH
LOP
PUSIF
*
I
I
*
I
I
(=
POP
ASH
FLOAT
LOF
LDE
tRIRO).
SUBRF
LOF
tlPYF
LOF
LDI
POP
tUfHHtHHHHffUHffHfHHfHfHHffHHffHffHtH
.GLOB!. tR
tv
INTERNAL CONSTANTS
Q
C
DATA
SCALING CDEFFS. FOR LNIl+X)
LNRH
CO
.FLOAT O.693147100b
.FLOAT 1.0000000000
; LN(2)
; CO 11.0)
ca
FLOAT
.FLOAT
FLOAT
FLOAT
.FLOAT
FLOAT
FLOAT
.FLOAT
0.9999964239
-0.4998741238
0.3317991l2S8
-0.2407338084
0.1676540711
-0.0953293897
D. D360B84937
-0.0064535442
ACB
WORD
CB
(=
X ( 1.
; Til' OF (I
; TOP OF C2
;TDP~C3
; TOP Of C4
; TIP ~ C5
; Til' OF CO
;TOP~C7
; TOP Of ca
RO,RO
LOF
RETSLE
SAVE IF
LOAD DATA PAGE POINTER
SAVE AS FLT. PT.
R3 (= INTEGER FORMAT
R3 (= E = SIGNED EXP.
RI (= FLT. PT. E VALUE
R2 {= 1.0
EXP. RO (= 0 II (= X ( 2)
R2 (= X - I 10 (= X ( I)
RO (= tR(2)
RO (= E*tR(2)
R3 (= EILN(2)
ARO -) COEFF. i ABLE
UNSAVE DP
IARO--,RO
; RI
; RO
; RO
tlPYF
ADDF
RI.RO
IARO--,RO
; RO
; RO
HPYF
ADDF
RI,RO
IARO--.RO
; RO
; RO
tlPYF
ADDF
RI.RO
IARO--,RO
; RO
; RD
tlPYF
ADDF
RI.RO
IARoe-.RO
; RO
; RO
RND
HPYF
ADOF
RO
RI.RO
IARo--.RO
; ROUND BEFORE I
; RO (= XI(C3 + RO)
; RO (= C2 + RO
RND
HPYF
ADDF
RO
RI,RO
; ROl*W BEFORE I
; RO (= IIIC2 + RO)
; RO (= CI + RD
BUD
RND
HPYF
ADDF
START OF LN PROGRAM
\0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RND
HPYF
ADDF
POP
LN:
DP
lACS
RO
R3
-24.R3
R3.RI
@CO,R2
R2.RO
RO,R2
@LNRM,RO
Rl.RO
RO,R3
@AC8.ARO
DP
R2,RI
'~RO--,RI,RO
fARO-,RO
(=
(=
(=
(=
(=
(=
(=
(=
(=
(=
(=
RND X
IIC8
C7 + RO
IIIC7 + RO)
CO + RO
lllCO + RO)
C5 + RO
XIIC5 + RO)
C4 + RO
X'(C4 + RO)
C3 + RO
TEXT
Ul
SCALE VARIABlE X
; TEST X
; RETI.IlN NOW IF X (= 0
R2
R2
RO
RI.RO
R3.RO
R2 (= RETURN ADDRESS
RETURN IllOLA YEO)
RIfflI) BEFORE I
RO (= XIICI + RO)
RO (= tRIX) + E'LN(2)
HHHftHHffHHf**fHHfHHHftHHHfHffHffHHHf
<
PROGRAII' ATAN
SCALE VARIABlE X
PUSH
LDP
<
<
<
<
<
<
<
(=
ABSF
SUBF
BLED
RND
RND
lOI
ATAN(RO).
PUSHF
ABSF
ADDF
1),
69.
<
LDF
CALL
R2
SKIP
flO,R3
RO,RI
I,IRO
,
;
,
;
,
NEGF
R3,R3
I,IRO
, R3 (= -X'
, IRO <- -2, (-P1/4)
RI,RI,flO
!AC17,ARO
, flO (= 1><2
, ARO -) COEFF, TABLE
, tmAVE Ill'
.FLOAT -0,7853981035
.FLDAT 0.7853981635
,FLOAT O.OOOOO~
B.
'C.,'">
S,..
CI7
~17
,FLOAT
.FLOAT
.FLOAT
,FLDAT
FLOAT
FLOAT
,FLOAT
.FLOAT
FLOAT
1.0000000000
-0,3333314528
O.lffl355085
-o,1420S89944
0,1065626393
-0.0752896400
0,0429096138
-0,0161057367
0,OO2a662257
WORD
C17
~
N
TEXT
<:::>
<:::>
ATAN'
SUBI
; -PI/4
SKIP'
, PI/4
, ZERO
;Rl<=lX~+l
, RO (= :x: - I
, RO (= <:X: - ll/(lX: + 1)
POPF
WED
RND
RNO
SUBI
;:s
, SAVE RND X
, RI (= IX:
.GLOIll ATAN
,GLOIll FDIV
::...
RI
RO,RI
@CI,RI
R2,RO
FDIV
INTRNAl CONSTANTS
, SAVE Il'
, LOAD DATA PAGE POINTER
, R2 (= IX:
, R2 (- :x: - I
, IF : X: ) I THEN SCALE (DELAYED)
,R3(=RNDX
, RI (= RND X
, lRO (= 0, POST SCALE INDEX
DATA
!AC17
RO,R2
@CI,R2
SKIP
RO,R3
RO,RI
O,IRO
HHHHHUHfH**HfHHfHHHIHHHfHHUfffHfHH
Ill'
, CI
;C3
,CS
; C7
, C9
,W
, C13
, CIS
, CI7
(=
X (= 1.
/PYF
lOI
POP
Ill'
GET ORIGINAl X
IF X ( 0 THEN RO (= -X' (DELAYED)
R3 <= RND X'
RI (= RND X'
lRO <= -I, (PI/4)
RO,RI
>ARO--, Rl, RO
fARO--,RO
, RI (= RND U<2
; RO <= XH2>C17
; RO (= CIS + flO
/PYF
ADOF
RI,RO
fARO--,RO
PlPYF
ADOF
Rl,RO
IARO-,RO
PlPYF
ADDF
RI,RO
fARO-,RO
; RO (= X1f2f(Cll + ROI
, RO (= C9 flO
RND
PlPYF
RO
RI,RO
fARo-,RO
R<X.tID IlEFORE 1
RO (= X"21(C9 RO)
RO <= C7 RO
ADDF
n
~
~
Q.
g'
AND
If'\'F
ADIf
RND
If'YF
AIlIlF
RND
If'VF
::
ADIf
~.
'c>
.,
So
'"
RO
RI,RO
<MO-,RO
; RIX.ND BEmIE 0
; RO <= XH2<1C7 + ROI
;RO<=C5+RO
RO
RI,RO
<MO-,RO
, RIX.ND BEFORE f
, RO <= Xo02f1C5 + ROI
,RO<=eJ+RO
RO
RI,RO
oARO-,RO,RI
, ROONlI IIEFCIIE 0
; RO <= XH20leJ + ROI
;RI<=CI+RO
ffHHHfHfHfHHIHHHHfHHHJHfllffHHH1ffHtH
PROORM. SQRT
o
o
o
o
POP
BUD
R2
R2
RND
If'YF
RI
Rl,RI,RO
o++AROllROI,RO
AIlIlF
o
.0
HfHfHIHIHHHfHfffttHfHfHffHlfHHlHHHHfflf
.GLOIIL SQRT
ac
.DATA
INTERNAl. COOTANTS
OOTi
OOT2
SET
SET
CNST3
OOT4
.FLDAT 1.103553391
. FLDAT O. 780330086
SI1SK
.WORD
0.5
1.5
; ADJUSTED 1.0
; AIUISTED SQRTU121
0FF7FFFFFH
.TEXT
START If
SQRT
Llf
RETSLE
RO,R3
PROORM.
SQRT:
!S
PUSH
DP
SAllE DP
LIP
I!SIlSK
PUSHF
RO
R2
1SIISK,R2
R2,RI
POP
XDR
LDI
00
LDI
LSH
ASH
POSH
f'(ff
LIIE
LIIF
LSH
LIIFIf/
rl'Yf
POP
R2,R4
8,RI
-I,R2
R2
R2
R2,RI
!CNST3,R2
7,R4
@CNST4,R2
R2,RI
lIP
;
;
;
;
;
,
,
,
,
,
,
R4 (= RI
RI (= RI EXP. REI1OI'EIl
R2 (= R2 WITII -E/2 EXP,
SAVE R2 AS INTEGER
R2 (= FLT, PT,
RI (= (H/2)f2ff-E/2
R2 (= 1,1 .. , fOR ODD E
TEST LS8 (f E (AS SIGN)
IF E EVEN R2 (= 0.78 .. ,
RI (= CORRECTED ESTlMTE
lNSAVEIIP
CNSTl, RO
RO
RO
, RO
(=
(=
V/2 TRIH:,
RHO Vl2
I1ARCH 1989.
(=
lIRO
ffHJ.IHHHflfHfffffffHHHHfffffffHHfHHfHHfHf
::t..
~.
~
::s
~
~.
'"
~
..,
So
~
N
C
ac
R2 (= X[O]"2
R2 (= (Vl2) X[O]ff2
R2 (= 1,5 - (VI2) X[O]1I2
RI (= X[1] = no] * (1.5 - (V/2)<x(O]ff2)
rl'Yf
I!PYf
SUBRf
rl'Yf
RI,RI,R2
RO,R2
CNST2,R2
R2,RI
I!PYf
rl'Vf
SUBRf
I!PVf
RI,RI,R2
RO,R2
CNST2,R2
R2,RI
,
;
R2 (= X[1]ff2
R2 (= (VI2) * XCI]ff2
R2 (= 1,5 - (VI2) X[1] ..2
RI (= xm = XCI] (1.5 - (Vl2)*X[lJ1I2)
I'I'VF
I1PYF
SUBRF
I1PYF
RI,RI,R2
RO.R2
CNST2,R2
R2,RI
,
,
;
,
R2 (= X[2]*,2
R2 (= (VI2) f m]"2
R2 (= 1.5 - (VI2) X[2]"2
RI (= X[3] = X[21 * (1,5 - (V/2)*X[2]*,2)
SET
SET
1.0
2.0
!15K
WORD
OFf7fFFFFH
TEXT
RHO
I1PVF
RNIl
I1PYF
SUBRF
RHD
II'Yf
RI
RI,RI,R2
R2
RO,R2
CNST2,R2
R2
R2,RI
;
;
;
,
,
;
ROUND
R2 (=
ROUND
R2 (,
R2 (=
ROUND
RI (=
BEFORE *
H3]*,2
BEFORE
(VI2) f H3]ff2
1.5 - (Vf2) f X[3lff2
BEFORE
X[4] = XC3] (1.5 - (V/2)'X[3]*,2)
R2
R2
R3
RI
RI,R3,RO
R2 (= RETlQlN ADDRESS
RETURN ([lAVED)
ROUND BEFORE ,
ROUND BEFORE
RO = SlIlHV) = V.SlIlTU/V)
OO,RO
TEST F
,RETURHNCIIIFF=O
PUSH
LDP
PUSHF
POP
XOR
PUSH
POPF
POP
lIP
MSK
RO
RI
MSK,RI
RI
RI
OP
;
,
;
;
g
~
Q.
g'
.s;,
~
;:::
Q.
g'
'"
~
...
s..
~
HHHffHHHHlflffUft**ff+fHfHtHH*****"*I**f**U
PROORAII: FDIV
MPVF
SUBRF
MPYF
RI,RO,R4
TWO,R4
R4,RI
, R4 (. F X[O]
, R4 (. 2 - F X[Q]
, RI (. XCIl X[O] 12 - F XCO]I
rlPYF
SUBRF
MPYF
RI,RO,R4
TWO,R4
R4,RI
, R4 (. F xm
, R4 (. 2 - F X[I]
, RI (. X[2] ': XII] 12 - F XlllI
MPYF
SUBRF
RI,RO,R4
TWO,R4
R4,RI
, R4 {= F X[2]
, R4 (. 2 - F X[2]
, RI (. XI3] X[2] 12 - F X[2]1
MPYF
RO,R4
RI,RO
RO,R4
ftH***U**IHfffflnl********fIfIHfHH**UHHU***flf
pop
BUD
SUBRF
MPYF
.GLOBL FDIV
.GLOBL FPINV
~
W
0C
ADIF
RZ
R2
0NE,R4
RO,R4
R4,RI,RO
R2 (. RETlilN ADORtSS
RETlilN (DELAYED I
R4 {= 1 - F Xl3] = EPS
R4 (. X[3] EPS
RO (= XI4] 1X13]HI - 1F<X[3]111 + x[3]
TEXT
START IF FDIV PROGRAM
FDIV:
RND
LOF
CALL
AND
MPYF
RETS
END
:8
R3 (. AND X
Rl (= Y
RO (. l/Y
RO,R3
RI,RO
FPINV
RO
R3,RO
ROiJND BEFDRE
RO (. X
,
RE~
f**H**fffffHfffff"****ffHffHHfffHHffffffIHHlffHHHtffHfff*HHlff
".'HfI*HH+HHfff**fff-lfff-tHfHHf+HHH-fH-HHHff
PROORAI\: SINX
COSX
EXPX
L/iX
ATANX - COMPUTES AN
eo
IHIIHHIfIIHHHfIHIHI**HffffffHlfftHHHHfIHff
.GLDBL SINX
GLOBL ECOSX
OLDBL FMum
;:..
H**,*HIHfffHffflffflff**HHffffH*HfffHlfIfIIHfIHII*****HH*ff*HII*
INTERNAL CONSTANTS
DATA
~
~
~.
.s;,
SHF2
Q.
SHFI
COF
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
WORD
OOOOOOOA3H
00049QFDAH
OOOOOOODIH
OFFDAA2ISH
00OOOO0E3H
OFC2335EOH
OFSE69754H
OF3280B2SH
0E09997B4H
ACOF
WORD
COF
...
s.
'"
~
f:2
tv
0000OOO6FH
OFF22F9S3H
; BOTTOM OF 21PI
; TOP OF 2/PI
;:,
'
'"
'0>
WORD
WORD
; BOTTOM OF CI IPlI2)
; TOP OF CI IPlI2)
; BOTTct1 OF C3
; TOP OF C3
; BOTTct1 OF C5
; TOP OF C5
; TOP OF C7
; TDP OF C9
; TOP OF Cll
; ADORESS OF COEFFS.
CON
ACON
WORD
o
C
TEXT
CON
; ADORESS OF CONSTS.
;:...
~
~
PUSH
LDP
g'
~
;::s
~
g'
'"
~
..,
PUSHf
ABSf
LDf
OR
FIX
RO
00
@NRi1I,RI
I!NRI12,RI
FMULTX
RO,IRO
IRO,RI
RI,RO
RO,R3
I,IRO
3,100
2,IRO
R3,OO
~ON
@ACilN,ARO
++AROIIRO),RO
OO,R3
~Of,ARO
; SAVE ORIGINAL X
;OO(=:X:
; RI (= TOP II' 2/PI
; OR IN BOTTCI1 Of 2/PI
; RO (= a:*2/PI
; IRO (= INTEGER tlUADRANT G
; RI (= FLOATING Gli\DRANT Q
; RO (= X, -I ( X { I
: R3 (= -x
; R2 (= Q + I
; IRO (= TABLE INDEX
; LOOI< AT 2ND LSB
; If I THEN RO (= -x
; LOAD DATA PAGE POINTER
; ARO -) CONST. TABLE
; FINAL MAPPING, RO (= X + C
; R3 (= -x
; ARO -} COEFF, TABLE
LDF
CALL
LDF
RO,RI
FMULTX
RO,RI
; RI (= X
; RO (= XH2
; Rl (= X**2
MPYf
ADDf
*ARO--,RI, RO
*ARO-c,RO
; RO
{=
X**21C11
; RO
{=
C9 + RO
MPYF
ADDf
RI,OO
*ARO--,RO
; RO (= X**2>1C9 + RO)
; 00 (= C7 + 00
~nF
OR
ADDf
RI,RO
*ARO--,R2
*ARo--,R2
R2,RO
00 (= XM2t(C7 + RD)
R2 (= TOP II' C5
OR IN BOTTOM Of C5
RO (= C5 + RO
CALL
LDf
OR
ADDf
FIUTX
*ARO--,R2
*ARO--,R2
R2,RO
R2 (= TOP (f C3
OR IN BOTTOI1 OF C3
00 (= C3 + 00
LDF
o
.-
RO
(=
X**2*(C5 + RO)
FMULTX
*ARO--, R2
*AOO,R2
R2,OO,RI
RO (= XH2*1C3 + 00)
R2 (= TOP (f CI
OR IN BOTTOI1 (f CI
RI(=CI+RO
FLOAT
SUBf
NEGf
ADDI
AND
TSTB
LDFNZ
LDP
LDI
ADDf
NEGF
LDI
oa
; SAVE OP
; LOAD DATA PAOE POINTER
ECOSX:
CALL
tv
OP
@NRi11
So,
~
CAll
LDF
OR
ADDf
SINX:
R3,OO
fMULTX
AS
R3,OO
OP
00 (= X
00 (= HRI = SINIX), (DELAYED>
TEST ORIGINAL X
IF X ( 0 THEN RO (= -x
UNSIIVE OP
...,
13
H*ftHfHfHHfH*H*H*f*****HfHf*****HHH***,****f
**ffHHHHflf****Hf+Hf***************HHfUfHHHH
PflOORAI'\: COSX
PROGRAl1: EXPX
I
I
I
I
I
*HHffflfffHIHHHftHHHffHHHHHHHfffffHfHH
.GLOBL ElPX
GLOiIL FMULTX
.GLOBL FPIN~X
GLOlIL COSI
GLOlIL ECOSl
INTERNAL CONSTANTS
:A.
.TEXT
~.
<Q.,
~
;:::
DATA
SCALING COEFFS. FOR 2""X
COSI:
; SA~ lIP
, LOAD DATA PAGE POINTER
PUSH
LlIP
lIP
_1
II!D
ECOSI
tslFl,RI
tsIF2,RI
RI,RO
LIF
!XI
AIIIF
RO
Rl
III
RO
(=
(=
IN
(=
ENRM2
ENRMI
WORD
WORD
C7
AC7
WORD
""
RETIBI 0CClIiS
FRO'(
'C'
..,
it
~
<::>
Cl
<::>
, IIOTI!l1 OF l/LN(21
: TOP OF I/LNt2I
WORD
WORD
WORD
.WORD
.WORD
.WORD
WORD
.WORD
WORD
WORD
WORD
~
~.
00OOOO029H
0003SAA3BH
OOOOOOOOOH
OOOOOOOOAH
OFFCE8DEBH
00OOOOO6EH
OFD7SFDEDH
OOOOOOO4bH
OFB9CA833H
OF91D8CSbH
OFbDIE7A9H
OF3IAA7D7H
OEFC9BD9CH
C7
TEXT
START OF ElPX PROGrulI1
, CO (1.0)
, BOTIOM OF CI
, TOP OF CI
, BOTTOM OF C2
, TOP OF C2
; BOTI!l1 OF C3
,TOPOFC3
; TOP IF c\
; TOP OF CS
; TOP OF Cb
; TOP OF C7
g
~
~
;:s
;:s
;:s
'"
...
S.
~
ElPI'
BNO
ADDF
itIL VMIAIIlE X
PUSH
UP
II'
un
RO,II3
R3,RI
RI,RO,RI
113
24,113
113
113
IN:7,ARO
;S4M;1I'
; lOAD MTA PAGE POINTER
;R2<=-X
; RI <= X
; IF X <OTIENRI <= IX:
; RI <= Ta> 0' I/LNI21
, m IN BOTTaI 0' I/LNI21
, RO <= X = :x:tLN121
, 113 <= I = INTEGER 0' X
, RI <= FLT. PT. I
, RI <= FROCTIOO 0' :X:, 0 <= X ( I
, 113 <= -I
, Ifl'IE -I TO EXP
, S4M; AS IN!.
; 113 (= FLT. PT. 2....1
, ARO -) COO'F. TABLE
pa>
II'
, LtiSAVE II'
LIF
UfII
LIF
Ol
au
FII
FlOAT
SUIF
IEGI
LSH
PUSH
POPF
1N:7
RO,R2
RO,RI
R2,RO
IBHIl,RI
_,RI
FlU.TX
tztv
If'iF
AllIIF
IARO--,RI,RO
IARO--,RO
, RO (= IIC7
, RO (= C6 + RO
If'YF
AllIIF
RI,RO
<ARO-,RO
, RO (= X'IC6 + ROI
, RO (= a; + RO
If'YF
AllIIF
RI,RO
<MO-,RO
; RO (= XI-{CS + RO)
, RO (= C4 + RO
; RO (= Xf(C4 + RO)
, R4 (= TOP 0' C3
, m IN BOTTOM OF C3
,RO(=eJ+RO
If'YF
LIF
RI,RO
IARO--,R4
fARO-,R4
AllOF
R4,RO
If'YF
LIF
Ol
AllIIF
RI,RO
fARO-,R4
'ARO-,R4
R4,RO
, RO
(=
au
, RO
, R4
(=
AllIIF
Fl!UI.TX
<ARO-,R4
'ARO-,R4
R4,RO
, RO
(=
CI + RO
au
Fl!UI.TX
, RO
(=
IIICI + ROI
LIF
, RO
, R4
(=
{=
, m IN
(=
lI(eJ + ROI
TOP 0' C2
SOTTIli'I OF C2
C2 + RO
X<lC2 + ROI
TOP OF CI
, til IN BOTTOM OF CI
LIF
R2,R2
, TEST ORIGINAL
-x
II'YF
LDI1
RETS
FPINVX
IARO,RO,RI
R3,RI,RO
RI,RO
(IF
tl FPINVX BRANCHI
HHHfHffHftHftHffffffHffHtffff***ffff*ffflffffff*
PIIOGRIIII: LHI
~'UTTEN8Y:
GARY. A.
.WffiI)
CB
TEXT
SlTT~
ACB
1NlERW. ClJj5TANTS
LDF
LDI
lIP
eACS
RO
R3
-24,R3
R3,RI
@C0,R2
R2,RO
RO,R2
@lHR"I.RO
@lIIRI12,RO
FlU.Tl
RO,R3
tACS,AAO
DATA
POP
DP
EV~UATE
PUSH
LDP
PUSlf'
POP
ASH
FLOAT
LDF
EI~_NAIS
.a.ra
m.oa.
llIE
SUBRF
LHI
FlU.Tl
LDF
(Il
~L
~
.
~
~
!::
;:
URI2
URU
po"YIDII~
CO
CS
;:
'"
'C'
....
So
~
~
C
II
f(Il
.IQUJ
:IQUJ
,IQUJ
.IQUJ
.IQUJ
,IQUJ
.IQUJ
.IQUJ
.IQUJ
IIOOOOIIOFFH
i IIOTIOM OF CI
1IFF7FFFC3H
, TIIP OF CI
, IIOTIOM OF C2
,TllPOFC2
; IIOTI~ OF C3
; TIIP OF C3
;_OFC4
;TllPOFC4
; IIOTI~OFC5
; TIIP OF C5
; IIOTI~ OF Cb
,TllPOFCb
, IIOTI~ OF C7
; TIIP OF C7
; TIIPOFCS
000000084H
OFE80107fH
OOOOOOOIl'!ti
0fE29E11fH
00000009711
~13H
00000004IH
III'D2IIIDI2H
0000000E7H
IJ'CIICC3'IH
;IQUJ
.IQUJ
.IQUJ
1fB130187H
,IIIRI
COO'fS.
.FlOAT 1.0
.IQUJ
~
C
, 8OTIOM OF LHI21
, TIIP OF LHI21
0000000F7H
OFF317217H
LDF
~YF
LDF
.IOID
.IOID
000000043H
IF8M:lI?IfH
, TEST X
, RETUfIN IiJW IF I (= 0
OR
ADDF
~YF
LDF
OR
ADDF
~YF
LDF
OR
ADOF
~L
LDF
OR
ADOF
~L
LDF
,
:
,
,
,
,
,
,
,
,
,
,
,
,
,
SAVE lIP
LOAD DATA PAGE POINTER
SAVE AS FLT. PT.
R3 (= INTEGER FORMAT
R3 (= E = SIGNED EIP.
RI (= FLT. PT. E V~UE
R2 (= 1.0
EIP. RO (= 0 11 (= X ( 2)
R2 (= I - I 10 (= X ( 11
RO (= TIIP OF LHI21
(Il IN 8OTIOM OF LHI21
RO (= E'LH121
R3 (= EflNI21
ARO -) COEFF. TABlE
UNSAVE lIP
TRUNCATED SERIES
R2,RI
'ARo-. RI, RO
fARO--,R2
tARO-,R2
R2,RO
, RI (= I
, RO (= x.es
,R2(=TIIPOFC7
, OR IN IIOTIOM OF C7
, RO (= C7 t RO
RI,RO
'ARO--,R2
fARO--.R2
R2,RO
,
,
,
,
RO
R2
OR
RO
RI,RO
'ARQ-,R2
*ARO-,R2
R2,RO
,
,
;
;
RO (= 1.ICb + ROI
R2 (= TOP OF C5
OR IN IIOITOM OF C5
RO (= C5 + RO
FII.JLTX
'ARO--,R2
tARo-,R2
R2,RO
,
,
,
,
RO
R2
OR
RO
FII.JLTX
'ARo-,R2
, RO (= 1.IC4 + ROI
, R2 (= TOP OF C3
(=
(=
IN
(=
(=
(=
IN
(=
1.IC7 + RO)
TIIP OF Cb
IIOITOM OF Co
Cb t RO
XfIC5 + ROI
TIIP OF C4
IIOITOM OF C4
C4 + RO
g
~
B.
;:
B.
'C....'"i'
(II
au.
UF
(II
AIIF
au
UF
III
au
,IIIINIIOTTOIIFCl
,RO(=Cl+RO
AIIF
RETS
PROORAII: ATANX
I
Flll.TX
1IIRO-,R2
1IIRO-,R2
R2,RO
Flll.TX
1IIRO-,R2
1IIRO-,R2
R2,RO
, RO (= XIIC2 + 1101
, R2 (= TIP IF CI
, III IN IIOTTOIIF CI
,RO(=CI+RO
Flll.TX
R3,RO
I
I
I
I
, RO (= LNIXI + EtlNI21
So
'"
HHHtftHHHHtffHftHHHHfHIIHtIHHHHHHHH
1IIRO-,R2
R2,RO
HfltHHHfftffHfHHtHflfHfHftHtHHtfff-HHHHII
; IIET\Rl
~
N
GLOBL ATANX
.GLOBL FItULTX
.GLOBL FDIVX
Cl
INTERNAl. COOSTANTS
.MTA
SCAlING COEFFS. FOR ATANIXI
WORD
.WCIlII
OOOOOOOSDH
OFFB6F0251
WORD
0000000A2H
.WCIlII
OFF49OFMH
OOOOOOOOOH
OSOOOOOOOH
.IIORD
.WCIlII
BOTIon
TIP IF
IIOTIon
TIP OF
SOTTon
TIP OF
IF -P1I4
-P1I4
IF PII4
PII4
OF ZERO
ZERO
.WOOD
.IIIIRD
WORD
.IIORD
WORD
WORD
1lFD4C88E4H
OOOOOOOFFH
OFDEE8038H
000000056li
OFC5A3D83H
.IIORD
000000093H
.WCIlII
OFCE5CEeIIH
OOOOOOOBFH
OF82FCIFDH
.IIORO
WORD
.IIORO
OOOOOOOOOH
000OOOO6EH
0FEII55594H
OOOOOOOD9H
.IIORO
WORD
;
,
;
;
;
;
;
;
;
,
;
;
,
TIP IF
SOTIO"
TIP IF
IIOTTGn
TIP IF
IIOTIDn
TOP IF
IIOTTDn
TIP OF
IIOTIGn
TIP OF
IIOTTDn
TOP OF
CI (1,01
OF Cl
Cl
OF C5
C5
OF C7
C7
OF C9
C9
IF ell
Cll
OF ell
CI3
.1lRD
Cl7
.1IIIlII
OfAFB9IFEH
Of73BD74AH
ACl7
.1IIIlII
Cl7
, TOP OF Cl5
, TIP Of Cl7
UF_
UF
UlI
PUSIF
ABSF
AIIF
UF
au
IP
1AC17
RO,R2
1e1,R2
SKIP
RO,R3
RO,RI
O,IRO
RO
RO,RI
IeI,RI
R2,RO
FDIYX
15'
;:,;
POPF
&D
UF
UF
stili
IEOf
~.
'C'"....>
So
stili
SIClPI
,SAYEIP
, lOA1J OOTA PAGE POINTER
, R2 <= IX;
,R2(=:X:-I
, IF IX: ) I TIN SCALE (InAYEDl
, R3 (= X
, Rl (= X
, lRO (= 0, POST SCALE INDEX
au
UlI
I'U'
SAYE X
Rl (= IX;
Rl <= IX: + I
RO <= IX: - I
RO (= !iX: - lImx: + 11
!lET ORIGINAL X
IF I ( 0 TIN RO <= -I' (InAYEDI
R3 <= X'
Rl <= I'
lRO <= -Z, IPII4J
R4
SKIP
RO,R3
RO,RI
2,IRO
,
,
,
,
,
RO,R3
Z,IRO
, R3 (= -X'
, lRO <= -4, I-P1I4J
RlLTX
1AC17,ARO
IP
, RO <= XH2
, ARO -) COO'F. TABLE
, lNSAI'E IP
II'Yf
,
,
,
,
RO
R2
OR
RO
(= IHZ'ICll + ROl
(= TOP OF C9
IN roTTCft OF C9
(= C9 + RO
FnTX
tARG--,R2
tARO-,R2
RZ,RO
FIIlUI
tARQ--,R2
tARG--,R2
R2,RO
,
,
,
,
1IF
00
ADDF
FIIlI.TX
tARo--,R2
tARO-,R2
R2,RO
, RO (= IHZt(C5 + ROJ
, R2 <= TOP OF C3
, OR IN ronCft OF C3
,RO(=C3+RO
CALL
FI1I.ILTX
; RO
UF
NIIf
IPYF
UF
011
RO,RI
_ _ ,RI,RO
_ _ ,RO
RI,RO
--,Ri
_ _,R2-
CALL
LDF
OR
ADOf
au
lDF
00
ADDF
RO
R2
OR
RO
(= IHZt(C7 + ROJ
(= TOP OF C5
IN roTTOI1 OF C5
(= C5 + RO
(=
XH2f(C3 + RO)
FINISH lP
[3
FnTX
'ARO--,R2
fARG--,R2
R2,RO
CALL
,
,
,
,
_,
<1>
~
tv
c
(= XHZ'ICI3 + ROl
(= TOP Of ell
IN ronOll OF Cll
(= Cll + RO
00
ADIF
;:,;
RO
R2
OR
RO
LDF
!LED
,
,
,
,
au
ABSF
5UBF
;:,;
RI,RO
IARO--,R2
'ARQ--,RZ
RZ,RO
LIP
tl'YF
00
ADIF
SCALE VARIABLE X
, RO (= Cl3 + RO
.TEXT
PUSH
R2,RO
L]f
ATANI'
ADIF
, Rl <- XH2
, RO <= XH2ft17
, RO<=CI5+RO
RO <= XH2tICI5 + ROJ
R2 <= TIP Of Cl3
OR IN _
Of Cl3
ADDF
1IF
au
NOP
fARO-,RO,RI
R3,RO
FIIlI.TX
_!lROJ
,
,
,
,
RI (= Cl + RO
RO (= I (SIGNEDl
RO (= ATANI!Xl = XI(1 + ROl
ARO -) C (0,0, PI/4 III -P1/4J
LDF
00
ADDF
R4
R4
tARO--,RI
tARO,RI
RI,RO
R4 (= RETI.IlN ADIflESS
RETURN IInAYEDJ
Rl (= TOP Of C
OR IN ronCft OF C
RO (= ATIIN!Xl + C
~
~
LSH
ASH
I
I
g'
.:;,
~
;:s
~
~.
I
I
I
I
.GLOIL SllRTX
GLOIIL FIlLTI
1 _ CONSTANTS
~
N
a
o
.DATA
CNSTl
SET
CNST2
CNST3
CNST4
.SET
S/tSI(
.IIlRD
0.5
1.5
.FLOAT 1.103553391
.FlOAT 0.7S033OOSI>
, ADJJSTED 1.0
, ADJUSTED SllRTIlI2)
OFF7FFFFFH
rl'VF
;
;
;
;
;
;
;
,
,
RI (= RI EXP. REIIlVED
R4 (= R4 WITH -E12 EXP.
SAVE R4 AS INTEGER
R4 <= FlT. PT.
RI (= fl-IV2)12H-E12
Ri <= 1.1 ... Fill ODD E
~ LSS OF E lAS SIGH)
IF E EVEN R2 <. O. 7B ...
RI <= COIRECTED ESTJIlATE
CNSTl, RO
R3,RO
, RO
, RO
(=
Vl2 TRIJ'lC.
All PREC.
<= Vl2
=X -
VH-2
=0 ...
RI,RI,R2.
RO,R2
CNST2,R2
R2,RI
R2
R2
R2
RI
rl'VF
rl'VF
SUDRF
rI'VF
RI,RI,R2
RO,R2
CNST2,R2
R2,RI
, Ri <=
~VF
rI'VF
SUDRF
~VF
LDF
CALL
LDF
LDF
LDF
SORTX'
CALL
LDF
RETSLE
RO,R3
<= x[0]H2
<= IV/2) X[OIH2
<= 1.5 - IVl2) x[0]H2
<= XIll = X[OI * 11.5 - IVl2)'X[0]"2)
rl'VF
rI'VF
SUBRF
rl'VF
LDF
.TEXT
SUBRF
LDF
CALL
, R2
, R2
<= XIllH2
<= IVI2) * x[IlH2
,. RI
<=
RI,RI,R2
RO,R2
CNST2,R2
R2,RI
,
,
,
,
R2
R2
R2
RI
(= X12]1I2
(= IVl2) X[2)1I2
<= I.S - (Vl2) x[2]1I2
<= X[3] =X[2) U.5 - (Vl2)1XI2]ff2)
RO,R2
RI,RO
FIt.l.TX
RI,R4
R2,RI
R4,R2
Flt.l.TX
CNST2,RO
R2,RI
FItLlTX
,
,
,
,
,
,
,
,
,
,
R2
RO
RO
R4
RI
R2
RO
RO
RI
RO
(= Vl2
(= x[3)
<= X[3)1I2
(= X13]
<= Vl2
<= x[3]
<= IVl2) f X[3]1I2
<= I.S - (Vl2) x[3)H2
<= X[3]
<= x[4] =X[3] U.S - (Vl2)fX[3)'f2)
IIRD
LDF
PUSH
LDP
PUSHF
I'(P
LSH
8,RI
-1,R4
R4
R4
R4,RI
lCNST3,R2
7,R5
1CNST4,R2
R2,RI
"IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIHHHflllllllllllllllfH
It
::.l
f'(f'F
LD
LDF
LDFI'fj
I
I
'0...
PUSH
lOR
LDI
LDI
no] =SQRTUI2)'U-K/2)f2H-E/2
IlP
ISI1SK
RO
R4
@SltSI<,R4
R4,RI
R4,R5
SAVE II'
LOAD DATA PAOE POINTER
SAVE V AS FlT. PT. V = U+K)f211E
R4 <= v AS INTEGER
R4 (= COll'LEltENT ALL SUT SIGN
RI <= I H1/2)'2"-E
RS <= RI
I'(P
NlP
FMULTX
R3,RI
DP
RO = SIlRTlV)
RI <= v
ltlSAVE IlP
DEAD CYCLE
=VtSllRTIl/V)
IDELAYED)
o00
HftffHHHfffHffHffHH*****HIU*HHHH*****Htflf
PROGRAII: FPINVX
(=
I/RO.
11.IIIII.J.I.tfHHHfHHfHHHHHHHHHfHfHflHH
EXTERNAl. PROORAII
"~.
,DATA
TIll
.SET
SET
I,D
2.0
l15li
.1IIJllJ
0fF7FFFFFH
(J
.TEXT
START IF FPINIIX _
;::
~.
F1'INIIX'
UF
RO,RO
'\)'
...
;:;.
'"
~
~
N
C
ac
; TEST F
; RETlRHDI IF F = 0
ITSZ
Il'
IV'f
RI
lP
I'll'
IIISK
RO
RI
IIISK,RI
RI
RI,RO,R4
TWO,R4
R4,RI
R4
R4
RI
(= F I HO]
<= 2 - F I nOJ
<= X[I] = HO]
12 - F
I1PYF
SUBIIF
I1PYF
RI,RO,R4
TWO,R4
R4,RI
R4
R4
RI
(= F I X[I]
<= 2 - F I XI I]
<= X[2] = X[I] I
12 - F X[I])
MPYF
SUBRF
MPYF
RI,RO,R4
TWO,R4
R4,RI
R4
R4
RI
(= F I X[2]
(= 2 - F I X[2]
<= X[3] = X[2]
12 - F I X[2])
CAll.
SUBRF
CAll.
ADDF
.END
INTERNAl. COOTIINTS
MPYF
SUBRF
I1PVF
RETS
,Gl.O!IL FPINIIX
,GlOII. F19JLTl
::...
SAVEll'
LOAD DATA PAIi: POINTER
SAlE AS FLT. PT, F = I1+H) I 2HE
FETCH lIACl( AS INTEGER
COfLEIIENT E ~ N BUT IflT SIGN BIT
SAlE AS INTEGER, AND BY MGIC ...
RI (= X[OJ = 11-11/2) I 2H-E,
lNSA\E Il'
FrI.IlTX
M,RO
FMlUX
RI,RO
RO
RO
RO
RO
= 1X[3]
<= F I
(=
<=
(=
11 - IF
X[O])
X[3]))) X[3]
Xl3] = I + EPS
I - F X[3] = EPS
Xl3] I EPS
X[4] = 1X[3ltil - IFlm]) + X[3]
; RETURN
_ . FDIYX
'
..s;,
~
::s
~
~.
'&
....
So
'"
HHtHHHfHffl tHHHfHHI**"IHf**HHHfIHHH
: ..... 11111111111111111111111.11111111.
- -
PROGRAII' FlU.TX
WRITTEN BY, GARY A. SITTCW
GAS LIGHT SlfTWARE
IIlJSTON, TEXAS
MARCH 1989.
(=
RO/RI.
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIHtf
I
I
I
I
fHHfHfHfHfIHfHffffHf,**"**HfflfffHltiHtHtIU
.1l.OII. FDIVX
.1l.OII. FPINVX
.1l.OII. FlU.TX
.GLoa. FllULTX
,TEXT
ac
TEXT
FlIULTXI
FDIVX:
ABSF
LDF
LDF
CALL
LDF
IIR
RO,R3
Rl,RO
FPINVX
R3,RI
FlU.TX
ROfRI.
~
tv
(=
R3
Rl
RO
(=
ABSF
I1PVF
(=
I/V
LDF
RI<= X
RO
XOR
(=
(=
XIV
ANON
SUBRF
I1PYF
ADDF
LDF
ANON
SUBRF
Pl'YF
ADDF
IGF
RO,R4
Rl,RO
RI,R7
R4,R7,R6
R4,R5
OFFH,R5
R4,R5
R7,R5
Rb,R5
R7,R6
OFFH,R6
R7,R6
R4,R6
Rb,R5
RS,R6
,
,
,
;
,
,
,
;
,
R4
RO
R7
R6
R5
R5
R5
R5
R5
R6
(=
(=
(=
(=
(=
(=
(=
(=
(=
<=
, Rb (=
, R6
(=
, R6
(=
; RS
(=
(=
, R6
:XA:
SIGN INFO ..
:XB:
AlB
:XA:
A = XA - EAt2H-24
EA12tt-24
BlEAt2H-24
AlB + BtEA'2"-24
:XB:
B = XB - EB'2H-24
EBt2H-24
AtEB*2H-24
:XAtXB: =AlB + (B*EAtA*EB)*2H-24
- :XAIXB:
IN
f5
POP
R4
R4
!IUD
R4
RETtffl (DELAYED)
LDF
LDFN
LDF
RO,RO
Rb,R5
R5,RO
(=
RETURN ADDRESS
w
.....
o
HHHHfftHfHffHHflftHH**ffHfffff:l-HHHffHfHIHHH**HHf**IHHH
IHHHlfHIHHH*******HIHHfHH***HIHHHHHflH
PROGRAi'I:
INPUT RESTRICTlONS: RO ) O.
REGISTERS FOR INPUT: RO.
REGISTERS USED AND RESTORED: SP.
REGISTERS ALTERED: lRO-l AND RO.
REGISTERS FOR OUTPUT: RO.
ROUTINES NEEDED: NONE.
PROGRAM: SI1ATHI.AS/1
INTEGER 132-BITl I1ATH ROUTINES
SI1ATHI.AS/1 CONSISTS Of THE FOLLOWING ROUTINES:
ILOO2'- COIfUTES M= LOO2INl, N=( 2nM FOR USE WITH RAOlX 2 FFT
PROORAIIS.
'1
I1ARCH 1989.
lum
*
*
I
<=
IINTEGERl LOG2IROl.
fffUfHflHHHHHfHHHHHHH*HHHHHHfHHHH
;:...
~.
;::
~
~.
'C....'">
;;.
'"
~
~
ac
LOOP:
LDI
lOI
1,IRO
-l,IRl
; IRO (. I I IN IT. 11
; IRI (. M IINIT. -11
CMPI
IRO,RO
LOOP
1,IRO
1,IRl
100,00
; COMFARE ITO N
; LOOP IF N ) I IDElAYEDl
; I (= 2*1
; M =H + 1
; COMPARE I TO N
IRl,OO
; 00 (= LOO2INl
; RETURN
BOlD
L5H
ADOI
CMPI
LDI
RETS
::...
g
~
~
~.
~
....
So
o
o
o
o.
o
SUBRI
SUBRB
>
OONE'
HHHHfHHHfllllllllllllllfHHHUHfHHfHUfHfff
EXTERNAl. _
NArES
.GLOIL linT
ac~
.lEXT
START
(F
llU.T PROOIW1
IIU.TI
XIIl
ASSI
ASSI
RO,RI,ARO
RO
RI
-16,ARI
ARI,RO,R2
OFFFFH,RO
ARI,RI,R3
OFFFFH,RI
ARI (= -16
R2 (= XI =
RO (= XO =
R3 (= YI =
RI (= YO =
(f(Il
SHIFTSI
UPPER 16 BITS
(F
LOWER 16 BITS OF
UPPER 16 BITS OF
LOWER 16 BITS OF
RO,RI,R4
R3,RO
R2,RI
RO,RI
R2,R3
R4
RO
RI
RI
R3
(=
(=
(=
(=
(=
XO<YO
XO<YI
XIfYO
P2+P3
XI>YI
PI
P2
P3
P4
LDI
LSH
CllPI
RI,R2
16,R2
O,ARO
IlOI
ARI,RI
R4,R2,RO
R3,RI
IF
RI
RO
RI
)=
(=
(=
(=
~
;:
~.
LSH
ADDI
ADDC
1JI.ISl'(Jj.lEXAS
IIAROi 1989.
~
~
BGED
PIaMI. llU.T
R2 (= P2+P3
R2 (= LOIIER 16 BITS OF P2+P3
CHECK THE SIGN OF THE PRODLtT
HETS
O,RO
O,RI
RO
, RI
(=
(=
(F
OPPOSITE SIGN
-110
-WI (WITH B!IlROW)
,RETURN
HHffffHfHllHHHfffH.HffHlfHfffffHtHHHHffU
PROGRM: IDIV
SUBI
LSH
IRO,IRI
IRI,RI
I1ARCH 1989.
IRI
RI,RO
LOI
SUBRI
LSH
NEGI
LSH
SUBRI
LSI!
INPUT RESTRICTIONS: RI != O.
RO,RI
31,IRI
IRl,RO
lRI
IRI,RO
-32,IRI
IRI,RI
RI (= lREI1AINDER, IlOOTlENr:
IRI (= 32 - (IRl+lI
RO {= RO SHIFT LEFT IRI
IRI (= -IRI
RO {= lXi/IVI
IRI (= -(JRI+D
RI (= lREI1AINGERI
tHtHHIIIII.I.I IIIIIIIIIHHHffHftHHfHfHfHfH
EXTERIW. _
NEGI
NAItES
ASH
LOINZ
Cll'1
.1i.OBL IDIV
RO,R3
-31,R2
R3,RO
O,RO
RETS
R3 (= -1Xi/IVI
TEST SIGN BIT
IF SET RO {= -RO
SET STATUS FROII RESULT
RETURN
START IF IDlY _
:t.
12
~
;:;
~.
~
~
;:;
.TEXT
ZERO:
IDlY:
RETS
XOO
ASSI
ASSI
RO,RI,R2
RO
RI
R2
RO
RI
{=
(=
(=
SIGNUIt (RO/Rli
IXI
IVI
0'
i:;
Cll'1
IIIUD
'0'
....
FlOo\T
PIJSIF
p(I'
LSH
oc
FlOo\T
tv
C
LOI
LOI
PIJSIF
p(I'
LSH
RO,RI
ZERQ
RO,R3
R3
IRI
-24,IRI
R3 (= NlRIIAlIZED DIVIDEND
PUSH AS FLOAT
IRI (= INTEGER
IRI (= DIVIDEND EXPfIIENT
RI,R3
R3
IRO
-24,IRO
R3 (= NIlM.IZED DIVISOR
PUSH AS FlOo\T
IRO (= INTEGER
IRO (= DIVISOR EXPONENT
RO,RI
0,00
RI (= lREI1AINDERI
RO (= IlOOTlENT
RETURN
::t..
1IIIIIIIIIIIIIIIIIHHHfffHfHffHffHHHfffHHHfHffflfHffHfffflHHH
ffffl**HfffffUHffHffffflffffltftHlffHHffHffHH+HfH
PROGRAM: tCffil1ULT
t
t
~.
'0'
...,
PROORIIIU '<'{CTal.ASII
<'{CTOO UTILITIES
g.
.s;,
~
;::
~
~
IV
C
ac
FEBRUAAY 1989
->
IHln**fHfHH**fffHnl*'*HHfHl-tnHHHftfffHlfflffl:lH
ARRAY LENGTH N
ADDRESS OF I NPUT
ADDRESS OF I NPUT
ADDRESS OF INPUT
ADDRESS OF Uf'UT
$N
SIAD!
SIAD2
SSAD!
S5AD2
X!
VI
X2
V2
w
w
TEXT
I'ICORItULT:
"""
LOP
LDI
LDI
LDI
LDI
LDI
t-UUHItHIHHH.fHHHfHHltHHHHIHHUHHfIHHHHf
HPARIIS
@SN,Re
HIADI,ARO
HIAD2,ARI
HSADI,AR2
@SSAD2,AR3
PROORAI1: fCOO~lLT
I
I
~PIIJI. T
RCtRtJl.T:
I,Re
;Re(=N-I
RPTB
LOOPI
~YF
fARO, fAR2,RI
fARI, fAR3,R3
lAR2++,fARI,RO
RI,R3,R2
fARO, fAR3++ ,RI
RI,RO,R3
R2,fARO++
R3,-lAR1++
~YF
~YF
::
ADIF
~YF
SUBF
UXPJ: STF
::
STF
~
~
:4.
o
;=::
RETS
; RETlI\N
ENTRY PROTOCOl:
VARIABLES FOR 11f'IJT'
SIAD! -) mOl, SIAD2 -) mOl,
SSADI -) 12[01, SSAD2 -) Y2[0),
$N = N lLENGTH), SPARIIS = DATA PAGE.
INPUT RESTRICTJ~' $N ) O.
REGISTERS ALTERED' Re, DP, ARO-3 AND RO-3.
HHfHHHHfHHHfHH-HfHfHHHHllllllllllllllllllllff
~.
.GlO81.
.GlOBL
.GlO81.
.GlOBL
,GlO81.
;=::
'"
'Cl'
...
s.
'"
~
~
N
C
a
c
ARRAY LENGTH N
ADmESS IF IIf'IJT
ADmESS OF IIf'IJT
ADmESS IF IIf'IJT
ADmESS IF INPUT
$N
SIADI
SIAD2
SSADI
SSAD2
EXTERNAL _
.GlO81. I1CONIU.T
.GlO81. Rrof1I.I.T
START OF _
XI
YI
X2
Y2
NAIS
TEXT
PEI1IllY BASED PARrITER ENTRY
::...
1tC3fU.T:
g
~
~
'
~
;::
~
.
'c'"s>'
HHHnfHHHfHf*H*ftHIHHl-H+HHfHffHHHfHHI
f
UP
I$PMIIS
IlII
IlII
IlII
IlII
IlII
@SH,Re
I$IADI,ARO
I$IAlI2,ARI
HSADI,AR2
1$SAD2,AR3
....
SUBI
I,RC
, RC (= N - I
So
RPTB
If'YF
If'YF
If'YF
SUBF
If'YF
ADDF
STF
STF
LOOP2
tARO, tAR2,Rl
tARI, tAR3, R3
IAR2++,tARI,RQ
R3,RI,R2
tARO, fAR3++ , R1
RI,RQ,R3
R2,tARO++
R3,4AR1++
'"
e:J
N
::
ac
UJ(P2:
"
RETS
, RETURN
PROOlAII: fCBITREV
WRITTEN BY: GAAY A. SITTON
GAS LIGHT SOfTWARE
HOUSTON, TEXAS
MARCH 1m.
f
I
I
RCBITRE~
*
I
*
ENTRY PROTOCOL:
REGISTERS FOR INPUT:
ARO -) XlOl, ARI -) YIOl, RC = N (LENGTH).
INPUT RESTRICTIONS: RC )= 4.
REGISTERS ALTERED: RC, IRO, ARO-3 AND RQ-3.
IHHH*****H-HHIHIHfffHfHfHHHHHHHfHIHHH
ARRAY lENGTH N
ADDRESS OF INPUT X
ADDRESS If INPUT Y
Vt
M<BITREV:
LOP
LDI
lOI
LDI
0 '\
UPARMS
@SN,Re
@SIADI,ARO
@SIAD2,ARI
*lfttltfHHfftftfHHHfHHIH*HnHntHftHIfHHHH
PROGRAM: 'F11IEEE
lOI
RC,IRO
:
3,Re
;
-I,IRO
;
ARO,AR2
;
fAR2++IIRO)B
fARO++
;
ARI,AR3
;
IRO (= N
Re (= N - 3
lRO (= N/2 FOR BIT REVERSE
AR2 -J ARRAY I IBIT REV.)
: INCR. 8RIAR2) (OUTSIDE LOOP)
INCA. ARO (OUTSIDE LOOP)
AR3 -J ARRAY Y (BIT REV.)
~MlEEE
ENTRY PROTOCOL:
VARIABLES Foo INPUT:
SIADI -J 1[0l, SN = N lLENGTH),
SPARMS = DATA PAGE.
INPUT RESTRICTIONS: $N J O.
REGISTERS ALTERED: Re, OP, ARO--I ~ RD-t.
::...
9
~
~
15'
;:;
<Q,
~
;:;
UF
UF
"
II
::
UO'3:
LDF
STF
STF
STF
STF
NP
RETS
LOIJ'3
;
AR2,ARO
;
LOO>3
;
fARl ++
;
'AR3++(!RO)B
'ARO++,RO ;
fAR2,R2
;
fARl,RI
;
fIIR3,R3
;
RO, fAR2
;
R2, f-ARD
;
RI,fAR3
;
R3, fARl
;
fAR2++(!RO)B
R2 (= XIJl
RI (= vm
R3 (= YrJl
x[Jl (= RO
ICll (= R2
YIJl (= Rt
YCll (= R3
; INCA. liR(AR2)
.'
HHHlffH**HHHHHHH-HHHHHfHHfHHffHHHH
; RETURN
t
c
; ARRAY LENGTH N
; ADDRESS OF INPUT X
;:;
'a...'">
Gl.OBL MFMlEEE
GLOBL RFMlEEE
s-o:.
~
f2
N
<::>
a
<::>
WORD
WOOD
WORD
WOOD
WORD
OfFSOOOOOH
OFFOOO()()()!l
07FOOOOOOH
OSOOOOOOOH
OSIOOOOOOH
::....
TAIIA
g
~
HHHfffHfHHfHHfffHffffHHfffHHffHHfHHHfH
MEA
.TEXT
g.
.Q,
~
::s
CTAB
.I0Il)
START OF _
IflllEEE'
UP
"-
~
...
So
'"
N.RC
ISIADI,ARO
RRUEEE.
SUBI
I,RC
ICTAB
ITAIIA,ARI
;RC<=N-I
; lOAD DATA PAGE POINTER
; ARI -) aJNSTANT TABlE
L111
tv
L111
L111
::s
_ . *TOIEEE
<
SASEIl PAIWJER ENTRY
UP
RPTB
POPF
lOOP4
tARO, tARI,OO
tARO,OO
_1111,00
tMo,Rl
lOOP4
_1121,00
00
00
NEGF
00
GLOBl SPARtIS
; RETURN
.GLOBL SN
.GLOBL SIADI
AND
ADDI
L11IZ
L111
BGED
SUBI
PUSH
lOOP4' STF
RETS
RO,fARO++
fHfffHHfHfHHfl-tHl-HfHHffHI-H4Hfff*fffHHfHff
; ARRAY LENGTIl N
; ADDRESS OF INPUT X
....-...J
mOIEEE.
....
00
LOP
LOI
LOI
HPARMS
HN,RC
@$iADI,ARC
**HHftHfHfffffH**HffHfHffHH*HffffHH...HfHHHH
PROGRN1: *VECI1ULT
RC{=N-I
LOAD DATA PAGE POINTER
ARI -) CONSTANT TABLE
I,RC
@CTAB
eTASA,ARI
RPTB
ADDI
LSI!
:
:
,
,
,
,
,
,
,
,
OR
HAR1I3l,RO
RO,<ARO++
LSH
PUSHF
LDP
IlGED
POP
::to.
~
~
~
g'
~
;::
LOOI'5
<MO,RO
HAR1I4l,RO
I,RO
RO
tARO,RI
LOOPS
RO
HAR1!2l,RO
-I,RO
ABSF
LDPI
tHffHHtfffHfHUHfHHfffffHfUHfHHHfffHfHffHfH
UXP5' STI
RETS
, RE1LIiN
.GLOBL IN
GLOBL SCNST
.GLOBL SIADI
I'
;:;.
~
....
GLOBL IIIWI.I.T
,GLOBL RVECI1ULT
tv
[3
C
TEXT
!VECI1ULT:
LOP
LOI
HPARI1S
HN,RC
LDI
UF
KIADI,ARO
KCNST,RO
, ARO -) nOl
,RO(=C
~
;:s
'"'
~.
~
....
RPTS
",YF
STF
So
~
SKIP!: STF
RETS
2,RC
RO,fARO,RI
O,RC
SKIPI
RC
RO,HtARO,RI
RI,>ARO
RI,'ARO
RC(=N-2
RI (= c.no]
CIlIf'ARE RC TO 0
IF RC ( 0 THEN SKIP LIXP
; RETURN
ac
PROGRAM: fCON/lO'l
WRImN BY: GARY A. SITT~
GAS LIGHT SOFTWARE
HOUSTON, TEIAS
FEBRUARY 1989.
R'IECItl.T:
SUBI
"'YF
Cll'I
lilT
HtffHffHfHffffff**fHfftHHfHHIIIIIIIIIIIIIIHHHHH
ffHHfffHfHHHI-HHHfH-tHfHHHffHHffHftHfHHHH
ARRAY LENGTH N
ADDRESS OF CONSTANT C
ADDRESS OF INPUT X
MC~~MOV:
YJ
10
LOP
lDI
WARMS
@IN,RC
LDI
LlF
ISIADI,ARO
IItNST,RO
ARO -) xtoJ
,RO(=C
flfHHHfffftffHfHftHfHffHfffHHHffHfHHHfftHHH
I
PROORAI!' f\l:C/fJV
VECTOR
I1'IE~V
RWftI'i.
SUBI
I,RC
,RC<=N-I
RPTS
STF
RETS
RC
RO, IARO++
~YE:
(N)= Il.
ENTRY PROTOCOL:
VAlUABLES Fill IIf'UT:
$IADI -) I[OJ, $1AD2 -) Y[OJ,
$N = N (LENGTHI, tPARI1S = DATA /'ME.
INPUT RESTR[CTlONS' $N ) O.
REGISTERS ALTERED: ftC, DP, ARO-I, AND RO.
,1m <= C
,RETLIlN
ffftHtHffffttHfHHHfffHHHHHflHHfffll.111111111111
-g'
.GLOB!. tPARI1S
~
~
.GLOB!. $N
.GLOB!. $IADI
.GLOB!. $1AD2
ADDRESS OF IIf'UT I
ADIIRESS IF IIf'IJT Y
.GLOB!. I1'IECIIlII
.GLOB!. RVEOIJII
g.
'0'
.,
START OF _
So
Q
c
.Tm
""
f::J
N
ISPARI1S
m,RC
ISIADI,ARO
LDI
g
~
R
g.
.s;,
~
B.
'C'
...
s-
Ilo
~
c
Q
c
ISIAIl2,1IR1
, IIRI -) YIOI
tHHHfHffffHIIIIIIIIIIIIIIII.lllllllllltHiHHHHHHIIIIIIIIIIIIIIIIIII
RADIX 2
R'iEOIlYI
SUBI
Uf
Cll'I
lILT
2,RC
tMO++,RO
O,RC
Sl(IP2
RC
S1F
RO,tARI++
RO,tARl
Sl(IP2: S1F
RETS
.EIID
tMO++tRO
CFFFT2 -
I.
RPTS
Uf
I RE11JIN
ROOTINfS
IfFT2.ASII CCIISISTS
,RC<=N-2
, RO (= UOI
, ilII'ARE RC TO 0
I IF RC ( 0 TIEN Sl(IP LOOP
(F
TI FIILLII/IM> ROOTINES:
CIlI'l)(
CIFFT2 - COlt'LEX DIT INVERSE RADIX 2 FFT USING SEPARATE REAl lIND
IIVIGINARY ARRAYS lIND 314 CYCl SUE TABLE IlXES tlT ItnUlE
THE liN SCILE FACTOR.
ffffHftfHffHfftfffffHHHtfHHHfffHfHHtHffHfHHfHHlftHfffHtHf
HHUHHftffHHfHfHHHH**HHH**HfHHHfHIIHHHI
PROORAM: CFFFT2
LOI
LSH
LOI
lOI
LSH
lOI
MRCH 1989,
I
I
I
::...
~
OUTER LOOP
I
I
I
I
I
I
I
K (= K + 1
AR() -) XIOI
ARI -) XILI
AR2 -) YIOI
AIl3 -) YILI
SETUP 1ST INNER LOO' REPEAT COONTER,
RC lONE LESS THAN TI lESlRED II
I,AR6
@$IADI,ARO
R7,ARO,ARI
@$IAD2,AR2
R7,AR2,AR3
RS,RC
I,Re
STF
STF
FBLKI
fARO,lARI,RO
fARI,fARO,RI
IAR2,IAR3,R2
tARl, IAR2, R3
RO, tAR0++IIROI
RI,IARI++IIROI
R2,1AR2++IIROI
R3, fAR3++( IRO)
;
;
;
;
;
'
.s;,
.GLOBL S511
GLOBL WARMS
;:;
~'
~
....
$N
$M
SIAOI
SIAD2
,TEXT
CFFFT2:
UI'
ADDI
lOI
ADD!
LDI
ADOI
LOI
SUBI
twES
~
N
FLOOP:
HIIII""III'IIIIIIIIIIIIHflHfHHH-lltHIHHHHfH.Hff
EXTERNAl _
IRI (= N
IRI (= N/4, OFFSET FOR COSIN!:
AR6 (= K IINIT, 01
R7 (= NI
R7 (= N2 IINIT, NI2I
RS (= IE IINIT,I1
lRO,IRI
-2,IRl
O,AR6
IRO,R7
-I,R7
I,RS
!.DI
tSN, lAO
; COMPARE M TO K
; IF K )= " TIN IlET\Rl
J (= 2, IPRE-INCREIlENTEDI
ARO (= I IINIT. II
AR2 (= I IINIT, II
ARS (= SINTABllAl IINIT. IA
2,AR7
I,ARO
I,AR2
@$SINE,AR5
RS,ARS
fARS,R6
AR5,IRI,AR4
@$IADI,ARO
@$IAD2,AR2
R7,ARO,ARI
R7,AR2,AR3
RS,RC
I,Re
RPTB
FBLK2
01
(= IA + IEl
R6 (= SINIXI, IX = 121P1IN)fIAI
AR4 -) COSIXI
ARO -) xm
AR2 -} YIII
ARI -) XILI
AR3 -} YILI
SETUP 2ND INNER LIXJ> REPEAT COONTER.
RC lONE LESS THAN THE lESlRED II
; AR5 -) SINTABlIA
;
;
;
;
;
;
;
;
;:....
SU!iF
g
~
'"Cl
::to
;::!
~
;::!
B.
Cl
;::!
'"
~
....
S<1\
~
~
a
C
:1
5IJBF
II'YF
ADIF
II'YF
STF
SUIIF
II'YF
::
ADDF
II'YF
II
STF
ADIF
FIiLK2' STF
STF
II
::
Cll'I
*MI, <MO, R2
tIIR3,tAR2,RI
R2,Rb,RO
tAR2,tIIR3,R3
RI,*M4,R3
R3, IM2++! lROI
RO,R3,R4
RI,R6,RO
<MO, *MI,R3
R2,<AR4,R3
R3,*MO++IIROI
RO,R3
R3, *MI ++ I lRO I
R4, IAR3++ II RO I
. R7,AR7
,
,
,
,
,
,
,
,
,
,
,
,
,
,
R2 (= XT = XIII - XILI
RI (= YT = Y1I1 - YILI
RO (= XTtSIN AND ...
R3 (= YIII + Y!L1
R3 (= YTtCOS AND ...
YIII (= YIII + YILI, INCR. AIl2
R4 (= COStYT - SINIXT
RO (= SINtYT AND ...
R3 (= XIII + XILI
R3 (= eoslXT AND ...
XIII (= XIII + XILI , INCR. ARO
R3 (= eoslXT + SIN<YT
XILI (= eoslXT + SINIYT, INCR. ARI AND ...
YILI (= eoslYT - SINtXT, INCR. AR3
, COMPARE N2 TO J
IILTD
LOI
LOI
ADDI
FIN1.Cf
AR7,ARO
AR7,AR2
I,AR7
IIRD
LSI!
LOI
LSI!
FLOOP
I,RS
R7,IRO
-I,R7
PROGRAM' CIF'l2
f
I
fIHHHfffHHHfHfltff**fffHHfHIHfHHHflffHfffff
)=
...,
LDI
@.?ARMS
I!$~. IRO
LDI
LSH
LDI
LDI
LDI
LSH
LDI
IRO,IRI
-2,IRI
@$M,ARb
I,R7
IRO,RS
-1,R5
2,IRO
IRI (= N
IRI {= N/4, OFFSET FOR COSINE
ARb (= K lINn. MI
R7 (= N2 IINIT. II
R5 (= N
RS (0 IE IINIT. N/21
IRO (= NI lINn. 21
OUTER LOOP
ILOOP: LDI
ADDI
LDI
ADDI
LDI
SUBI
FIRST
::....
g
~
B.
<Q,
~
;::
B.
Co
'&
..,
S~
RPTB
ADDf
SUBF
ADlF
SUBF
STF
I:
STf
IBLKI: STF
::
STf
CllPI
BEQD
!$lADI,ARO
R7,ARO,ARI
mAD2,AR2
R7,AR2,AR3
RS,RC
I,RC
I~
,
;
;
,
;
,
ARO -) 1101
ARI -) XILI
AR2 -) VIOl
M3 -) VILI
SETUP 1ST INNER LOOP REPEAT COUNTER.
RC lONE LESS mAN THE DESIRED II
"
"
;
,
;
,
;
;
,
;
R3, fM3tt( IRO) ,
@1II,ARb
SKIP
,CCMPAREMTOK
; If K = MTHEN SKIP TWIDDLED LOOP
MPYF
SUBf
MPYF
SUBf
ADDf
SUBF
STF
ADDF
STF
"
ADDF
IBLK2: STF
STF
"
IBLKI
tARO, tARI,RO
tARI, tARO, RI
*AR2, >AR3, R2
fM3, *AR2, R3
RO, tARO++ II RO I
RI,fARI++llROI
R2, tAR2++1 IROI
SKIP:
LDI
LDI
LDI
LDI
IIII.(P' ADDI
LDF
ADDI
ADDI
ADDI
ADDI
ADDI
LDI
SlJBI
2,AR7
I,ARO
1,M2
ISSIt,ARS
,
,
;
,
J {= 2, IPRE-INCREMENTEDI
ARO (= I lINn. 11
AR2 (= I IINIT. 11
ARS (= IA lINn. 01
RS,ARS
tARS,Rb
ARS, IRI, AR4
mADI,ARO
HIAD2,AR2
R7,ARO,ARI
R7,AR2,AR3
RS,RC
I,RC
,
,
,
;
;
;
,
,
,
RPTB
tf'YF
tf'YF
IBLK2
tAR4, tARI,R4
Rb,>AR3,R3
*AR4, fAR3,RO
R3,R4,R2
; RO
; R2
;
;
;
;
R3, fARl H( lRO) ;
;
R2, 'ARO,R3
R3,fAR3t+(IRO) ;
,
R4, .AR2,R4
R3, tAROHI IROI ;
R4,'AR2++IIROI ,
Rb, 'ARI,RI
R2, .ARO,R3
RO,RI,R4
R4,.AR2,R3
(=
(=
COSJ.y(U, AND ..
XT =COS*X(L) - SINfV(U
CMPI
R7,AR7
; CCMPARE N2 TO J
BLTD
LDI
LDI
ADDI
IINW'
AR7,ARO
AR7,AR2
I,AR7
;
;
,
;
SUBI
eMPI
I,ARb
O,ARb
ILOOP
-I,RS
IRO,R7
I,IRO
,K(=K-I
; CCMPARE 0 TO K
, IF K ) 0 TIN LOOP IDELAYEDI
, IE (= IE/2
; N2 (= NI
, NI (= 2INI
BGTD
LSH
LDI
LSH
tv
"
; RETURN
;:...
111 II II III.IIII.llfHUHHHffHHHUHHHHfUHfUHHHHHHHU
_ : $lINALG.ASI1
'
.Q,
iJ
;:
~
~.
'C...>
;;.
~
~
~
N
C
ac
HHHH*******H4HHHIi********HH***HUUIUHHHH
PROGRAM: 'SOLUTN
..
<
<
******fH*****************tii****t************************
W
N
UI
\j)
GLOBL I1S(LUTN
0l0Bl. RSa.UTN
GLDBL FPINY
0'1
CALL
RND
FPINV
RO
; RO (= -liBIK, KI
; ROUND INIJERSE
,GLOBl fIADI
.0l0Bl SIflOI
,OlOIL SNCOl
INTERNlLW6TANTS
ADDI
LDI
RPTB
MPYF
RND
DlOOP: STF
,FlOAT 1,0-8
0,0
.SET
ZERO
_:
; AR7 -) BIK, KI
; RC (= N-K-2
0l00P
RO, f++/IR7 ,R2
R2
R2,tAR7
.DATA
EPSN
AR3,IRO,AR7
ARb,RC
LDI
LDI
; SINWLAAITY CRITERION
, SINWLAAITY FLAG
START 5W/TN _
CI1PI
llOOP: BEQ
O,IRI
ARO,AR4
; IRI (= I IINIT. 0)
; AR4 -) BIO, 0]
lRO,lRI
SKIP
, COIf ARE I TO K
; IF I = K TlN SKIP PIVOT Rill
" ,TElT
;:t...
~
;:s
Q.
~'
~
..,
So
<11
~
N
lOP
HPARIIS
LDI
LDI
LDI
ISIAIlI,ARO
_,ARI
1tHOO..,AR2
SUBI
ADDI
MPYF
I,RC
AR3,IRO,AR7
RO, f++/IR7 ,RI
RSW/TNI
5ETU' lOOP REGISTERS
UP
LDI
LDI
SUBI
LDI
SUBI
IEPSN
O,IRO
ARO,AR3
I,ARI
AR2,AR6
2,AR6
RPTB
MPYF
ADDF
RND
..lOOP: STF
II
KlOOPI lDF
ABSF
CII'F
ILT
HAR3(JRO),R3
R3,RO
IEPSN,RO
SINl
..lII(P:
--
R3,RO
ELEIEirr
, RO <= -B1K, KJ
RI, t++AR5, R2
R2
R2,_
, RC <= N-K-3
; AR7 -) BIK, JJ
, RI <= B1K, K+I]tm, KJ
(J
INDEll
RI, t++MS, R2
R2
R2,_
BlTD
ARI,IRI
IlOOP
, COMPARE I 10 "-I
; IF I < 11-1 lIEN lOOP (DElAYED)
ADDI
ADDI
CI1PI
AR2,AR4
I,IRI
IRO,IRI
ADDF
RND
STF
;
,
,
,
JlOOP
RO,*++AR7,Rl
; AR5 -) Bll, KI
, RO <= B1I, KJ
; RC <= N-K-2
; COIfARE RC TO I
; IF RC < I TlN t() RPTB IDElAYED)
BlTD
AR4,IRO,AR5
tAR5,RO
ARb,RC
I,RC
JUMP
ADDI
lDF
LDI
CI1PI
Q.
'
SKIP:
CI1PI
AR4 -) Bll+I, OJ
I <= 1+1
COMPARE I TO K
;:..
~
;:s
a
c
ADDI
ADDI
SUBI
AR2,AR3
I,IRO
1,AR6
, cot'ARE K TO IH
, IF K ( IH TIN LOOP
UF
RETS
ZERO,R3
PROGRAI1: lSOLUTNX
I
I
I
I
I
I
AR3 -) 8[K'I, 01
K (= K'I
ARb (= IHH
,RETURN
RETS
~.
So
~
ARI,IRO
{(lOOP
'&
...
01'1
Il.TD
flUHHffHHHHHHHtfHHHtIIIIIIIIIIIIII.111111111
n****fU**H****fHfiUffU*************UHfUffUIHH
!j
GLOBL
.!LOB!.
.GLOB!.
.!LOB!.
to.)
00
IIS(LUTNX
RSOLUTNX
FPINVX
FI1ULTX
NEGF
CALL
LDF
RO
RO
RI
R3,RO
FPINVX
RO,RI
(=
(=
(=
-BIK, Kl
-I/BIK, Xl
-I/BIX, Kl
ELE~NT
IPARIIS
SIADI
SNROW
SNCOl.
INTeRIW. CONSTANTS
ADDI
LDI
RPTB
LDF
CALL
RHO
DLOOFX: STF
AR3,IOO,AR7
ARb,RC
, AR7 -) BIK, Xl
, RC
DLOOFI
H+AR7,RO
FMULTl
00
RO, 'AR7
(= N-J(-2
.DATA
START INNER LOOP II INDEll
EPSNX
ZEROX
.FLDAT I.Of-IO
.SET
0.0
,. SINllARITY CRITERION
, SINGULARITY FLAG
UlI
UlI
CMPI
lLOOPI' BEQ
TEXT
I'8OlY BASED PARAITER ENTRY
::...
UP
IIPARIIS
ISIADI,ARO
_,ARI
IfI:(L,ARl
UlI
UlI
UlI
'
<5;,
~
;::
RSIl.UTNX'
UP
'0...>
UlI
. UlI
stili
UlI
stili
~.
Q
c
tEPSNX
O,IRO
ARO,AR3
I,ARI
ARl,AR6
2,AR6
LIF
AIISF
, COMPARE I TO K
, IF I = K TIN SKIP PIVOT
ADDI
LDF
UlI
CI1?I
BLTD
SUBI
ADDI
MPYF
I,Re
AR3,IRO,AR7
RO,H'AR7,RI
RPTB
LOAD DATA PAlE POINTER
100 (= K UNIT. 0)
AR3 -) B[O, 01
ARI (= 11-1
ARb <= N
ARb (= N-2
~YF
ADDF
RHO
JLOOPX' STF
ARS -) BlI, Kl
RO (= BII, Kl
RC
<= N-J(-2
COMPARE RC TO I
IF RC < I THEN NO RPTB IDaAYED)
RC
<= N-J(-3
AR7 -) BIK, Jl
RI <= B[K, K+ll'BII, Kl
CIFF
B!.T
HAR3URO) ,R3
Ra,RO
tEPSNX,RO
SIrlX
COfUTE
RECI~
OF -PIVOT ELEMENT
JLOOPX
RO, +++AR7,Rt
RI,H'ARS,R2
R2
R2, .ARS
IRO,IRI
SKIPI
, IRI (= I IINIT. 0)
, AR4 -) B[O, 01
I1SILUTNX'
O,IRI
ARO,AR4
SKIPX:
, R2
S[I, N-Il + RI
ADDF
RHD
STF
Rl,f++AA5,R2
R2
R2, tARS
;ROltIDt
CI1?I
BLTO
ARI,IRI
ILOOPI
, COMPARE I TO M-I
, IF I ( 11-1 1lN LOOP CDaAYED)
ADDI
ADDI
ARl,AR4
1,1RI
, AR4 -) SlI'l, 01
; I <= 1+1
(=
, B[I, N-ll
(=
R2
g
~
~
ClPI
IRO,IRI
ClPI
MI,IRO
"
LTD
KLlD'X
ADDI
ADIlI
SUBI
AR2,AR3
I,IRO
1,ARt.
~"
'&
...
So
."
~
~
Q
c
,ClJll>AREITOK
(I
INIEIl
, CIJII>ARE K TO 11-1
, IF K <It-I TIII ltD'
AR3
00)
BIK+!, OJ
K (z K+l
ARt.
(=
IH-I
RETS
ZEROX,Rl
330
331
332
TMS320C30
Hardware Applications
Jon Bradley
Digital Signal Processor Products-Semiconductor Group
Texas Instruments
333
334
Introduction
The TMS320C30 is a high-speed, floating-point, digital signal processor. The TMS320C30s
advanced interface design allows it to be used to implement a wide variety of system configurations. Its two external buses and DMA capability provide a parallel 32-bit interface to byte- or
word-wide devices, while the interrupt interface, dual serial ports, and general purpose digital I/O
provide communication with a multitude of peripherals.
This application report describes how to use the TMS320C30s interfaces to connect to various external devices. Specific discussions include implementation of parallel interface to devices
with and without wait states, use of general purpose I/O, and system control functions. All interfaces shown in this report have been built and tested to verify proper operation.
Major topics discussed in this report are as follows:
System Configuration Options Overview
Primary Bus Interface
- Zero Wait Interface to RAMs
- Ready Generation
- Bank Switching Techniques
Expansion Bus Interface
- ND Converter Interface
- D/A Converter Interface
System Control Functions
- Clock Oscillator Circuitry
- Reset Signal Generator
Serial Port Interface
XDSIOOO Target Design Considerations
335
External
DMA
Interface
Interrupt
Interface
.. 32
24
DO31
AO23
{
{
{
HOLD
HOLDA TCLKO1
4
System Reset
ROM Enable
..
Man"
Clock {
Clock
Outputs
..
~
.. 32
13
Data
Address
XR/W
R/W
STRB
RDY
External Flags
System
Control
XDO31
XAO12
Expansion
Bus
XRDY
IOSTRB
MSTRB
INT0-3 CLKXO1
lACK
DXO1
FSXO1
XFO1 CLKRO1
DRO1
RESET FSRO1
MC/MP
X1
X2/CLKIN
H1
H3
TMS320C3C
2
2
2
2
2
2
2
Timer Interface
~~
Dual
Serial
Ports
All of the interfaces are independent of one another and different operations may be per
formed simultaneously on each interface.
The Primary and Expansion buses implement the memory mapped interface to the device.
The external DMA interface allows external devices to cause the processor to relinquish the Prima
ry bus and allow direct memory access.
336
Perlpherlals
Primary Bus
Perlpherlals
Interrupt
Interface
Bit I/O
External
Flags
External
DMA
Interface
External
Bus
Timer
Interface
. Peripherals
I/O Devices
TMS320C30
Serial Ports
System
Control
TCM29C13
CODEC
TLC32040 AIC
Analog I/O
This block diagram constitutes essentially a fully expanded system. In an actual design, any
subset of the illustrated configuration may be used.
337
lays and the fact that typically some gating is required for chip select generation. Therefore, slightly
faster memories are generally required in most systems. If one level of reasonably high-speed (below 10 ns in propagation delay) gating is used to generate chip select for the memories, 20 ns devices may be used.
Among currently available RAMs, there are two distinct categories of devices with different
interface characteristics. These two categories are RAMs without output enable control lines (OE),
which include the I-bit wide organized RAMs and most of the 4-bit wide RAMs, and those with
OE controls, which include the byte wide and a few of the 4-bit wide RAMs. Many of the fastest
RAMs do not provide OE control, and use chip select (CS) controlled write cycles to insure that
data outputs do not turn on for write operations. In CS controlled write cycles, the write control line
(WE) goes low prior to CS going low, and internal logic holds the outputs disabled until the cycle
is completed. Using CS controlled write cycles is an efficient way to interface fast RAMs without
OE controls to the TMS320C30 at full speed.
In the case of RAMs with OE controls, the use of this signal can provide added flexibility
in many systems. Additionally, many of these devices can be interfaced using CS controlled write
cycles with OE tied low, in the same manner as with RAMs without OE controls. There are, however, two requirements for interfacing to OE RAMs in this fashion. First, the RAMs OE input must
be gated with chip select and WE internally so that the device's outputs do not turn on unless a read
is being performed. Second, the RAM must allow its address inputs to change while WE is low,
which some RAMs specifically prohibit.
The circuit shown in Figure 3 shows an interface to Cypress Semiconductor's CY7C186
25 ns 8K x 8-bit CMOS static RAMs with the OE control input tied low and using a CS controlled
write cycle.
338
Primary
Address Bus
A(23-0)
A23
A12
10
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
AO
7
6
5
4
3
2
25
24
23
21
20
9~
STRB~
74AS04
27
A12
1/07
A11
1/06
A10
1/05
A9
1/04
A8
1/03
A7
1/02
A6
1/01
A5
1/00
031
18
030
17
029
16
028
15
027
13
026
12
025
11
024
A4
A3
A2
A1
AO
I/O
(0-7)
CS1
I/O
CS2
R/W~ WE
19
OE
8" 0(16-23)
8
0(8-15)
8/.
0(0-7)
(0-7)
I/O
(0-7)
In this circuit, the two chip selects on the RAM are driven by STRB and A23, which are
ANDed together internally. The use of A2310cates the RAM at addresses OOOOOh through 03FFFh
in external memory and STRB establishes the CS controlled write cycle. The WE control input is
then driven by the TMS320C30 R/W signal, and the OE input is not used, and is therefore connected
to ground.
The timing of read operations, shown in Figure 4, is very straightforward since the two chip
select inputs are driven directly. The read access time of the circuit is therefore the inverter propagation delay added to the RAMs chip select access time or tl + t2 =5 + 25 =30 ns. This access time
therefore meets the TMS320C30s specified 30 ns requirement.
339
H1~
A23-0
Valid
\l
STRB
I
I
I
I
I
I
I
I
14-
A23
031-0
!I
I
I
tj
~j 4 - t
<
>
Valid
I
I
2 ~.
During write operations, as shown in Figure 5, the RAMs outputs do not turn on at all, due
to the use of the chip select controlled write cycles. The chip select controlled write cycles are gen"
erated by the fact that R/W goes active (low) before the STRB term of the chip select input. Because
the RAMs output drivers are disabled whenever the WE input is low (regardless of the state of the
OE input) bus conflicts with the TMS320C30 are automatically avoided with this interface.The circuit's data setup and hold times (t1 and t2 in the timing diagram) of approximately 50 and 20 ns,
respectively, also easily meet the RAMs timing requirements of 10 and 0 ns.
A23-0 _ _---'X~
STRB
R/W
031-0
_---J
''---
_________________'X'_____
\.~___---,A
I
\.~- ______________~iI __~/
_-"!?>-------
----------<~....' _____--.-;
if.~----tj -----t!~
I
I
I
~t2 ~
If more complex chip select decode is required than can be accomplished in time to meet
zero-wait state timing, wait states or bank switching techniques (discussed in a later section) should
be used.
340
It should be noted that the CY7C186's OE control is gated internally with CS, therefore the
RAMs outputs are not enabled unless the device is selected. This is critical if there are any other
devices connected to the same bus; if there are "no other devices connected to the bus, then OE need
not be gated internally with chip select.
RAMs without OE controls can also be easily interfaced to the TMS320C30 using a similar
approach to that used with RAMs with OE controls. If there is only one bank of memory implemented, and no other devices are present on the bus, the memories' CS input may often be connected
to STRB directly. If several devices must be selected, however, a gate is generally required to AND
the device select and STRB to drive the CS input to generate the chip select controlled write cycles.
In either case, the WE input is driven by the TMS320C30 R!W signal. Provided sufficiently fast
gating is used, 25 ns RAMs may still be used.
As with the case of RAMs with OE control lines, this approach works well if only a few banks
of memory are implemented where the chip select decode can be accomplished with only one level
of gating. If many banks are required to implement very large memory spaces, bank switching can
be used to provide for multiple bank select generation while still maintaining full speed accesses
within each bank. Bank switching is discussed in detail in a later section.
Ready Generation
The use of wait states can greatly increase system flexibility and reduce hardware requirements over systems without wait state capability. The TMS320C30 has the capability of generating
wait states on either the primary bus or the expansion bus and both buses have independent sets of
ready control logic. Ready generation is discussed in this subsection from the perspective of the
primary bus interface, however, wait state operation on the expansion bus is similar to that of the
primary bus, therefore these discussions pertain equally well to expansion bus operation. Thus,
ready generation will not be included in the specific discussions of the expansion bus interface.
Wait states are generated on the basis of the internal wait state generator, the external ready
input (RDY), or the logical AND or OR of the two. When enabled, internally generated wait states
effect all external cycles, regardless of the address accessed. If different numbers of wait states are
required for various external devices, the external RDY input may be used to tailor wait state generation to specific system requirements.
If the logical OR (or electrical AND since the signals are true low) of the external and wait
countready signals is selected, the earlier of either ofthe two signals will generate a ready condition
and allow the cycle to be completed. It is not required that both signals be present.
The OR of the two ready signals can be used to implement wait states for devices that require
a greater number of wait states than are implemented with external logic (up to seven). This feature
is useful, for example, ifa system contains some fast and some slow devices. In this case, fast devices can generate a ready signal externally with a minimum oflogic, and slow devices can use the
internal wait counter for larger numbers of wait states. Thus, when fast devices are accessed, the
external hardware responds promptly with a ready signal that terminates the cycle. When slow devices are accessed, the external hardware does not respond, and the cycle is appropriately terminated after the internal wait count.
The OR of the two ready signals may also be used if conditions occur that require termination
of bus cycles prior to the number of wait states implemented with external logic. In this case, a
TMS320C30 Hardware Applications
341
shorter wait count is specified internally than the number of wait states implemented with the external ready logic, and the bus cycle is terminated after the wait count. This feature may also be used
as a safeguard against inadvertent accesses to nonexistent memory that would never respond with
ready and therefore lock up the TMS320C30.
If the OR of the two ready signals is used, however, and the internal wait state count is less
than the number of wait states implemented externally, the external ready generation logic must
have the ability to reset its sequencing to allow a new cycle to begin immediately following the end
of the internal wait count. This requires that, under these conditions, consecutive cycles must be
from independently decoded areas of memory and that the external ready generation logic be capable of restarting its sequence as soon as a new cycle begins. Otherwise, the external ready generation logic may lose synchronization with bus cycles and therefore generate improperly timed wait
states.
If the logical AND (electrical OR) of the wait count and external ready signals is selected,
the later of the two signals will control the internal ready signal, and both signals must occur. Accordingly, external ready control must be implemented for each wait state device in addition to the
wait count ready signal being enabled.
This feature is useful if there are devices in a system that are equipped to provide a ready signal but cannot respond quickly enough to meet the TMS320C30s timing requirements. In particular, if these devices normally indicate a ready condition and, when accessed, respond with a wait
until they become ready, the logical AND of the two ready signals can be used to save hardware
in the system. In this case, the internal wait counter can be used to provide wait states initially, and
become ready after the external device has had time to send a not ready indication. The internal wait
counter then remains ready until the external device also becomes ready, which terminates the
cycle.
Additionally, the AND of the two ready signals may be used for extending the number of wait
states for devices that already have external ready logic implemented but require additional wait
states under certain unique circumstances.
In the implementation of external ready generation hardware, the particular technique
employed depends heavily on the specific characteristics of the system. The optimum approach to
ready generation varies depending on the relative number of wait state and non-wait state devices
in the system and the maximum number of wait states required for anyone device. The approaches
discussed here are intended to be general enough for most applications, and are easily modifiable
to comprehend many different system configurations.
In general, ready generation involves the following three functions:
1) Segmentation of the address space in some fashion to distinguish fast and slow devices.
2) Generating properly timed ready indications.
3) Logically ORing all of the separate ready timing signals together to connect to the physical ready input.
342
Segmentation of the address space is required so that a unique indication of each of the particular areas within the address space that require wait states can be obtained. This segmentation is
commonly implemented in a system in the form of chip select generation. Chip select signals may
be used to initiate wait states in many cases, however, occasionally chip select decoding considerations may provide signals that will not allow ready input timing requirements to be met. In this
case, coarse address space segmentation may be made on the basis of a small number of address
lines, where simpler gating allows signals to be generated more quickly. In either case, the signal
indicating that a particular area of memory is being addressed is normally used to initiate a ready
or wait state indication.
Once the region of address space being accessed has been established, a timing circuit of
some sort is normally used to provide a ready indication to the processor at the appropriate point
in the cycle to satisfy each device's unique requirements.
Finally, since indications of ready status from multiple devices are typically present, the signals are logically ORed using a single gate to drive the RDY input.
One of two basic approaches may be taken in the implementation of ready control logic depending upon the state in which the ready input is to be between accesses. If RDY is low between
accesses, the processor is always ready unless a wait state is required; if RDY is high between accesses, the processor will always enter a wait state unless a ready indication is generated.
If RDY is low between accesses, control of full speed devices is straightforward; no action
is necessary since ready is always active unless otherwise required. Devices requiring wait states,
however, must drive ready high fast enough to meet the input timing requirements. Then, after an
appropriate delay, a ready indication must be generated. This can be quite difficult in many circumstances since wait state devices are inherently slow and often require complex select decoding.
If RDY is high between accesses, zero wait state devices, which tend to be inherently fast,
can usually respond immediately with a ready indication. Wait state devices may simply delay their
select signals appropriately to generate a ready. Typically, this approach results in the most efficient
implementation of ready control logic. Figure 6 shows a circuit of this type which can be used to
generate 0, 1, or 2 wait states for multiple devices in a system.
343
TMS320C30
Address Bus
STRB
15
14
13
12
11
74ALS138
A
B
C
G2A
Device
Selects
G1
Other 1
Walt
Status
Devices
74AS32
+5V
2 Walt
Status
Devices
Other 0
Walt
Status
Devices
4.7kQ
,-/'--,.
J PRE
Q 9
14
H1 --------~~----~------------~
RESET----------------e-------------------~
In this circuit, full speed devices drive ready directly through the '74AS2I, and the two fJipflops delay wait state devices' select signals one or two HI cycles to provide 1 or 2 wait states.
Considering the TMS320C30's ready delay time of 8 ns following address, zero wait state
devices must use ungated address lines directly to drive the input of the '74AS21, since this gate
contributes a maximum propagation delay of 6 ns to the RDY signal. Thus, zero wait state devices
should be grouped together within a coarse segmentation of address space if other devices in the
system require wait states.
With this circuit, devices requiring wait states may take up to 36 ns from a valid address on
the TMS320C30 to provide inputs to the '74AS20s inputs. Typically, this allows sufficient time
for any decoding required in generating select signals for slower devices in the system. For exam344
pie, the 74ALS138 driven by address and STRB, can generate select decodes in 22 ns, which easily
meets the TMS320C30s timing requirements.
With this circuit, unused inputs to either the 74AS20s or the 74AS2I should be tied to a logic
high level to prevent noise from generating spurious wait states.
If more than 2 wait states are required by devices within a system, other approaches may be
employed for ready generation. Ifbetween three and seven wait states are required, additional flipflops may be included, in the same manner as shown in Figure 6, or internally generated wait states
may be used in conjunction with external hardware. If greater than seven wait states are required,
an external circuit using a counter may be used to supplement the internal wait-state generator's
capabilities.
345
~
BAO-12
1'28
I
I
II
I
I
I
I
I
I
I
I
I
II
II
I
I
I
I
~
N
<::>
Q
<::>
~
~
~
"5
.,
g.
;:s
'"
~
'19'
r,;---
BAO to AO D7
BANKSEL " C51
.'TAB - " CS,
"WE
DE
1">
Gf!!'
~--------r
-----t
Bank 1 ~
~
'L.5.,
J 7
-----.I Bank 3 ~
~
00-31
~
,
.M' J!1
.M "
BAS "
BA> -'
~B"" ~
~
r--,,~
~
~
17'
I~
BANKSEL"
B<TAB . . C51
C52
" WE
11"
'!/
-/
~
".1O:n
M'
AH
A10
. . ."
AS
BA, " A'
BA' -' A'
BAS , AS
BAO . . . . .
f'-B.A' , M
BII' , II'
'"
_ BM 9 A1
I BAO 10 AO
v,,
A"
AH
A10
AS
..
A> DO H
A, D1
..
M D3
A' D4
A:! D5"",
A1 D6
AO
BM'
BAH
BAO
BM __
- BAO ,
BA:! ,
_BA1 9
I BAO 10
~
I~
"'19'
r,;--r----
BANKSEL"
BOTAB ""
.--"
OataBusOO-31
D3
D4
D5"",
D6
~
,,~
_
""TAB" C52
" DE
WE
GND
GND--,
_
BankO._
B~
~
,,~
~
~
DO "
D1
BANKSEL" CS1
C51
C52
WE
DE
1;"
'!/
_>
~~
~ ~
"1i?J
DE
GND J
15
151~
28
Vee
1
BM'
BAH
"'19'
-+
BANKSEL1
v"
Bm , A"
BAH" AH
. , , " " A10
.M " A9
BA' " AS
BA> -' A> DO H
BA' , '" D1
r--- BAO ' . .
BM -' A4 D3
BII' , A3 D4
BA> -' A:! D5
BA1 -'- A1 D6
1 BAO 1!! AO
~
~
,,~
r,;--- -
BSTRB
BANKSELO
I
BR/Wi
1
i:i.
.,::E
v"
BA" , A1,
BAH "'- AH
.,," " A10
Ai. " A9
BAS: ... A,
SA' -' A' DO H
BA, , A, D1
B". ... AS
BA' -' A4 D3
BA' , A3 D4
. , A:! D5"",
BA1
A1 D6
'
15
128
"15
II
11' ,
'!/_>
_ _____
__ >
A wait state is required with this implementation of bank memory because of the added propagation delay presented by the address bus buffers used in the circuit. The wait state is not a function
of the fact that the memory is organized as multiple banks or the use of bank switching. When bank
switching is used, memory access speeds are the same as without bank switching once bank boundaries are crossed. Therefore, no speed penalty is paid when using bank switching except for the occasional extra cycle ihserted when bank boundaries are crossed. It should be noted, however, that
if the extra cycle inserted when crossing bank boundaries d()es impact software performance significantly, code can often be restructured to minimize bank boundary crossings, thereby reducing the
effect of these boundary crossings on software performance.
The wait state for this bank memory is generated using the wait state generator circuit presented in the previous section. Because A23 is the signal which enables the entire bank memory system, the inverted version of this signal is ANDed with STRB to derive a one wait state device select.
This signal is then connected in the circuit along with the other one wait state device selects. Thus,
any time a bank memory access is made, one wait state is generated.
Each of the four banks in this circuit is selected using a decode ofAlS-A13 generated by the
74AS138 (see Figure 8). With the BNKCMPR register set to OBh, the banks wiII be selected on
even 8K-word boundaries starting at location 080AOOOh in external memory space.
347
2
3
4
5
6
7
8
9
Al
A2
A3
A4
AS
A6
A7
A8
Gl
Yl
Y2
Y3
Y4
Y5
Y6
Y7
Y8
G2
18
17
16
15
14
13
12
11
19
BAO
BAl
BA2
BA3
BA4
BAS
BA6
BA7
74ALS2541
2
A8
3
A
4
Al
5
All
6
Al
7
RiW
8
9
Al
A2
A3
A4
AS
A6
A7
A8
Gl
Yl
Y2
Y3
Y4
Y5
Y6
Y7
Y8
G2
18
17
16
15
14
13
12
11
19
BA8
BA9
BA10
BAll
BA12
BR/W
74AS04
74AS138
3
A15
2
A14
A13
A23
348
6
4
5
STRB
C
B
A
BANKSELO
BANKSEL1
BANKSEL2
BANLSSEL3
BSTRB
G1
G2A
G2B
The 74ALS2541 buffers used on the address lines are necessary in this design since the total
capacitive load presented to each address line is a maximum of20 x 5 pF or 100 pF (bank memory
plus zero wait-state static RAM), which exceeds the TMS320C30 rated capacitive loading of 80
pF. Using the manufacturers derating curves for these devices at a load of 80 pF (the load presented
by the bank memory) predicts propagation delays at the output of the buffers of a maximum of 16
ns. The access time of a read cycle within a bank of the memory is therefore the sum of the memory
access time and the maximum buffer propagation delay or 25 + 16 = 41 ns, which, since it falls between 30 and 90 ns, requires one wait state on the TMS320C30.
The 74ALS2541 buffers offer one additional system performance enhancement in that they
include 25-ohm resistors in series with each individual buffer output. These resistors greatly improve the transient response characteristics of the buffers especially when driving CMOS loads
such as the memories used here. The effect of these resistors is to reduce overshoot and ringing
which is common when driving predominantly capacitive loads such as CMOS. The result of this
is reduced noise and increased immunity to latchup in the circuit, which in turn results in a more
reliable memory system. Having these resistors included in the buffers eliminates the need to put
discrete resistors in the system which is often required in high speed memory systems.
Thiscircuit could not have been implemented without bank switching, since data output's
turn-on and turn-off delays would have caused bus conflicts. Here, the propagation delay of the
74AS 138 is only involved during bank switches, where there is sufficient time between cycles to
allow new chip selects to be decoded.
The timing of this circuit for read operations using bank switching is shown in Figure 9. With
the BNKCMPR register set to OBh, when a bank switch occurs, the bank address on address lines
A23-A13, is updated during the extra HI cycle while STRB is high. Then, after chip select decodes
have stabilized, and the previously selected bank has disabled its outputs, STRB goes low for the
next read cycle. Further accesses occur at normal bus timings with one wait state as long as another
bank switch is not necessary. Write cycles do not require bank switching due to the inherent address
setup provided in their timings.
349
H1
A23-13
-+i
t4 j4-
I
____-J><~------------~:--V-al-Id----------------
~,.,..I-1-1--II,....-"""'\~
A12-0
____-J)[~I___________V_al~i~------------JX~----I
______~!t
-.!
~~
t~
______________________
______-JJrrl----------~-+1-t5--~----------------I
~t3~
\yl--------------Ir-_______________
__________~I
031-0
Bank 0 on Bus
}~-------_"'"__B_a_n_k_1_0_n_B_u_s_ __
Event
Time Period
t1
t2
t3
t4
t6
14 ns
10 ns
10 ns
10 ns
3 ns
ND Converter Interface
AID and D/A converters are components that are commonly required in DSP systems and
interface efficiently to the I/O expansion bus. These devices are available in many speed ranges
and with a variety of features, and while some may be used at full speed on the I/O bus, others may
require one or more wait states.
Figure 10 shows an interface to an Analog Devices AD1678 analog to digital converter. The
AD1678 is a 12-bit, 5 Ils converter allowing sample rates up to 200 kHz and with an input voltage
range of 10 volts bipolar or unipolar. The converter is connected according to manufacturers specifications to provide 0 to +10 volt operation. This interface illustrates a common approach to connecting devices such as this to the TMS320C30. Note that the interface requires only a minimum
amount of control logic.
ms-TRB
4___.. 6
X R/W
74AS04
Ys
Vee
10J
lOR
XA 12 12p.....c 13
74AS32 r'
11
XOO
X01
X02
X03
X04
X 5
X06
X07
14
12
2A1 11
13
15
9 2Y1
S
3
17
1G
2G
XOBus
1G
1 A1
JSOQ
REFIN
DO
16
01
17
02
~9
20
21
22
23
BIPOFF
03
04
OS
06
07
~
~
~ONE
Analog
Inpul
+S
g:
A01678
PGNO
~
~
"}ooo
r
AIN 6
t4
20K Q
2S 010
26 011
74LS244
18 1Y1
16
14
12
REFOUT
v;:
24
1 I
X08
X09
X010
X011
OE
SC
~ CS
12/8
SYNC
1
EOCEN
ONE~
1A1 2
4
6
8
:8 1Y1
Voo
74LS244
28
11
74As32
~~IOW
sJ
EOC 27
Vee
INTO
AGNO
J: r
The AD1678 is a very flexible converter and is configurable in a number of different operating modes. These operating modes include byte or word data format, continuous or non-continuous
conversions, enabled or disabled chip select function, and programmable end of conversion indication. This interface utilizes 12-bit word data format, rather than byte format to be compatible with
the TMS320C30. Non-continuous conversions are selected, so that variable sample rates may be
used, since continuous conversions occur only at a rate of200 kHz. With non-continuous conversions, the host processor determines the conversion rate by initiating conversions through write operations to the converter.
TMS320C30 Hardware Applications
351
The chip select function is enabled, so the chip select input is required to be active when accessing the device. Enabling the chip select function is necessary to allow a mechanism for the
AD1678 to be isolated from other peripheral devices connected to the expansion bus. To establish
the desired operating modes, the SYNC and 12/S inputs to the converter are pulled high and EOCEN is grounded, as specified in the AD1678 data sheet.
In this application, the converter's chip select is driven by XA12, which maps this device at
S04000h in I/O address space. Conversions are initiated by writing any data value to the device,
and the conversion results are obtained by reading from the device after the conversion is completed. To generate the devices Start Conversion (SC) and Output Enable (OE) inputs, IOSTRB
is ANDed with XR/W. Therefore, the converter is selected whenever XA12 is low, and OE is driven when reads are performed, while SC is driven when writes are performed.
As with many AID converters, at the end of a read cycle the AD1678 data output lines enter
a high impedance state. This occurs after the Output Enable (OE) or read control line goes inactive.
Also common with these types of devices, is that the data output buffers often require a substantial
amount of time to actually attain a full high-impedance state. When used with the TMS320C30,
devices must have their outputs fully disabled no later than 65 ns following the rising edge of
IOSTRB, since the TMS320C30 will begin driving the data bus at this point if the next cycle is a
write. If this timing is not met, bus conflicts between the TMS320C30 and the AD1678 may occur,
potentially causing degraded system performance and even failure due to damaged data bus drivers.
The actual disable time for the AD1678 can be as long as 80 ns, therefore buffers are required to
isolate the converter outputs from the TMS320C30. The buffers used here are 74LS244s that are
enabled when the AD1678 is read, and turned off30.8 ns following IOSTRB going high. Therefore,
the TMS320C30 requirement of 65 ns is met.
When data is read following a conversion, the AD1678 takes 100 ns after its OE control line
is asserted to provide valid data at its outputs. Thus, including the propagation delay of the 74LS244
buffers, the total access time for reading the converter is 118 ns. This requires two wait states on
the TMS320C30 expansion I/O bus.
The two wait states required in this case are implemented using software wait states, however, depending on the overall system configuration it may be necessary to implement a separate wait
state generator for the expansion bus (refer to section on ready generation). This would be the case
ifthere were multiple devices that required different numbers of wait states connected to the expansion bus.
Figure 11 shows the timing for read operations between the TMS320C30 and the AD1678.
At the beginning of the cycle, the address and XR/W lines bej::ome valid t1 = 10 ns following the
falling edge ofH1. Then, aftert2 = 10 ns from the next rising edge ofH1, IOSTRB goes low, beginning the active portion of the read cycle. After t3 =5.S ns, the control logic propagation delay, the
lOR signal goes low, asserting the OE input to the AD1678. The '74LS244 buffers take t4 = 30 ns
to enable their outputs, and then, following the converters access delay and the buffer propagation
delay (t5 = 100 + 18 = 118 ns) data is provided to the TMS320C30. This provides approximately
46 ns of data setup before the rising edge of IOSTRB. Therefore, this design easily satisfies the
TMS320C30s requirement of 15 ns of data setup time for reads.
352
Figure 11. Read Operations Timing Between the TMS320C30 and AD1678
HI
x:1~-~~--,-:
I
(4-'2-01
, 4;
1---
"ill
I
IOSTRB
lOA
READO
DATA
_____________________>C
/
_ _ _ _ _~~--------------------~
-::...'3
\l
/
i ~'Io..'________-,)>-----~I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
~4
It
ts
I
I
.!
Unlike the primary bus, read and write cycles on the I/O expansion bus are timed the same
with the exception that XR/W is high for reads and low for writes and that the data bus is driven
by the TMS320C30 during writes. When writing to the AD1678, the '74LS244 buffers do not turn
on and no data is transferred. The purpose of writing to the converter is only to generate a pulse
on the converter's SC input, which initiates a conversion cycle. When a conversion cycle is completed, the AD1678's EOC output is used to generate an interrupt on the TMS320C30 to indicate
that the converted data may be read.
It should be noted that for different applications, use ofTLC1225 or TLC1550 NO converters from Texas Instruments may be beneficiaL The TLC1225 is a self-calibrating 12-bit-plus-sign
bipolar or unipolar converter which features 10 JlS conversion times. The TLC1550 is a lO-bit,
6 JlS converter with a high speed DSP interface. Both converters are parallel-interface devices_
353
the converter exhibits output signal ranges 0 to +10 volts, which is compatible with the conversion
range of the AID converter discussed in the previous section.
Vee
4 REF. OUT
50
VEE 7
-12 V
20V SPAN 11
10
10 V SPAN I-'-'--~-----,-:;-;c----,
DAe OUT .-9_ _-"1
74LS377
XDO
XDI
XD2
XD3
XD4
XD5
XD6
XD7
XDB
XD9
XD10
XD11
1Q ~
~ _ _-,---------,1-"-13 Bit 12 (LSB)
14 11
6
15 10
9
16 9
AD565A
12
2.4 K
17 8
U25
15
18 7
16
19 6
19
20 5
21 4
11 CLK
EN 1
22 3
23 2
74LS377
Power 12
24 Bit 1 (MSB)
2
3
GND
4
6
7
AGND
U26
8
9
3 1D
4
7
8
13
14
17
18
11 CLK
XD Bus
Analog
Out
-12
EN 1
12
XA12
Because this DAC essentially performs continuous conversions based on the digital value
provided at its inputs, periodic sampling is maintained by periodically updating the value stored
in the external latches. Therefore, between sample updates, the digital value is stored and maintained at the latch outputs that provide the input to the DAC. This results in the analog output remaining stable until the next sample update is performed.
The external data latches used in this interface are '74LS377 devices that have both clock
and enable inputs. These latches serve as a convenient interface with the TMS320C30; the enable
inputs provide a device select function, and the clock inputs latch the data. Therefore, with the enable input driven by inverted XA12 and the clock input driven by IOW, which is the AND of
IOSTRB and XR/W, data will be stored in the latches when a write is performed to I/O address
805000h. Reading this address has no effect on the circuit.
Figure 13 shows a timing diagram of a write operation to the D/A converter latches.
354
H1\
XA12-XAO
XA12
~
,
t1-W \
I
,I
I
I
:I
I
I
'OSTRB
,
,
:I
,
I
I
I
I
I
14"' t3~
/ I,
A
\l
t2-~
>C
\l
I
I
XD32-XDO
~t4
lOW
I
I
I
I
J+----t5----~
>I
I
14"-- t6--t1
Because the write is actuall y being performed to the latches, the key timings for this operation
are the timing requirements for these devices. For proper operation, these latches require simply
a minimal setup and hold time of data and control signals with respect to the rising edge of the clock
input. Specifically, the latches require a data setup time of20 ns, enable setup of25ns, disable setup
of 10 ns and data and enable hold times of 5 ns. This design provides approximately 60 ns of enable
setup, 30 ns of data setup, and 7.2 ns of data hold time. Therefore, the setup and hold times provided
by this design are well in excess of those required by the latches. The key timing parameters for
this interface are summarized in Table 2.
Event
Time Period
10 os
5 TIS
10 ns
5.8 ns
30 ns
7.2 TIS
355
TMS320C30
X1
X2/CLKIN
33.33 MHz
01--------,
47 pF
TO:.::H1 TOO
pF
(2)
wp -- ./Lc
At frequencies significantly lower than wP' the 1/(wC) term in (1) becomes the dominating
term, while wL can be neglected. This gives:
(3)
z (w) = jwL for w < wp
In (3), the LC circuit appears inductive at frequencies lower than wp' On the other hand, at
frequencies much higher than wP' the wL term is the dominant term in (1), and 1/(wC) can be neglected. This gives:
356
z (w)
= -.-
JWC
(4)
for w > w p
The LC circuit in (4) appears increasingly capacitive as frequency increases above wp' This
is shown in Figure 15, which is a plot of the magnitude of the impedance of the LC circuit of Figure
14 versus frequency.
Capacitive
Region
w
(rad/s)
Based on the discussion above, the design of the LC circuit proceeds as follows:
1) Choose the pole frequency wp approximately halfway between the crystal fundamental
and the third harmonic.
2) The circuit now appears inductive at the fundamental frequency and capacitive at the
third harmonic.
In the oscillator of Figure 13, choose wp =22.2 MHz, which is approximately halfway between the fundamental and the third harmonic. Choose C =20 pF. Then, using (2), L = 2.6 f-lH.
357
+5V
74LS14
74LS14
Rl = 100 KQ
DGND
The voltage on the reset pin (RESET) is controlled by the R 1C1 network. Mter a reset, this
voltage rises exponentially according to the time constant R 1C1, as shown in Figure 17.
- - - -
- - -
-~---~'---
Time
The duration of the low pulse on the reset pin is approximately t1, which is the time it takes
for the capacitor Cl to be charged to 1.5 V. This is approximately the voltage at which the reset input
switches from a logic a to a logic 1. The capacitor voltage is given by:
V
358
= Vee
[ 1- e - r
~)
where
=RICI is the reset circuit time constant. Solving (5) for t gives:
t = - RIC I In [1 - -
Vee
(6)
=
=
100 kQ
4.7 IAF
Vee =
5V
VI=1.5V
gives t = 167 ms. Therefore, the reset circuit of Figure 16 provides a low pulse of long enough
duration to ensure the stabilization of the system oscillator.
Note that if synchronization of multiple TMS320C30s is required, all processors should be
provided with the same input clcock and the same reset signal. Mter powerup, when the clock has
stabilized, all processors may then be synchronized by generating a falling edge on the common
reset signal. Because it is in the falling edge of reset that establishes synchronization, reset must
be high for a period of time (at least ten HI cycles) initially. Following the falling edge, reset should
remain low for at least ten HI cycles and then be driven high. This sequencing of reset may be accomplished using additional circuitry, based on either RC time delays or counters.
359
TlC32044
IN+
IN-
FSXO
DXO
FSRO
ORO
CLlO(O
ClKRO
TClKO
02
14
03
12
P3
01
M5
10
FSX
OUT+
OX
OUT-
FSR
DR
Voo
SHIFTClK
Vcc+
Vcc_
AGND
N4
P4
MSTR ClK
26
AGND
22
21
7
20
19
18
AGND
WOR01 BYTE
RST
XFO
G2
ADV
AOUT
+5
+5
+5
AGND
13
2
+5
DGND
9
DGND
To provide the master clock input for the AlC, the TCLKO timer is configured to generate
a clock signal with a 50% duty cycle at a frequency ofHl/4 or 4.167 MHz. To accomplish this, the
timer 0 global control register is set to the value 3Clh, which establishes the desired operating
modes. The timer 0 period register is set to 1 which sets the required division ratio for the HI clock.
To properly communicate with the AlC the TMS320C30 serial port must be configured appropriately. To configure the serial port, several TMS320C30 registers and memory locations must
be initialized. First the serial port should be reset by setting the serial port global control register
to 2170300h. (The AlC should also be reset at this time. See description below of resetting the AlC
using XFO). This resets the serial port logic and configures the serial port operating modes including data transfer lengths and enables the serial port interrupts. This also configures another important aspect of serial port operation: polarity of serial port signals. Because active polarity of all serial port signals is programmable, it is critical that the bits in the serial port global control register
that control this be set appropriately. In this application all polarities are set to positive except FSX
and FSR which are driven by the AIC and are true low.
The serial port transmit and receive control registers must also be initialized for proper serial
port operation. In this application, both of these registers are set to 111h, which configures all of
the serial port pins in the serial port mode, rather than the general purpose digital I/O mode.
With the operations described above completed, interrupts are enabled, and provided the serial port interrupt vector(s) are properly loaded, serial port transfers may begin after the serial port
is taken out of reset. This is accomplished by loading El70300h into the global control register.
To begin conversion operations on the AI C and subsequent transfers of data on the serial port,
the AIC is first reset by setting XFO to zero at the beginning of the TMS320C30 initialization rou360
tine. Setting XFO to zero is accomplished by setting the TMS320C30 IOF register to 2. This sets
the AIC to a default configuration and halts serial port transfers and conversion operations until
reset is set high. Once the TMS320C30 serial port and timer have been initialized as described
above, XFO is set high by setting the IOF register to 6. This allows the AIC to begin operating in
its default configuration, which in this application is the desired mode. In this mode all internal filtering is enabled, sample rate is set at approximately 6.4 kHz, and the transmit and receive sections
of the device are configured to operate synchronously. Conveniently, this mode of operation is appropriate for a variety of applications, and if a 5.184 MHz master clock input is used, the default
configuration results in an 8 kHz sample rate which makes this device ideal for speech and telecommunications applications.
In addition to the benefit of a convenient default operating configuration, the AIC can also
be programmed for a wide variety of other operating configurations. Sample rates and filter characteristics may be varied, in addition to which, numerous connections in the device may be configured
to establish different internal architectures, by enabling or disabling various functional blocks.
To configure the AIC in a fashion different from the default state, the device must first be
sent a serial data word with the two LSBs set to one. The two LSBs of a transmitted data word are
not part of the transferred data information and are not set to one during normal operation. This condition indicates that the next serial transmission will contain secondary control information, not
data. This information is then used to load various internal registers and specify internal configuration options. There are four different types of secondary control words distinguished by the state
of the two LSBs of the control information transferred. Note that each secondary control word
transferred must be preceded by a data word with the two LSBs set to one.
The TMS320C30 can communicate with the AIC either synchronously or asynchronously
depending on the information in the control register. The operating sequence for synchronous communication with the TMS320C30 shown in Figure 19, is as follows:
1) The FSX or FSR pin is brought low.
2) One 16-bit word is transmitted or one 16-bit word is received.
3) The FSX or FSR pin is brought high.
4) The EODX or OEDR pin emits a low-going pulse.
DR
OX
--;:==~
For asynchronous communication, the operating sequence is similar, but FSX and FSR do
not occur at the same time (see Figure 20). After each receive and transmit operation, the
TMS320C30 asserts an internal receive (RINT) and transmit (XINT) interrupt, which may beused
to control program execution.
TMS320C30 Hardware Applications
361
u u u
u
u
EMU1
GND
EMUO t
GND
EMU2 t
GND
PO (+5V)
EMU3
10
GND
11
12
GND
H3
NO PIN (KEY)
TOP VIEW
362
Description
Emulation pin O.
Emulation pin 1.
Emulation pin 2.
Emulation pin 3.
TMS320C30 H3.
Ground.
Presence detect. It indicates that the cable is connected and target system is powered up. It
should be tied to +5 volts in the target system.
In addition to the signals required atthe emulation connector, the EMU4 through EMU6 signals on the TMS320C30 must also be appropiately connected to ensure proper emulation operation.
The EMU4 signal must be tied to +5 volts and EMUS and EMU6 must be left unconnected. Also,
the RSVO through RSVlO signals must be tied to +5 volts as described in the Third-Generation
TMS320 User's Guide (literature number SPRU031).
Summary
The TMS320C30 is a high-performance 32-bit floating-point digital signal processor. Its
dual parallel-interface busses and serial ports, along with a wide variety of additional support interfaces make the device an extremely flexible system-level DSP microprocessor. Using the techniques described in this report, the TMS320C30 can be used to implement sophisticated signal processing applications with the high precision and dynamic range provided by 32-bit floating-point
arithmetic.
This application report has described the use of external interfaces on the TMS320C30 to
connect it to memories, ND and D/A converters, and numerous other peripheral devices, as well
as the generation of wait states and other system functions.
The interfaces described in this report have all been built and tested to verify proper operation, and the techniques described can be extended to encompass design of more complex systems.
363
364
TMS320C30=IEEE JFH({atiill1lg=P((J)llll1lt
Format C01I1lveIrteIr
365
366
Introduction
Certain applications require the exceptionally high arithmetic throughput inherent in the
TMS320C30 Digital Signal Processor but must use the IEEE floating-point number format, which
differs from the TMS320C30's number format. The TMS320C30 uses a 2's complement format
for the mantissa and exponent. Besides making the device more compatible with analog to digital
converters, it is computationally more efficient in both speed and die size than the IEEE format.
Applications requiring the IEEE format can benefit from the use of a custom chip for this conversion. For this reason, a chip has been designed, built, and tested. This report describes that chip.
The TMS320C30-IEEE Floating-Point Number Format Converter is a peripheral that performs floating-point number conversions between the native format of the TMS320C30 and the
Single-Precision IEEE Standard 754-1985. This conversion is performed in hardware and can convert an incoming (IEEE-formatted) or outgoing (TMS320C30-formatted) floating-point number
in less than one TMS320C30 instruction cycle. Normally, the part is placed between memory and
the TMS320C30.
This peripheral has two operating modes.
Mode 1 does not pipeline any data through the chip. Instead, one wait state is automatical"
Iy generated to compensate for the converter's propagation delays. This mode is equivalent in performance to equipping the TMS320C30 with a single-cycle convert instruction.
In those applications where speed is of utmost importance, the pipeline mode is provided.
.. Mode 2 enables the converter's built-in pipeline.
Because propagation delays through the chip reduce the access time required for
TMS320C30 external memory, the pipeline mode allows conversions to take place on one data value while a previously converted value is being read, or written, by the TMS320C30. Depending
on the TMS320C30 instruction cycle time and the access time of memories being used, the pipeline
mode can eliminate degradation in TMS320C30 throughput entirely. However, it should be noted
that values fed through the pipeline appear at the output in the next cycle. Therefore, an extra read
or write (i.e., the same operation that was being performed) must be performed to flush the pipeline.
Consequently, when pipeline mode is used, data values and their addresses are skewed from one
another. This mode is intended for high-speed block transfer/conversion, and the address skew
should be acceptable.
All control signals to and from the converter are compatible with TMS320C30 signals so that
no extra circuitry is required to use this chip. In fact, it has been designed to appear as much as possible like a simple bus transceiver (e.g., SN74LS245). Consequently, it has two data buses. Data bus
A (pins DA31 through DAO) should be connected directly to one of the TMS320C30's data buses
and the other to memory. Its direction pin (DIR) should be tied to the read/write pin (RIW), and
its output enable pin (DE) can be tied to either STRB or MSTRB of the TMS320C30, depending
on where in the TMS320C30 memory map IEEE numbers are stored.
Key Features
This device is designed to fit into systems equipped with TMS320C30 external memory into
which IEEE formatted numbers are stored. Below is a list of some specific features of the
TMS320C30-IEEE Floating-Point Converter:
TMS320C30-IEEE Floating-Point Format Converter
367
Report Overview
External Interfaces - Describes the external interfaces of this chip, the pinout, and pins.
Architectural Overview- Describes the functions of the converter. Gives an overview of
the TMS320C30 and IEEE Standard 754-1985 number formats and the scope of numbers
that can be converted.
Converter Operating Modes - Describes the converter's operating modes.
Interrupts - Describes the Not a Number interrupt generated by the converter.
Software Application Examples - Contains software application examples.
Hardware Application Examples - Contains hardware application examples.
JTAG/lEEE-1149.1 Scan Interface - Contains the JTAG/IEEE scan interface description.
Typographical Conventions
In this report, buses are signified with the bus name in capital letters, followed by the range
of signals (bits) enclosed in parentheses and separated by a colon. For example, TI(31:0) is bus
"TI", bits 31 through 0 (31 is the most significant bit, 0, the least). Table 1 shows the symbols and
their corresponding meaning that are used in sections of the report concerning control logic, algorithm overview, and bit-specific conversion algorithms.
&
!
"
Name
plus
pipe
ampersand
exclamation point
minus
caret
Meaning
arithmetic summation
logical OR
logical AND
one's complement
two's complement
EXCLUSIVE OR
External Interfaces
Packaging
The TMS320C30 device is housed in an 84-pin package. This pinout was chosen for efficient
flow through connection to the buses. The TMS320C30-IEEE Converter's pin assignments are
shown in Table 2, and the pin locations are shown in Figure 1.
368
Name
Pin
Name
Pin
Name
1
2
3
4
5
6
7
8
9
10
GND
DB15
DB14
DB13
DB12
DB11
DBlO
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DBI
DBO
WAIT
PIPE
eLK
vee
GND
NAN
DIR
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DA3
DA4
DAS
DA6
DA7
DA8
DA9
DAlO
DA11
DA12
DAB
DA14
DA15
vee
GND
DA16
DA17
DA18
DAl9
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
DA29
DA30
DA31
TDI
TMS
TCK
vec
GND
TDO
TIP
RST
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OE
DAD
DAl
DA2
DAZO
DAZI
DAZ2
DAZ3
DAZ4
DA25
DA26
DA27
DA28
77
78
79
80
81
82
83
84
DBl8
DBl7
DBl6
vee
369
~~~~~~~~~~Zu~~~~~~~~~
OOOOOOOOOO~>OOOOOOOOO
OB5
OB4
OB3
OB2
OB1
11109 8 7 6 5 4 3 2 1 84838281807978777675
12
74
71
OBO
WAIT
PIIPE
ClK
Vee
GNO
NAN
OIR
OE
OAO
OA1
OA2
OA3
OA4
OA5
OA6
OB25
OB26
OB27
OB28
OB29
OB30
OB31
RST
TIP
TMS320C30 - IEEE
FLOATING POINT
FORMAT CONVERTER
65
22
23
62
24
61
25
26
60
27
59
58
28
57
29
56
30
55
31
54
32
333435363738394041424344454647484950515253
TOO
GNO
Vee
TCK
TMS
TOI
OA31
OA30
OA29
OA28
OA27
OA26
Pinout Description
Table 3 describes the pin functions.
Pins
TYpe
Description
DIR
Input
OE
Input
370
Pins
Type
Description
WAIT
Output
PIPE
Input
Pipeline Enable - When this is high, the converter is configured in pipeline mode. It must be tied low for nonpipeline
mode.
CLK
Input
NAN
Output
DA(3I:O)
32
Input/Output
DB(31:0)
32
Input/Output
TCK
Input
Test Clock.
TMS
Input
RST
Input
TDI
Input
TDO
Output
TIP
Output
371
Architectural Overview
Figure 2 shows the block diagram of the converter.
T
M
S
3
2
C
3
N
T
E
R
F
A
C
HOLDING
REGISTER
HOLDING
REGISTER
IEEE TO
TMS320C30
CONVERTER
o
G
S
C
HOLDING
REGISTER
TMS320C30
TO IEEE
CONVERTER
HOLDING
REGISTER
I
C
A
N
E
M
o
R
y
I
F
A
E
TEST CONTROL LOGIC
Introduction
The TMS320C30 attains a peak performance of 33 MFLOPS, largely due to the floating-point format that it uses. In this format, both exponent and mantissa are represented in 2's-complement form.
In the IEEE format, the mantissa is represented in signed-magnitude form, and the exponent
includes a bias (i.e., an offset). Additionally, values of numbers are not determined by the same formula. Instead, the exponent is used to flag numbers that are encoded differently. For example, if
the exponent is 255, the value is considered not a number (NaN). Another exception is signaled
when the exponent is zero. In this case, the mantissa is defined to be denormalized.
The TMS320C30's floating-point format is considerably simpler; most numbers can be converted
to it without any loss of precision. However, some denormalized IEEE numbers are smaller than
can be represented in TMS320C30 format. When these numbers are converted, they are translated
to the closest TMS320C30 values. The error is less than 2-127.
in 32 bits, which is the bus width of the TMS320C30, and is the only format supported by the converter.
The format of the single-precision IEEE Standard 754-1985 is shown below:
23 22
31 30
EXPONENT
MSB
FRACTION
LSB
MSB
LSB
In this format,
5 is the sign bit of the mantissa (0 = positive, 1 = negative).
EXPONENT is an unsigned 8-bit field that determines the location of the binary point
of the number being encoded.
FRACTION is a 23-bit field containing the fractional part of the mantissa.
LSB is the least significant bit of a field
MSB is the most significant bit of a field
The decimal value (v) of some number X is defined by one of five separate cases shown below:
Case 1: If EXPONENT = 255 and FRACTION .. 0, then v is NaN.
Case 2: If EXPONENT = 255 and FRACTION = 0, then v = infinity.
Case 3: If 0< EXPONENT < 255, then v = (_l)S 2 exp-127 (1.FRAC)
where:
5 is either
or 1
Note that an implied 1 exists to the left ofthe binary point as shown above. This means
the mantissa of an IEEE-encoded value has 24 bits of precision.
or 1
Note that an implied exists to the left of the binary point as shown above. This means
the mantissa of an IEEE-encoded value has 24 bits of precision.
TMS320C30 IEEE Floating-Point Format Converter
373
24
EXPONENT
MSB
S
LSB
23 22
+- BIT #
FRACTION
MSB
LSB
ss.fraction
Note that the bit to the left of the binary point is implied and is the complement of the sign
bit. This gives the TMS320C30's mantissa 24 bits of precision and not 23 bits as might be expected.
For example:
The most positive TMS320C30 mantissa is
01.11111111111111111111111 = 2 - 2-23
The least positive TMS320C30 mantissa is
01.0000 0000 0000 0000 0000 000 = 1
The most negative TMS320C30 mantissa is
10.0000 0000 0000 0000 0000 000 =-2
The least negative TMS320C30 mantissa is
Exponent
Value
Mantissa
Type
Case
0
0
0
0
0
0
FF
FF
FE
FE
FE
FE
0
0.000 ... 000
1.111...111
1.111...110
1.111...101
1.111...100
not applicable
+ infinity
(2_Z-23)x2127
(2_2-22)x2127
(2_2- 21 +2-231X2127
(2_Z-21)x212
NaN
+ Infinity
+ Normalized
+ Normalized
+ Normalized
+ Normalized
Number
Number
Number
Number
1
2A
3A
3A
3A
3A
0
0
0
0
0
FE
FD
FD
FD
FD
1.000... 000
1.111...111
1.111...110
1.111...101
1.111...100
2127
(2_Z-23)x2126
(2_Z-22)x2126
(2_2-21+2-23Jx2126
(2_2-21 )x212
+ Normalized Number
+ Normalized Number
+ Normalized Number
+ Normalized Number
+ Normalized Number
3A
3A
3A
3A
3A
0
0
0
0
0
01
00
00
00
00
1.000...000
0.111...111
0.111...110
0.111...101
0.111...100
Z-126
(1_Z-23)xZ-126
(1_Z-22)xZ-126
(1_2-21+Z-23ix2-126
(1_Z-21)xZ-1 6
+ Normalized Number
+ Denormalized Number
+ Denormalized Number
+ Denormalized Number
+ Denormalized Number
3A
4A
4A
4A
4A
0
0
0
0
00
00
00
00
Z-127
(1_Z-22{xZ-127
(1-Z-2 )xZ- 127
(1_2-20+2-22)x2-127
+ Denormalized Number
- Denormalized Number
- Denormalized Number
- Denormalized Number
4A
4B
4B
4B
0
0
0
0
1
1
00
00
00
00
00
00
00
00
(1+Z-1)x2-14S
Z-148
Z-149
- Denormalized Number
- Denormalized Number
- Denormalized Number
+ Zero
-Zero
- Denormalized Number
- Denormalized Number
- Denormalized Number
4B
4B
4B
+ 0.0
-0.0
-(2- 149)
-(2- 148;
-(1+Z- )xZ- 148
5
5
4D
4D
4D
375
Exponent
Mantissa
Value
Type
Case
1
1
1
00
00
00
00
00
-{1_T22)xT127
-{T12,?
-{1+2- 2)x2- 127
-{1+2-21)x2-127
-{I +2-21+2-22)x2-127
00
0.ll1...1ll
-{1_2-23)x2-126
1
1
1
1
01
01
01
1.000... 000
1.000... 001
1.000... 010
1.000... 011
-{T126
-{1+2- 3)xT126
-{I +T22)xT126
-{1+T22+T23)x2-126
Normalized Number
Normalized Number
Normalized Number
Normalized Number
3C
3B
3B
3B
1
1
1
1
1
01
02
02
02
02
1.111...1ll
1.000 ... 000
1.000... 001
1.000... 010
1.000 ... 011
-{2_2-23)x2-126
-{2- 12
-{2+T 3)xT125
-{2+ 2-22)x2-125
-{1+2-22+2-23)x2-125
Normalized Number
Normalized Number
Normalized Number
Normalized Number
Normalized Number
3B
3C
3B
3B
3B
1
1
1
1
FE
FE
FE
FE
1.111...100
1.111...101
1.1ll ... ll0
1.111... II 1
-{2_2-21)x2127
-{2-2-21+2-23Jx2127
-{2_T22)x212
-{2_T23)x2127
Normalized
Normalized
Normalized
Normalized
3B
3B
3B
3B
FF
=0
- infinity
- Infinity
1
1
01
Denormalized Number
Denormalized Number
Denormalized Number
Denormalized Number
Denormalized Number
4D
4D
4C
4C
4C
- Denormalized Number
4C
Number
Number
Number
Number
2B
376
EXPFF=
IEEE(30)
IEEE(26)
& IEEE(29)
& IEEE(25)
& IEEE(28)
& IEEE(24)
& IEEE(27)
& IEEE(23)
&
EXPOO =
!( IEEE(30)
IEEE(26)
IIEEE(29)
I IEEE(25)
I IEEE(28)
I IEEE(24)
I IEEE(27)
I IEEE(23)
I
)
MANTO = !( IEEE(21)
IEEE(17)
I IEEE(16)
I IEEE(20)
IIEEE(19)
I IEEE(15)
IIEEE(18)
I IEEE(14)
IEEE(13)
IEEE(9)
IEEE(5)
IEEE(l)
I IEEE(12)
I IEEE(8)
I IEEE(4)
I IEEE(O
I IEEE(ll)
I IEEE(7)
I IEEE(3)
I IEEE(lO)
I IEEE(6)
I IEEE(2)
Then
Case 1: NaN
1\
!MANTO)
377
Note:
Exponent
Sign
l.
elEEE
SIEEE
2A.
2B.
3A.
3B.
3C.
4A.
4B.
4C.
40.
5.
7Fh
7Fh
SIEEE
fIEEE
7F FFFFh
OOOOOOh
SIEEE
+ 81h
elEEE + 81h
SIEEE
fIEEE
SIEEE
-fIEEE
SIEEE
-fIEEE
SIEEE
2 x flEEE
OOOOOOh
2 x -fIEEE
OOOOOOh
OOOOOOh
eIEEE
elEEE "
Fraction
80h
81h
80h
81h
80h
80h
SIEEE
SIEEE
0
0
f-----i..
CASE4D
CASES
378
TMS320C30(23)
'
--
:=)
ab
CASE3C
"1"
aB
"0"
Ab
IEEEBIAS(30)
AB
TMS320C30(31 )
IEEE(n)
--------ef
- - - - - - - - - . t aB
"0"
- - - - - - - - - . t Ab
--------ef
24
ab
"1"
IEEEBIAS(n)
<!:
1----. TMS320C30(n+ 1)
AB
IEEE(23)
"1"
aB
"0"
-"" Ab
IEEEBIAS(23)
AB
TMS320C30(24)
/'
b = CASEI , CASE3C , CASE4B , CASE4D , CASES
B= !b
379
IEEE(O)
--------~
ab
"1"
--------~
as
"0"
--------~
Ab
1-----. TMS320C30(0)
B=CASE2A
b =!B
. Case
Type
Value
Mantissa
Exponent
Sign
7F
7F
7F
7F
0
0
0
0
1.111...111
1.111...110
1.111...101
1.111...100
(2_r23)x21U
(2_2-22)x2127
(2_r21+r23jx2127
(2_r21 )x2 12
Positive
Positive
Positive
Positive
Number
Number
Number
Number
6
6
6
6
7F
7E
7E
7E
0
0
0
0
1.000... 000
1.111...111
1.111...110
1.111...101
2127
(2_2-23)x2126
(2_r22)x2126
(2_2-21+2-23)x2126
Positive
Positive
Positive
Positive
Number
Number
Number
Number
6
6
6
6
00
FF
FF
FF
0
0
0
0
1
1_2-24
1_2-23
1_r22+2-24
Positive
Positive
Positive
Positive
Number
Number
Number
Number
6
6
6
6
FF
FE
FE
FE
0
0
0
0
r 1
(2_r23)xr2
(2_2-22 )xr2
(2_2-21+2-23)x2-2
Positive
Positive
Positive
Positive
Number
Number
Number
Number
6
6
6
6
82
81
81
81
81
0
0
0
0
0
1.000... 000
1.111...111
1.111...110
1.111...101
1.111...100
r 126
(2_r23)xr127
(2_2-22)xrI27
(2_2-21+2-23Jx2-127
(2_2-21 )x2-1 7
Positive Number
Positive Number
Positivr Number
Positive Number
Positive Number
6
7 (note
7 (note
7 (note
7 (note
81
81
81
0
0
0
1.000... 010
1.000 ...001
1.000... 000
(1 +2-22)xrI27
(1 +r23)xrI27
2- 127
Positive Number
Positive Number
Positive Number
7 (note 1)
7 (note 1)
7 (note 1)
80
80
80
0
0
0
0.111...111
0.111...110
0.111...101
(note 2)
(note 2)
(note 2)
Implied Zero
Implied Zero
Implied Zero
8
8
8
80
(note 2)
Implied Zero
1)
1)
1)
1)
381
Case
Sign
80
0.0
Zero
80
80
80
1
1
1
10.111...111
10.111 ... 110
10.111 ... 101
(note 2)
(note 2)
(note 2)
Implied Zero
Implied Zero
Implied Zero
(note 3)
(note 3)
(note 3)
80
80
80
1
1
1
(note 2)
(note 2)
(note 2)
Implied Zero
Implied Zero
Implied Zero
(note 3)
(note 3)
(note 3)
80
10.000... 000
(note 2)
Implied Zero
81
81
81
1
1
1
10.111...111
10.111...110
10.111...101
(_1_Z-23)xZ-127
(_1_Z-22rz-127
(-1-2-2 +2-23)x2-127
Negative Number
Negative Number
Negative Number
9 (note 1)
9 (note 1)
9 (note 1)
81
81
1
1
(_2+2-22)x2-127
(_2+Z-23)xZ-127
Negative Number
Negative Number
9 (note 1)
9 (note 1)
81
82
82
82
1
1
1
1
10.000... 000
10.111...111
10.111...110
10.111...101
-(Z-126j
(-1-Z- 2 )xZ- 126
(_1_Z-22)x2-126
(_1_2-21+2-23)x2-126
Negative
Negative
Negative
Negative
Number
Number
Number
Number
10
11
11
11
FF
FF
00
00
00
1
1
1
1
1
10.000... 001
10.000 ... 000
10.111...111
10.111...110
10.111 ... 101
_1+Z-24
-1
(_1_2-23 )x2- 1
(_1_Z-22)xZ-l
(_1_2-21+2-23)x2-1
Negative
Negative
Negative
Negative
Negative
Number
Number
Number
Number
Number
11
10
11
11
11
00
00
01
01
01
1
1
1
1
1
_2+2-23
-2
_2_2-22
_2_Z-21
_2_2-20+Z-22
Negative Number
Negative Number
Negative Number
Negative Number
Negative Number
11
10
11
11
11
7F
7F
1
1
10.000... 001
10.000... 000
(_2+Z-23)x2127
-(2 128 )
Negative Number
Negative Number
11
12
382
Mantissa
Type
Exponent
Value
Notes:
1) Numbers converted to IEEE denormalized values lose one least significant bit of accuracy.
2) The TMS320C30 does not produce these numbers under normal arithmetic operations. Because the exponent
of these numbers is -128, the TMS320C30 considers them zero. TMS320C30 Boolean operations are capable of producing numbers of these forms. Because of this, proper conversion to IEEE format is unclear and
should be avoided. See note 3.
3) Case 8 & Case 9 are activated simultaneously. This is the only instance where the cases are not mutually exclusive. The TMS320C30 does not produce these numbers under normal arithmetic operations. Because the
exponent of these numbers is -128, the TMS320C30 considers them zero. TMS320C30 Boolean operations
are capable of producing numbers of these forms. Because of this, proper conversion to IEEE format is unclear. This dilemma can be resolved with minor modification to the case qualifier logic. See note 2.
I C30(30)
I C30(26)
I C30(29)
I C30(2S)
I C30(28)
EXP7F=
lC30(31)
C30(27)
& C30(30)
& C30(26)
& C30(29)
& C30(2S)
MANTO =
C30(22)
C30(lS)
C30(14)
C30(1O)
C30(6)
C30(2)
I C30(21)
I C30(17)
I C30(13)
I C30(9)
I C30(S)
I C30(1)
I C30(20)
I C30(16)
I C30(12)
I C30(S)
I C30(4)
I C30(O)
I C30(19)
I C30(lS)
I C30(1l)
I C30(7)
I C30(3)
EXPSO Sl
Then,
Case 6: positive numbers
2:
126
2- 127 2: N 2: 2-127
Case 8: zero
= EXPSO_81 & C30(24)
383
(_2+2-23)x2-127
;0'
Sign
sC30
sC30
0
sC30
sC30
sC30
sC30
Exponent
eC30+ 7Fh
00
00
00
eC30+80h
eC30+7Fh
FFh
Fraction
fC30
(fC3Oi'2)+400000h
OOOOOOh
(fC30+ 1)/2+400000h
OOOOOOh
fC30+ 1
OOOOOOh
The following bit algorithms are shown in bit-descending order, starting with TMS320C30
bit 31.
TMS320C30SIAS(31) --------~ ab
"1" ------------~aB
"0" ____________
TMS320C30(31) ~
CASE10
-+-/
Ab
( - - - - - - . IEEE(30)
)----.!AB
B = CASEIO I CASE12
b =!B
a = CASE61 CASEll I CASE12
A= !a
TMS320C30SIAS(n)
:2:
:2:
24
>
---------~
..
"1"
~-------..
~
aB
"0"
------------~
Ab
TMS320C30(n)
--------~
AS
( - - - - - - . IEEE(n1)
B CASElO I CASE12
b =!B
a = CASE6 I CASEll I CASE12
A= !a
_ ___---I
CASES
.
1 - - - - IEEE(31)
385
TMS320C30(22)
---------1~
ab
"1"
---------i~
aB
"0"
--------~
Ab
TMS320C30NEG(22)
---------1~
AB
1-----+ IEEE(22)
TMS320C30(n+1)
~ D ~
--------~~
TMS320C30(n) --------~
1------1~.
"0"
--------~
TMS320C30NEG(n+1)
--------~
IEEE(n)
TMS320C30NEG(n) --------~
.. /
C = CASE6 I CASE9
c= !C
386
.. ~
ab
TMS320C30(O)
---------1~
TMS320C30(1)
---------1~
as
"0"
---------pt
Ab
TMS320C30NEG(1)
..
.. IEEE(O)
----------.t AS
B = CASE7 I CASE9
b =!B
a = CASE61 CASE71 CASEll
A= !a
Scope of Conversion
This section describes the actions taken by the converter when it converts to and from the
IEEE format. When there is not a match between formats, the converter forces the translated number to the closest approximation.
IEEE-to-TMS320C30 Exceptions
The match is not exact in translating from four sets of IEEE numbers to TMS320C30 numbers. They are: NaN, infinity, zero and denormalized numbers too small to represent.
NaN (Not a Number)
The NaN format is especially useful in passing commands to another process. So that commands can be passed through the converter, NaNs are not converted. However, the bit positions of
the sign and exponent bits are altered. That is, the sign bit of the IEEE number is transferred to the
sign bit of the TMS320C30 format. Likewise, the exponent field is transferred. In this way, the sign
of the NaN is preserved which may aid in quick detection of the code. In other words, the
TMS320C30 Branch on Positive instruction (BP) or Branch on Negative instruction (BN) are effective. So that the command can be acted on quickly, a NaN interrupt is generated.
Infinity
When positive or negative infinity is passed through the converter, the most positive or negative TMS320C30 number is produced.
387
TMS320C30toIEEE Exceptions
There are two sets ofTMS320C30 numbers that do not perfectly match IEEE numbers. One
set consists of a single value (- 2127). The other consists of numbers converted to IEEE denormalized numbers.
_2127
The single value, - 2127 , is a very large negative number. When this number is translated, negative infinity is produced.
Numbers Translated to Denormalized Values
When the exponent is-127, denormalized IEEE numbers are produced, and one least significant bit of accuracy is lost. This occurs because the TMS320C30 mantissa must be right-shifted
one bit in order that the exponent be increased to -126, which is the most negative exponent the
IEEE format can use.
Pin
Memory
PIPE=O
Pipeline
PIPE=l
388
Description
elK
f--~I
Pipelined Operation
Pipeline mode permits consecutive conversions every instruction cycle without wait cycles.
However, because the pipeline has two internal stages, it takes two consecutive occurrences of the
same operation (i.e., two reads or two writes) before it is filled. Therefore, the first read after a transition from a write will not provide properly converted data, and vice versa.
There is an address skew of one address when consecutive data values are converted. This
should not be a major problem when blocks of memory are converted. The only added task will
be to perform one extra transfer (read or write) to convert the last value remaining in the pipeline.
With this exception, operation is identical to the Memory mode. Figure 18 shows a timing diagram
for this mode of operation.
389
elK
DIR
J,
-~
~:
8(31:0) --.\
I
'C30:IN 2
JC
I
IEE~ OUT 1:
~
,
Interrupts
The converter automatically generates an interrupt whenever the conversion of an IEEE
number classified as Not a Number (NaN) is attempted. The interrupt pulse is 1.5 HI cycles wide.
This is compatible with the TMS320C30 edge-triggered interrupt types. Table 9 shows this interrupt and its trigger. Note that the converter does not change the value of the NaN, but it does alter
its bit positions. This assures that the sign bit of the IEEE number remains a sign bit in the
TMS320C30 format. The same is true of the exponent field. The fractional field is left unchanged.
If NaN is used to pass a code or command to the TMS320C30, interpretation of the code requires
onl y the alteration of the comparison mask in software. For more information, refer to the previous
subsection NaN (Not a Number).
390
Name
Function
Sources
NAN
Not a Number
.word
0800000h
LOI
LOF
@EXTO,ARO
*ARO,RO
.word
0800000h
LOI
STF
@EXTO,ARO
RO, *ARO
.word
0800000h
LOI
LOF
@EXTO,ARO
*ARO,RO
LOF
*ARO,RO
.word
0800000h
LOI
STF
STF
@EXTO,ARO
RO,*ARO
RO,*ARO
EXTO
OAOR
.set
.word
.word
03FFh
0800000h
0809800h
N = # of values to convert - 1
put external address here
put destination address here
*
TMS320C30 IEEE Floating-Point Format Converter
391
RCR:
LOI
LOI
LOF
LOI
RPTB
LOF
STF
@EXTO,ARO
@OAOR,AR1
*ARO++,RO
N,RC
RCR
*ARO++,RO
RO,*AR1++
EXTO
DAOR
*
*
II
.set
.word
.word
03FEh
0800000h
0809800h
N = # of values to convert - 2
put external address here
put destination address here
LOI
LOI
LOF
LOF
RPTS
@EXTO,ARO
@OAOR,AR1
*ARO++,RO
*ARO++,RO
N
LOF
STF
*ARO++,RO
RO, *AR1++
EXTO
SAOR
*
AC:
.set
.word
.word
0400h
0800000h
0809800h
LOI
LOI
LOI
@EXTO,ARO
@SAOR,AR1
N,RC
RPTB
LOF
STF
AC
*AR1++,RO
RO,*ARO++
EXTO
SAOR
II
.set
.word
.word
03FFh
0800000h
0809800h
LOI
LOI
LOF
RPTS
@EXTO,ARO
@SAOR,AR1
*ARO++,RO
N
LOF
STF
*AR1++,RO
RO,*ARO++
STF
RO, *ARO++
or to bypass it, as the case may be. The following TMS320C30 code uses the TMS320C30 XFO
pin to do this (see Hardware Applications Examples section later in this report for the hardware
configuration). Nonpipelined mode is assumed.
N
EXTD
SADR
II
.set
.word
.word
03FFh
OBOOOOOh
OB09BOOh
LDI
LDI
LDI
LDF
RPTS
LDF
STF
@EXTD,ARO
@SADR,AR1
2,IOF
*ARO++,RO
N
*AR1++,RO
RO,*AR1++
LDI
6,IOF
EXTD
DADR
.word
.word
.set
.word
.word
OBOBOOOh
OC53h
0400h
OBOOOOOh
0809800h
@OMA,ARO
@EXTO,RO
@OAOR,Rl
N,R2
@GLBL,R3
RO,*+ARO(4)
Rl,*+ARO(6)
R2,*+ARO(8)
R3, *ARO
393
I
XA(12:0)
ADDR(12:0)
MSTRB
CS
IEEE CONVERTER
T
M
5
3
2
0
C
3
0
H1
----
SRAM
8Kx32
OE
ClK
WAIT
XRDY
XD(31:0)
DA(31:0)
r--
DB(31:0)
DATA(31:0)
DIR
r-
WE
XRiW
OE
r-
r--
SN74AlS04
394
(4) SN74AlS245
8(S:1)
SN74AlS32
@-
G
A(S:1)
OIR
AOOR(12:0)
XA(12:0)
CS
MSTR8
IEEE CONVERTER
T
M
S
XFO
3
2 XO(31:0)
0
C
3
0
=D-
SRAM
SKx32
OE
OA(31:0)
WAIT
XROY
08(31:0)
f-
OATA(31:0)
ClK
H1
....--
OIR
WE
XRiW
.~
OE
SN74AlS04
395
TOO
TDI
INSTRUCTION REGISTER
TMS
TITAP
>---+---
TIP
TCK
TMS
The TMS input signal is clocked in by TCK. TMS controls the test mode of the device. Using
TMS and TCK, a test controller can scan registers through the device, perform tests, or place the
device in a normal functional mode.
396
TDI
The IDI input signal is used to input serial data through the registers in the device. All data
is clocked in by TCK and shifts according to the state ofthe test logic set up by an external test controller using TMS and TCK.
TDO
The IDO output signal is used to scan serial test data out of the device under the control of
the test host. While shifting data, TDO is active-shifting data out on the falling edge ofTCK. When
through shifting data, IDO is tri-stated.
TIP
TIP is an output indicating good or bad parity in the instruction register. The indication defaults to good if the external controller does not check for parity. To check parity, the test controller
places the device in the instruction register pause state. While in this state, the device will output
the actual (Le., hardware-determined) parity of the device's instruction register. A high logic level
indicates good parity, while a low logic level indicates bad parity.
Architectural Elements
TITAP
The Texas Instruments' Test Access Port (TITAP) is a 16-state state-machine designed according to the JTAG and IEEE-1149.1 specifications. The TITAP controls the test logic and is controlled by the TMS and TCK inputs to the device from an external test host controller.
Instruction Register
The Instruction Register is eight bits in length. Table 10 lists the instructions available for
this device.
Instruction
00000000
10000001
10000010
00000011
00000110
10000111
00001010
10001011
00001100
11111111
All Others
Boundary Scan
ID Register Scan
Sample Boundary Scan
Boundary Scan
Control Boundary HI-Z
Control Boundary 1/0
Read Boundary-Normal
Read Boundary-Test
Boundary Selftest
Bypass Scan
Bypass Scan
The Instruction Register is preloaded with 00000001 (msb-Isb) in the instruction register
capture state of the TITAP. This is not per the JTAGIIEEE-1148.1 standards.
TMS320C30 IEEE Floating-Point Format Converter
397
398
This instruction places the device in normal mode: all function inputs and outputs operate
in their normal modes. The bypass data register is selected in the data register scan path during data
register scans.
Boundary Data Register
The boundary data register contains 70 bits and is ordered according to Figure 22.
The Bypass Data Register is one bit in length and is operated in accordance with the JTAG/
IEEE-1149.1 specifications.
Scan References
Refer to the following documents for further descriptions of the test logic of this device:
1) A Test Access Port and Boundary Scan Architecture; Technical Sub-Committee of the
Joint Test Action Group (JTAG).
2) IEEE Standard 1149.1- IEEE Standard Test Access Port and Boundary-Scan Architecture.
399
400
401
402
Implementation of a CELP
Speech Coder for the TMS320C30
Using SPOX
Mark D. Grosen
Spectron Microsystems, Inc.
403
404
Introduction
Speech coders are critical to many speech transmission and store-and-forward systems. With
the emergence of universal standards, it is possible to develop systems that are interoperable. Quality and bit rate for speech coders vary from toll quality at 32 kilobits/second (kbps) (CCITT
ADPCM) to intelligible quality at 2.4 kbps (DOD LPC-lO). Recently, a new standard for 4.8 kbps
with near toll-quality has been proposed and is based on code-excited linear prediction (CELP)
techniques [1,2]. Unfortunately, products based on new coding algorithms are often slow to appear
because of the considerable time and effort required to develop real-time implementations.
The purpose of this article is to demonstrate how a CELP coder based on this new standard
can be quickly developed using SPOX. Utilizing the power of the TMS320C30 DSP plus the ease
of use provided by C and the SPOX DSP library, an efficient and portable coder can be written in
a much shorter period of time than that required by conventional assembly language methods. Because of the portability of SPOX andC, the coder can also be compiled and executed on a variety
of hardware platforms.
405
SYNTHESIZED
SPEECH
.'NDEH_Gf :--r=-J------J
CODEBOOK
~
I
FROM CHANNEL
DECODER
-+-
INPUT
SPEECH
LSP
CODES
-"I
I
I
I
r-------------------~ I
r-------.J
I
I
DELAY!
GAIN
INDEX!
GAIN
L ____ ,
I
I
I
I
r-J
TO CHANNEL
ENCODER
Bit allocations are given in Table 1 [2,4].
Table 1. 4.8.kbps CELP Parameters
Spectrum
Update
Parameters
Bps
30 ms (240 samples)
10 LSP
1133.3
Pitch
7.5 ms (60)
1 delay, 1 gain
1466.7
Codebook
7.5 ms (60)
1 of 1024 index, 1 gain
2000
Remaining 200 bps reserved for expansion, error protection, and synchronization
406
The standard also specifies an error protection scheme utilizing forward error-correcting
Hamming code and parameter smoothing.
The major computational parts of the algorithm are the pitch search and the codebook search,
both of which are performed four times per frame. An important technique to reduce the computations is the end-correction convolution technique (see Pitch and Codebook Search). This is a recursive convolution method that reduces the number of multiply-adds by an order of magnitude.
In addition, the codebook is designed to have approximately 75% of the samples equal to
zero. This allows many of the convolution updates in the codebook search to be reduced to a simple
shift of a vector of samples. On DSP processors with circular addressing, this shift can be replaced
by using circular buffers.
To further reduce complexity, the pitch search is limited in range for every other subframe.
During even-numbered subframes, the optimal pitch value is performed over the range 20 to 147
(128 values). On the odd subframes, the search is only over the range 16 from the previous pitch
value. This also decreases the bit rate with a negligible effect on speech quality.
If adequate processing power is not available, you can implement an interoperable coder by
using a subset of the full codebook. For example, if only the first 128 vectors from the codebook
could be used, the sub-optimal coder would work with an optimal coder if the same frame structure
and bit rate were used.
These techniques produce complexity estimates for the USFS CELP coder ranging from 5.3
MIPS to 16.0 MIPS for a 128-vector and 1024-vector codebook, respectively[4].
- printf(), seanf( )
- fopen(), fread( ), fwrite( )
Stream I/O to move data efficiently
Standard set of DSP math functions
- Filters
- Vector operations
- Windows
- Levinson-Durbin algorithm
Processor independence
Both FORTRAN and Cversions of the Version 2.3 USFS CELP coder were available as starting points for the real-time implementation. The initial development was done on a Sun workstaImplementation of a CELP Speech Coder for the TMS320C30 Using SPOX
407
tion equipped with SPOX/SUN [6] and the usual UNIX programming tools, such as the symbolic
debugger dbx. SPOX/SUN is a library of SPOX DSP math functions that can be used for developing SPOX applications on Sun workstations. The new version of the coder utilizing SPOX was
checked against the existing implementation for correctness. After the new version was debugged
on the workstation, the source code was recompiled employing the Texas Instruments TMS320C30
C compiler and linked with the SPOX;XDS library for the XDSlOOO development system.
The same facilities for testing the code on the workstation were available on the XDSIOOO.
A SPOX stream function (see Input/Output section) read digitized speech from a disk file. Status
information was printed to the console screen. Command line arguments were used to vary the encoder's parameters such as the codebook size.
The software development process for the USFS CELP coder followed three evolutionary
steps:
C program using standard I/O
C program using SPOX functions for faster math and I/O
C program using SPOX and assembly language optimizations
The first step was taken because an existing C implementation was available. The C standard
I/O provided by SPOX made it possible to run the application code written in C directly on the
XDSIOOO. For example, functions (fscanf( that read control information from a disk file on the
Sun also worked on the XDSIOOO using the PC's hard disk.
In general, it would have been easier to start with the SPOX library functions to implement
some of the common operations contained in the coder. Many of the functions needed (filtering,
correlation, dot-product) are in the SPOX DSP library. In this case, the C implementations ofthese
standard vector and filter functions in the existing program were replaced with the corresponding
SPOX functions. The SPOX functions, written in optimized assembly language, execute several
times faster than the corresponding C functions.
The last step was needed to meet real-time constraints. XDS 1000 timing capabilities allowed
the identification of two time-critical sections of the code which were then rewritten in
TMS320C30 assembly code. Since the interface to the SPOX math functions is open, new math
functions can be written that work with SPOX data structures such as vectors and filters.
Implementation
Several major parts of the USFS CELP encoder are implemented with a mixture of C, SPOX,
and TMS320C30 assembly language functions. The decoder can be easily constructed from the
material presented here. An adaptive postfilter for the decoder is not described here.
The framework of the resulting encoder is shown in Figure 2. A description of the major
functions performed can be found in the following sections. Appendix A provides a short summary
of the SPOX functions employed in the next four sections (Input/Output, Spectrum Analysis, Filters, and Pitch and Codebook Search).
408
) {
/*
*/
SV_a2lsp(invcoeffs, lsps);
quantizeLSP(lsps, qntzlsps);
SV_lsp2a(qntzlsps, invcoeffs);
/*
packParams();
SS~ut(outstream,
Input/Output
Input speech samples are obtained by employing a function (SSJet( which reads data
from a named stream (instream). The creation of instream during program initialization determines the source of the data. During development, the easiest source is a disk file with digitized
speech. When real-time testing is needed, a codec connected to a TMS320C30 serial port could be
utilized. For example, instream could be created to read from standard input with the following
code segment.
#define FRAMESIZE
240
* sizeof(Float)
The output stream (outstream) consists of the packed frame parameters. It could also go to
a disk file or a serial port by using SSJ>ut().
Spectrum Analysis
After preconditioning the signal with a highpass filter (see the Filters section), the coefficients of the short term prediction filter can be found by using the function calcuIateLP( ) shown
below.
Implementation of a CELP Speech Coder for the TMS320C30 Using SPOX
409
The vector window is initialized to contain the desired window; in this case, a Hamming window is used. The autocorrelation terms are stored in the vector cor that has the same length as the
order of the short term filter. SV_autorc() uses a Levinson-Durbin type algorithm to compute the
inverse filter coefficients. As a side effect, the reflection coefficients are also stored in rc. Finally,
a IS-Hz bandwidth expansion is produced by the multiplication of the inverse filter coefficient vector by a vector (gammavec) consisting of the terms
g[i]
= 0.994 i
for i
= 0,
1, . ,
m-1
Filters
Three filters in the encoder can be realized by use of SPOX filter objects. The inverse filter
A(z) and the short term predictor l/A(z) share the same fiitercoefficients. The former is an FIR filter
and the latter an all-pole filter. The final filter is the all-pole weighting filter W(z) with coefficients
given by l/A( f... z), with f... = 0.8.
During the initialization of the encoder, the filters are created with the code fragment shown
below.
#define FILTERSIZE
SF Filter
SV-Vector
SA=Array
11 * sizeof(Float)
invfilter, predfilter, wgtfilter;
invcoeffs, wgtcoeffs;
array;
410
Note that the inverse and prediction filters are both bound to the same coefficient vector. For
each new frame of speech, this vector is updated when it is passed to calculateLP().
An important consideration is that the filters are used more than once during a frame. A different signal is filtered each time, but the state (history) of the filter must be the same. This is accomplished before each filter operation by using the
o SF_getstate() function to recover a vector with the state of the filter at the end of the previous frame
SF_setstate() function to restore the filter's state
The following code segment shows how the short term prediction residual is generated for
the pitch search.
SF setstate(predfilter, NULL, predstate);
SV-fill(residual, 0.0);
SF=apply(predfilter, residual, residual); /* zero input of filter */
SV_sub3(residual, speech, residual);
/* speech - history */
Ii
h
(WEIGHTING FILTER
IMPULSE RESPONSE)
r
(RESIDUAL)
ERROR
i----...-__+ GAIN
CODEBOOK
The search in Figure 3 minimizes the distance between the input vector and one of many generated vectors. The quantity being minimized is the Euclidean norm:
Implementation of a CELP Speech Coder for the TMS320C30 Using SPOX
411
e =
II r-r W
= r' r -
2 r'
r + r'
(1)
r
where
r
lation of rand r and the energy of r ;' this is because the energy of the original residual is invariant
over all the generated residuals. It appears that there would be N convolutions and 2N dot products
to perform for each sub-frame. Implemented directly, the codebook search would thus require 66
MIPS if N =256 and a sub-frame length of 60 are specified.
Instead, the USFS CELP coder uses a specially structured codebook that greatly reduces the
computational load. The biggest savings comes from the elimination of all but one of the convolutions for each subframe. The codebook is overlapped, as shown in Figure 4.
Figure 4. Structure of Overlapped Codebook
~~
X3
ESt
X2
X1
XO
This. structure permits a recursive convolution computation. The first code book vector is
convolved normally with the weighting filter. Subsequent convolutions, however, make use of the
following relationships.
(2)
where R;(z) is the Z-transform of the generated residual. Given the convolution of the previous codebook vector with the weighting filter, the convolution employing the next vector can be
found with only 120 (2 x 60) multiplies and adds.
This number can be further reduced by another property of the codebook. The vectors are
generated by center-clipping a gaussian noise source, which causes approximately 75% of the elements to be zero. Thus, 75% of the updates to the convolutions require no multiplications or additions; however, the convolution elements must still be shifted. The following function update( )
implements the recursive update operation. Note that it must be called twice per codebook vector,
once for each new term.
412
len
SV_getlength(res);
rptr = (Float *) SV_loc(res, len - 1);
rptrrnl = rptr
1;
if ( x == 0.0 ) {
for (; len> 1; len--) {
*rptr- - = :*rptrrnl--;
}
*rptr
0.0;
else {
/* update using new input */
wptr = (Float *) SV_loc(wgtirnpulse, len - 1);
for (; len> 1; len--) {
*rptr-- = *rptrrnl-- + x * *wptr--;
*rptr = x * *wptr;
Once the convolution has been determined, the corresponding error and gain can be found.
The following function calculates the error and gain terms.
Float error(res, reshat, gain)
SV Vector
res, reshat;
Float
*gain;
Float
cor, energy;
The codebook search function with update( ) and errore ) functions is shown below. The
first convolution must be calculated directly, so it is done outside of the main for loop. The error
for each entry is compared against the current maximum; if it is greater than the maximum, this
entry becomes the new best vector. The process is repeated for each of the N vectors.
codebook, wgtirnpulse;
codeSearch(res, reshat)
SV_Vector res, reshat;
Float
Float
Int
findlrnpulse(wgtirnpulse);
SV_setbase(codebook, FIRSTVEC);
convolve (codebook, wgtirnpulse, reshat);
errrnax = error(res, reshat, &gain);
413
best = 0;
cbptr = (Float *) SV_loc(codebook, 0) - 1;
for (i = 1; i < N; i++) {
update(*cbptr--, reshat, wgtimpulse);
update(*cbptr--, reshat, wgtimpulse);
if ( (err = error(res, reshat, &gain)) > errmax ) {
errmax = err;
best = i;
After the search is completed, the gain of the best vector is recomputed and quantized. The
corresponding gain index and index of the codebook element can then be readied for transmission.
414
* Synopsis:
*
*
*
*
*
#include <sv30.h>
FP
.set
ar3
.global _update
.text
_update:
push
ldi
*
*
*
FP
sp, FP
*
*
*
ldi
SV_getl
ldi
SV_get2
*-FP(2), ar2
ar2, SV LOCO, arO
*-FP(3)-; ar2
ar2, SV_LENlsV_LOCO, rc, arl
ldf
bzd
subi
addi
ldi
*-FP(4), rl
shift
1, rc
rc, ar1
arl, ar2
*
x
x is 0 so just shift
1]
1]
11
addi
subi
rc, arO
2, rc
mpyf
addf
r1, *arO--, r2
r2, *--ar2, rO
x * wgt[i]
rptb
mpyf
addf
20 :
stf
lp20
rl, *arO--, r2
r2, *- -ar2, rO
rO, *ar1--
bud
stf
mpyf
stf
*
* Case for x
*
shift:
subi
Idf
slp:
II
rptb
ldf
stf
stf
ldf
stf
end:
pop
rets
x * wgt[i]
end
rO, *arl-rl, *arO, rO
rO , *arl
--
res[O]
x*wgt[O]
0.0
2, rc
*--ar2 I
slp
*--ar2, rO
rO, *ar1-rO, *ar1-0.0, rO
rO, *ar1
loop 1 - 1 times
prime the pipe
rO
final store
first term = 0.0
FP
415
Performance
A complete CELP encoder was implemented as described above. Two versions were tested:
One encompassing C and standard SPOX functions
One having C, SPOX, and two custom TMS320C30 assembly language functions
Table 2 shows the execution times for different combinations of codebook size, processor,
and implementation. To achieve near real-time performance for a codebook with 128 vectors, the
codebook and pitch search functions were completely rewritten in assembly language. Each function required approximately 130 lines of assembly code.
Sun (C/SPOX)
16,000
24,000
IDS
IDS
C30 (C/SPOX)
C30 (C/SPOX/ASM)
88.2 IDS
114.6 IDS
39.0 IDS
54.3 IDS
Memory requirements for the program on the TMS320C30 were approximately 14,000
words for instructions and approximately 6,000 words for data. The application code required approximately 4500 words of instructions. The SPOX operating system and DSP math functions consumed the remaining 9500 words of memory. This figure reflects many functions that are essential
for easing development but unnecessary for a real-time implementation.
Once a real-time implementation has been achieved, the SPOX memory requirements can
be greatly reduced by porting (or customizing) SPOX to a custom hardware implementation. In this
case, the SPOX memory requirements can be reduced to approximately 4000 words, making a
12K-word implementation feasible (both data and instruction memory requirements).
These timings show that a real-time CELP coder can be implemented on a single
TMS320C30. They also illustrate the power of the TMS320C30 compared to a standard microprocessor. Note that a TMS320C30 implementation has approximately 500,000 instruction cycles
available in a 30-ms frame.
Version 3.0 of the USFS CELP coder has significant improvements in computational complexity, including:
Ternary codebook to eliminate multiplications
Shorter codebook
Faster LSP conversion and quantization
Work to bring the SPOX implementation up to Version 3.0 is continuing. An investigation
of a two-processor implementation is also being performed.
416
Summary
A 4.8-kbps CELP coder based on a Department of Defense-proposed standard has been implemented on a TMS320C30. Several of the functions used in the encoder were illustrated. A suboptimal implementation of the encoder using a 128-vector codebook is possible on only one
TMS320C30. Work is continuing on both the algorithm and the software implementation to improve the coder's real-time performance.
With SPOX, the encoder was developed in less than one month. The resulting source (with
the exception of two TMS320C30 assembly language functions) can be compiled and run on a Sun
workstation, a PC, or a TMS320C30 system such as the Texas Instruments XDS1000. This represents a considerable improvement in development time and effort over previous implementation
methods.
References
1)
2)
3)
4)
5)
6)
7)
8)
Kemp, D.P., Sueda, R. A., and Tremain, T. E., "An Evaluation of 4800 bps Voice Coders," Proceedings of ICASSP '89, IEEE, May 1989.
Campbell, J. P., Welch, V. c., and Tremain, T. E., "An Expandable Error-Protected 4800
bps CELP Coder," Proceedings of ICASSP '89, IEEE, May 1989.
Atal, B. S., and Schroeder, M. R., "Stochastic Coding of Speech at Very Low Bit Rates,"
Proceedings of ICC '84, pages 1610-1613, 1984.
Tremain, T. E., Campbell, J. P., and Welch, V. c., "A 4.8 kbps Code Excited Linear Pre- .
dictive Coder," Proceedings ofMobile Satellite Conference, pages 491-496, May 1988.
Texas Instruments, Inc., Third-Generation TMS320 User's Guide, 1988.
Spectron MicroSystems, Inc., SPOX/SUN User's Guide, April 1989.
Soong, F. K., and Juang, B. H., "Line Spectrum Pair (LSP) and Speech Data Compression," Proceedings of ICASSP '84, pages 1.10.1-1.10.4, IEEE, 1984.
Spectron MicroSystems, Inc., Adding Math Functions to SPOX, March 1989.
417
Appendix A
The SPOX functions used in the code examples are briefly described below. Complete descriptions can be found in Getting Started With SPOX and the SPOX Programming Reference M anual. These manuals are supplied with the XDSIOOO. They are also available from Spectron MicroSystems, Inc.
Stream Functions
Ss_get - get data from a stream into an array
lnt SS get(stream, array)
SS=stream
stream;
SA_Array
array;
SS_put - put data from an array to a stream
lnt SS_put(stream, array)
SS_Stream stream;
SA_Array
array;
Vector Functions
sv_autorc - perform inverse filter calculations
void SV_autorc(cor, inv, rc, alpha)
SV vector
cor;
SV-Vector
inv;
SV-Vector
rc;
sv=vector
alpha;
SV_corr
418
SV window
Filter Functions
SF_apply - apply a filter to a vector
SV_Vector SF_apply(filter, input, output)
SF Filter
filter;
Sv-vector
input;
SV-Vector
output;
SF_bind
419
420
Part V. Computers
12. A DSP-Based Three-Dimensional Graphics System
(Nat Seshan)
421
422
A DSP-Based
Three-Dimensional Graphics System
Nat Seshan
Digital Signal Processor Products-Semiconductor Group
Texas Instruments
423
424
This application report is based on the author's bachelor's thesis at the Massachusetts Institute of Technology.
The placement of a high-performance computational engine, such as an advanced digital signal processor, between the host processor and the video controller in a graphics system can improve
performance tremendously. Several factors make the Texas Instruments TMS320C30 Digital Signal Processor well-suited to this task:
32-bit floating point arithmetic provides both high-resolution and large dynamic range in
calculation.
.. Single-cycle, 60-ns instruction execution and parallel bus access greatly improve system
throughput.
A hardware single-cycle multiplier facilitates the matrix arithmetic, which is frequently
required in 3D graphics.
The ease of programmability allows the design of flexible and expandable systems.
Software tools, such as simulators[1], assembler/linkers[2], and high-level language debuggers/compilers[3], decrease product development time.
In-circuit scan-path emulators[4], decrease hardware prototyping and debugging time.
The use of a standard device lowers the overall system cost.
With the use of the TMS320C30, the host processor can request higher-level commands of
the rest of the system. Instead of issuing requests for line-draws or screen clears, it can, for example,
request that a 3D object be rotated 90 degrees and then be redrawn. In addition, a rendering element
(usually a video controller or graphics system processor) can devote its resources solely to screen
management rather than doing some portion of the computationally intensive processing. The following pages provide a description of how a 3D graphics system used the TMS320C30 to compute
object transformations.
The digital signal processor resides on the TMS320C30 Application Board (C30AB) designed for the IBM PC/AT or compatible. The PC's 80x86 acts as the host processor and communicates to the C30AB through an 8-bit bus slot. Also resident on the bus is a Texas Instruments
TMS34010 Software Development Board (SDB)[5,6]. The SDB contains a TMS34010 Graphics
System Processor (GSP) [7], which manages the screen memory and drives the video display.
Overall, this system is meant to serve as an instructional model of how a graphics system can be
designed using an advanced digital signal processor.
425
4)
A rendering engine to control the video memory and to drive the video display.
These four tasks are common to many graphics systems, whether they be intended for CADI
CAM, fractal graphics, heads-up displays in fighter aircraft, or Postscript printer control. If one or
more processors are assigned to each function, the resulting pipeline will achieve greatly improved
system throughput.
In a single-processor system, the CPU is directly responsible for all computations. It must
write to video memory, perform all necessary computations, interface to the user, and manage all
data storage and recovery. Although additions to the system, such as a video-memory controller
or a floating-point coprocessor, may speed up the system, the CPU remains overly burdened as the
only intelligent component of the system.
A Multiprocessor Pipeline
Adding more links in the graphics pipeline can further relieve the CPU of burdensome tasks.
Performance improvements result from each stage being optimized for a particular function. In addition, throughput increases with the number of stages. The pipeline may also contain multiple processors running in parallel at a particular stage to further improve the latency of that stage. Figure
1 shows a full-scale implementation of a graphics pipeline for 3D graphics.
426
TRANSFORM
ENGINE
CLIPPING AND
)+----1 PERSPECTIVE 1----+1
ENGINE
LIGHTING
ENGINE
DIGITAL
SIGNAL
PROCESSOR
GENERAL
PURPOSE
CPU
<>
GRAPHICS
SYSTEM
PROCESSOR
In a large-scale graphics pipeline, the host processor runs the applications program. The user
may be trying to use a CAD program, model the formation of galaxies, animate 3D objects, etc.
The host runs these programs at the top level, provides the user interface, and communicates to all
I/O devices, including mass storage systems. For numerically intensive applications it may be appropriate to have a digital signal processor as this host. For example, modeling the formation of
galaxies requires numerical solutions to systems of differential equations. But even in such a case,
it would be reasonable to have a more general-purpose CPU act as a user front end to the digital
signal processor.
The purpose of the object manager is to communicate with the host by receiving data and
transferring it to other processors in the system. It manages the global representation of all screen
parameters and objects. A Reduced Instruction Set Computer (RISC) processor would be
well-suited as either the host or the object manager because of its high-performance general-purpose architecture.
Because a DSP has a highly parallel architecture, a fast execution cycle time, an instruction
set optimized for numerical processing, and several development tools, it would perform well as
any of the computational stages in a graphics pipeline. For example, a DSP could act as a transform
manager that calculates the new universal coordinates of globally stored objects according to rotaA DSP-Based Three-Dimensional Graphics System
427
tion, translation, and scaling commands from the object manager. Also, the DSP could act as a lighting manager that accepts parameters of environmental lighting settings from the object manager
and applies them to the transformed objects. For example, the user may set ambient intensities as
well as other sources of varying geometries, intensities, and colors. The lighting manager then applies these light sources to the surfaces of the objects, which may have varying degrees of specular
or diffuse reflection, to compute the necessary shading.
Although the perspective and clipping stage of the system is represented in Figure 1 by a
single processing unit, the task may be further partitioned to several DSPs working in series. The
perspective calculation takes viewing parameters from the object manager, such as direction of
view, location of viewer, and zoom, and produces a two-dimensional projection for the screen. Objects that are too high, too low, or too far right or left can be clipped automatically because the resulting two-dimensional coordinates are off screen. However, clipping objects fully or partially obscured by other objects may require additional stages. Also, objects behind the viewer and those
too far away for the user to recognize should be clipped appropriately.
Although digital signal processors are well-suited to be the computational stages of a graphics pipeline, a processor optimized to be a rendering engine might serve better to drive the video
display and manage the video memory. Such a processor could also help with the clipping tasks
described above. A z-buffer could hold the transformed z-coordinate of each pixel that is projected
on to the x-y plane of the screen to facilitate hidden surface removal. Adevice such the Texas Instruments TMS34010 or the recently introduced TMS34020 could serve as the rendering engine in a
full scale system. Both these processors have 32-bit general-purpose architectures with instruction
sets and external memory interfaces optimized for graphics.
IBM PCXT
BUS
INTEL 80X86/7
428
TRANSFORM
AND
PERSPECTIVE
TI TMS320C30
TITMS34010
One strength of this system is its complete use of standard, commercially available parts. In
general, use of standard parts allows for faster design and manufacturing, as well as a more reliable,
easier-to-support product. Even the three hardware subsystems can be found on the market:
1)
2)
3)
Another strength of this system is the complete use of portable software. Use of portable software often speeds design times because system software can be mostly debugged before the actual
target hardware is available. All software for this system was written in Kernigan and Ritchie C.
The command and rendering routine was first debugged on the PC and GSP with the intermediary
stage removed. Once debugged, the computationally intensive portion of the software was ported
to the DSP, which then assumed control of the GSP. The software on the TMS34010 SDB used
many of the graphics routines in the TMS34010 Graphics/Math Library. These routines have been
used in many other graphics systems using the TMS3401O.
System Hardware
The IBM PC was chosen as the host because of its extensive support by TI development tools.
In addition, a large amount of documentation is available concerning interfacing to the PC bus. The
system described in this report is designed to run best on an 80386-based IBM PC compatible with
an AT power supply and an 80387 floating-point coprocessor. However, either Intel 8086 or 80286
general-purpose microprocessors can also act as the host to the computational engine. The host
computer sends commands to
Load and delete objects
Target an object for adjustment
Adjust a particular object
Recalculate the perspective or
Redraw the screen.
The 80X87 floating-point coprocessor is not absolutely necessary but greatly improves the
time to generate floating-point parameters for the next stage.
This graphics demonstration was the first application developed using the TMS320C30
Application Board (C30AB). Since that time, the C30AB has been included as a part of the
XDS1000 emulation system for the TMS320C30 Digital Signal Processor. The TMS320C30's features include
60-ns single-cycle execution time (more than 33 MFLOPS)
2K x 32-bit dual-access RAM
4K x 32-bit dual-access ROM
64 x 32-bit instruction cache
Two 32-bit external memory expansion buses
Single-cycle floating-point multiply/accumulate
1\vo external 32-bit memory ports
A DSP-Based Three-Dimensional Graphics System
429
The TMS320C30 executes commands from the 80X86 to transform objects, load objects into
or delete objects from the system, and compute the projection oOD objects on the 2D screen. When
given a directive to draw the screen, it sends a command to the rendering engine to clear the current
screen. Then, the TMS320C30 transfers lists oflines, points, and polygons for the next stage to render.
The TMS34010 Software Development Board (SDB) has been used in TMS34010 development support since 1987. It is configurable for a variety of monitors. The board supports the
TMS34010 Graphics/Math Function Library [8] (a library of high-level routines callable from any
C program). This board was slightly modified to receive commands from the C30AB as well as
from the PC host. Program loaders, C compilers [9], assemblers, and C language standard I/O library support have been developed for this board, as well as for the C30AB. Both cards interface
to an IBM PC through an 8-bit slot on the AT bus. The TMS34010 GSP on the SDB is an advanced
high-performance CMOS 32-bit microprocessor optimized for graphics display systems. Its key
features include:
160-ns instruction cycle time
FuIJy programmable 32-bit general-purpose processor with a 128M-byte address range
Pixel processing, X-Y addressing, and window clip/pick built into the instruction set
Programmable pixel size with 16 boolean and 6 arithmetic pixel processing options (Raster-Ops)
31 general purpose 32-bit registers
256-byte LRU on-chip instruction cache
Direct interfacing to both conventional DRAM and multipart video RAM
Dedicated 8116-bit host processor interface and HOLD/HLD interface
Programmable CRT control (HSYNC, VSYNC, BLANK)
FuII line of hardware and software development tools, including a C compiler
The TMS34010 GSP receives commands from the TMS320C30, along with arrays of points,
lines, and filled polygons to be drawn. It then uses library routines to render these images on the
video display.
430.
System Limitations
The system described here is an instructional system built in a limited development time. Aspects of the system could be optimized for speed and for memory usage. A high-speed 3D graphics
system has many features that were not implemented.
This design is non-optimal in several ways. The C routines could be hand-coded to execute
faster. A 32-bit host bus interface would allow word-at-a-time data transfers to the TMS320C30.
The GSP could be interfaced to faster video memory. At the time of this writing, the TMS34020
second-generation graphics system processor is available. The entire TMS320C30 program could
be configured to run from internal memory. Many of these optimizations were not realized because
of the limited time available for developing the system.
Many operations that an advanced digital signal processor could easily perform were not designed into this system. These tasks include curved and textured surface generation, lighting, shading, and front and back clipping. For demonstrative purposes, only the endpoint transformation and
perspective calculations were implemented.
Similarly, the capabilities of the GSP are clearly underutilized in this pipeline. The GSP is
adept at managing multiple windows for display. It can also display text in various fonts. The presented system simply requires that the GSP manage a single graphics-only (no text) window.
431
larly, SX, sy, and sz determine the scale of an object. These factors determine how many units of
the untransformed object's coordinates are represented by one unit of the transformed object's
coordinates. The three parameters shown in Appendix Listing 1 that represent all possible orientations of an object (theta, phi, and omega) are described in Table 1.
Table 1. Angles of Rotation
Angle
Axis Rotation is
Around
Direction of
Positive Rotation
Zero Value
x to y
Positive x-axis
(J)
y to z
Positive y-axis
<j>
z to x
Positive z-axis
Hierarchy
The final array contained within an object (the parent object) is a list of pointers to child objects defined with respect to the transformed frame of the parent. The number of potential internal
objects, MAXOB, sets the static size of the array of pointers to child objects. (In this implementation, MAXOB =10.) In addition, the parameter obnum keeps track of how many of these potential
child objects are utilized. The final bookkeeping parameter is subnum. If subnum equals n, then
the object was the nth object pointed to in its parent object's child-object array.
432
EARTH
MERCURY
OBNUM=O
SUBNUM=1
OBNUM=1
PLUTO
00000
OBNUM=1
SUBNUM=3
SUBNUM=9
MOON
CHARON
OBNUM=O
OBNUM=O
SUBNUM=1
SUBNUM=1
1
The solar system (Figure 3) represents a classical example of a hierarchical structure. The
sun slowly revolves around the galaxy. Wherever the sun travels, the planets follow in the same
frame. In turn, each planet may have satellites that revolve around them. The planet is defined with
a certain offset (radius of orbit) from the sun, and the satellite is defined similarly with an offset
from the planet. To describe the movement ofthe earth over a period of time, you need only to adjust
for its revolution around the sun and the revolution of the moon around the earth. You do not need
to describe the rotation of the moon around the sun because when a planet is moved, its satellites
automatically move with it.
Transformation parameters are referenced to the frame of the object's parent. Thus, to fully
describe a planet orbiting the sun, one must define an empty frame revolving about the sun at some
offset, and then define a planet within that frame rotating about some axis. The levels of abstraction
within this hierarchy give this data representation its power.
The flexibility of the object structure permits the system to model the viewer. The viewer
is considered to be at the absolute origin of the system. At system initialization, the first object
loaded is the universal object *universe. An appropriate choice for such an object would be a set
of axes. The view is then adjusted by modifications to the parameters of the *universe:
dx, dy, dz
sx, sy, sz
433
These three sets of parameters respectivel y represent the position of the origin of the universe
with respect to the viewer (viewing position), how much the view is magnified to the user (zoom),
and where the origin is with respect to the user (pan).
Transformations
Transformations of locations in 3D space can be reduced to four-dimensional matrix arithmetic[10]. A location in space can be represented by a four-dimensional row vector (x y z 1). When
this vector left-multiplies any 4-by-4 transformation matrix, the resulting row vector represents the
transformed point. Tables 2, 3, and 4 illustrate the 4-by-4 transformation matrices for rotation
around each axis.
Table 2. Z-Axis Rotation Matrix
cos
-sin
0
0
sine
cos
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
cos
0
sin
0
0
1
0
0
-sin
0
cos
0
1
0
0
0
0
cos
-sin
0
0
sin
cos
0
It can be shown that these matrices can be used to account for a rotation about any arbitrary
axis passing through the origin. The transformation matrix shown in Table 5 corresponds to scaling
a location by (sx, sy, and sz) and then moving it by (dx, dy, and dz).
434
sx
0
0
sy
dx
dy
0
0
sz
dz
0
0
0
1
The arbitrary transformation of a frame can be defined by a matrix resulting from a multiplication of a subset of the above transformation matrices. However, this multiplication is in general,
not commutative. That is, rotating around the x-axis and then translating is not the same as translating and then rotating about the x-axis. By sending values for the nine parameters, the host can request the adjustment of an object. However, this system defines these operation as always taking
place in the order below:
1) Scale object by (sx, sy, and sz)
2) Translate object by (dx, dy, and dz)
3) Rotate object around z-axis by theta.
4) Rotate object around x-axis by omega.
5) Rotate object around y-axis by phi.
When the matrices shown in Tables 2 through 5 are multiplied, the resulting matrix always
contains (000 I)T as its final column. Thus, to denote an arbitrary transformation, you need only
remember the first three columns of the composite matrix. If you were to apply the transformations
in the order stated previously, the resulting equations in Table 6 would determine the element of
the transformation matrix R.
435
(2.2)
r13 = szsinQ
(2.3)
(2.4)
(2.5)
(2.6)
(2.7)
(2.8)
(2.9)
(2.10) .
(2.11)
(2.12)
Note that there also exists a matrix p[3][4] (see Listing 1 in the Appendix) that represents
the product of all the ancestral transform matrices of an object and that object's R matrix. This matrix represents the object's transformation from the absolute origin of the system.
loaded into the system to calculate the transformed location of the point. Therefore, as the transformation and the projection on to two-dimensional co-ordinates are done in one step, the original 3D
coordinates can be retained and only the final modified two-dimensional screen representation
need be updated. The point of view can simply be modified by adjusting the *universe as one would
adjust any other object. Overall, the hierarchical object structure provides a powerful and flexible
way to manage graphical data.
Initialization
As its first initialization task, the PC maps the dual-port SRAM of the C30AB into its address
space by writing the 8 MSBs of address to the mapping register. It then brings the C30AB out of
reset by writing a 1 to the SWRESET in the C30AB's control register. The PC then loads the
TMS320C30 application program into the dual-port SRAM. Loader support software on the
C30AB EEPROM moves the code to the proper location in the TMS320C30's address space. Finally, the PC switches the TMS320C30's memory map into run mode to start program execution. The
first part of the main routine initializes the system (see Listing 8 in the Appendix).
For the system software to run properly, the DSP software must initialize several different
items.
1)
2)
3)
In
1)
2)
3)
4)
It sets the external flag bit on the C30AB target connector to transfer control of the rendering system from the PC to the C30AB (This assumes that the PC loaded the rendering
software before it started up the C30AB).
It configures both the primary and the expansion bus with zero software wait-states.
Thus, all wait states are generated by the address-decoding PALs on the C30AB.
addition, the linker configures
Primary bus SRAM as program storage
Expansion bus SRAM as heap memory allocation
Zeroth page of internal RAM as space for system constants
First page of internal RAM as the system stack. This configuration maximizes the potential for parallel data and instruction accesses
437
The initialization procedure then appropriates several local variables for system use, including
1)
2)
3)
The TMS320C30 initially sets the contents of these GSP registers to indicate that the computational stage does not have any requests of the rendering stage.
The TMS320C30 system software contains the global variables shown in Listing 7 oftheAppendix. The dual-port SRAM pointer dual_port is initialized to point to the lowest location on the
I/O expansion bus. This pointer points to an integer array that contains all data and command from
the Pc. Another pointer to the currently targeted object (*to) is set to reference the universe. The
*universe is set as its own parent with an obnum of 0, indicating no internal objects are loaded.
During the final part of initialization, the C30AB software waits for the PC to load the static
*universe object. To understand how the PC loads objects into the system, you must comprehend
the general communications protocol between the TMS320C30 and the 80X86.
6)
7)
The PC waits for the dual-port SRAM to become free by polling the ACKNOWLEDGE word for a zero.
The PC loads all command parameters into the dual-port SRAM.
The PC then loads the appropriate command byte into COMMAND.
Once the TMS320C30 returns to its command detection loop, it acknowledges a received command by writing the same byte into the ACKNOWLEDGE word.
The PC sees that the TMS320C30 has acknowledged the command and writes OOh into
COMMAND to withdraw its command. The PC thereby relinquishes control of the
dual-port SRAM.
The TMS320C30 reads all necessary p&rameters into its main memory.
The TMS320C30, by writing a zero to the ACKNOWLEDGE word, indicates that the
PC can request another command. This returns the sequence
to step (1).
.
.
The TMS320C30 treats all of its data types as 32-bit values, but it can read only one byte of
valid data from the dual-port SRAM. Thus, the TMS320C30 must mask and concatenate the bytes
that the PC maps into contiguous locations to form multibyte words. In addition, since Intel and
438
the TMS320C30 have different standards, floating-point values from the PC must be converted before the TMS320C30 can use them.
The TMS320C30 can receive either unsigned 8-bit chars or unsigned 16-bit short integers
from the Pc. The macros shown in Listing 6 of the Appendix are used to access thes'e data types
from the dual-port SRAM. The DPLONG macro takes a certain location in the dual-port, finds the
short integer located there, and concatenates it into a 32-bit value for the TMS320C30. The word
LONG in the macro indicates all integers whether chars, shorts, or longs are represented as 32-bit
values by the TMS320C30.
Table 7. Comparison ofIntel and TMS320C30 32-Bit Floating-Point Formats
Standard
Exponent
Field Bits
Exponent
Format
Sign
Bit
Mantissa
Field
Mantissa
Format
TMS320C30
Intel
31-24
30-23
mo's Complement
Offset Binary
23
31
22-0
22-0
Two's Complement
Magnitude
Table 7 illtistrates the differences between the TMS320C30 and the Intel single-precision
floating-point formats. For every floating-point value that the TMS320C30 receives, it must extract the appropriate fields, convert the fields to the appropriate numerical representation, and then
reassemble the fields in TMS320C30 floating-point format. The dpfloat routine shown in Listing
9 of the Appendix uses the union structure flIong shown in Listing 6 ofthe Appendix to allow manipulations normally available only for integers on the floating-point value. The program first concatenates the four-byte value in the dual-port SRAM into a single 32-bit integer and then converts
this word to TMS320C30 format.
439
space for the location, point, and line arrays. Because the size of each polygon varies, space is allocated as each polygon is read.
After allocating global space for the new object and loading the locations, the TMS320C30
requests more data from the PC. It first requests the points, then the lines, then each polygon. The
dual-port SRAM limits the primitive arrays to 2047 points and 1364 lines. In addition, each polygon is limited to 4092 vertices. The TMS320C30 makes a data request by replacing the current
COMMAND byte that it wrote in ACKNOWLEDGE with 127, the flag for the PC to load more
data. Although the roles of ACKNOWLEDGE and COMMAND are reversed in this case, the
TMS320C30 requests data in much the same way the PC requests commands. Once the
TMS320C30 completes loading the object, it selects the object as the new target object. Finally,
using the equations in Table 6, the TMS320C30 calculates the initial value of the object's transformation matrix.
The target object is the object in the hierarchy selected for adjustment, deletion, or calculation
of screen coordinates. The PC can either target an object's parent or one of the object's child objects.
The command to target a child requires the PC to specify either the child object's sibling number
or subnum. Thus, when selecting objects for adjustment, the PC must remember where it loaded
objects into the hierarchy.
To adjust the transformation parameters of a given object, the PC simply loads the new parameters into the dual-port SRAM. The TMS320C30 adds the values of the new angles of rotation
and translation factors to the previous ones. In addition, the TMS320C30 multiplies the old scaling
factors by the new ones. Then, the TMS320C30 calculates the transformation matrix of the object
by using the equations in Table 6. It does not recalculate screen locations, however, until this is specifically requested by the pc. The TMS320C30 can thus avoid calculating screen coordinates until
all adjustments have been made.
Once the PC requests all the changes for a frame on the display, it requests recalculation of
screen coordinates at each node it changed. The PC can request recalculation for a particular object
and thus update its internal objects as well. This allows the TMS320C30 to avoid recalculating
screen coordinates of unchanged locations. For maximum efficiency, the PC must request recalculation in the highest node that it adjusted along any particular path. Thus, in the planetary example
given earlier, if, in a period of time, only Pluto and its moon Charon were moved (the other bodies
miraculously standing still), only Pluto would need to be targeted for recalculation.
To calculate transformations, the TMS320C30 multiplies the object's transformation matrix
by its parent's parent transformation matrix to obtain its own parent transformation matrix, p[3] [4].
The TMS320C30 right-multiplies all locations within that object by this matrix to achieve the
transformation from the absolute origin of the system. The computational engine calculates perspective by dividing the transformed x- and y-coordinate by the transformed z-coordinate so that
locations farther away appear closer together. The plane z=O is defined to be the plane of the screen.
This also has the feature that objects behind the viewer appear upside-down in front of the viewer
because the objects' z-coordinates are negative. Thus, the program running on the PC must maintain all objects in front of the viewer. Then, the TMS320C30 recursively executes this procedure
for each object within the targeted object.
Unlike the recalculation of screen coordinates, the redrawing of objects is done for all objects
within the system. Thus, the draw_object routine is called with the *universe as the argument. The
440
precise manner in which the TMS320C30 uses this program to redraw the screen is described in
the TMS320C30 Drawing Routine Section found later in this report.
441
The TMS34010 architecture supports a variety of pixel sizes, frame buffer sizes, and screen
sizes. On-chip functions have been carefully selected so that no functions tie the TMS34010 to a
particular display resolution. This enhances the portability of graphics software and allows the
TMS34010 to adapt to graphics standards such as MIT's X, CGIICGM, GKS, NAPLPS, PHIGS,
and other evolving industry and display management standards,
442
R i
Bj
RiGiBjlj
TMS34070
COLOR
PALETTE
DOTCLK
DIGITAL
INTERFACE
f-i~
DRAM
512K
BYTES
VRAM
128K
BYTES
+
CONTROL
BUFFER
PROM
1K BYTES
OPTIONAL
VRAM
128K
BYTES
...
DATA
TRANSCEIVER
ADDRESS
LATCH
AND
DECODE
USART
DATA
ADDRESS
VIDEO SIGNALS
T
1
LAD
1
0
<t
J:
oJ,
..J..J
<to
00::
01..JZ
0
0
<t
l<:
J:
..J
>
!z
VIDEO
TIMING
I--
J:
oJ,
I-
en
J:
J:
<t
~ I
CLOCKOUT
..r
8<t
..J
SYSTEM
CLOCK
TMS34010
HDATA
ADDRESS
DATA
HOST
INTERFACE
CONTROL
S
W
D
S
T
A
R
G
E
T
C
0
..J
0::
IZ
0
0
en
en
W
0::
0
0
<t
N
N
E
C
T
PC XT BUS
l/'
This board comes with interactive debug software. Its features include software breakpoints,
software single-step and run with count. At the same time, current machine status is displayed on
the top half of the host monitor.
The SDB contains 512K bytes of program RAM for the TMS34010 to execute drawing functions, application programs, and displays. Both the program RAM and the frame buffer are accessible to the host through the TMS3401O's memory-mapped host port.
A DSP-Based Three-Dimensional Graphics System
443
The frame buffer consists of eight SIP memory modules organized into four color planes.
This allows 16 colors per frame from the digital monitor. The TMS34070 color palette incorporates
a 12-bit color lookup table to give you a choice of 16 colors in a frame from a 4096-color palette.
Furthermore, the palette incorporates a variety of unique line load features to allow the color lookup
table to be reloaded on every line; this means that 16 of 4096 colors can be displayed per line.
444
9
0
0
0
0
HSFI &
HSFO
HREAD
HWRITE
XX
00
00
01
01
10
10
11
11
0
1
0
1
0
1
0
1
1
0
1
a
1
0
1
0
Operation
No Operation
HSTADRL read
HSTADRL write
HSTADRH read
HSTADRH write
HSTDATA read
HSTDATA write
HSTCNTL read
HSTCNTL write
The fields in HSTCNTLcontrol host interrupt processing, auto-incrementing ofthe host address register, and protocol in byte-at-a-timeaccesses to the 16-bit host port (whether the lower or
the higher byte comes first). HSTCNTL also contains the status of interrupts from the host to the
GSP and from the GSP to the host and a three-bit message word in either direction. These control
bits are shown in Table 9.
Table 9. TMS34010 Host Control Register Fields
Field
Name
0-2
3
4-6
MSGIN
INTIN
MSGOUT
INTOUT
NMI
NMIN
Unused
INCW
INCR
LBL
CF
HLT
8
8
9
10
11
12
13
14
15
Purpose
Input Message Buffer
Input Interrupt Bit
Output Message Buffer
Output Interrupt Bit
Nonmaskable Interrupt
Nonmaskable Interrupt
Unused
Increment Pointer Address on Write
Increment Pointer address on Read
Lower Byte Last
Cache Flush
Halt TMS34010 Processing
Write Access
Host Only
Host Only
GSP Only
GSP Only
Host Only
GSP and Host
Neither
GSP and Host
GSP and Host
GSP and Host
GSP and Host
GSP and Host
445
These signals map the GSP's host interface registers in the TMS320C30's address space (also
shown in Table 10). The TMS320C30 mapping is actually replicated in four-word blocks untillocation 8057FFh.
Table 10. Mapping ofTMS34010 Host Control Registers
Register
PC Mapping
TMS320C30 Mapping
HSTDATAO
HSTCNTL
HSTADRL
HSTADRH
C7000h - C7CFFh
C7DOOh - C7DFFh
C7EOOh - C7EFFI1
C7FOOh - C7FFFh
805002h
805003h
80500011
805001h
The modified SDB board must be able to select either the PC or the C30AB as its host. The
C30AB target connector makes the two external flag bits XFO and XFl available to the SDB. The
TMS320C30 can configure these flags as either input or output pins. Upon leaving reset, these pins
default to inputs and remain in the high-impedance state. XFO is pulled Iowan the SDB to appear
off when the TMS320C30 is in reset. After the PC loads the rendering software into the GSP, it activates the C30AB and loads the TMS320C30's software. As discussed earlier, the TMS320C30,
during initialization, configures XFO as an output and loads it with a one. The address-decoding
PALs on the SDB use this signal to select the C30AB as the SDB's host. When the TMS320C30
controls the SDB, it communicates through a full 16-bit interface to the GSP. Thus, before the integer screen coordinates are sent in two's-complement form to the GSP, they must be clipped to a
range of -32,768 to 32,767. Fortunately, this range is still two orders of magnitude greater than the
resolution of most monitors.
In general, the above interface is fairly straightforward. The only complication is that the designers of the GSP expected a relatively slow microcoded general-purpose processor as a host. This
allows the GSP to actually assert its HRDY line 80 ns before it is actually ready to process a transaction. When interfacing to the TMS320C30, PALs become necessary as state machines to create the
appropriate number of wait-states on host reads and writes and thus ensure proper interprocessor
communication.
taining a particular value for a command, the value of 3 (binary 011) in either of these fields indicates that a command or an acknowledge exists. Upon reception of a command request, the GSP
refers to the first location of the shadow RAM for a command word from the TMS320C30. Thus,
the overall command scheme proceeds as follows:
1) The TMS320C30 waits until it sees that the MSGOUT field contains a O.
2) The TMS320C30 stores all command and data into the shadow RAM.
3) The TMS320C30 writes a 3 to the MSGIN field and waits for acknowledgment.
4) The GSP acknowledges the reception of a command by writing a 3 to the MSGOUT
field.
5) The TMS320C30 withdraws its request by writing a 0 to MSGIN.
6) The GSP reads the first word of the shadow RAM for the command and jumps to the
appropriate case to process it.
7) Once the GSP is finished with all data in the shadow RAM, it resets the values of the
host address registers and then writes a 0 to the MSGOUT bit, indicating that the
TMS320C30 is free to request another command.
Drawing Routines
Several drawing routines are also provided in the TMS34010 Math/Graphics Function Library User's Guide [8]:
A DSP-Based Three-Dimensional Graphics System
447
For each primitive in an array sent from the TMS320C30, the GSP sets the proper drawing
color with the set_color command.
The TMS320C30 commands the GSP to execute to the clear_screen before it starts to request drawing of primitives for the next view.
The TMS320C30 requests a wait_scan execution from the GSP to ensure that the GSP
has fully displayed the last view before drawing the current view.
The GSP uses the drawyoint(x,y) function to render a point on the display.
Similarly, it uses the drawJine(xl,yl,x2,y2) command to draw a line. The arguments are
the screen coordinates of the two end-points of the segment.
The fillyolygon (n, Iinelist, ptIist) function takes as arguments of the number of vertices,
an array of the line segments forming the sides of the polygon, and a list of screen coordinates referenced by the linelist.
Summary
The TMS34010 Software Development board provides a good rendering module for this
graphics system. The support hardware has been debugged and used in industry since 1987 and thus
makes a reliable rendering subsystem. The target connector to the C30AB provides access to the
TMS320C30 as an alternate host. Three PALs and two transceivers allow the TMS320C30 to assume control of the GSP, once both have started running their software. The draw_object program
on the TMS320C30 can command the GSP to draw graphics primitives. Functions in the
TMS3401 0 M ath/G raphics Function Library User Guide [8] allow the GSP to initialize the monitor interface, clear the screen, ensure that an entire screen has been drawn, and draw the graphics
primitives. Overall, the TMS34010 development tools provide an easy means to develop a rendering subsystem for this graphics pipeline.
Possible Improvements
Several changes may be incorporated into the system to improve performance. Some simple
enhancements involve modifications of the computational subsystem's software to allow faster and
more transparent command execution. Restructuring the method in which the data and command
pass through the pipeline, a more complex modification, can greatly increase throughput. Addi"
tional features such as more complex primitives, lighting, windowing, and text display would require major software modifications to the system. However, any such modifications would not
need to change the communication protocols or the command detection loops significantly. Finally,
although the TMS320C30 represents the state-of-the-art in digital signal processing, the host processor and the rendering engine may be improved.
objects that have been adjusted directly or indirectly by having their ancestors adjusted. Instead,
this routine should be called once with the *universe as the argument. The object structure should
contain a flag that is set when an object is adjusted and reset when it is drawn. Thus, the new
screen_object procedure would recursively search down the hierarchy of objects until it encounters an object that has been adjusted and then should recalculate all the screen coordinates for it and
those of its internal objects. Upon completion, it should search the rest of the hierarchy for adjusted
objects. Thus, the host would have to request only adjustment, targeting, and draw commands.
Screen representations would be automatically recalculated whenever a draw command is executed.
Computational Features
The DSP is suited to perform many other types of computational features. Because these
functions are more complex, they were not implemented in the limited design time available. This
system truncates objects that are too high, too low, too far right, or too far left by using the GSP's
drawing routines that automatically clip coordinates outside the screen boundaries. However, the
system cannot determine whether one object is in front of another and draw the objects appropriately. Functions to do this hidden-surface removal require complex algorithms to determine whether
A DSP-Based Three-Dimensional Graphics System
449
one 3D surface obscures another. Simpler routines could be made to clip objects that are too far
away to see or objects that are behind the viewer.
A lighting feature would allow appropriate factors of light intensity and reflection to determine the shading of surfaces. Lighting may be ambient (equal everywhere) or come from several
possible source geometries. Reflections could either be diffuse and scatter light equally in all directions, or be specular like those off any shiny surface. With these parameters, the TMS320C30 can
compute the appropriate shading of a given pixel. In this scenario, the GSP is reduced to drawing
single points with a given color. Thus, any lighting function would slow rendering time.
More complex primitives can be produced by using the TMS320C30 to generate arrays of
pixels representing solutions to equations. The PC could dispatch a command to draw a primitive
based on a particular type of equation (such as the parametric equations representing a sphere) and
then load the appropriate parameters for that equation. The DSP would generate the appropriate set
of pixels for that object and send it to the GSP as arrays of points.
Rendering Features
The TMS34010 Math/Graphics Function Library [8] permits the user to create and select
various windows for display. Once a window is selected the DSP can run the existing system software within that window. Thus, the host would also need to be able to direct the DSP to tell the GSP
how to manipulate its windows. The Library also enables the GSP to print text on the screen. This
feature also would not be very difficult to implement.
Conclusion
Despite its shortcomings, this system still demonstrates the dataflow in a graphics pipeline
using a digital signal processor as a computational element. One main benefit of the digital signal
450
References
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
451
452
Appendix A
Graphics Programs
Listing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
453
.j>.
****f**fUHffHHfHHHHIHHffHnHIUHffHfffHHfHHHfffHflffHfltt
HHflHlflHffHHHUHHHHHIHIHHfHflffHHHHHHlfHHHffHfHflf
struct object
typedef struct
str-uct object fparent;!f object within who's frall the object is defined *1
long subnulrt;
float sz;
float dz;
/f offsets
long locfllJm:
1clOg ~tnlJm;
long 1nnUIrI;
long pgnum:
long oonulI;
float sx;
float dx;
float sy;
float dy;
float theta;
/f angle of rotation around z-axis (x to y)
float phil
1* angle of I'otation al'ound x-axis (y to zl
float omega;
1* angle of rotation around y-a.xis (z to xl
floa.t r[3H41;
1* matl'ix formed by scale, the offset, then rotate
float 0(3)[4];
1* ascending product of all ancestral I' matrices
loc
*locs;
1* poirlter to location array
point
fpointsl
1* pointer to point array
line
llines:
1* pointer to line arr-ay .
polygon "polygons;
II pointer to polygon array
struct object fobjects[!1AXOB1;
II pointer to anay of
Ilpointers to child objects
::....
.,
*1
*1
lHf*************I****HfIHIIH*IHIHfHffffHfHfflf-ffllfflfflffffffIIHffHI
1/
1/
1/
1/
1/
flllffIHfffflffH+HI**Uffff*-HlffIHH*HfllffIHIfIUIIIIIIIIHIHIIHfflf
II
II
II
II
II
II
II
*1
fHHfHfHH"*UHfIHUfHfHHftfHfffllllffffHfHfflHlffHfHffHllfflf
[
G'l
~
'g.
~.
long color;
long startlocn;
long endlocn;
} line;
II
tHlfttffftlfff*ffffttHlfnffffHlfflHffllHflfHIHHflllHlffllfflfffffIff
HHftHflfffllfHlfflfHffHffltfHfffffUUHHHHlfffHHHHIH+HlffffH
;;l
typedef struct
+I
H***HfHfllfffHHHIHfHHHffHHHHflflfffHIfHHHlfHHffHfffffflff
*1
tl
1/
l,
long color-;
long locn;
} point;
typedef struct
{
float x;
long a;
} toc;
float y;
long b;
float z;
II world
coordinates *1
1* screen cMrdinates II
ttffffftfHffHffHffffIHHlffHfHlfflffffHlffl*HfffHllfflfHffH***lflff
typedef struct
{
long color-;
long vertnum;
10llg tvertlocn;
} polygon;
II number of vertices
*1
1* array of vertices 1(lC numbers H
********lflfffIHHHHH-*lIH**HHHffHfIHfffffHfffHHfffffffHflfffffH
tl
g,
a'"
~
~
~
IHIHHHHflfHHHfHHHffffHHfffHfHfHfHfHfHfHffflffHHtHIHHf
HffHfHfHffHfffHfHffHHfHtHHHfftHHfHHftHHHfHfftHlfHfHfff
/1--------------------------------11
void Hine)
/1
COI1IUUCATIOOS I1ACROS TO GSP
1/
/1-------------------------------1/
Ide fine
Idefine
'define
#define
Ide fine
CTLfRf[
0x0800
CTLREQ
CTLACI(
0><0803
0x0033
0x0830
('h.tcntl
CTLWITH
HOSTCNTL
OxOOfFF)
/1---------------------------.,.---------------1/
/1
IIIIUII.II1 NI.ItBER IF INTERIIAI. OOJECTS
1/
/*--------------------------------------1/
'deline l1li108
10
/1-----------------------------------------1/
/1
PC COItI..WlCATIOO LOCATIONS
f/
/1--------------------------------------------'---1-,
C)
'define rottAND
I
~
'g.
~.
(Idual-port Ie 0x0fF1
/.------------------------------------------------*,
'*
DATARECO'.{RY FROI1 THE lXW. POOT
*'
/1-----------------------------------------------1/
'define
Idefint
.define
'define
Idefine
[fOCal
[fI(al
lP2Cai
[f3(il
DPl(ttJ(a)
dual_por-t[aJ
dual-porth. + 1]
dUil_port[a + 2]
duaLporHa + 3]
(liongi {{iPUol
OxOOFFl
B:
(OPO(al
OxQIlFFill
. .IU....H*HfIHlfHHHH.HflfffHffHlllffHHIHffHIIHIHlffH.H.ffH
(
*.I*'HIHf*IHffltHIHfI*Hf-HHfHfHftIHHHHfHfH-fffHIII"fffHHfffl
/1
long k,l;
struct object luniverse, fto, Ino; /1
urlsigned long IduaLport;
/1
unIon
/f
{
float
unsigned long
} fllong;
f;
i;
II
1/
1/
1/
1/
1/
fIHfHflflffHfHf.HIHHfHHffffHUHHfffffHIHfffHIHffHIHU.HHH
.hile(COI1I1AHlJ == 01,
j = COMAND,
ACKNIREOOE = j,
IiIhilelCUV1AND != 0);
switch Ij)
1* .acknowledge request
/1 wait for PC to withdraw request
/1 execute requested conand nUlber
'I
I'*'
*'
f/
*'*'
co.. U
LOAD A lIAlilHTER OBJECT
if (to-)obnull = I'IAXOB) break; /* abort if ) !taxi.um objects 1/
j = Hto-)obnulI;
/1 increase nuaber of daughter objects */
/1 allocate space for nelll object
1/
to-)objects[jl = (str-uct object II Iftil10c (sizeof(struct object));
no = to-)objects[jl; /1 next object is daughter object
1/
no-)subnua = j;
/1 set sibling nuaber of next object
1/
no-)parent = to;
/1 assign current objfCt as no's paret
II
to = no;
/1 target daughter object
*/
10ad_object();
/1 load daughter object
I'
ACKNltA.EOOE =0;
/1 show that dual port is free
*/
I'Iitrixll;
/* calculate transform r.atrix
1/
break;
case 2:
j
= IPl.(HH21,
*'
0\
ACktOA..EJ&: = 0;
If sholl! thit dual port is free
.,
if (j ) to-)obnulII) break; /. can only target existing object 1/
./
break;
me 3'
ACKtOLEOOE = 0;
to = to-)parent;
"'
case 7:
siblings
--t-o-}obnul;
brnk;
~
I:;:,
;;i
~
"''6
'
~
'"
[
~
.
~
~'
~
'"
1\
;!!
ClSe
./
.,
screen_objectlto);
break;
f/
1/
default:
AtmlIUDGE : 0,
break;
./
/1
.,
1/
./
1/
./
1/
1/
5:
to-)sx
to-)sy
to-)sz
to-)dx
I.-)dy
to-}dz
to-)theta
I.-)phi
to-}oltga
ACktOA..EJ&: = 0;
If, shOll! that request dual port is free 1/
if (to = universe) break;/' don't allow deletion of universe f ,
j = to-)subnUfD + 1; /f get nUlllber of next sibling
f/no = to-)parent;
/f set next object to parent
1/
delete_object(to); /* delete current object
1/
to -= no;
1 -= to-)obnul;
.,
brtik;
1/
./
brnk;
case 4'
.,.,
.,
.= dpf1.itH01,
*'.,
dpf1.1I13()),
+= dpfloat(34);
/1 sho. that dua.l port is. free
AOON.EDGE : 0,
to
'*to-)theta.
keep angles in the IO,2pU range)
flodlto-)theta, hlopi);
*'
*,
.,
.,
=
I.-)phi = flodUo-}phi ,tlllopi);
to-)oltga = f.odUo-)o~ga, tIilOPU;
Cise 6:
~=.O,
./
.,
I'
CTLFREE);
wa.it for 340 to be free
I'
enter cOlRnd
a screen clea.r
whilell4lSTCNTL ~=
/*
It
for
'h.ldili =4,
.h.le.11 : CTl.REQ,
/1 tequest service frOM 340
.hiltlHOSTCNTL != CTLACK); /i "'it for icknOlllledgement
/f ~ithdrh request
'h,le.11 =CTlWITH,
draw-object( uni verse);
HUffIIHlffUHIHfHHHHlfffflffltHtfffff-ffHHHHHfHHfHHIfffH-H1
Ihltrix(to);
break;
'1IIIfffIffIfIffHIfHfIHff'lffIHfIHllIfIfHlIHlf-H-fIHffHffIIHfffHfffff
/i dra... universe
.,
"'"'
"'
II
IDP)I.)
24
if (sign)
./
.,.,
.,
.,.,
"'
fHlffflfffffHHlflffffHfffflfHfflllffHfffftulftHHHHfflHlfHllHlH-I
::a,.
tl
tHHHHtHHHHtflfttH+HHHflHHtHHffHffHffHffffftHHHHHfHfH
--}Listing 10;.
'ft'IS32OC3O Objed
void load_object()
register IDe
register- Jine
'"~
~
'I>
{3
~.
Routin.
if (lnl
(
ft ploe;
tte.pln;
fteappg;
1/
1/
tIghter long i, j;
register struct object to;
polygon
'f
point t-t.rtppt;
long Ie DPUlIGI21,
long pi 1PL(N;141,
long In '1PL(N;lbl,
long pg IPL(N;ISI,
If nUllber
If nullber
/f nultber
/f nulIOel'
o = to;
of points
= Ie;
= pt;
= In;
= pg;
= -1;
o-)sx
.-)dx
dpfloolllOI
dpfl.otlnl
= &:(o-}JintS[ill;
= lPLCN3(j);
tellpln-)startlocn = DPLOOOCj + 2);
1/
1/
1/
.,
of 1ines
of polygons
o)tocnu.
o-)ptnuli
0-)1nolllll
0- )pgnuD
o-)obntlll
more_dataO;
is
*,
tempTn
ttll:pln->color
get color
tl
It get starting location II
get ending location
= rPL(NJ(j + 4):
hllpln-)endlocn
of coordinate locations 1/
o-)sz
= dpfloat(18J
o-)dz
dpfl .. tlJOI
'-)0"9' = dpflool1421
'*
I'
= &(o-)polygonsfil);
= [l>L~121,
= D!'LlI'lI41,
tellpP9-}vertnufI I,
0, j=46; i
*/
1/
f/
1/
1/
1l;
f/
0-}10[S
I'
't
if Ipgl
o-).y = dpfl.ol1l41
o-)dy dpfl.otl2bl
.-)p.i dpfl.oll381
t/
/f
0-)1.,10 dpflootl341
for Ii
I'
[
~
l~ding
for (k = 0, j = 6;
k ( 1; +tk, j += 2)
/f load verteres f/
tuppg-}vertlocn[kl = DPlONO(j I;
*,
ttlpJoc
= &:(o-)locs[Bl;
I ploc-( dpflot!ljl,
I ploo-)y' dpflodlj + 41,
tellllploc-)z z dpfloatlj + 8);
I'
if Ipll
(
.ore_datal);
for H c Or j.2 ; i
< pt;
++i" j += 4)
ItllPPI
LI,-)pointsCill;
toppt-)color'.'IPLCNjejJ;
I ..ppt-)l.en DPI.DIIGlj
+ 21;
'f'f
I'
t'"
IfUfitUHf.HffHfflHfHlfHffHlIHtfHfflHfftftffHHlfHflffliHffffffff
00
if
if
(I )
<-32000)
<-32000)
k = -32000,
I = -32000,
1*
Sft
1/
screen coordinates
t.oploc-)b = I,
tellploc-)a = k;
void serNn_object(ol
register long i , j;
register loc fteap1oc;
fI ..t
teapob
z,d,
*'
1/
1/
ffHfllffflffffffffHffflffHHHftHHHfHfHHHHlfHHHHHHtHffHlHf
=o-)parent;
1/
1/
fHffHffHffHflfHfHlHffHflfHHHl-tHHlllHfflHHffffflHHHfffHffH
forti = 0; i
<3;
o-)p[iHjl = o-)r[i][jl;
Mtrix()
{
'I
::to..
.->p[iJ[Ol = 0-),[0][01
+ o-)r[2][0]
.-)p[i1ll1 = 0-),[0][\1 I
0-),[21111
0-)p[iJ[21 = 0-)r[0]{21 I
0-),[2l!2]
0->p[i]{31 = 0-)r[0]{3] I
0-),[2][3]
[
;;l
~
r
[
G)
'g.
~.
register float
cost, sint;
float
coso, sino,
register struct object 10;
cosp~
/1 transfotl'l telllporary
sinp;/l.variables
I'
II
tl
I'
o = to;
cost = coslo-}thetal
sint = sinlo-)theta)
coso = cos(o-}oIHQil
sino = sinlo-)oltgal
cosp = cos(o-)phil;
sinp = sin(o-)phi I;
o-)r[O](Ol = o-)sx I cost I- coso;
o-)r[O](l] = - o-)sy I sint I coso;
o-)r[O][21 = o-}sz I sino;
0-)rCOH31 = (o-)dx I cost - o-)dy I sintl I- coso + o-)dz I sino;
o-)r[t](O] = o-)sx I Isint I cosp + cost. sino f sinp);
o-}rCl](U = o-)sy .. (cost .. cosp - siot f sino f sinp);
0-}r[t][2J = - o-)sz I coso I sinp;
o-}rU](31 = ((o-)dx" cost - 6-)dy f sint) * sino - o-)dz * coso) f sinp
+ (o-}dx I sint + o-)dy .. cost) f cosp;
0-)r[2](O] = o-)sx .. (sint sinp - cost * sino" cosp);
0-)r[2](1] = o-)sy f Icost * sinp + sint I sino * (osp);
o-)r[2H21 = o-}sz f coso f cosp;
o-)r(2H31 = - o-)dx I cost + o-)dy f sint) * sino t o-)dz f coso)
f cosp
+ (o-)dx f sint + o-)dy * costl I sinp;
IlfllffflfllfflflfflfffftfflHfftfffHffHffffffHllHlflfflHIIHIIHIHfHff
t ..pob-)p[i][Ol o-),[1]{Ol
I
t pob-)p{iJ[11
teapob-)p[iH21;
./
for Ii = 0; i { j; +t:i>
(
tellploc = ItCo-)locs[i)j
x = tnploc-)x;
Z = tuploc-)z;
Y = tt!lploe-)y;
+ Z 0-)p[0l!21
I = (long) x ....>p[1J{OI + y
Z I 0-)P[1J{21
,. clip to a 16 bit integer
o-)p[OI[3])
'-)p{IJ[]I
o-)p[J]{3])
200),
200),
"
II
;:...
t:I
~
~
fftfHfHfffHffHffHHfIHHUlffH****fHffHftHHHffHffHftHffHfHfH
10;
/f
register long i, j;
tellp~rary,
looping variables *1
free (0-)10(50);
II delete location array
free (o-)points);
II delete point array
free (o-)lines);
II delete line array
j = o-)pgnulII;
/1 get number of polygons
for (i = 0; i {= j: +ti) free (o-)polygons[i).vertIClcn); II deleh
for (i = 0; i (= j; Hil free (o-)polygonsl;
II polygons
j = Cl-)obnulI;
/1 get number- of daughhr objects
for (i = 0; t (= j;++i) delete_object(o-)objectsfi)); II delete objects
free (0);
II deJete object
i-
t/
II
1/
II
II
1/
1/
1/
1/
c;)
1******ftHHI**HfllllffHlfH**fUfH**HffffH*HHffff*ff**IHIIUIHH+f1
HffHIHffffffffIHffH-f+flffl**I*,**I+f****I****IHfffHH**HlffffIHI**lff
'"~
;:
register long
register loc
point
register line
polygon
fO;
1;
ftellploc;
ftelllppt;
fteltpln;
*teIlPP9;
register long fhstdata ::: (long *J 0:<805002; /f 340 host data register
1/
register long- fhstcntl = (long *l Ox805003; /f 340 host control register II
register j = o-)lnnulII;
II~tellporary, looping variable II
.,
i:!
~
fH********fHHHfffftHlfHHHffHHfHftHfffUHHfftHffHftfffHffffHI
= 127;
~=
127);
ACKIlWlEDGE = 1;
while(COMl'1AND != 0);
II
II
II
/*
1/
1/
1/
templrl =~do-)lines(i]);
Ihstdata = tupln-)color;
thstdata = o-)!ocs{tupln-)startlocnJ.a:
Ihstdata = o-)locs[tellpin-)startlocnJ.b;
Ihstdata =o-)locs[tellpln-)endlocnJ.il;
Ihstdata = o-)locs[tempin-)endlocnLb;
ACKNIlWlED6E
void aore_data{)
IIIhile(CM'1AND
1/
*/
*1
*/
IIlhile(HOSTCNTL != CTLAClO;
fhstClltl = CTlWITH;
1/
1/
1/
1/
II
1/
IfUHfIIHUflnfllnl"*fln****Ulffl**U'UffffIHff+flUfI****ffH***'**f
,. DRAW ANY POINTS
j = 0-)ptnulI;
If (j)
f'f'
.hi I, (HOSTCNTL
fhstdata
Ihstcnt1
Ihstdata
for(i=O;
'= CTtFREEl;
= 1;
= CTlREQ;
= j;
i ( j; Hi)
temppt =&Co-)points(iJ);
II saye point pointer
*1
/1 send color
II
Ihstdata = tellppt-)coior;
Ihstdah = o-)loes[tellppt-)locnJ.a; /f send scrfen coordinhs '1/
thstdata = o-)locs[telllppt-)locnJ.b;
'I
*'
= o-}pgnul;
if (1)
{
for(i = 0; i
< 1;
++il
/f
dra~
polygons
= 5;
= CTLREQ;
= telppg-)color;
= j:
I'
.,*'*'
*'*'
*'*'
II send point connect list (0,1 , 1,2, 2,3 .... j-2,j-l , j-l,O *1
fhstdata = 0;
forlk '=, 1; Ie ( j; ++Ie)
ffftHHffHffHtHffftHfHHfHftffHHtHffffffffffffffffHHHffHHfHHf
typedef str-uet
{
short color; /f
short xl;
/1
short yl;
/f
short x2;
/1
short y2;
line color
x co-ordinate of starting point
} line;
*'
*'*'*'
*'
ftfffffffffHHffffHfffHffffffHffHHHIHfUfffHHHHflHIHtlHllHllf1
ttIHH**f******fHIHHfHHHHIHfIHHIHIHtllHHfHHIIHIItHHHHIH
fhstdata = k;
fhstdata
= k;
fhstdata = 0;
10)0<1
color[1~)
ceo. ect,
['"
C':l
i:l
'g.
~.
II
ItHHHHfHfHffHfIHffHHHHHffHflHllffHHffffftHHffHHHftHHH
'"
ceo,
t******f*ttf*lftll**fHfH**fHIHftIHffItIlHHlfffItIHHffIHtlfltIHtIHt
t:J
~
~
tl
={
'* =
for
o-)obnulI;
{i = 0; i
ilcknQl~ed9t
requestll
II
*'
short mypaleHlb) = {
OxOOoo, OxFOOO, OxOOFO, OxFOFO, 0x0F00, OxFfOO, OxOFFO, OxFFFO,
OxOAFO, 0,0900, OxfAlO, Oxf4AO, 0xI7BO, OxbbOO, Oxmo, OxBBBO I;
j; ++i) drilll_objectlo-)objects[iJl;
flfttfflfffffHttHfffffHfHfflHHHffHlffHfHfffHfflllHllHlfHlfHIHI
fHHfHflHHIHHHfHlIHHHfHHfHffHllHffHlflfHIHIfHHfHffHfffl
fHfHHffffffffflffHlffffflHfHHHfllffffHHfffllllffffHfffffHffHHHf
typedef struct
short colOor;
short x;,
short y;
} pOint;
1* point color
II x co-ordinate
II y co-ordinate
*/
*'*'
ffHHflHHIIHHfHfHtHfHfHlffHlfllffHllHllHlfHfflflflHHlllflflH
::to.
tl
~
~
6
"
Co
[
~
{3
;:~"
1:
telpint = fnullber;
for (i=O; i < ttl'lpint; ++i)
lMin()
Cise
case 123:
tempint = IhunDer;
for {i = 0; i ( hlllpint;
1* get number
1* of 1ines
"
II
.1
templn = t(lioes(i));
set_co 101'1 (co Jor[terlp 1n-)col or] J;
draw_line! templn-)xl,
telllpln-)yl,
templn-)x2,
tellpln-)y2J;
*l1stadrh =adrh;
*hstadrl = adr!;
fnstctll = 0;
II
*1
,<
<,
/f savt point
1* set colors
/1 dr-alii point
*1
tJ
DRAW POINTS
/1 get number Offl
/f
points *1
= Ic<points[i]);
set_co lorl (co 1or[tuppt-)co lor] 1;
te&ppt
brea.k;
HHHIHU**.*HfHf'fHffIfHUtUfUHUHfHffUffHffHHlfffffHfffHfff
dralll_point( tellppt-)x,
*/
t"ppt-)yl,
fhshdrh = adr-h;
If reset start data address
II
*hsh.drl = adrl;
Ihstctl1 =0;
II turn off any command to the 340
*1
break;
case 3:
SET SCREEN BOCKGROLffiI
nelll_screen(color(fnulllber),aypalet); II clear screen
*hshdrh = 'ldrh;
If reset start data address
Ihstadrl = adrl;
Ihstctll = 0;
II turn off any COMand to the 340
Dreak;
cas~ 41
SET BACKGROUND BLACK
instadrh = adrh;
If reset start data address
Ihstadrl = adrl;
ihstdll = 0;
1* turn off any cOlfllDand to the 340
*1
nelll_screenfO,mypalet); 1* clear screen
break;
case 5:
If MAW A FILLED POLYGON *1
seLcolort(color[*nulllberl);
1* set polygon color
*1
tempint = 'IpghUIt;
If get number of verteces *1
fiILpolygon(tempint,
1* fill polygon
il
(short f) (pointer + 3),
(short f) (pointer + 3 + (telllpint 1)));
fhstadrh = adrn;
II reset start data addr~ss
*hsta~rl = adrl;
If turn off any cOllllr!a.nd to. the 340
Instctll = 0;
break;
case 6:
WAIT FOR COIIPLETE SCREEN RESCAN
*hstadrh = adrh;
1* res!t start data addr~ss
fhstadrl = adrl;
II turn off any cO/lllind to the 340
*1
Ihstdll = 0;
waiLscan(Q);
I*lalait ti 11 scan reaches top of screenil
waiLscan(479);
Iflalait till scan reaches bottoll (line 479)11
break;
default:
lostadrh = adrh;
II reset start data address
'nstadrl = adrl;
1* turn off any COllilind to. the 340
*hstdll =0;
break;
,<
,<
*'<,
*,
*,
*'
"
"
<,
,<
.,.,"
*,
*'
"fffffffHIHfHfffffffffffffffHftH*fHffHfHfftHflfHIHffH*ffHIHltH
.j>.
HHHHtfHtlHH****fHH*****fIHfHHfHfHHHHffHHHfHfffffHffHHf
HHHfH**H**HfHHHHHfHfIIHHHfHHH"UtHIHHfHHHIHIHHIHlfl
tYDedef struct
void adjusLobjectlsx, sy, sz, dx, dy, dz, theta, phi, omega)
double sx, sY. sz, dx, dy, dz, theta, phi, oaegaj
shOrt ptnum;
short dtnlJlfI;
short lnliYllj
short pgnUJII;
float
5Xj
float dx;
float theta;
If:
1*
/f
1*
number of 1ines
number of fi 11ed polygons
floa.t sYi
float sz;
scale factors
float dYi
float phi;
float dz;
offset factors
float o~9a.i /f angles of T'otation
} trans;
*'
*'
*,
*,
f/
IIlhi1e(ACK~lEDGE ~=
>x,
OJ;
DATAFLOATl21 =
DATlifLIlATl61 = sy,
IlATlifLOATI141 = dx,
DATIlfLOAH181 = dy,
DATAFLOATl261 = thet., IlATAFLIlATI~1 = phi,
COMMAND = 5,
Ifhi le(ACKNOWlEDGE != 5);
f/
./
COMMAND
sz,
DATlifLOATll01 =
IlATlifLOATl221 = dz,
DATIifLOAT!341 = ,meg',
= 0,
fH**HltHIHnt**HHU***HlnH***ffHftHHffnH*tHIUfHHfUlfHHfH
'H*I**lfll-+HHHtH'H**HffH4fH*lfIHHHHHHfHfIIHHHHfffIHIHHHf
f1HfHfHfHfHfHfHHHHHHHHHHffHfHHHlffHlffHHHHfHHH****
**H*fIHIII*f*HUHfHHH+HHIHfHffHHlfHHHfHHHflflfHtIHHHHf
;:..
~
~
~
'"
6
ff
[
~
.
;:,~.
'"
;:;:
''';(.jd seLparalfieters(sx, sy, SZ, dx, dy, dz, theta, phi, ortega)
.:l(Euble sx, sy. sz, dx, dy, dz, theta, phi, o~ga;
I:;:j
~t
a))
Ulhi le CACKNmjlEOOE
data-)sx
= sx;
11a.ta-)dx
= dx;
tlata-)theta = theta;
HHlfIHfHfHH**HHHHHffH*HHHfIHlfHHHH***HHfHffHlfHfHHf
~=
0);
dah,-)sy
d.t.-)dy
data-)phi
= sy;
= dy,
*'
.... *I************I**llffHI**HltIHIHHHII**lfHl**II**IIHIHHIHHfffnH
flfflflllft***fHHHfHIltIHllfHHflffHfffHHIIHllltlfffffffflllfffIHHI
***II*****lt"HIII**I****HHllfH*HfH****I**HffftffftflffHlfllffIIHffHf
fll**lfIHHHtHHHIfHfH+IIHIHfIIHIHlfHIIUttHfflHItItHffHlfHHI
while(ACKNOWlEDGE
COMAND = 3,
IIIhile(ACKOOWlEDGE
COI1I1AND
= 0,
~=
01;
~=
3);
1**11**f1HIIHlfflUflllnll**fIHllflHHHfIIHfflf***ttlttttt***HtH"**I*
tl
~
~
U*HfHHfHf*****HHHfHHfffHHHHHfffHHHHffffffffHlfHfHffHfH
x,
~.
.hi!eIACKNOWlEDGE !- 0),
DATASHORT(2) COI1I'I\ND - 2,
whilelACI<NtU.EDGE != 2);
COI1I'I\ND - 0,
t::,
~
-
void cubelcl
long c;
void h.rgeLchildlx)
int X;
I'
C~i1d
ffH*ffl*ffffIHffffHHfHHHHHHf~HHHt,tHfftHHHfHffHffHtHHf
/f
/f
If
/f
/f
1/
1/
lIIithdralil request
1/
fffHffffHHHUHffH*Hf4HHtfHffUHof,HHHlffHffffHffHffHffHHfH
HH4HffHUfffHiHffHffHHHffHHHflHffffffHffllfflfflffffffUI,UfH
IIIhileCACKtOlEDGE
catWID - 7,
whil.i_EDGE
catWID - 0;
tlhileCACKMJWlEDGE
00'I1ANIl ; 6,
IIIIhi leCACKNlIUOOE
OOWIND - 0,
!== 01;
!- 7),
!== 01;
!=
6);
II
1/
/1 lliitMrillll request
II
IHfIHffHlfHfHHHIHfHHffHffHHHIHfffffflffHHHIHHlfffflffHfH
= 12;
data-)pgnum = 0;
data-)lnnun
DATAFLOATl4b)
DATAFLOATlSS)
DATIiFLOAT(70)
DATIIFLOATlS2)
DATIiFLOAT(94)
DATIIFLOAHlOb)
DATAFLOATU1S)
DATAFlOATlI30)
COMMND - I,
1,
I,
I,
I,
-I,
-I,
1/
1/
1/
1/
1/
DATAFLOATlSO) - 1, DATAFLOATl54) - 1,
DATAFLOAT(62) - -1, DATAFlOAT(66) - 1,
DATAFLDAT(74) - -1, DATAfLOATl7B) - -I,
DATAFLOATlBb) - 1, DATAFLOAT(90) - -1,
DATAFLOAT(98) - 1, DATAflOATIl02) - 1,
DATAFLOATlll0) - -I, DATAFlOATl114) - I,
DATAFLOATIl22) DATAFLOATIl26) - -1,
-I, DATAFLOATIl34) - 1, DATAfLOATIl3B) - -1,
/1 cOllllind to load object
II
\lIhile (ACKNOWlEDGE != 1);
/1 lllait for C30 to acknowledge request.1
It tlHhdralil request
II
COIWIND - 0,
/1 !Hi t for C30 request lines
II
.hll. IACKoo.tEDGE '- 127),
II cOlIHnd to IOid Jines
II
COIWINll - 127,
I< llt COLOR--- START POINT----- ENDPOINT---1/
DATASHClRT(2) DATASlJRT(4) - 0, DATASHORTlb) - 1,
DATASHORTlS) -" DATASHQRTIlO) - 1, DATASl()RTIl2) - 2,
DATASHORTiI4) - " DATASHORTI W - 2, DATASHollTllB) - 3,
DATASlmTl20) - " DATASHORT(22) - 3; DATASl()RTl24) - 0,
DATASHORTI2b) - " DATASHORTl2S) ; 4, DATASHORT(30) - 5,
DATASHORTl32) - " DATASHORT(34) - 5, DATASHORT(36) - 6,
DATASHORT(38) - " DATASHORT(40) - b, DATASHORT(42) - 7,
DATASlIJRT(44) - " DATASHORTl46) - 7, DATASl()RTl4S); 4,
DATASlIJRTlSO) - " DATASHORTiS2) - 0, DATASHollT(54) - 4,
DATASl()RTl5Io) DATASHORTlSS) - 1, OATASHORTlbO) - 5,
DATASHORTlb2) DATASHORTlM) - 2, DATASHORT(66) - b,
DATASHORTlbS) - " DATASHORT(70) - 3, DATASl()RTl72) - 7,
while IACKNClLEOOE !== 11;
/1 lH.it for C30 to resulle loading
II
-
-1,
-1,
c,
c,
c,
_-0,
II shotl no requests
1/
HllfHfffffffffffffoHfffffflHfoHlfffftfHlHlffHltHHHIHffHffHflffflH
->Lilli., 30' PC lIIi. Rolli .. 10, Dr... 'Pl ... lvy 51,1.. 01' Cub..
t..,et-pu'.W,
.m....objectll,
.drUl...Scrttn( l;
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(
rt9i1ttr ilt. XI
l ...gtt-ll....oIO,
M.W,
targtl_Pll'tfttll,
targtt-w.nW ,
Ht..parllltt.rst.3,.3, .3.0.,0,,6 . 0.,0.,0. I;
c.m.m,
t ... gtt_Pll'tntl I,
~
tI
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[
~
{l
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c,,"151,
targtl-lll..ntl',
Ht...,tl"Ultters(.3, .3,.3,0.,-6.,0.,0. ,0-.,0.);
c,,"UI,
t ...gtt-lll/'tnto,
Iorlx 0, x
<1000;
I,,'x 00, x
.,
./
< lillO,
++xl
targtt-w.nW,
tarttt_cbild'3I,
adjust_objtetll 1 1 0 0 0 0 25.0. I,
tlrltt_pattntt);
larg.t_,bi Idl41,
a.djust_o'i.ctCl.,l., J. ,0. ,0. ,0. ,0. ,.15,0.);
t&rg.t..pltent ();
tarttl..dild'OI,
Idjust_objtctU., 1., . ,0.,0.,0.,0. ,0.,-.4);
targtt_chi IdlOl,
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larg.t-w.nW,
I.. ttt_,hildlll,
adjust_objectll 1 1 0. ,0 0 3.0 0.1,
targtt-lllrtnW,
targ.LporfOW,
sctHft..objtctCI;
drtILscreH()C
++xl
tUltt_partBt();
hrgtt_cbildl4l,
adjust.obj.cllI 1 1 0 0 0 0 2.0.1,
t&rgtt-w.nt( I,
targtt_childIOl,
tdjusl-Objecl II 1 1 0 0 O 0 0 -. 41,
t&rttt_chiidlOI,
idjust_o~jtd( 1.,1. ,1 0.,0.,0.,.4,0. ,0.);
l"gtt_W,
largtt_chil dIll,
466
The TMS320C30
Applications Board
Functional Description
467
468
Introduction
This report describes the architecture of the TMS320C30 Applications Board (APPB),
which is part of the TMS320C30 XDSlOOO Development System. The XDS1000 is an in-circuit
emulation tool for TMS320C30 hardware/software system development. The APPB was designed
with two goals: to provide a basic platform for software development and to provide a variety of
interfaces to the TMS32C30. There are four key interfaces used on the APPB:
1) SRAM
2) EPROM
3) Dual-port SRAM
4) DRAM
The SRAM and EPROM interfaces on the APPB are quite simple; thus, this report focuses
on the dual-port SRAM and the DRAM interfaces. Figure 1 shows a basic block diagram of the
APPB.
16K x 32
SRAM
iii'
.J
a:
a:
w
I-
I-
I-
XDS/SOO
EMULATOR
PORT
f-+1-+-'-'
13
32
DUALPORT
SRAM
ADDRESS
MAPPER
(t
4Kx8
0
DUALPORT
SRAM
A
32
10 2K x 32 1
A EPROM
12 {
32
32
Of-+- ~ TMS320C3~
32
10 16K x 321
A
SRAM
AI--
32
I/O
AI-+EXPANSION
BUS
Drt-
32
10 512K x 32 1
A
DRAM
.J
iii
II)
a:
::::l
In
I-
11.
CONTROL
REG.
II)
::::l
In
Z
II)
::::l
In
>
a:
~
><
w
::E
enZ
ex:
11.
469
Host/TMS320C30 Interface
The host/TMS320C30 interface is composed of two basic blocks, the dual-port SRAM and
the control logic. The control logic consists of address decoding, a read/write control register, and
a write-only mapping register. The control registers are mapped into the host I/O space as shown
in Table 1. Figure 2 is a block diagram of the host interface.
Contents
0330 - 0337
0338
0339
Control register R
I
DUAL-PORT SRAM
a:
en
:::I
ID
I-
en
o
::J:
oQ.
w
u.
u.
:::I
ID
I
DPRAM
NAP
REGISTER
CONTROL
REGISTER
<t
0
CONTROL
BUS
a:
w
u.
u.
:::I
I--
ID
oJ
I-
z
a:
HOST/DPRAM CONTROL
0
0
<{
470
One of the major problems in developing an application for a PC is finding a block of memory
that does not conflict with other memory-mapped cards. To ease this problem, the dual port SRAM
interface has been designed to be relocatable on 4K-byte boundries throughout the lower 1M-bytes
of host memory space. A software example of how to map the dual-port SRAM into this space is
given later in this report.
Writing a value to a hardware mapping register on the APPB relocates the dual-port SRAM.
When a host memory access is generated, the value in the mapping register is compared to host address bits A12-A19. If they match, a dual-port SRAM access is allowed. To ensure PC and PC/XT
compatibility, the dual-port SRAM can be located only in the lower 1M-bytes of host memory.
The APPB contains one general-purpose control register. This register is broken into two
four-bit nibbles. The lower nibble can be read from and written to by the host and read by the
TMS320C30. The upper nibble can be read from and written to by the TMS320C30 and read by
the host. The lower nibble of the control register is cleared by any reset to or from the host Pc. The
upper nibble of the control register is cleared by any reset to the TMS320C30. The names of the
APPB control register bits and host/TMS320C30 access capabilities are given in Table 2. Table 3
gives the control register bit definitions.
Name
Host Access
C30 Access
0
1
CINT
XINTCLR
DPSEL
SWRESET
XINT
CINTCLR
MBANK
MSWAP
Write/Read
Write/Read
WritelRead
Write/Read
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
WritelRead
Write/Read
WritelRead
WritelRead
2
3
4
5
6
7
471
Name
Function
CINT
XINTCLR
DPSEL
Dual-port SRAM select. When this bit is set to 1, the dual-port SRAM
is memory-mapped in the 4K-byte space of the host PC specified by
the 8-bit value in register Q. When DPSEL =0, the dual-port SRAM
will not be mapped in the host PC's address space. On reset, DPSEL
is read as a O.
SWRESET
XINT
Interrupt to the host Pc. The TMS320C30 may interrupt the host by
setting this bit to 1. The host clears and re-enables XINT by writing 0,
then 1 to XINTCLR. The TMS320C30 cannot generate an interrupt to
the host while XINTCLR =O. On reset, XINT is read as a O.
CINTCLR
Clears and disables interrupts from the the host to the TMS320C30
(CINT). CINTCLR must be set to 1 before the host can generate an interrupt to the TMS320C30. The TMS320C30 clears and re-enables
CINT by writing 0, then 1 to CINTCLR. On reset, CINTCLR is read
as a O.
MBANK
MSWAP
Memory Swap. The MSWAP bit is used to swap the address map for
EPROM and SRAM space O. MSWAP = 0 maps the EPROM at
OOOOOOh-003FFFh and SRAM space 0 at FOOOOOh-F03FFFh.
MSWAP = 1 maps the EPROM at FOOOOOh-F03FFFh and SRAM
space 0 at OOOOOh-003FFFh. On reset, MSWAP is read as a O.
The last portion of the control section contains the dual-port SRAM semaphore registers.
Semaphore registers are used to coordinate communications between the host and the
TMS320C30. Note that these semaphores do not provide hardware protection of the memory array.
Instead, they provide a basic means (via software control) to ensure that data can be accessed from
both sides of the dual-port SRAM without being corrupted. A software example that uses the semaphores is presented later in this report.
472
char O'cntlreg
i f (mem_type)
else
(char O')Ox00805FF7j
O'cntlreg 1= Ox80j
O'cntlreg &= Ox7Fj
There are 16K-words ofSRAM on the expansion bus; however, the TMS320C30 can directly
access onl y 8K-words. Instead of wasting the unaddressable 8K-words, you can use a bank addressing bit (MBANK) in the APPB control register to select between the lower and upper 8K-word segments.
The following code segment selects the current bank of memory.
#define BANKO
#define BANKl
o
1
sel_mbank(bank)
int bankj
{
char O'cntlreg
i f (bank)
else
TheAPPB supports 2K-words of one wait-state EPROM on the primary bus for a boot loader
and operating system support. As stated earlier, this EPROM is remappaple.
DRAMlnterface
The APPB provides a DRAM expansion module that is connected to the TMS320C30 primary bus. Historically, DRAM interfaces to DSP devices have not been popular because of interface
TMS320C30 Applications Board Functional Description
473
difficulty and limited processor address space. The TMS320C30 supplies solutions to both of those
issues with its memory interface and 16M-words address space. Two areas of the TMS320C30
memory interface are most useful for DRAM design:
Use of bank mode
The ability to do continous reads while in a bank without de asserting the STRB signal
When you use these two features, it is quite simple to design a medium-speed interface to
page-mode DRAMs.
The TMS320C30 DRAM module consists offour banks of memory, each bank 256K x 32
bits, that provide 1M-word (4M-bytes) of medium speed storage for the TMS320C30 (see
Figure 3). The bank-switch function on the TMS320C30 provides fast page-mode access on backto-back read cycles within a DRAM page. All address and control lines to the memory array are
buffered and series-terminated for good signal quality. The memory array uses CAS-before-RAS
refresh to reduce component count. There is no onboard refresh timer; instead, SDACKO from the
host PC provides a refresh request every 12-16 lAS. The D RAM access/cycle times are summarized
in Table 4.
~IS
::IE
::IE
<
a:
ADDRESS
ROWSEl
ADDRESS
MUXES
MADDR
o
~
x
II)
DRAM
CONTROllER
<
a:
0
~
x
~
CD
CTl/ClKS
::IE
CD
II)
C')
IS
N
<
N
C')
x
~
IS
...!:!r-
r-r-
r--
'-.--CTl SEl
DATA
474
3/2 t
3
2
4
First page-mode access takes 3 clocks; the following accesses take 2 clocks each.
The four banks of DRAM are mapped into the TMS320C30 memory space at the address locations shown in Table 5.
Table 5. DRAM Bank Memory Locations in the TMS320C30 Memory Space
DRAM Memory Bank No.
a (RASO,CASO)
400000H-43FFFFH
440000H-47FFFFH
480000H-4BFFFFH
4COOOOH-4FFFFFH
1 (RASl,CASl)
2 (RAS2,CAS2)
3 (RAS3,CAS3)
475
Figures 4 through 6 show the timing for the various DRAM cycles.
H3
H1
;x
ADD~
STRB
--n
:,
;><=
RAS
I
I
I
,
'\
ROWSEL
\1
I
MADD
CAS
ROY
RO~
:x
I
I
1
1
~
I
DATA
I~~:
476
~OL
:X
CO:L
,
,
,
,
H<:
l-
H3
.1
H1
ADD
STRB
.=>:
---1-\
I
I
REN
ROWSEL
MADD
:X
I
I
I
I
"\1
1
RO~
1
1
ROY
1
I
1
CO:L
1
1
II
1
\1
1
1
I
I
I
I
I
;X :
I
1
1
1
1
1
1
CAS
DATA
I
I
I
I
I
I
I
I
I
I
I
I
I
WRi\
RAS
I
1
I
1
):
477
5,
H3
H1
ADD~
STRB~
RAS
ROWSEL
MADD
I
I
I
I
I
I
I
I
:\
I
I
I
I
I
I
I
I
"
/
'/
CAS
ROY
:X :
CO:L
I
I
I
I
'\I
I
DATA
\'
YI
\1I
RO~
I
I
I
I
I
I
I
I
I
I
:<
):
Expansion Interface
The APPB 's two expansion connectors contain the signals from the TMS320C30 expansion
port, serial ports, flag pins, etc. Each 50-pin connector (P3 and P4 of Figure 7) is composed of a
dual row of25 pins located on O.l-inch centers. These expansion connectorsprovide easy connection to other hardware via standard 50-wire flat ribbon cable. Figure 6 shows the orientation of the
connectors. See schematic sheet 7 of Appendix C for pinout details.
478
PIN 1
PIN 1
cccccccccccccccccccccccc
cccccccccccccccccccccccc
ccccccccccccccccccccccc
ccccccccccccccccccccccc
i!:HS~otOOi!:&Sl'fl
479
2)
Each of the seven data segments is totally independent from any other data segment.
However, only one processor can own a particular segment at any given time. The
TMS320C30 and host can simultanously access the dual-port SRAM as long as both are
not trying to access the same segment.
3) The host is the master; the TMS320C30 is the slave. The TMS320C20 polls the
dual-port control segment to determine if the host has deposited a command. If a command is present, the TMS320C30 executes the command and then returns to polling.
4) Only the first semaphore register is used in the dual-port. Each processor uses this semaphore to gain access to the control segment. Access to the seven data memory segments
are coordinated via the control structures, not the semaphores.
5) There are seven control structures in the control segment, one for each data segment.
Each control structure consists of 22 bytes and are defined as follows:
Byte
Name
0
1
2
3
4-7
8-11
12...,21
pfJag
command
buf_stat
nc
count
addr
message
Definition
Buffer present (i.e., being used)
Command to execute
Status of the data buffer
Reserved
Number of 32-bit words to transfer
TMS320C30 to read/write data
Ten bytes reserved for message passing
Appendix A contains routines for the communication primitives used by the host and the
TMS320C30. Appendix Al contains routines for the PC side, Appendix A2 rQutines for the
TMS320C30 side. Note that the routines on both sides have the same names and perform essentially
the same function. Appendix A3 contains a memory map and description (TMS320C30 view). After the code has be~n compiled, use the following sequence to execute the test program:
1) Reset the XDS/I000:
xreset
[RETURN]
c30reset [RETURN]
2)
Get into the emulator and load the TMS320C30 dual-port code.
emu30
xr
10
xd
[esc)
q 'yes'
[RETURN)
'file name'
load emulator
reset the c30
load the object file
execute disconnect
escape to main menu
quit emulator
At this point, your dual bus code should be executing and waiting for a host input.
3)
The host code will then print the numbers 0 through 25 to the screen.
480
Conclusion
This report has provided basic functional details of the TMS320C30 APPB. Because of their
complexity, the DRAM and dual-port SRAM interfaces have been discussed. The features of the
TMS320C30 allow it to encompass a wide range of interfaces. The TMS320C30 bank-switch mode
and continuous strobe signal on back-to-back read cycles overcome traditional DSPIDRAM problems of interface difficulty and limited processor address space. A set of communications primitives routines to use with dual-port SRAM have been provided in Appendix A. These routines are
written in C for ease of understanding and modification to meet individual needs.
481
Appendix A
TMS320C30 Application Board Routines, Memory Map and Description
Al
A2
A3
482
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~
~
~
tv
ac
.~
~
8"
~"
./
/.
i'
/.
/.
APRENDIX Al
TMS320C30 APPLICATION BOARIi ROUTINES - PC SIDE
/,
/.
/.
/.
/.
'/
./
*/
./
./
10125/89
'/
Functions:
./
./
*/
/,
/.
/,
/.
i'
int APPBstset{)
Reset APPB
t/
int APPB_dpinitO
Irltialize {fPB.
int APPB_getsell( i
./
'/
./
'/
int APPB_relsem()
/.
If
il
/.
/.
tnt APPB_9.tctlblkll
lnt APPB_relctlblkO
int APPB_9I'!tmtlllblk()
lnt APPB_putlDflllb]kO
'/
./
./
./
All codl'! !lias cOlpi 11'!d with MICrosoft C coltpi In vus.ion 5.1 using ttll'! II
Jarill'! model. If small modI'! I is uSl'!d, thl'!n pointers used to access the 1/
dual port SRAM ~ould have to be declared and used as /farJ pointers
./
(I.e. 32-bit pOInter). Under the large Itodel, all pointers. ar-e
</
./
dehulted to 32 bits.
./
i'
~
;::
/,
/1
IlHH***fHIUffHllu*****UHIUUIHflflflUHHllffflfffHHfff-fHfIHfH/
~
q
'1:;"
/.
/.
if
Include (stdio.h)
00
0:<1000
7
512
S
10000
Itdefine
BUF_EMPTY
BUFJ'ULL
#define
.define
'define
.NOP
HOSTJfEJ'LWR
HOSU1EJ1-RD
typedef
~.
0<00
Ox80
Ox81
typede-f
typedef
strutt
UCHAR
UCHAR
IXHAR
ULQNG
ULONO
UCHAR
lDPCNTL;
:=
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typedef
UCHAR
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r:n
w
N
pflug:
cOMland;
buf_stat;
nc;
count;
addr;
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if
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t/
if
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t/
l*fltfHfHlf********IHIHf***HfffHlfHfffUflUIUHfHIHIHIIIHf+ffHII
(Iutport
irloort
SEM_BASE
MAPJlEG
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inp
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0.0338
~x0339
/'
IN
tdefine
DPRAILSIZE
DPRAIUILJ(S
DPRAILBLJCSIZE
NIJILSEIIS
MAX-SEll_TIllE
0;
1**lfHHHlf**HfHlffHfIIHHIUH****HIUffUUUlffIHHHfHfffHff**11
#define
#ddine
#deflne
idefine
'define
'define
.define
'define
.define
'define
.define
ide fine
idefinl1'
#dl1'firlt'
#define
#define
#defHlf
""define
CINT
XINTCLR_
DPSEL
SWRESET_
XlNT
CINTCtR_
MBANK
MSWAP
idefine
'define
Iddine
0X(900000Q
DPRAILCTL
DPRAI1..SEG
OxC9
DPRAlLtEMBASE 0xC9000200
OxOl
0.02
Ox04
OxOB
0,10
0x20
Ox40
OXSO
o
:=
CIJ
eo
"1
Q.
:=
.....
S
~
CIJ
("j
r:n
s:
~
/*t.HlffHftHt***tHHfHUfHHHHHffIUHHfIUH....tlHHIIHHHtfHH/
I '*ftHltHIHftH'.+HIH*f*IHHHH:lHHHHHf4tfIH"fHfftHtfHHIHH I
*/
/t
/I
IV'P[Lresettl,PC side
I,
*/
*/
If
Reset APPB.
./
*/
/.
*/
*/
*/
If
'*If
/fH*'*fHHH:lHfffH"*.tHHH**H**fHHtHHf"tfH"*lfHfttHffHtHH/
If
/I
Test
prQ~riLli.
/*
/*
/*
SeQuence:
/*
/*
/*
H
./
-*/
./
Sequence:
1) Cleu control rtgister.
2) Set Sltrf.SEL to 1.
./
./
./
i'
/HfH""*flffffHfHfHHfHHHf**fffHf**HHHfH**ff+********ffHHHUf*/
IrIilO( )
lnt APPB_restt()
GINT
sermuli(DPRAILBtJ;Sl;
int i;
ULONG
outport(CTLREG.OJ;
outport (ClL.REG. SWRESET _i;
return(O);
1If!lIIarrayC25J,/fle1l2array[251;
APPB_dpiot(};
/HH*****UfHf*HHf**fHfHffUHfff****UHUf******fHfH****UH****f** I
~
~
tv
ac
~
'15
r
~
a.
;::
l~
q
"6.
g'
=OOL;}
/I
'*/.
APPB_dpintO, PC side
i*
Sequence:
'*/*
/*
/.
/.
./
*/
./
*/
*/
*/
*/
*/
JHHHlffHfHfl**HHIHfHfHIHHflfffHflf******HHHHf**UfIHffH+H/
f!).atWh
iot APF'B_dpintt)
(
iot 1:
UINT uw,ddr = saLBASE;
LOiAR fdDrar.
= (UCHAR
fJDPRA/'LCTL;
;;a
~
ac
~
~
2
~"
;::,
it
~
IHHHI.U**UHUtU**********U**************HffHtHHtf****UHUU****1
IHfHHttH*******UHUHttHHHfHffHffHHH****tffHHHU*****U*U**/
H
1*
/.
/f
H
/.
/f
/.
/t
/t
II
APPILgetstlO, PC Slde
./
+i
./
H
APPB-rel sel() , PC side
/.
/. Relust selrlilPhore at "selnul /
/. Return a 0 if successful, a -1 if filled:
/.
/. Sequence
/.
H I) Wrt te 1 to semaphore.
1* 2) Decreaent tilteout, check for tUleout = 0,
II 3) Return pass/fai 1.
/.
./
./
./
+i
*/
./
*/
./
./
Sequence
+i
./
1/
1)
Write 0 to SfDipnore.
= O.
*'
1/
q
'B"
.j>.
00
VI
seuphore = 1.
*/
./
*,
/HfHfHffH**H***HU*******Htftftitt-Htt+tHftHHHfH**fU********t****1
IffHfHUHfHHffHfHfffHfHU. . .fHffHIH+tHHfHfHHHilfHtffH**H'1
int APPB_getsem(seltnulII)
UINT selrloufI;
UINT tir.eout
= I1ALSEM_TII1E:
till'leout
=MAX-SaLTIME;
outport{snaddr, OJ;
t1hile{ --tilleout lo:& (wport(sewddrl & 1));
outoort(selMddr ,11;
while( --til1eout U !(iilport(Seiliddr) &: 1));
ifltir.eoutl retur-:tIOI;
else returrl(-ll;
;::
./
(It
else returrd-l};
j*********llfHlfHUU***ftH**H*f**f**fffffHHIIfH4HHfUHfHf***nUf/
It*f*HHHt**HHHtHttfHHfUfffHfftfffftffHffHHttff**flftHHtt***H I
C1'I
1*
H
If
00
'*
'*
/f
1*
/'t
Sequence
'*
1)
If
if
,.
/4
.,
.,
*1
APPB-getctlblldl, PC iide
*1
*'
t/
*1
*'.,*',
!H**f***U**********HHH-U****-**H****U**U*****f*HfHlfflftHt**tnHltf!
'*
,.''**
'*
"
,.,,*
U'PB_f"elctlblk.(). PC side
Reiea.se block of memory in the dual por-t.
Return a 0 if successflJI, a -1 If fa.ileo.
Sequence
t)
2)
Int APPB_reldlblk(selilnUIII)
UINT sell'lf\um;
'"
~
~
ac
.~
:g
[
~"
a
~
;:::
[
~
'lj"
'
If\t 11
DI'CNTL "pctl = IIJPCNTL ,)OPRAM_CTL;
tselllrlUIIl;
iot i;
DPCNTL *,octl = IIJPCNTL *)IJPRAM_CTL;
lfU\PPB_getsell(Q})
r-eturrd-U;
= 1;
dpdl[il.collDliod = NOP;
oPctHl),tluLstat = BUF_Et1PTY:
fsemnum
= 1:
it(APPB_reisem(O)l r-ehrn(-U:
else r-eturn<Ol:
APPB_l'tdseIl'lW): f"eturn(-ll;
*,
*,*'
.,.,*'
.,.,
*I
It**HftHttfHffHHu"***ltltfHtHHHtfHHt*tftfft**t**tU:**HHHtHtH:IHI
lnt APPB_getctlblk(sellloul)
UINT
U
*1
i******HUHUIHtlfHI.HfHHUHUfIH*tHfffH********UffHHHHHff**!
;;'l
'"
i!~
~
Q
c
~
'15
r
~
a.
~
H
/f
I'
,.,.
,*
,.,*
,.
i*
"
APPB_putlleflblkO, PC side
it
/HfH*HHHH-fHf****HfH**HffH*f:HHHHHHHHHH*****HHfHH*HH/
int APPB_putllellblk(cnt,src,dst)
ULONG cot:
ULClH3 *src;
ULONG dst,
''**
,.'*'*
,.,.
APPB.g,tleflblktl, PC side
I'
*'.,
.,
"
./
*,
*'
Sequence
,*
'*
'*
;*
21
3)
lot
i;
dpra.
= IUlONi)'IIDPR/iU'EIiBASE
+ Idpblk fl'RAII-IlLLSIZEII,
= *5r(++;
IHAPPB_gehelft(OJ)
"tu"I-II,
if(APPB.getstll(O)) returnl-lI;
r'eturn{-H;
dpctHdpblkLcolMtand = HOSTJlB'LWR;
dpctHdpblkl.buLstat = BUF-FULL,
(iDctHdpbIU.colJot
= cot;
dDctHdpblkJ.ador
= dst:
if(APPB_r~lsem(O))
returnl-ll;
opctJ[dpblkJ.co_no = HDSUElLRD,
dpctHdpblkl.buLstat = Blf-B1F'TY;
dpctHdpblkLcount
= cnt;
dpctl[dpblkl.a.ddr
= sre;
wlllle( -timeout )
(
iFl!APPB.getse/lW) U (dpctHdpblkl.buLstat
if(APPB_relsellt(O return(;"ll;
00
-...J
*,.,
!ttttttUU*HfftffHHUtftt***ffffUHff**tUUttUfftfffUUUHHtUfHlf!
lILONG fopram;
'pblk,
*,
*'
*,
w
g.
/HffHHHffff:lfHffffffHUfHHfHHUffHtHUtHtHtff:lfffftffffftttfltt!
,."
/1
;:s
~.
.,
.,.,"'
.,
"'.,
*,
.,*,
1/
BUF.FULl) I break;
!UftHUHUffUfUUUffHtHfHffHffffffffffHfIfHfffffHffffffffHHfff!
00
00
,.,.'I
,.
tI
I'.,
III'PENDIX A2
./
1/
/.
'I'I
'I,.'I
/1
/.
/.
/.
;;i
Intiilizt APPB.
Get iCc.tSS to stHPhore bit N
RelttSt iCCesS to stlliphort bit N
Get i control block in tfRAl1
ReltHt control block in CfRAK
Get I block of lWIIory fro. mwt
Put I block 'Of at.'Ory t'O f.fRM
Rtid I long lnt fro. tht rfRAI1
Rud l cOIIIlnd ind pirueters frOi
I'
-,I'
I fflffflfffulffluUllullIMIHIHHl-fffUffffllHfffffffffffHflffflHffffl
/HfHHflfnHMfffHfHHHUHl-ffHHfffHHHlffffHfIHHlffHIHfffffff!
~
-.;:;
::::
5-
~.
a.
~
if
/.
/.
'dtfirrt
Idtfine
itdehne
'4ffint
Id-ahnt
'dehnt
.dthnt
.dthne .
'dtfine
.<ltho.
SClLBASE
CTUlEG
0x00805FF8
OxOO805fF7
CINT
UNTCI.R..
DPSEL
SIillESEL
UNT
CINTCI.R..
0.01
0.02
0x04
OXOO
Oxl0
I1SWIV'
0x80
0><20
Ox4O
tl.
~o
I<Itfint
'dtfine:
tl
'4tfint
Idtfint
'd.fint
Id+hrrt
0x00804000
0x00804200
Oxlooo
lfRAIUll(S
7
lI'RAIl.Bl.K.SlZE 512
IUUaIS
8
MX_SCILTll
10000
'defin.
Idtfi ..
8UF..EIf'TY
8UF-FI.lL
..gO
~o
0x80
typtdtf
typtdtf
typt<ltf
ty.. dtf
Idtfiat
lfRAILCTl
lIPAAUIEltlIASE
lPRAII..SlZE
Ox81
>
struet
(
!.CHAR
lCltM
lCHAR
lCltM
I.CHAR
UCfWl
lCltM
pflog,
cOlRnd;
buf_sh.t;
nc;
count[41;
lddr[4J,
aesngt(101;
l~TL,
Iyp.d.f
struct
(
lOiAR
I.CHAR
!LOll)
!LOll)
om,
ICld;
.ent;
Nddr;
"0
"0
tl)
=
....
Q.,
~
~~
.
=
....
S J-3
tl)
~~
~~
./
CJ)('j
./
./
N=
=>
0"0
="0
/ffffflfUftfftHfffffiffffHfHfHHHHffHfHHHfffffHfHfffHfffffffHII
;:
0x00
IflST..IEIUIl
fIlST..I'IElI..RD
llf'ARI1S,
Q
C
ra
./
1/
./
./
./
/.
./
/.
/.
tI
./
/1.
~ 1/
./
/.
/. All coGe WiS coapiltd wlth TI'tS320C30 C co.plltr version 2.1, IJsing the II
./
/. SKlI lodel.
./
/.
,.
'"
III'PLdpinito
APPB_getStl()
APPBJ'elstllO
III'PB_9tlctlblkll
APPB_rtlctlblkl)
III'PL9tt...blkll
III'PLput...blkO
Af'PILgetlongO
tfPfLgetcolIMndl)
.,
.,
Idtfint
IeItfine
Idtfint
~fM
CJ) _.
.... r')
Q.,I
tD ::.
Q
=
r:Il
Q
I
,.,
Q.,
']he
/IHHIIHfIHIIHHHHHHIfHHIHI*"lunfHHHHHHlIHHIHHltHfH/
/.
/.
/.
/.
/.
/.
/.
/.
/.
<::>
a
<::>
~
'15
8
~.
;::
t
~
!:i
"i:j'
g'
t!
./
./
It
/. ~B_rtlse.(), TI1S32OC3O side
/.
/
Releue stlapnore olt ~se.nuI'
/.
/. Sequence
/.
II - 1) Writt 1 to se.a.phore.
/. 21 Ilia till rud 1.
./
./
ItfHffHHIHfI"*IHfftHIHfffftHfffffffHfHfHfnHIHHffHfffHfHfH I
int APPB_gehtll(seenuI)
UINT seanu.;
*seli.ddr
flfftHffHlfffffHfffHHffHffHfffflllHffflHlflffHHflflflHfffHHHf/
./
./
./
t!
IfHfHfHflHfllfffffffHlfHfHHffHfffHffffffffflfffffflHHtfttfffflffl I
l.ICWIR fseNddr
~
~
~sellnua~
Sequence
./
./
./
./
/
./
./
=0;
= (UCHAR fHsaLBASE
./
./
+ semnu.J;
UCHAR fsefliddr
fseHddr
= 1;
= (OCHAR
1)(SEl'LBASE + sunuI);
IIIhile(~tfselliddr ~
lll)); returntO);
<I>
~
N
C
Q
c
~
"'5
2
~.
it
~
;::
~
t
~
/,*HIHHfHfIIHf**H'HHfffftffttfHfHtUUHHHHHffIfUf'-IHf*******1
H
/*
'*/*
/t
/t
/*
/.
/.
/.
Ii
21
31
if
1/
*/
1/
If
II
*/
1*
1/
II
*'t/
/.
II
II
If
H
~PBselctlblk(),
TMS320C30 side.
2)
int APPB_relctlblk(selnulII)
UINT sellnult;
APPB_getseaW) ;
dflctHsflllnulrI1.pfla9
dpctl[snnulJIl.colllland
dpctHselllnulIIJ.buLstat
IULII
dPctHiJ.pHag
= 1;
dpct\[il.colllllli.nd = NCfi;
dpctHU.buLstat = BLF_OIPTY;
fselll~ulI
= 1:
APPB_ri!!sflllO);
returntO);
~PPB_relselrl(OJ;
returll(-U;
*/
*i
./
*/
*/
*/
APPB_getsem(OJ;
ifl~ldpctlm.pfl.g ~
.,
*/
/HH******H*lltfHHHIIHHIHI*IH*I*HHflffff**H**I**lfftffHitfffftlft/
iot i;
Dl'CNTL *dpctl = IDPCNTL 'IDPRAII..CTL;
iot i;
*1
~.
t....
*/
*/
./
/*
/1
*/
/HHfHf,**********f********************tf*****tI-Hfff***UfffffHfffH*HH/
iot APPB_getctlblHselllflUII)
UINT *sellnum:
<":>
g'
1***HfHHfftff:tlfffHffHHHfHHHfHfHHfHffflffflfffffffHfHfffff**11
APPB_relsem(O);
=0;
= NOP;
=BUF.B1PTY;
returnlOl;
IHnUHfffHftHfffHffUfHfftHfffHHffffffHfffffHfHflfHHHHHffH!
~
't
~B_putllt.Olldl.
TttS32OC3O side.
't
't
't
't
'I
'I
't
/t
"t'
t'
t/
t'
t/
1/
t'
I'
I'
I'
I'
I'
I'
't
'I
'I
't
'I
'I
'I
Sequence
21
jff"**HHf-ffHHtHfoffH-IIHHHHHtHffHffHff*. .ffHffffHHHHHfHfti
int APPB_get...blklcnt,dst,dpblkl
u..0N3 ent;
cnt;
LlL(W ISl'e;
ll.CKi itdst;
lilNT opblk;
U!NT dpblk;
DPC~TL
'"
t'
I'
t'
t,
StQutnce
UL~
;;l
/fffHfllfftHfHHfffHHHHUffHfffttIHHHffflfffllffHffHffltHltttH/
L(;HAR
tdpru;
lII.OJ(i
temp;
lnt
i.H
LtHAR IdprH;
ULON)
int
ttop;
i,jl
APPB_9@tsellll!ol:
top =OUL;
for(j=O;j<32;j+=81 teep
doctl[d,blkJ.buL,t.t BUfJULL;
*dst++
~
tv
'1:l
'"
it
~
'i'
g'
DPRAILBUCSllEll;
= hip
J; }
:=
*dpru++) WxOOOOOOffl
= telP;
APPB-reiselrl{O); returnW);
APPB_re lctlblkldpblkl;
returnlOI;
j;
;;l
/HfUHHf****t*UfHU*******ffU4f*********UH+fHf.HU******U**fnfnfl
I *****U. .I-HHH***fHffHHHHffffHfHfHHHHf****HffffffH*HHfHtff I
'II
'"
1*
1/
/.
/.
/.
/*ffHfHUH**fH***fffHf*******H+HHI**********ffHff***fffHffHfUHH/
It
Int APPB_getlong(src,'15tl
ULONG "sre:
/.
/.
/.
/.
/.
~
tv
ac
~
~
~
~.
it
~
;:
~
~
-e.'...."'
.
h
/f
H
Get a long 1II0l'd of data froll the dllal port.
ULONG jj.dst;
int j;
*dst = OUL;
for(j=O;J<3'2;j+=8) -Idst 1= (1*5rc++) & OxOOOOOOffl
return(Oi:
/*
j;
/.
H
fff'B_getcolIlI'tandll, T11S32OC30 side.
"
*/
./
*/
./
*/
*/
SeQuence
11
21
31
41
51
./
IHfUf*****Hf*fH*flfflffff**ffffHffHHHf**Hff**H*ff*H**Hffffffff*ffl
int APPB_getcohlla.nd(lIIpuIAS)
MPARI'IS filipa-tillS;
DPCNTl *dpctl = (DPCNTl fIOPRAfLCTl;
static int currer,LbH: = -1;
HPPB_getsf!lll(O);
if(curru,Lblk
)=
while(currenLblk++
< DPRAI'LBLKS)
if(dpctHcurrenLblkl.pflag II lULi
(
APPB_relsem(O); mpa.rlRs-)lIcmd
tY>
./
H
./
=NOP;
r-eturn(O);
003FFF
3FFFFF
4FFFFF
43FFFF
47FFFF
4BFFFF
4FFFFF
7FFFFF
801FFF
805FFF
805FFF
804FFF
805FF6
FOO800-
FFFFFF
494
805FFF
807FFF
8097FF
809BFF
809FFF
EFFFFF
F03FFF
495
Appendix B
Modules
Appendix
Bl
B2
B3
B4
B5
B6
496
Name
Module U5 - TMS320C30 Software Development Board
ModiHe U6 - TMS320C30 Software Development Board
Module RAMDEC - TMS320C30 Software Development Board
Module RDYEN - TMS320C30 Software Development Board
Module RAMCONTROL - TMS320C30 SWDS DRAM Module
Module RAMDEC - TMS320C30 SWDS DRAM Module
Pin 1;
Pin 2;
Pin 3;
Pin 4;
Pin 5;
Pin 6;
Pin 7;
Pin 8;
Pin 9;
Pin 10;
Pin 11;
Pin 12;
Pin 13;
Pin 14;
Pin 15;
Pin 16;
Pin 17;
Pin 18;
Pin 19;
Pin 20;
Pin 21;
Pin 22;
Pin 23;
Pin 24;
SA = [SA9, SA8, SA7, SA6, SAS, SA4, SA3, SA2, SAl ,SAO];
X = .x.;
equations
!NQG
= !XAEN & (SA == "h338);
!NRG
= !XAEN & (SA == "h339);
!NDPSEML = !XAEN & SA9 & SA8 & !SA7 & !SA6 & SAS & SA4 & !SA3
& !NSIOW
# !XAEN & SA9 & SA8 & !SA7 & !SA6 & SAS & SA4 & !SA3
& !NSIOR;
TMS320C30 Applications Board Functional Description
497
!NDPCEL
SGAB
!NSGBA
end US
498
XSUF10
Device
CIOAO
CIOA1
CIOA2
CIOA3
CIOA4
CIOAS
CIOA6
CIOA7
CIOA8
CIOA9
CIOAlO
GND
CIOA11
CIOA12
TIOW
NSRANGE
CIORNW
NFR
NFG
NDPMEMGR
NDPSEMGR
TIOR
NCIOSTRB
VCC
Pin 1;
Pin 2;
Pin 3;
Pin 4;
Pin 5;
Pin 6;
Pin 7;
Pin 8;
Pin 9;
Pin 10;
Pin 11;
Pin 12;
Pin 13;
Pin 14;
Pin 15;
Pin 16;
Pin 17;
Pin 18;
Pin 19;
Pin 20;
Pin 21;
Pin 22;
Pin 23;
Pin 24;
'P20L8';
X = X;
C= .c.;
CIOA = [CIOA12,CIOA11,CIOAlO,CIOA9,CIOA8,
CIOA7,CIOA6,CIOAS,CIOA4,CIOA3,CI0A2,CIOAl,CIOAO];
equations
!NSRANGE
499
!NFG
!NFR
!TIOR
!TIOW
= NCIOSTRB
# (CIOA >= "hlFF7)
# !CIOA12
# !CIORNW;
= NCIOSTRB
# (CIOA >= "hlFF7)
# !CIOA12
# CIORNW;
test vectors
[0,0,0, 1, 1, 1,0];
[0, 0, 0, 1, 1, 1, 0];
[0,0,0, 1, 1, 1,0];
[0,0,0, 1, 1, 1,0];
[0,0,0, 1, 1, 1,0];
[0,0,0, 1, 1, 1,0];
[0,0,0, 1, 1, 1, 0];
[0,0,0,1,1,1,0];
WRITE TO F REGISTER
["h1FF7, 0, 0] -> [0,0,0,0,1,1,1];
READ FROM F REGISTER
["h1FF7, 0,1] -> [0,0,0,1,0,1,1];
NCIOSTRB DISABLED
[ X , 1, X] -> [0, 0, 1, 1, 1, 1, 1];
EXTERNAL READS
["b1000000000000, 0,1] -> [1,0,1,1,1,1,1];
["blO00000000001, 0,1] -> [1, 0, 1, 1, 1, 1, 1];
["b100000000001O, 0, 1] -> [1,0,1,1,1,1,1];
["b1000000000011, 0,1] -> [1, 0,1,1,1,1,1];
["b1000000000100, 0,1] -> [1,0,1,1,1,1,1];
["b1000000000101, 0, 1] -> [1,0,1,1,1,1,1];
. ["b1000000000110, 0,1] -> [1,0,1,1,1,1,1];
["b1000000000111, 0,1] -> [1,0,1,1,1,1,1];
["blO00000001000, 0, 1] -> [1,0, 1, 1, 1, 1, 1];
["blOOOOOOOOlO01, 0,1] -> [1,0,1,1,1,1,1];
500
test vectors
([CIOA12, NCIOSTRB, CIORNW] ->
. [TIOR, TIOW, NSRANGE, NFG, NFR, NDPSEMGR, NDPMEMGR));
DUAL-PORT SRAM READ OR WRITE
[0, 0, X] -> [0,0,0,1, 1, 1 ,0];
end U6
TMS320C30 Applications Board Functional Description
501
device
'P16L8';
a12
a13
a14
a15
a16
a17
a18
a19
a20
a21
a22
a23
m_swap
vss
Pin 1;
Pin 2;
Pin 3;
Pin 4;
.Pin 5;
Pin 6;
Pin 7;
Pin 8;
Pin 9;
Pin 11;
Pin 13;
Pin 14;
Pin 15;
Pin 10;
memen
sram
eprom
busen
vee
Pin 18;
Pin 17;
Pin 16;
Pin 12;
Pin 20;
madd = [a23,a22,a21,a20,a19,a18,a17,a16,a15,a14,a13,a12];
equations
"On reset the eprom and sram maps are swapped
"
m_swap = 0
m_swap = 1
"sram
FOOOOO-F03FFF
000000-003FFF
"eprom
000000-003FFF
FOOOOO-F03FFF
sram
eprom
= !(!eprom # !memen);
TMS320C30 Applications Board Functional Description
test vectors
([madd, m_swap] -> [sram, eprom, memen, bus en])
["hOOO, 1 ] -> [0, 1, 1,
1 ];
["hOOO, a ] -> [ 1, 0, 1,
0];
["h004, 1 ] -> [ 1, 1, 1,
1 ];
["hFOO, 1 ] -> [ 1, 0, 1,
0];
["hFOO,
1 ];
] -> [0, 1, 1,
["hFFO, 1 ] -> [ 1, 1, 1,
1 ];
["hFOO, 1 ] -> [ 1, 0, 1,
0];
["h400, a ] -> [ 1, 1, 0,
["h4CF, 1 ] -> [ 1, 1, 0,
0];
1 ];
["hBOO, 1 ] -> [1, 1, 1,
];
endRAMDEC
503
device
c1k
busen
eprom
strb
rd_wr
bhiz
oe
vss
Pin 1;
Pin 2;
Pin 3;
Pin 4;
Pin 5;
Pin 7;
Pin 11;
Pin 10;
dat_rd
dat_wr
prdy
epromcs
vcc
Pin 19;
Pin 18;
Pin 17;
Pin 12;
Pin 20;
c=
'PI6R4';
"eprom/dram data bus enable
"epram select
"c30 strobe
"c30 read/write
"dram expansion bus hold
.c.;
equations
"note: bhiz is active for 1 TMS320C30 clock cycle at the end of a dram
"
access. This provides the necessary turn off time between
"
dram/eprom accesses.
epromcs
prdy
504
!rd~wr
& bhiz);
!(!busen & !strb & rd_wr & prdy & !eprom & bhiz);
test vectors
([elk, strb, busen, rd_wr, eprom, oe, bhiz ] -> prdy)
[ c, 1, 1, 1, 1, 0, 1 ]-> I',
[c, 0, 0, 1, 0, 0, a ]-> I',
[ c, 0, 0, 1, 0, 0, 1 ] -> 0',
[ c, 0, 0, 1, 0, 0, 1 ] -> 1;
[ c, 0, 0, 1, 0, 0, 1 ] -> 0',
[ c, 1, 0, 1, 0, 0, 1 ] -> I',
[ c, 1, 0, 1, 0, 0, 1 ] -> I',
test vectors
([strb, busen, rd_wr, eprom, bhiz ] -> [datJd, dat_wr, epromcs])
1 ];
[ 1, 1, 1, 1, 1 ] -> [ 1, 0,
1 ];
[ 0, 0, 1, 1, 1 ] -> [ 0, 0,
1 ];
[ 0, 0, 0, 1, 1 ] -> [ 1, 1,
1 ];
[ 0, 1, 1, 1, 1 ]-> [ 1, 0,
1 ];
[ 1, 0, 1, 1, 1 ] -> [ 1, 0,
check eprom
1 ];
[ 1, 0, 1, 0, 1 ] -> [ 1, 0,
];
1 ] -> [ 0, 0,
[ 0, 0, 1, 0,
1 ];
[ 0, 0, 1, 0, a ] -> [ 1, 0,
1 ];
[ 0, 0, 0, 0, 1 ] -> [ 1, 1,
1 ];
1 ] -> [ 1, 0,
[ 0, 1, 1, 0,
1 ];
1 ] -> [ 1, 0,
[ 1, 0; 1, 1,
end RDYEN
505
device
'P16R8';
elk
refre'L
strb
rd
memen
oe
vss
Pin 1;
Pin 2;
Pin 3;
Pin 4;
Pin 5;
Pin 11;
Pin 10;
"refresh request
"c30 strobe
"c30 read/write
"memory board chip select
"pal output enable
sO
refelr
casen
ren
rasen
mrdy
busact
s1
vcc
Pin 19;
Pin 18;
Pin 17;
Pin 16;
Pin 15;
Pin 14;
Pin 13;
Pin 12;
Pin 20;
"state variable
"refresh clear
"column address strobe
"write strobe
"row address strobe
"dram ready strobe
"dram bus active
"state variable
idle
rasO
casO
cas1
whld
trp
refl
ref2
ref3
ref4
=
=
=
=
=
=
=
=
=
=
refreq
strb
me men
oe
c = .c.;
506
c = .c.;
output = [refclr,rasen,casen,mrdy,busact,sO,sl];
equations
.!(lrd &
ren
state_diagram output
!strb~;
state idle:
case (refreq & strb & memen)
( refreq & strb & !memen)
(refreq & !strb & memen)
(refreq & !strb & !memen)
(!refreq & strb & memen)
(!refreq & strb & !memen)
(!refreq & !strb & memen)
(!refreq & !strb & !memen)
endcase;
:refl;
:refl;
:refl;
:refl;
:rasO;
:idle;
:idle;
:idle;
state
rasO:
goto casO;
state
casO:
case rd
!rd
endcase;
state
casl:
case strb & !refreq
strb & refreq
!strb & !refreq
!strb & refreq
endcase;
state
whld:
case strb & !refreq
strb & refreq
!strb & !refreq
!strb & refreq
-endcase;
state
trp:
case refreq
!refreq
endcase;
"cas,ras high
:refl;
:idle;
state
refl:
goto ref2;
"cas,refclr low
state
ref2:
goto ref3;
"ras low
507
state
ref3:
goto ref4;
"cas high
state
ref4:
goto idle;
"ras high
0,
1,
1,
1,
1,
1,
0,
0,
0,
1
1
1
1
1
1
1
1
1
]->[idle, 1];
]->[rasO, 0];
]->[casO, 0];
]->[whld, 0];
]->[refl, 0];
]->[ref2, 0];
]->[ref3, 1];
]->[ref4, 1];
]->[idle, 1];
end RAMCONTROL
508
device
'P16R4';
clk
refclr
a18
a19
memen
strb
mux
oe
vss
Pin 1;
Pin 2;
Pin 3;
Pin 4;
Pin 5;
Pin 6;
Pin 7;
Pin 11;
Pin 10;
rasO
ras1
ras2
ras3
rowsel
vec
Pin 17;
Pin 16;
Pin 15;
Pin 14;
Pin 13;
Pin 20;
"ras select 0
"ras select 1
"ras select 2
"ras select 3
"row address select
c= .C.;
equations
rasO :=
ras1 :=
ras2 :=
ras3 :=
rowsel = mux;
509
];
];
];];
test_vectors "rowsel
(mux -> rowsel)
1 -> 1;
-> 0;
endRAMDEC
510
Appendix C
TMS320C30 Application Board Schematics
Appendix
Cl
C2
Title
TMS320C30 Software Development Schematics
TMS320C30 SWDS DRAM Module Schematics
511
512
:;l
""
~
.---_~ ____~ ______7~ ____~ ____~ ____~ ____~ ____~~ ____~ _ _._~----~-----L----~~--~------~----
REVISIONS
NOTES,
ALS.
I_~
ac
z vee
'
i'
4.
'2
~
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ee AHD e4
1. 2. AND 3
vee. At1D va?
il
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-
7.
IN OHMS.
11'4 UATT,
S~.
IN MICROFARADS.
COItTDITS
TITLE PAGE
PC leT COHHEC1URS. BUFFERS. _
TRAHSCEIVEIIS
DUAL PORT SRAH ./WiD EXPAltSIOH BUSS COIn'ROL CI RaJ I TRY
EXPAHSIOH BUSS 16K >< 32 SRAH
'D1S328C38 IlUSSES
'D1S3211C38 TIHERSIGHALS, 12-PIH Itn'ERFACE, PIJLL--IJP PACKAGES
ADDRESS BUSS AND alH'l'ROL SIGNAL BUFFERS
DATA BUSS ~IVES
TARGET ~ cotItECTllRS, ItEI1OI1Y EXPAHSIOH ~ COHHEC1URS
PARALLEL BUSS HIttORY EXPAHSIOH
MRALLEL BUSS COITROL CI RaJI TRY' AND EPROHS
DECOUPLIHG CAPACITORS
S
6
gO
REFERENCE DESIGNATORS
1
2
3,
4
W
"S'
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5
1:0
PAGE
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TMS320 Bibliography
Since the TMS32010 was disclosed in 1982, the TMS320 family has received an ever-increasing amount of recognition. The number of outside parties contributing to the extensive development support offered by Texas Instruments is rapidly growing. Many technical articles are being
written about TMS320 applications in the field of digital signal processing.
The following articles and papers have been published since 1982 regarding the Texas Instruments TMS320 Digital Signal Processors. Readers who are interested in gaining further information about these processors and their applications may obtain copies of these articles/papers from
their local or university library.
The articles are broken down into 12 different application categories. Articles in each category are in reverse chronological order (most recent first). Articles having the same publication date
are shown in alphabetical order by authors name.
The application categories are:
1) General Purpose DSP
2) Graphics/Imaging
3) Instrumentation
4) Voice/Speech
5) Control
6) Military
7) Telecommunications
8) Automotive
9) Consumer
10) Industrial
11) Medical
12) Development Support
General Purpose DSP
1) R. Chassaing, "A Senior Project Course in Digital Signal Processing with the TMS320,"
IEEE Transactions on Education, USA, Volume 32, Number 2, pages 139-145, May
1989.
2) P.E. PapamichaIis, C.S. Burrus, "Conversion of Digit-Reversed to Bit-Reversed Order
in FFT Algorithms," Proceedings of ICASSP 89, USA, pages 984-987, May 1989.
3) P.E. Papamichalis, "Application, Progress and Trends in Digital Signal Processing,"
Proceedings of Mikroelktronik Conference, Baden-Baden, March 1989.
4) R. Chassaing, "Adaptive Filtering with the TMS320C25 Digital Signal Processor," Proceedings of 1989 ASEE Conference, USA, pages 215-217, 1989.
5) P.E. Papamichalis, R. Simar, Jr., "The TMS320C30 Floating-Point Digital Signal Processor," IEEE Micro Magazine, USA, pages 13-29, December 1988.
6) K. Rogers, "The Real-Time Thing (Digital Signal Controller)," Electronic Engineering
Times, USA, Number 506, page 85, October 1988.
7) P.E. Papamichalis, "Impact of DSP Devices on Fast Algorithms," Proceedings of the
1988 IEEE DSP Workshop, USA, September 1989.
Digital Signal Processing Applications with the TMS320 Family, Vol. 3
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25) W.S. Gass, R.T. Tarrant, T. Richard, B.I. Pawate, M. Gammel, P.K. Rajasekaran, R.H.
Wiggins, C.D. Covington, "Multiple Digital Signal Processor Environment for Intelligent Signal Processing," Proceedings of the IEEE, USA, Volume 75, Number 9, pages
1246-1259, September 1987.
26) L. Johnson, R. Simar, Jr., "A High Speed Floating Point DSP," Conference Record of
MIDCON/87, USA, pages 396-399, September 1987.
27) K.S. Lin, G.A. Frantz, R.Simar, Jr., "The TMS320 Family of Digital Signal Processors,"
Proceedings of the IEEE, USA, Volume 75, Number 9, pages 1143-1159, September
1987.
28) S.L. Martin, "Wave of Advances Carry DSPs To New Horizons. (Digital Signal Processing)," Computer Design, USA, Volume 26, Number 17, pages 69-82, September 1987.
29) C. Murphy, A. Coats, J. Conway, P. Colditz, P. Rolfe, "Doppler Ultrasound Signal Analysis Based on the TMS320 Signal Processor," 27thAnnuai Scientific Meeting ofthe Biological Engineering Society, Great Britain, Volume 10, Number 2, pages 127-129, September 1987.
30) G.S. Kang, L.J. Fransen, "Experimentation With An Adaptive Noise-Cancellation Filter," IEEE Transactions on Circuits and Systems, USA, Volume CAS-34, Number 7,
pages 753-758, July 1987.
31) R. Chassaing, "Applications in Digital Signal Processing with the TMS320 Digital Signal Processor in an Undergraduate Laboratory," Proceedings ofthe 1987ASEEAnnual
Conference, USA, Volume 3, pages 1320-1324, June 1987.
32) D. W. Horning, "An Undergraduate Digital Signal Processing Laboratory," Proceedings
of the 1987 ASEE Annual Conference, USA, Volume 3, pages 1015-1020, June 1987.
33) D. Locke, "Digitising In The Gigahertz Range," lEE Colloguium on Advanced AID
Conversion Techniques, Great Britain, Digest Number 48, 10/1-4, April 1987.
34) S. Orui, M. Ara, Y. Orino, E. Sazuki, H. Makino, "Realization of IIR Filter using the
TMS320," Resident Reports of Kogakuin University, Japan, Number 62, pages
195-204, April 1987.
35) R. Simar, T. Leigh, P. Koeppen, 1. Leach, 1. Potts, D. Blalock, "A 40 MFLOPS Digital
Signal Processor: The First Supercomputer on a Chip," Proceedings of ICASSP 87,
USA, Catalog Number 87CH2396--0, Volume 1, pages 535-538, April 1987.
36) R. Simar, "TMS320: Texas Instruments Family of Digital Signal Processors," Proceedings of SPEECH TECH 87, USA, pages 42-47, April 1987.
37) G.Y. Tang, B.K. Lien, "A Multiple Microprocessor System For General DSP Operation," Proceedings of ICASSP 87, USA, Catalog Number 87CH2396-O, Volume 2,
pages 1047-1050, April 1987.
38) L. Vieira de Sa, "Second MicroProcessor Enhances TMS32020 System," EDN: Electronic Design News, USA, Volume 32, Number 9, pages 230-232, April 1987.
39) T.J. Moir, T.G. Vishwanath, D.R. Campbell, "Real-Time Self-Tuning Deconvolution
Filter and Smoother," Internationallournal ofControl, Great Britain, Volume 45, Number 3, pages 969-985, March 1987
40) R. Simar, M. Hames, "CMOS DSP Packs Punch of a Supercomputer," EDN: Electronic
Design News, USA, Volume 35, Number 7, pages 103-106, March 1987.
Digital Signal Processing Applications with the TMS320 Family, Vol. 3
535
41) S. Sridharan, "On Improving the Performance of Digital Filters Designed Using the
TMS32010 Signal Processor," Journal of Electrical and Electronic Engineers ofAustralia, Australia, Volume 7, Number 1, pages 80--82, March 1987.
42) R. McCammon, "Software Routine Probes TMS32010 Code," EDN: Electronic Design
News, USA, Volume 32, Number 4, pages 200,202, February 1987.
43) J. Prado, R. Alcantara, "A Fast Square-Rooting Algorithm Using A Digital Signal Processor," Proceedings of IEEE, USA, Volume 75, Number 2, pages 262-264, February
1987.
44) T.G. Vishwanath, D.R. Camppbell, TJ. Moir, "Real-Time Implementation Using a
TMS32010 Microprocessor," IEEE Transactions on Industrial Electronics, USA, Volume 1E-34, Number 1, pages 115-118, February 1987.
45) R Chassaing, "Applications in Digital Signal Processing with the TMS320 Digital Signal Processor in an Undergraduate Laboratory," Proceedingsof1987ASEE Conference,
OSA, pages 1320--1324, 1987.
46) R.M, Sovacool, "EPROM Enhances TMS32020 Mu C's Memory," EDN: Electronic
Design News, USA, Volume 32, Number 1, page 231,1987.
47) F. Kocsis, F. Marx, "Fast DFT Modules For The TMS32010 Digital Signal Processor,"
Meres and Automation, Hungary, Volume 35, Number 1, pages 6-11,1987.
48) Y.v.V.S. Murty, W.J. Smolinski, "Digital Filters for Power System Relaying," International Journal of Energy Systems, USA, Volume 7, Number 3, pages 125-129, 1987.
49) S. Wang, "The TMS32010 High Speed Processor and Its Applications," Mini-Micro
Systems, China, Volume 8, Number 3, pages 24-32, 1987.
50) G.A. Frantz, K.S. Lin, J.B. Reimer, J. Bradley, "The Texas Instruments TMS320C25
Digital Signal Microcomputer," IEEE Microelectronics, USA, Volume 6, Number 6,
pages 10--28, December 1986.
51) P. Renard, "ND Converters: The Advantage of a Mixture of Techniques," Mesures,
France, Volume 51, Number 16, pages 80--81, December 1986.
52) M. Ara, E. Suzuki, "Design of Real Time Filter Using DSP," Resident Reports ofKogakuin University, Japan, Number 61, pages 115-127 October 1986.
53) 1. Reidy, "Connection of a 12-Bit ND Converter to Fast DSPs/' Electronik, Germany,
Volume 35, Number 22, pages 132-134, October 1986.
54) G.R.Steber, "Implementation of Adaptive Filters on the TMS32010 DSP Microcomputer," Proceedings of IECON 86, Catalog Number 86CH2334-1, Volume 2, pages
653-656, September/October 1986.
55) D. Collins, M.A. Rahman, "Digital Filter Design Using The TMS320 Digital Signal
Processor," Proceedings of EUSIPCO-86, Volume 1pages 163-166, September 1986.
56) R. Simar, Jr., J.B. Reimer, "TheTMS320C25: A 100 ns CMOS VLSI Digital Signal Processor," 1986 Workshop on Applications of Signal Processing to Audio and Acoustics,
September 1986.
57) 1. pudas, A. Stipkovits, E. Simonyi, "On The recursive Momentary Discrete Fourier
Transform," Proceedings ofEUSIPCO-86, Volume 1, pages 303-306, September 1986.
58) E. Feder, "Digital Signal Processor - General Purpose or Dedicated? ," Electronics Industry, France, Number 111, pages 74-82,September 1986.
59) K. Herberger, "The Use of Signal Processors For Simulating Data Circuits," Proceedings of EUSIPCO-86, Volume 2, pages 1109-1112, September 1986.
536
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77) W.K Anakwa, T.L. Stewart, "TMS320 Microprocessor-Based System For Signal Processing," Proceedings of the ISMM International Symposium, pages 64-65, February
1986.
78) M. Orrienzetter, "Universal Signal Processors Offers High Data Throughput," Electronik, Germany, Volume 35, Number 4, pages 71-77, February 1986.
79) P.P. Regamey, "Matched Filtering Using a Signal Microprocessor TMS320," Mitt.
AGEN, Switzerland, Number 42, pages 31-35, February 1986.
80) "TI Set To Show 2nd-Generation DSP," Electronics, USA, pages 23-24, February 3,
1986.
81) "TI Preps CMOS Versions of Signal-Processor Chips," Electronics Engineering Times,
USA, page 6, February 3, 1986.
82) D. Wilson, "Digital Signal Processing Moves on Chip," Digital Design, USA, Volume
16, Number 2, pages 33-34, February 1986.
83) "TI Chip Heads for Fast Lane of Digital Signal Processing," Electronics, USA, page 9,
January 27,1986.
84) R.D. Campbell andS.R. McGeoch, "TheTMS32010 Digital Signal Processor-An Educational Viewpoint," Internationall ournalfor ElectricalEngineering Education, Great
Britain, Volume 23, Number 1, pages 21-31, January 1986.
85) P. Eckelman, "The Cascadable Signal Processor For Digital Signal Processing," Electronics Industry, Germany, Volume 17, Number 10, pages 26--27, 1986.
86) R. Cook, "Digital Signal Processors," High Technology, USA, Volume 5, Number 10,
pages 25-30, October 1985.
87) c.P. Howard, "A High-Level Approach to Digital Processing Design," Proceedings of
MILCOMP/85, USA, October 1985.
88) H.E. Lee, "Versatile Data-Acquisition System Based on the Commodore C-64/C-128
Microcomputer," Proceedings of the Symposium ofNortheastern Accelerator Personnel, USA, Volume 57, Number 5, pages 983-985, October 1985.
89) N.K Riedel, D.A. McAninch, C. Fisher, and N.B. Goldstein, "A Signal Processing Implementation for an IBM PC-Based Workstation," IEEE Micro, USA, Volume 5, Number 5, pages 52-67, October 1985.
90) KE. Marrin, "VLSI and Software Move DSP Into Mainstream," Computer Design,
USA, Volume 24, Number 9, pages 69-72, September 1985.
91) "Signal Processor ICs: Highly Integrated ICs Making DSP More Attractive," Electronics Engineering Times, USA, pages 37-38, September 2,1985.
92) KE. Marrin, "VLSI and Software Move DSP Techniques into Mainstream," Computer
Design, USA, September 1985.
93) "High-Speed Four-Channel Input Board," Electronics Weekly, USA, Number 1277, p.
31, July 24, 1985.
94) "4-ChanneIAnalog-Input Board Puts Signal-Processing on VMFBus," EDN: Electronic Design News, USA, Volume 30, Number 17, page 74, July 1985.
95) R.H. Cushman, "Third-Generation DSPs Put Advanced Functions On-Chip," EDN:
Electronic Design News, USA, July 1985.
96) w.w. Smith, Jr., "Agile Development System, Running on PCs, Builds TMS320-Based
FIR Filter," Electronic Design, USA, Volume 33, Number 13, pages 129-138, June 6,
1985.
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S. Magar, SJ. Robertson, and W. Gass, "Interface Arrangement Suits Digital Processor
to Multiprocessing," Electronic Design, USA, Volume 33, Number 5, pages 189-198,
March 7, 1985.
G. Kropp, "Signal Processor Offers Multiprocessor Capability," Elektronik, Germany,
Volume 34, Number 6, pages 53-58, March 1985.
S. Magar, D. Essig, E. Caudel, S. Marshall and R. Peters, "An NMOS Digital Signal
Processor with Multiprocessing Capability," Digest ofIEEE International Solid-State
Circuits Conference, USA, February 1985.
"TI 'Shiva' Chip Outlined," Electronics Engineering Times, USA, page 15, February
18,1985.
S. Magar, E. Caudel, D. Essig, and C. Erskine, "Digital Signal Processor Borrows from
P to Step up Performance, Electronic Design, USA, Volume 33, Number 4, pages
175-184, February 21, 1985.
C. Erskine, S. Magar, E. Caudel, D. Essig, and A. Levinspuhl, "A Second-Generation
Digital Signal Processor TMS32020: Architecture and Applications," Traitement de
Signal, France, Volume 2, Number 1, pages 79-83, January-March 1985 ..
S. Baker, "TI 'Shiva' Chip Outlined," Electronic Engineering Times, USA, Number
317, page 15,February 1985.
S. Baker, "Silicon Bits," Electronic Engineering Times, USA, Number 316, page 42,
February 1985.
H. Bryce, "Board Arrives For Digital Signal Processing on the VMEbus," Electronic
Design, USA, Volume 33, Number 2, page 266,1985.
K. Marrin, "VME-Compatible DSP System Incorporates TMS320 Chip," EDN: Electronic Design News, USA, Volume 30, Number 2, page 122, January 1985.
C. Erskine and S. Magar, "Architecture and Applications of A Second-Generation
Digital Signal Processor," Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, USA, 1985.
D.P. Morgan and H.E Silverman, "An Investigation into the Efficiency of a Parallel
TMS320 Architecture: DFT and Speech Filterbank Applications," Proceedings of
IEEE International Conference on Acoustics, Speech, and Signal Processing, USA,
Volume 4, pages 1601-1604, 1985.
P. Harold, "VME Bus Meeting Sparks Change in Standard, New Products," EDN:
Electronic Design News, USA, Volume 29, Number 26, page 18, December 1984.
W. Loges, "A Code Generator Sets up the Automatic Controller Program for the
TMS320," Elektronik, Germany, Volume 33, Number 22, pages 154-:-158, November
1984.
H. Volkers, "Fast Fourier Transforms with the TMS320 as Coprocessor," Elektronik,
Germany, Volume 33, Number 23, pages 109-112, November 1984.
Keun-Ho Ryoo, "On the Recent Digital Signal Processors," Journal of South Korean
Institute of Electrical Engineering, South Korea, Volume 33, Number 9, pages
540-549, September 1984.
D. Wilson, "Editor's Comment," Digital Design, USA, Volume 14, Number 9, page
14, September 1984.
"Signal Processors Will Squeeze Into One Chip, Says TI's French," Electronics, USA,
Volume 57, Number 9, pages 14,20, May 1984.
539
115) S. Mehrgardt, "32-Bit Processor Produces Analog Signals," Elektronik, Germany, Volume 33, Number 7, pages 77-82, April 1984.
116) S. Magar, "Signal Processing Chips Invite Design Comparisons," Computer Design,
USA, Volume 23, Number 4, pages 179-186, April 1984.
117) S. Mehrgardt, "General-Purpose Processor System for Digital Signal Processing,"
Elektronik, Germany, Volume 33, Number 3, pages 49-53, February 1984.
118) T. Durham, "Chips: Familiarity Breeds Approval," Computing, Great Britain,page 26,
January 1984.
119) J. Bradley and P. Ehlig, "Applications of the TMS32010 Digital Signal Porcessor and
Their Tradeoffs," Midcon/84 Electronic Show and Convention, USA, 1984.
120) 1. Bradley and P. Ehlig, "Tradeoffs in the Use ofthe TMS32010 as a Digital Signal Processing Element," Wescon/84 Conference Record, USA, 1984.
121) E. Fernandez, "Comparison and Evaluation of 32-Bit Microprocessors," Mini/Micro
Southeast Computer Conference and Exhibition, USA, 1984.
122) D. Garcia, "Multiprocessing with the TMS3201O," Wescon/84 Conference Record,
USA,1984.
123) S. Magar, "Architecture and Applications of a Programmable Monolithic Digital Signal Processor - A Tutorial Review," Proceedings of IEEE International Symposium
on Circuits and Systems, USA, 1984.
124) D. Quarmby (Editor), "Signal Processor Chips," Granada, England 1984.
125) R. Steves, "A Signal Processor with Distributed Control and Multidimensional Scalability," Proceedings ofIEEE NationalAerospace and Electronics Conference, USA,
1984.
126) V. Vagarshakyan and L. Gustin, "On A Single Class of Continuous Systems - A Solution to the Problem on the Diagnosis of Output Signal Characteristics Recognition Procedures," IZV. AKAD. NAUK ARM. SSR, SER. TEKH. NAUK, USSR, Volume 37,
Number 3, pages 22-27,1984.
127) 1. So, "TMS320 - A Step Forward in Digital Signal Processing," Microprocessors and
Microsystems, Great Britain, Volume 7, Number 10, pages 451-460, December 1983.
128) 1. Elder and S. Magar, "Single-Chip Approach to Digital Signal Processing," Wescon/83 Electronic Show and Convention, USA, November 1983.
129) M. Ma1cangi, "VLSI Technology for Signal Processing. III," Elettronica Oggi, Italy,
Number 11, pages 129-138, November 1983.
130) P. Strzelcki, "Digital Filtering," Systems International, Great Britain, Volume 11,
Number 11, pages 116-117, November 1983.
131) W. Loges, "Digital Controls Using Signal Processors," Elektronik, Germany, Volume
32, Number 19, pages 51-54, September 1983.
132) "TI's Voice Chip Makes Debut," Computerworld, USA, Volume 17, Number 15, page
91, April 1983.
133) L. Adams, "TMS320 Family 16/32-Bit Digital Signal Processor, An Architecture for
Breaking Performance Barriers," Mini/Micro West 1983 Computer Conference and
Exhibition, USA, 1983.
134) R. Blasco, "Floating-Point Digital Signal Processing Using a Fixed-Point Processor,"
Southcon/83 Electronics Show and Convention, USA, 1983.
540
135) R. Dratch, "A Practical Approach to Digital Signal Processing Using an Innovative
Digital Microcomputer in Advanced Applications," Electro '83 Electronics Show and
Convention, USA, 1983.
136) C. Erskine, "New VLSI Co-Processors Increase System Throughput," Mini/Micro
Midwest Conference Record, USA, 1983.
137) L. Kaplan, "Flexible Single Chip Solution Paves Way for Low Cost DSP," Northcon/83 Electronics Show and Convention, USA, 1983.
138) L. Kaplan, "The TMS3201O: A New Approach to Digital Signal Processing," Electro
'83 Electronics Show and Convention, USA, 1983.
139) S. Mehrgardt, "Signal Processing with a Fast Microcomputer System," Proceedings
ofEUSIPCO-83 Second European Signal Processing Conference, Netherlands, 1983.
140) L. Morris, "A Tale of Two Architectures: TI TMS 320 SPC VS. DEC Micro/J-ll,"
Proceedings ofIEEE International Conference on A coustics, Speech and Signal Processing, USA, 1983.
141) L. Pagnucco and D. Garcia, "A 16/32 Bit Architecture for Signal Processing," Mini/
Micro West 1983 Computer Conference and Exhibition, USA, 1983.
142) 1. Potts, "A Versatile High Performance Digital Signal Processor," Ohmcon/83 Conference Record, USA, 1983.
143) J. Potts, "New 16/32-Bit Microcomputer Offers 200-ns Performance," Northcon/83
Electronics Show and Convention, USA, 1983.
144) R. Simar, "Performance of Harvard Architecture in TMS320," Mini/Micro West 1983
Computer Conference and Exhibition, USA, 1983.
145) K. McDonough, E. Caudel, S. Magar, and A. Leigh, "Microcomputer with 32-Bit
Arithmetic Does High-Precision Number Crunching," Electronics, USA, Volume 55,
Number 4, pages 105-110, February 1982.
146) K. McDonough and S. Magar, "A Single Chip Microcomputer Architecture Optimized
for Signal Processing," Electro/82 Conference Record, USA, 1982.
147) L. Kaplan, "Signal Processing with the TMS320 Family," Midcon/82 Conference Record, USA, 1982.
148) S. Magar, "Trends in Digital Signal Processing Architectures," Wescon/82 Conference
Record, USA, 1982.
Graphics/Imaging
1) J.A. Lindberg, "Color Cell Compression Shrinks NTSC Images," ESD: Electronic Systems Design Magazine, USA, Volume 17, Number 10, pages 91-96, October 1987
2) S. Ganesan, "A Digitial Signal Processing Microprocessor Based Workstation For Myoelectric Signals," Fifth International Conference on System Engineering, USA, Catalog Number 87CH2480-2, pages 427-438, September 1987.
3) JU. Pokovny, O. Skoloud, "Digitisation of a Video Signal From a Television For a Microcomputer," Sdelovaci Tech., Czechoslovakia, Volume 35, Number 6, pages 207-211,
June 1987.
4) M.E. Bukaty, "A Vehicle Identification System For Surveillance Applications," Topical
Meeting on Machine Vision. Technical Digest Series, USA, Volume 12, pages 106-109,
March 1987.
Digital Signal Processing Applications with the TMS320 Family, Vol. 3
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Instrumentation
1) G.R. Halsall, D.R. Burton, M.J. Lalor, C.A Hobson, "A Novel Real-Time Opto-Electronic Profilometer Using FFT Processing," Proceedings of ICASSP 89, USA, pages
1634--1637, May 1989.
2) AJ. Pratt, R.E. Gander, B.R. Brandell, "Real-Time Median Frequency Estimator," Proceedings ofthe NinthAnnual Conference ofthe IEEE Engineering in Medicine andBiology Society, USA, Volume 4, pages 1840-1841, November 1987.
3) D.Y. Cheng, A Gersho, "A Fast Codebook Search Algorithm For Nearest-Neighbor
Pattern Matching," Proceedings of ICASSP 86, USA, Catalog Number 86CH2243-4,
Vall, pages 265-268, April 1986.
4) Y. Chikada, M. Ishiguro, H. Hirabayashi, M. Morimoto, K Morita, T. Kanazawa, H.
Iwashita, K Nakazima, S. Ishikawa, T. Takahashi, K Handa, T.Kazuga, S. Okumura,
T. Miyazawa, K Miura, S. Nagasawa, "A Very Fast FFT Spectrum Analyzer For Radio
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14) I. Lecomte, M. Lever, L. Lelievre, M. Delprat, A Tassy, "Medium Band Radio Communications," Proceedings of ICASSP 88, USA, April 1988.
15) J.B. Reimer, KS. Lin, "TMS320 Digital Signal Processors in Speech Applications,"
Proceedings of SPEECH TECH '88, April 1988.
16) M. Smmendorfer, D. Kopp, H. Hackbarth, "A High-Performance Multiprocessor System for Speech Processing Applications," Proceedings ofICASSP 88, USA, Volume V,
page 2108, April 1988.
17) P. Vary, K Hellwig, R. Hoffmann, R.J. Sluyter, C. Garland, M. Russo, "Speech Codec
for the European Mobile Radio System," Proceedings of ICASSP 88, USA, Volume S,
page 227, April 1988.
18) A Hunt, "A Speaker-Independent Telephone Speech Recognition System: The VCS
TeleRec," Speech Technology, USA, Volume 4, Number 2, pages 80-82, March-April
1988.
19) R.A Sukkar, J.L. LoCicero, J .W. Picone, "Design and Implementation of a Robust Pitch
Detector Based on a Parallel Processing Technique," IEEE J oumal of SeLected Areas
of Communications, USA, Volume 6, Number 2, pages 441-451, February 1988.
20) AZ. Baraniecki, "Digital Coding of Speech Algorithms and Architecture," Proceedings
of IECON '87, November 1987.
21) G.R. Steber, "Audio Frequency DSP Laboratory on a Chip-TMS32010," Proceedings
of IE CON '87, Volume 2, pages 1047-1051, November 1987.
22) S.H. Kim, KR. Hong, H.B. Han, W.H. Hong, "Implementation of Real Time Adaptive
Lattice Predictor on Digital Signal Processor," Proceedings of TENCON 87, South Korea, Volume 3, pages 1131-1135, August 1987.
23) J.B. Reimer, M.L. McMahan, W.W. Anderson, "Speech Recognition For a Low Cost
System Using a DSP," Digest of TechnicaL Papers for 1987 InternationaL Conference
on Consumer ELectronics, June 1987.
24) A Ciaramella, G. Venuti, "Vector Quantization Firmware For an Acoustical Front-End
Using the TMS32020," Proceedings of ICASSP 87, USA, Catalog Number
87CH2396-0, Volume 4, pages 1895-1898, April 1987.
25) G.A Frantz, KS. Lin, "A Low Cost Speech System Using the TMS320CI7," Proceedings of SPEECH TECH '87, pages 25-29, April 1987.
26) Z. Gorzynski, "Realtime Multitasking Speech Application on the TMS320," Microprocessors and Microsystems, Great Britain, Volume 11, Number 3, pages 149-156, April
1987.
27) P. Papamichalis, D. Lively, "Implementation of the DOD Standard LPC-1O/52E on the
TMS320C25," Proceedings of SPEECH TECH '87, pages 201-204, April 1987.
28) B.I. Pawate, M.L. McMahan, R.H. Wiggins, G.R. Doddington, P.K Rajasekaran, "Connected Word Processor on a Multiprocessor System," Proceedings ofICASSP 87, USA,
Catalog Number 87CH2396-0, Volume 2, pages 1151-1154, April 1987.
29) S. Roucos, A Wilgus, W. Russell, "A Segment Vocoder Algorithm For Real-Time Implementation," Proceedings of ICASSP 87, USA, Catalog Number 87CH2396-0, Volume 4, pages 1949-1952, April 1987.
30) H, Yeh, "Adaptive Noise Cancellation For Speech With a TMS32020," Proceedings of
ICASSP 87, USA, Catalog Number 87CH2396-0, Volume 2, pages 1171-1174, April
1987.
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48) K. Lin and G. Frantz, "Speech Applications with a General Purpose Digital Signal Processor," IEEE Region 5 Conference Record, USA, March 1985.
49) K. Lin and G. Frantz, "Speech Applications Created by a Microcomputer," IEEE Potentials, USA, December 1985.
50) M. Malcangi, "Programmable VLSI's for Vocal Signals," Electronica Oggi, Italy, Number 10, pages 103-113, October 1984.
51) V. Kroneck, "Conversing with the Computer," Elektrotechnik, Germany, Volume 66,
Number 20, pages 16-18, October 1984.
52) P.K.Rajasekaran and G.R. Doddington, "Real-Time Factoring of the Linear Prediction
Polynomial of Speech Signals," Digital Signal Processing -1984: Proceedings of the
International Conference, pages 405-410, September 1984.
53) M. Hutchins and L. Dusek, "Advanced ICs Spawn Practical Speech Recognition," Computer Design, USA, Volume 23, Number 5, pages 133-139, May 1984.
54) E. Catier, "Listening Cards or Speech Recognition," Electronique Industrielle, France,
Number 67, pages 72-76, March 1984.
55) O. Ericsson, "Special Processor Did Not Meet Requirements - Built Own Synthesizer,"
ElteknikAktuell Elektronik, Sweden, Number 3, pages 32-36, February 1984.
56) H. Strube, "Synthesis Part of a 'Log Area Ratio' Vocoder Implemented on a Signal-Processing Microcomputer," IEEE Transactions on A coustics, Speech and Signal Processing, USA, Volume ASSP-32, Number 1, pages 183-185, February 1984.
57) B. Bryden and H. Hassanein, "Implementation of Full Duplex 2.4 Kbps LPC Vocoder
on a Single TMS320 Microprocessor Chip," Proceedings ofIEEE International Conference on Acoustics, Speech and Signal Processing, USA, 1984.
58) M. Dankberg, R. litis, D. Saxton, and P. Wilson, "Implementation ofthe RELP Vocoder
Using the TMS320," Proceedings of IEEE International Conference on Acoustics,
Speech and Signal Processing, USA, 1984.
59) A. Holck and W. Anderson, "A Single-Processor LPC Vocoder," Proceedings ofIEEE
International Cqnference on Acoustics, Speech and Signal Processing, USA, 1984 .
.60) N. Morgan, "Talking Chips," McGraw-Hill, 1984.
61) A. Kumarkanchan, "Microprocessors Provide Speech to Instruments," Journal ofInstituteofElectronic and TelecommunicationEngineers, India, Volume 29, Number 12, December 1983.
62) L. Dusek, T. Schalk, and M. McMahan, "Voice Recognition Joins Speech on Programmable Board," Electronics, USA, Volume 56, Number 8, pages 128-132, April 1983.
63) 1.R. Lineback, "Voice Recognition Listens For Its Cue," Electronics, USA, Volume 56,
Number 1, page 110, January 1983.
64) D. Daly and L. Bergeron, "A Programmable Voice Digitizer Using the TI TMS320 Microcomputer," Proceedings ofIEEE International Conference onAcoustics, Speech and
Signal Processing, USA, 1983.
65) W. Gass, "The TMS32010 Provides Speech I/O for the Personal Computer," Mini/Micro
Northeast Electronics Show and Convention, USA, 1983.
66) A. Holck, "Low-Cost Speech Processing with TMS3201O," Midcon/83 Conference Record, USA, 1983.
546
Control
1)
2)
547
35) H. Henrichfreise, W. Moritz, H. Siemensmeyer, "Control of a Light, Elastic Manipulation Device," Conference on Applied Motion Control, 1987.
36) M.e. Stich, "Digital Servo Algorithm For Disk Actuator Control," Conference on
Applied Motion Control, pages 35-41,1987.
37) T. Takeshita, K. Kameda, H. Ohashi, N. Matsui, "Digital Signal Processor Based High
Speed Current Control of Brushless Motor," Electronic Engineering, Japan, USA, Volume 106, Number 6, pages 42-49, November-December 1986.
38) R. Lessmeier, W. Schumacher, W. Leonard, "Microprocessor-Controlled AC-Servo
Drives With Synchronous or Induction Motors: Which is Preferable?," IEEE Transactions On Industry Applications, USA, September/October 1986.
39) R. Alcantara, J. Prado, C Guegen, "Fixed-Point Implementation of the Fast Kalman Algorithm: Using the TMS32010 Microprocessor," Proceedings of EUSIPCO-86, Volume 2, pages 1335-1338, September 1986.
40) B. Nowrouzian, M.H. Hamza, "DC Motor Control Using a Switched-Capacitor Circuit," Proceedings of the lASTED International Symposium on High Technology in the
Power Industry, pages 352-356, August 1986.
41) N. Matsui, T. Takeshita, "Digital Signal Processor-Based Controllers For Motors,"
SICE, July 1986.
42) H. Hanselmann, "Using Digital Signal Processors For Control," ProceedingsofEICON,
1986.
43) H. Hanselman, W. Moritz, "High Banwidth Control of the Head Positioning Mechanism
in a Winchester Disc Drive," Proceedings of IE CON, pages 864-869, 1986.
44) R. Cushman, "Easy-to-Use DSP Converter ICs Simplify Industrial-Control Tasks,"
Electronic Design, USA, Volume 29, Number 17, pages 218-228, August 1984.
45) W. Loges, "Signal Processor as High-Speed Digital Controller," Elektronik lndustrie,
Germany, Volume 15, Number 5, pages 30-32, 1984.
46) W. Loges, "Higher-Order Control Systems with Signal Processor TMS320," Elektronik,
Germany, Volume 32, Number 25, pages 53-55, December 1983.
Military
1) Y. Lazzari, Quacchia, M. Sereno, E. Turco, "Implementation of a 16 Kbit/s Split
Band-Adaptive Predictive Codec For Digital Mobile Radio Systems," CSELTTechnical
Reports, Italy, Volume 16, Number 5, pages 443-447, August 1988.
2) P. Papamichalis, J. Reimer, "Implementation of the Data Encryption Standard Using the
TMS3201O," DigitalSignal Processing Applications, 1986.
Telecommunications
1) S. Casale, R. Russo, G.c. Bellina, "Optimal Architectural Solution Using DSP Proces-.
sors for the Implementation of an ADPCM Transcoder," Proceedings of GLOBE COM
'89, pages 1267-1273, November 1989.
2) A. Lovrich and J.B. Reimer, "A Multi-Rate Transcoder," Transactions on Consumer
Electronics, USA, November 1989.
3) J.L. Dixon, Y.K. Varma, N.R. Sollenberger, D.W. Lin, "Single DSP Implementation of
a 16 Kbps Sub-Band Speech Coder for Portable Communications," Proceedings of
ICASSP 89, USA, pages 184-187, May 1989.
Digital Signal Processing Applications with the TMS320 Family, Vol. 3
549
4)
20) O. Matsubara, K Yabuta, E. Sato, H. Takatori, "A Switched Capacitor Line Equalizer
For Digital Subscriber Loop Transmission," Conference Record of GLOBE COM Tokyo
'87, Japan, Volume 3, pages 1746-1751, November 1987.
21) Mills, J.D., v.P. Telang, C.E. Rohrs, "A Data and Voice System For The General Service
Telephone Network," Proceedings ofIE CON '87, Volume 2, pages 1143-1148, November 1987.
22) C. Nuthalapati, "A FET Processor Based Phase Noise Measurement System For Radar
ATE," Proceedings of AUTOTESTCON '87, Catalog Number 87CH2510-6, pages
47-51, November 1987.
23) N. Tamaki, S. Sugimoto, F. Mano, "A Line Terminating Circuit Using the DSP Technique," Conference Records of GLOBECOM Tokyo '87, Japan, Volume 3, pages
1731-1735, November 1987.
24) G.J. Saulnier, W.A. Haskins, P. Das, "Tone Jammer Suppression in a Direct Sequence
Spread Sprectrum Receiver Using Adaptive Lattice and Transversal Filters," Conference Records of MIL COM 87, USA, Volume 1, pages 123-127, October 1987.
25) R.N. Bera, KS. Rattan, "Real-Time Simulation of the Unmanned Research Vehicle Using Multi-Rate Sampling," Fifth International Conference on System Engineering,
USA, Catalog Number 87CH2480-2, pages 573-578, September 1987.
26) D. Shear, "Design and Build a Transponder Using DSP Tools. (A Related Article on the
Functional Capability of the Acoustic Transponder)," EDN: Electronic Design News,
USA, Volume 32, Number 18, pages 137-148, September 1987.
27) S.H. Kim, KR. Hong, H.B. Han, WH. Hong, "Implementation of Real Time Adaptive
Lattice Predictor on Digital Signal Processor," Proceedings ofTENCON 87, South Korea, Volume 3, pages 1131-1135, August 1987.
28) W Mattern, "Multifrequency Communications Channel Decoder With The Type
TMS32010 Signal Processor Circuit," Electronics Industry, France, Number 127, Supplement Number 13, pages 29-33, June 1987.
29) A. Ciaramella, G. Venuti, "Vector Quantization Firmware For an Acoustical Front-End
Using the TMS32020," Proceedings of ICASSP 87, USA, Catalog Number
87CH2396-0, Volume 4, pages 1895-1898, April 1987.
30) MJ. Pettitt, D. Remedios, AW Davis, A. Hadjifotiou, S. Wright, "A Coherent Transmission System Using DFB Lasers and Phase Diversity Reception," lEE Colloqium on
'High Capacity Fibre Optic Systems', Great Britain, Digest Number 23,9/1-5, February
1987.
31) GJ. Saulnier, K Yum, P. Das, "The Suppression of Tone-Jammers Using Adaptive Lattice Filtering," IEEE International Conference on Communications '87, USA, Volume
2, pages 869-873, June 1987.
32) H.H. Lu, D. Hedberg, B. Fraenkel, "Implementation of High-Speed Voiceband Data
Modems Using The TMS320C25," Proceedings ofICASSP 87, USA, Catalog Number
87CH2396-0, Volume 4, pages 1915-1918, April 1987.
33) S. Ono, N. Kondoh, M. Kobayashi, M. Hata, "A New Automatic Equalizer For Digital
Subscriber Loops," Electronics and Communications in Japan, Part 1, Japan, Volume
70, Number 4, pages 93-102, April 1987.
Digital Signal Processing Applications with the TMS320 Family, Vol. 3
551
552
50) F.L. Kitson, KA Zeger, "A Real-Time ADPCM Encoder Using Variable Order Prediction (Speech)," Proceedings ofICASSP 86, USA, Catalog Number 86CH2243-4, Volume 2, pages 825-828, April 1986.
51) G. Mirchandani, R.C. Gaus, Jr., L.K Bechtel, "Performance Characteristics of a Hard.ware Implementation of The Cross-Talk Resistant Adaptive Noise Canceller," Proceedings ofICASSP 86, USA, Catalog Number 86CH2243-4, Volume 1, pages 93-96, April
1986.
52) G.S. Muller, C.K Pauw, "Acoustic Noise Cancellation," Proceedings of lCASSP 86,
USA, Catalog Number 86CH2243-4,V6Iume 2, pages 913-916, April 1986.
53) 1. Rothweiler, "Performance of a Real Time Low rate Voice Codec," Proceedings of
ICASSP 86, USA, Catalog Number 86CH2243-4, Volume 4, pages 3039-3042, April
1986.
54) PJ. Wilson,J.M. Puetz,AY. McCree,D.T. Wang, "An Integrated Voice Codecand Echo
Canceller Implemented in a Single DSP Processor," Proceedings of ICASSP 86, USA,
Catalog Numb.er 86CH2243-4, Volume 2, pages 1333-1336, April 1986.
55) G. AIbertengo, S. Benedetto, E. Biglieri, "A DSP Application: An Adaptive Echo Canceller," Proceedings of the lASTED International Symposium: Modelling, Identification, and Control, MIC '86, pages 69-72, February 1986.
56) AW, Davis, S. Wright, MJ. Pettitt, J.P. King, K Richards,"Coherent Optical Receiver
For 680 Mbit/S Using Phase Diversity," Electron. Lett., Great Britain, Volume 22, Number 1, pages 9-11, January 1986.
57) C.R. Cole, A Haoui, P.L. Winship, "A High-Performance Digital Voice Echo Canceller
on a Single TMS32020," Proceedings ofIEEE International Conference on Acoustics,
Speech and Signal Processing, USA, 1986.
58) H. Hanselman, W. Moritz, "High Bandwidth Control of the Head Positioning Mechanism in a Winchester Disc Drive," Proceedings of IECON, 1986.
59) Sleeper Product - "A Combo VoicelData I/O Card - Awakens Interest," Electronic Engineering Times, USA, pages 80-81, November 11, 1985.
60) R. Chjirayil, P. Ehlig, J. Bradley, G. Troullinos, "Modem Implementation Using The
TMS3201O," Proceedings of the National Communications Forum, 1985, Volume 39,
pages 711-715, September 1985.
61)P. EhIig, "DSP Chip Adds Multitasking Telecomm Capability to Engineering Workstation," Electronic Design, USA, Volume 33, Number 10, pages 173-184, May 2,1985.
62) WJ. Christmas, "A Microprocessor-Based Digital Audio Coder and Decoder," International Conference on Digital Processing of Signals in Communications, Number 62,
pages 22-26, April 1985.
63) J. Reimer, M. McMahan and M. Arjmand, "ADPCM on a TMS320 DSP Chip," Proceedings of SPEECH TECH 85, pages 246-249, April 1985.
64) P. Mock, "Add DTMF Generation and Decoding to DSP- P Designs," Electronic Design, USA, Volume 30, Number 6, pages 205-213, March 1985.
65) V. Milutinovic, "4800 Bitls Microprocessor-Based CCITT Compatible Data Modem,"
Microprocessing and Microprogramming, Volume 15, Number 2, pages 57~74, February 1985.1)
66) G. Corsini and P. Terreni, "A Radar Echo Simulator Based on P TMS320," Proceedings
ofMELECONI85 IEEE Mediterranean Electrotechnical Conference (Sponsors: Mayor
Digital Signal Processing Applications with the TMS320 Family, Vol. 3
553
67)
68)
69)
70)
71)
of Madrid, Ministers of Industry and Energy, Spanish National Telephone Co.), USA,
Volume 2, pages 327-330, 1985.
T. FjaIIbrant, "A TMS320 Implementation of a Short Primary Block ATC-System with
Pitch Analysis," International Conference on Digital Processing of Signals in Communications, Number 62, pages 93-96,1985.
D.P. Kelly and J.L. Melsa, "Syllabic Companding and 32 Kb/s ADPCM Performance,"
IEEE International Conference on Communications, USA, Volume 1, pages 414-417,
1985.
A. Vaghar, and V. Milutinovic, "An Analysis of Algorithms for Microprocessor Implementation of High-Speed Data Modems," Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, USA, Volume 4, pages 1656-1659,
1985.
J. Perl, "Channel Coding in a Self-Optimizing HFModem," International Zurich Seminar on Digital Communications; Applications of Source Coding, Channel Coding and
Secrecy Coding: Proceedings, pages 101-106, 1984.
R. ChirayiJ, P. EhIig, "Integrating Low to Medium and High Speed Modems," Mini-Micro Southwest-84 Computer Conference and Exhibition, September 1984,
Automotive
1) Kun-Shan Lin, "Trends of Digital Signal Processing in Automotive," International
Congress on Transportation Electronic (CONVERGENCE '88), October 1988.
2) KE. Beck, M.M. Hahn, "A Real-Time Combustion Analysis Instrument," SAE Technical Paper Series, USA, February-March 1988.
3) M. Payne, "Do Not Disturb: Lotus in Action. (Lotus Racing Cars Use of an Active Suspension System)," Electronics Weekly, USA, i20 1394, page 12, January 1988.
4) D.A. Williams, S. Oxley, "Application of the Digital Signal Processor to an Automotive
Control System," 6th. International Conference on Automotive Electronics, October
1987.
5) CM. Anastasia, G.W. Pestana, "A Cylinder Pressure Sensor for Closed Loop Engine
Control," SAE Technical Paper Series, February 1987.
Consumer
1) A. Lovrich and J.B. Reimer, "A MuIti-Rate Transcoder,"Digest of Technical Papers for
1989 International Conference on Consumer Electronics, June 7-91989.
2) G.A. Frantz, J .B. Reimer, and R.A. Wotiz, " Julie, The Application ofDSP to a Product,"
Speech Tech Magazine, USA, September 1988.
3) J.B. Reimer and G.A. Frantz, "Customization of a DSP Integrated Circuit for a Customer
Product," Transactions on Consumer Electronics, USA, August 1988.
4) lB. Reimer, P.E. Nixon, E.B. Boles, and G.A. Frantz, "Audio Customization of a DSP
IC," Digest of Technical Papers for 1988 International Conference on Consumer Electronics, June 8-101988.
5) H. Mitschke, "Video Recorder: Picture From A Store," Funschau, West Germany, Number 9, pages 56--58, April 1988.
6) lB. Reimer, P.E. Nixon, E.B. Boles, G.A. Frantz, "Audio Customization ofa DSP IC,"
Digest of Technical Papers for 1987 International Conference on Consumer Electronics, June 1987.
554
7)
Industrial
1) R.C. Chance, T.A. Taufiq, "A TMS32010 Based Near Optimized Pulse Width Modulated Waveform Generator," Third International Conference on Power Electronics &
Variable Speed Drives, Conference Publication Number 291, July 1988.
2) G. Anwar, R. Horowitz, M. Tomizuka, "Implementation of a MRAC for a Two Axis Direct Drive Robot Manipulator Using a Digital Signal Processor," American Control
Conference, pages 658-660, June 1988.
3) D.E. Luttrell, T.A. Dow, "Control of Precise Positioning System with Cascaded Colinear Actuators," American Control Conference, pages 121-126, June 1988.
4) Y.V.V.S. Murty, WJ. Smolinski, S. Sivakumar, "Design ofa Digital Protection Scheme
For Power Transformers Using Optimal State Observers," lEE Proc. C, Generation
Transmission, Distribution, Great Britain, Volume 135, Number 3, pages 224-230, May
1988.
5) M. Ruscio, M. Santoro, M. Adomi, A. Chiaravalloti, "Digital Control System For The
Coordinated Boilerrrurbine Control in the ENEL Piombino Power Station," Elettrotencia, Italy, Volume 75, Number 3, pages 253-258, March 1988.
6) J.A. Taufiq, RJ. Chance, CJ. Goodman, "On-Line Implementation of Optimised PWM
Schemes For Traction Inverter Drives," International Conference of 'Electric Railway
Systems For aNew Century', Great Britain, Conference Publication Number 279, pages
63-67, September 1987.
7) Y. Dote, M. Shinojima, H. Hoshimura, "Microprocessor-Based Novd Variable Structure Control for Robot Manipulator," Proceedings of the 10th. IFAC World Congress,
July 1987.
8) H. Henrichfriese, W. Moritz, H. Siemensmeyer, "Control of a Light, Elastic Manipulation Device," Conference on Applied Motion Control, pages 57-66,1987.
9) Y. Wang, M. Andrews, S. Butner, G. Beni, "Robot-Controller System," 15th Annual
Symposium on IncrementalMotion ControISystems&Devices, pages 17-26, June 1986.
10) R. Cushman, "Easy-to-Use DSP Converter ICs Simplify Industrial-Control Tasks,"
Electronic Design, USA, Volume 29, Number 17, pages 218-228, August 1984.
11) P. Rojek and W. Wetzel, "Multiprocessor Concept for Industrial Robots: Multivariable
Control with Signal Processors," Elektronik, Germany, Volume 33, Number 16, pages
109-113, August 1984.
12) G. Farber, "Microelectronics-Developmental 'frends and Effects on Automation Techniques," RegelungstechnikPraxis, Germany, Volume 24, Number 10, pages 326-336,
October 1982.
Medical
1) ES. Schlindwein, D.H. Evans, "A Real-Time Autoregressive Spectrum Analyzer for
Doppler Ultrasound Signals," Ultrasound in Medicine and Biology, Volume 15, Number 3,pages 263-272, 1989
2) N. Dillier, "Programmable Master Hearing Aid With Adaptive Noise Reduction Using
A TMS32020," Proceedings of ICASSP 88, USA, Volume A, page 2508, April 1988.
Digital Signal Processing Applications with the TMS320 Family, Vol. 3
555
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
P.B. Knapp, H.S. Lusted, "A Real-Time Digital Signal Processing System for Bioelectric Control of Music," Proceedings of ICASSP 88, USA, Volume A, page 2556, April
1988.
R.B. Knapp, B. Townshend, "A Real-Time Digital Signal Processing System for an Auditory Prosthesis," Proceedings ofICASSP 88, USA, Volume A, page 2493, April 1988.
L.R. Morris, P.B. Barszczewski, "Design and Evolution of a Pocket-Sized DSP Speech
Processing System for a Cochlear Implant and Other Hearing Prosthesis Applications,"
Proceedings of ICASSP 88, USA, Volume A, page 2516, April 1988.
T.J. Sullivan, S.M. Natarajan, "VLSI Based Design of a Battery-Operated Digital Hearing Aid," Proceedings of ICASSP 88, USA, Volume A, page 2512, April 1988.
AJ. Pratt, R.E. Gander, B.R. Brandell, "Real-Time Median Frequency Estimator," Proceedings oftheNinthAnnual Conference ofthe IEEE Engineering in Medicine andBiology Society, USA, November 1987.
H. Xu, Y.H. Liang, L.G. Zhou, "The Real-Time Realization of Fetal ECG Heart Rate
Monitor by Adaptive System," Proceedings oftheNinthAnnual Conference of the IEEE
Engineering in Medicine and Biology Society, USA, (Catalog Number 87CH2513-0),
Volume 3, pages 1662-1663, November 1987.
L.R. Morris, page Braszczewski, J. Bosloy, "Algorithm Selection and Software Time/
Space Optimisation for a DSP Micro-Based Speech Processor For a Multi-Electrode
Cochlear Implant," Proceedings of ICASSP 87, USA, Catalog Number 87CH2396-0,
Volume 2, pages 972-975, April 1987.
K.c. McGill, K.L. McMillan, "A Smart Trigger For Real-Time Spike Classification,"
Proceedings ofthe EighthAnnual Conference ofthe IEEE Engineering in Medicine and
Biology Society, USA, Catalog Number 86CH2368-9, Volume 1, pages 275-278, November 1986.
C. Murphy, page Rolfe, "Application of the TMS320 Signal Processor For The
Real-Time Processing of The Doppler Ultasound Spectra," Proceedings of the Eighth
Annual Conference of the IEEE/Engineering in Medicine and Biology, USA, Catalog
Number 86CH2368-9, Volume 2, pages 1175-1178, November 1986.
"Innovations: Digital Hearing Aid," IEEE Spectrum, USA, 22 December 1985.
A Casini, G. Castellini, P.L. Emiliani, and S. Rocchi, "An Auxiliary Processor for Biomedical Signals Based on a Signal Processing Chip," Digital SignaIProcessing-1984:
Proceedings of the International Conference, pages 228-232, September 1984.
T.R. Myers, "A Portable Digital Speech Processor for an Auditory Prosthesis," Wescon/84 Conference Record, USA, 1984.
Development Support
1) M. Karjalainen, "A LISP-Based High-Level Programming Environment for the
TMS320C30," Proceedings of ICASSP 89, USA, pages 1150-1153, May 1989.
2) B.c. Mather, "Digital Filter Design Package (DFP2), Version 2.12," IEEE Spectrum,
USA, Volume 25, Number 7, page 16, July 1988.
3) R. Weiss, "PC Package Ends DSP Drugery. (Monarch Software Package,Digital Signal
Processing)," Electronic Engineering Times, USA, Number 494, p. 57, July 1988.
4) A Kohl, "PC Development Environment For Signal Processors," Elektron. Prax., West
Germany, Volume 23, Number 4, April 1988.
556
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
16)
17)
18)
19)
20)
21)
R. Simar, Jr., A Davis, "The Application of High-Level Languages to Single-Chip digital Signal Processors," Proceedings ofICASSP 88, USA, Volume 3, pages 1678-1681,
April 1988.
A Bindra, "New chips, Tools For Signal Processing on Tap: DSP Seminar Attracts
Third-Party Developers," Electronic Engineering Times, USA, Number 470, page 6,
January 1988.
R.1. Chance, "Simulation of Multiple Digital Signal Processor Systems," Journal ofMicrocomputer Applications, Great Britain, Volume 11, Number 1, pages 1-19, January
1988.
A. Kohl, "Pascal and C-Compilers for the Type TMS320C25 Signal Processor," Elektron. Ind., West Germany, Volume 19, Number 4, pages 58,60,62,1988.
R.1. Chance, B.S. Jones, "A Combined SoftwareIHardware Development Tool For The
TMS32020 Digital Signal Processor," Journal of Microcomputer Applications, Great
Britain, Volume 10, Number 3, pages 179-197, July 1987.
M.A Zissman, G.c. O'Leary, D.H. Johnson, "A Block Diagram For a Digital Signal
Processing MIMD Computer," Proceedings of ICASSP 87, USA, Catalog Number
87CH2396-0, Volume 4, pages 1867-1870, April 1987.
M.1. Tracy, "Forth as a Language For Digital Signal Processing," 1987 Rochester Forth
Conference on Comparative Computer Architectures, USA, Volume 5, Number 1, pages
221-224,1987.
A. Gharahgozlou, M. Banaouas, E. Babani, "Software Development For a Microprocessor on a 'Host' Computer," ElectronicIndustry, France, Number 115, pages 61-64, November 1986.
D.R. Campbell, C. Canning, K. Miller, "Crossassembler For The TMS32010 Digital
Signal Processor," Microprocessors andMicrosystems, Great Britain, Volume 10, Number 8, pages 434-441, October 1986.
J. Chance, "Simulation Experiences in the Development of Software For Digital Signal
Processors," Microprocessors andMicrosystems, Great Britain, Volume 10, Number 8,
pages 419-426, October 1986.
AC.P. van Meer, "TMS3201O Evaluation Module Controller," Einhoven University of
Technology, Report Number EUT-86,E-162, 42 pages, October 1986.
S.E. Reyer, "A Demonstration Unit For Digital Signal Processing Development and Experimentation," Proceedings of IECON '86, Catalog Number 86CH2334-1, Volume 2,
pages 641-646, September/October 1986
l.R. Parker, "A Subset FORTRAN Compiler For a Modified Harvard Architecture,"
SIGPLAN Not, USA, Volume 21, Number 9, pages 57-62, September 1986.
H. Harrison, "A High-Level Language Programming Environment for Speech and Signal Processing," Proceedings of Speech Technology 86, April 1986.
S. Suehiro, K. Sugimoto, "Forth Machine With Hardware Interpreter Designed to Increase Execution Speed," NekkeiElectron., Japan, Number 396, pages 213-245,1986.
G. Frantz and K. Lin, "The TMS320 Family Design Tools," Proceedings of SPEECH
TECH 85, pages 238-240, April 1985.
R. Schafer, R. Merseraeau, and T. Barnwell, "Software Package Brings Filter Design to
PCs," Computer Design, USA, Volume 23, Number 13, pages 119-125, November
1984.
557
22) G. Pawle and T. Faherty, "DSP/Development Board Offers Host Independence," Computer Design, USA, Volume 23, Number 12, pages 109-116, October 15, 1984.
23) R. Mersereau, R. Schafer, T. Barnwell, and D. Smith, "A Digital Filter Design Package
for PCs and TMS320," MIDCON/84 Electronic Show and Convention, USA, 1984.
24) R. Cushman, "Sophisticated Development Tool Simplifies DSP-Chip Programming,"
Electronic Design, USA, Volume 28, Number 20, pages 165-178, September 1983.
25) W. Gass and M. McMahan, "Software Development Techniques for the TMS320,"
SOUTHCON/83 Electronics Show and Convention, USA, 1983.
26) R. Wyckoff, "A Forth Simulator for the TMS320 IC," Rochester Forth Applications
Conference, USA, pages 141-150, June 1983.
558
Index
559
hardware multiplier 16
hartley transforms 67, 70
Harvard architecture 15
II
integer arithmetic 285
integer formats 38
interface categories (,C30) 335
inverse functions 280
II
560
memory, organization 35
multiply functions 284
overview of book 3
peripherals 37
peripherals (,C30) 24
pipelining 15,24,40
polynomial approximation 279
primary bus 337
references 8
reset signal 357
roundoff noise model 225
II
telecommunications 401
three-D graphics system 423
TMS320C30 applications board 467
TMS34010 graphics processor 441
II
XDS 1000 system 362
561
TEXAS
INSTRUMENTS
Printed in U.S.A., March 1990
SPRA017