library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
Entity uart1 is
port(
Clk : in STD_LOGIC;
BRS : in STD_LOGIC_vector(2 downto 0);
TxD : out STD_LOGIC;
RxD : in STD_LOGIC;
Mode_TxD_RxDBar : in STD_LOGIC;
TxDbusy : out STD_LOGIC;
RxDrdy : out STD_LOGIC;
Rst : in STD_LOGIC;
Load : in STD_LOGIC;
--Din : in STD_LOGIC_VECTOR(7 downto 0);
Dout : out STD_LOGIC_vector(7 downto 0));
end uart1;
architecture Behavioral of uart1 is
signal temp : integer;
signal top16 : std_logic;
signal TxDClk : std_logic;
signal clkdiv : integer;
signal RxDClk : std_logic;
signal RxDdiv : integer;
SIGNAL Din : STD_LOGIC_VECTOR(7 downto 0) := "10011010";
--signal ClrDiv : std_logic;
signal TxD_Reg : std_logic_vector(9 downto 0);
signal RxD_Reg : std_logic_vector(7 downto 0);
signal TxDBitCnt : integer;
signal RxDBitCnt : integer;
signal RegDin : std_logic_vector(7 downto 0);
type state is (idle, load_TxD, shift_TxD,stop_TxD);
signal TxDFSM : state;
type state1 is (idle, start_RxD, Edge_RxD, DataErr_RxD, shift_RxD,stop_RxD);
signal RxDFSM : state1;
begin
-- Baud rate selection
process (RST, CLK)
begin
if (RST='1') then
temp <= 0;
elsif rising_edge(CLK) then

case BRS is
when "000" => temp <= 14; -- 115200
when "001" => temp <= 27; -- 57600
when "010" => temp <= 41; -- 38400
when "011" => temp <= 82; -- 19200
when "100" => temp <= 163; -- 9600
when "101" => temp <= 326; -- 4800
when "110" => temp <= 651; -- 2400
--when "111" => temp <= 1302; -- 1200
when others => temp <= 1302; -- n.u.
end case;
end if;
end process;
-- Clk16 Clock Generation
process (RST, CLK)
variable Div16 : integer;
begin
if (RST='1') then
Top16 <= '0';
Div16 := 0;
elsif rising_edge(CLK) then
Top16 <= '0';
if (Div16 = temp) then
Div16 := 0;
Top16 <= not top16;
else
Div16 := Div16 + 1;
end if;
end if;
end process;
-- TxD Clock Generation
process (RST, CLK)
begin
if (RST='1') then
TxDClk <= '0';
ClkDiv <= 0;
elsif rising_edge(CLK) then
--TxDClk <= '0';
if (Top16='1') then
ClkDiv <= ClkDiv + 1;
if (ClkDiv = 15) then
TxDClk <= not TxDClk;
ClkDiv <= 0;
end if;
end if;
end if;
end process;
-- RxD Sampling Clock Generation
process (RST, CLK)
begin
if (RST='1') then
RxDClk <= '0';
RxDDiv <= 0;

--ClrDiv <='0';
elsif rising_edge(CLK) then
--RxDClk <= '0';
--if (ClrDiv='1') then
--RxDDiv <= 0;
if (Top16='1') then
if (RxDDiv = 1) then
RxDDiv <= 0;
RxDClk <= not RxDClk;
else
RxDDiv <= RxDDiv + 1;
end if;
end if;
end if;
end process;
--if(Mode_TxD_RxDBar = '1') then
-- Transmiter State Machine
TxD_FSM: process (RST, CLK,TxDClk,RxDClk)
variable edge_p : integer ;
variable edge_p1 : integer ;
variable err_chk : std_logic ;
begin
if(Mode_TxD_RxDBar = '1') then
if (RST='1') then
TxD_Reg <= (others => '0');
TxDBitCnt <= 0;
TxDFSM <= idle;
TxDBusy <= '0';
RegDin <= (others=>'0');
edge_P := 0;
elsif rising_edge(TxDClk) then
TxDBusy <= '1'; -- except when explicitly '0'
case TxDFSM is
when Idle =>
if (load='1') then -- latch the input data immediately.
RegDin <= Din;
TxDBusy <= '1';
TxDFSM <= Load_TxD;
else
TxDBusy <= '0';
end if;
when Load_TxD =>
if (TxDClk='1' and load='1') then
TxD_reg <= '1' & RegDin & '0';
TxDBitCnt <= 10;
TxDFSM <= Shift_TxD;
end if;
when Shift_TxD =>
if (TxDClk='1') then
TxDBitCnt <= TxDBitCnt - 1;
TxD_reg <= '1' & TxD_reg (TxD_reg'high downto 1);
if (TxDBitCnt=1) then
TxDFSM <= Stop_TxD;
end if;

end if;
when Stop_TxD =>
if (TxDClk='1') then
TxDFSM <= Idle;
end if;
when others =>
TxDFSM <= Idle;
end case;
end if;
TxD <= TxD_Reg(0);
--end process;
---- RECEIVER State Machine
--elsif (Mode_TxD_RxDBar = '0') then
----RxD_FSM: proces (RST, CLK, RxDClk)
----begin
--if (RST='1') then
--RxD_Reg <= (others => '1');
--Dout <= (others => '0');
--RxDBitCnt <= 0;
--RxDFSM <= Idle;
--RxDRdy <= '0';
--edge_P := 0;
---elsif rising_edge(RxDClk) then
--RxDRdy <= '0';
---case RxDFSM is
--when Idle => -- wait on start bit
--RxDBitCnt <= 0;
--if (RxD='0') then
--RxDFSM <= Start_RxD;
--end if; -- else false start, stay in Idle
----when Start_RxD => -- wait on first data bit
--if (RxDClk = '1') then
--edge_P := 0;
--edge_P1 := 1;
--RxDFSM <= Edge_RxD;
---end if;
---when Edge_RxD => -- should load near RxD edge
--if (rising_edge(RxDClk)) then
--if (RxDBitCnt = 9) then
--RxDFSM <= Stop_RxD;
---else
-if (edge_p1 = 1) then
-err_chk := RxD;
-edge_p1 := edge_p1 + 1;
-RxDFSM <= Edge_RxD;
-else
-if (edge_p = 5) then
-RxDFSM <= Shift_RxD;
-edge_P := 0;

-elsif(err_chk = RxD) then

-edge_p := edge_p + 1;
-RxDFSM <= Edge_RxD;
-else
-RxDFSM <= DataErr_RxD;
--end if;
--end if;
--end if;
--end if;
---when Shift_RxD => -- Sample data !
--if (RxDClk = '1') then
--RxDBitCnt <= RxDBitCnt + 1;
--RxD_Reg <= RxD & RxD_Reg (RxD_Reg'high downto 1); -- shift right :
--edge_P := 0;
--edge_P1 := 1;
--RxDFSM <= Edge_RxD;
--end if;
---when DataErr_RxD=>
--RxDFSM <= Stop_RxD;
---when Stop_RxD => -- during Stop bit
--if (RxDClk = '1') then
--Dout <= RxD_reg;
--RxD_Reg <= (others => '0');
--RxDRdy <='1';
--RxDFSM <= Idle;
--end if;
---end case;
--end if;
end if;
end process;
end Behavioral;