RossLightfoot

ECEN248504
Lab8
Mehnaz
4215

Objective
Theobjectiveofthisweekslabwastointroducesequentialcircuitsandstorage
elementssuchasflipflops.

Design
Includedarethesourcecodesforthemodulescreatedinlab,commentedto
showwhateachcomponentdoes.
//sr_latch
`timescale1ns/1ps
`default_nettypenone

//definemodulesetup
modulesr_latch(Q,notQ,En,S,R)
//output&inputs
outputwireQ,notQ
inputwireEn,S,R

//internalwires
wirenandSEN,nandREN

//gateswith4nsdelay
nand#4nand0(Q,nandSEN,notQ)
nand#4nand1(notQ,nandREN,Q)
nand#4nand2(nandSEN,En,S)
nand#4nand3(nandREN,En,R)

endmodule

//d_latch
`timescale1ns/1ps
`default_nettypenone

//definemodulesetup
moduled_latch(Q,notQ,En,D)

//input&outputwires

inputwireD,En
outputwireQ,notQ

//internalwires
wirenandDEN,nandNotDEN,notD

//gateswith2nsdelay
not#2not0(notD,D)
nand#2nand0(Q,nandDEN,notQ)
nand#2nand1(notQ,nandNotDEN,Q)
nand#2nand2(nandDEN,D,En)
nand#2nand3(nandNotDEN,notD,En)

endmodule

//d_flip_flop
`timescale1ns/1ps
`default_nettypenone

//definemodulesetup
moduled_flip_flop(Q,notQ,Clk,D)

//input&outputwires
outputwireQ,notQ
inputwireClk,D

//internalwires
wirenotClk,notNotClk
wireQ_m
wirenotQ_m

//gateswith2nsdelay
not#2not0(notClk,Clk)
not#2not1(notNotClk,notClk)

//instantiatethemasterslaved_latchmodules.
d_latchmaster(Q_m,notQ_m,notClk,D)
d_latchslave(Q,notQ,notNotClk,Q_m)

endmodule

//d_latch_behavioral
`timescale1ns/1ps
`default_nettypenone

//definemodulesetup
moduled_latch_behavioral(
outputregQ,
outputwirenotQ,
inputwireD,En
)

//WheneverThere'sEnableorData,ifenableishigh
//thenQsetstodata,otherwisejustpreviousQ
always@(EnorD)
if(En)
Q=D
else
Q=Q

assignnotQ=~Q
endmodule

//d_flip_flop_behavioral
`timescale1ns/1ps
`default_nettypenone

//definemodulesetup
moduled_flip_flop_behavioral(
outputregQ,
outputwirenotQ,
inputwireD,
inputwireClk
)

//Ontheclock'spositiveedgesetsQtoData

always@(posedgeClk)
Q<=D

assignnotQ=~Q

endmodule

//adder_2bit
`timescale1ns/1ps
`default_nettypenone

//definemodulesetup
moduleadder_2bit(Carry,Sum,A,B)

//input&outputwires
outputwireCarry
outputwire[1:0]Sum
inputwire[1:0]A,B

//internalwire
wirecin

//instantiatethefulladdermodules
full_adderf0(Sum[0],cin,A[0],B[0],1'b0)
full_adderf1(Sum[1],Carry,A[1],B[1],cin)

endmodule

//adder_synchronous
`timescale1ns/1ps
`default_nettypenone

//definemodulesetup
moduleadder_synchronous(Carry_reg,Sum_reg,Clk,A,B)

//input&outputwires
outputregCarry_reg

outputreg[1:0]Sum_reg

inputwireClk
inputwire[1:0]A,B

//internalnets
reg[1:0]A_reg,B_reg
wireCarry
wire[1:0]Sum

//instantiate2_bitadder
adder_2bitAdd1(Carry,Sum,A_reg,B_reg)

//onclock'spositiveedgeAinternalsettoA,BinternasettoB
always@(posedgeClk)
begin
A_reg<=A
B_reg<=B
end

//onclockspositiveedgecarryinternal=Carry,Suminternal=Sum
always@(posedgeClk)
begin
Carry_reg<=Carry
Sum_reg<=Sum
end
endmodule

Results
Includedarethewaveformsofthemoduleswecreatedandthensimulatedwith
testbenchfiles.

//sr_latch

//D_Latch

//D_Flip_Flop

//D_Latch_behavioral

//D_Flip_Flop_behavioral

//adder_2bit

//adder_synchronous

Conclusion
Thislabwaswasagoodwaytointroduceustosequentialcircuits.Welearneda
lotaboutimplementingthecircuitsthroughverilog,aswellashowtimedelayscan
affecttheoutcomeofsuchcircuits.

Questions
1
.(SeeDesign)
2
.(seeResults)
3.
LabQuestions

a.
Now,changethe2unitdelaysinyourcodeto4unitsandrun
thetestbenchagain.Explaintheresultsofthesimulation
ThedelaymadetheQandnotQsignalsdelay4nsinsteadof2,but
theinputsignalsstayedthesame.

b.
SimulateyourDflipflopusingthedflipfloptb.vfileinthe
coursedirectory.AddtheinternalnetswithinyourDflipfloptothe
waveformandexaminethewaveformafterrestartingthesimulation.
Dothelatchesbehaveasexpected?Whyorwhynot?
Yestheybehaveasexpected.

c.
Comparethewaveformsyoucapturedfromthebehavioral
VerilogtothosecapturedfromthestructuralVerilog.Arethey
different?Ifso,how?
TheQandnotQsignalswerefasterforthebehavioralcircuitsthan
thestructuralcircuits.

4.

Behavioralverilogallowsonetospecifyhowamodulebehaves
throughcommandsratherthanhavetofollowaspecificformlike
structuralverilog.Behavioralallowsyoutobypassmuchofthebasiclevel
assignmentsandstuffrequiredinstructuralverilog.

5.

Thecircuitcanbereducedto20nsandstillpassthetests,@a50
MHzclocksignal.Increasingthewidthoftheadderwouldmaketheclock
ratedropduetoincreasedinputs,increaseddelay.Improvingtheclock
ratewouldinvolvemakingthecircuitmoreefficientbyreducinggatesand
criticalpathstoaminimum.

Feedback
1.
Ilikedlearningthenewtricksofveriloglikethedelaycommandforthe
gates.TherewasntanypartofthelabIdisliked.

2.
Themanualwasclearandveryhelpful.

3.
Thelabwasgood,nosuggestions.