Beruflich Dokumente
Kultur Dokumente
Fig.1.
PARTS LIST
R1 R7
1k
R8
10k
R9
10k
R10 -R16
680
R17
10k
C1
0.1F (104)
Q1 Q7
C828
IC1
4033
S1 S3
Push to ON Switch
Display 1
S1 = COUNT
S2 = RESET
S3 = LAMP TEST
In normal operation, reset and clock enable are held at ground and the ripple blanking
input is connected to ground or a more-significant count stage. The counter advances
one count on each ground-to-positive (positive edge) transition of the clock input.
There are two types of outputs. At the 10 output, a square wave that is high for count
0 through 4 and low for counts 5 through 9 results. At the a through g outputs, a high
stage is produced if a display segment is to be lit. Segments b and c are used for the
1 output. Note that the 6 output includes segment a and the 9 output includes
segment d.
The counter is reset to zero by bringing the RST terminal high. This results in an a-b-cd-e-f low, along with a high on the 10 output. The RST input must be returned to
ground when counting is to continue. A high on the Test input puts all outputs high for
lamp or display test.
To automatically extinguish all right -hand zeros, ground the RB IN terminal of the mostsignificant stage and connect its RB OUT to the RB IN of the next most-significant stage,
and so on down the line. This zero blanking is defeated by making all RB IN terminals
positive.
The clock must be noiseless and have only one ground-to-positive transition per desired
count. Rise and fall times should be 5 microseconds or faster.
Maximum clock frequency is 5 megahertz at 10 volts and 2.5 megahertz at 5 volts.
Total package current at a 1 megahertz clock rate with unloaded outputs is 0.4 mA at 5
volts and 0.8 mA at 10 volts.
Fig.2.
You can add any number of fig.2. circuit for increase counting number.
You must connect;
All Y points and all Z points ( Fig.1. Y to Fig.2. Y and Fig.1. Z to Fig.2.
Z)
Fig.1. X to Fig.2. A
When you add 3rd display, second display circuit X point connect to third
display circuit (like fig.2. circuit) A point.