RX MID CHANNELS Internal

850: CH190 -- 881,6 Antenna

GSM: CH 62 -- 947,4 MHz
EGSM: CH 37 -- 942,4Mhz M100
DCS: CH 700 -- 1842,8MHz
PCS: CH 661 -- 1960MHz
Mechanical
DCS/PCS OUT Antenna Switch
HB_TX_OUT 9 J100
1 2 3
(BIAS)
21 BPLUS
Neptune
5
ANT_DETB (to Neptune) „Bypass-Caps“
BPLUS
D1, G2
Reset Circuit
LB_TX_OUT (PA Detect to Neptune) ISENSE 1
D2 G1
1 2 3 Power and Q801 RESETB
Antenna LCELL_BYP
GSM850/ Control S1,S2
U150 GSM900 OUT C805-C808
PA + Antenna Switch 16 15 14 13 8 7 3 4 6
M18....
PCS_RX_50 1900 MHZ V5 NEP_AVDD (VCC + 1,875V)
E2 REF_REG (VCC + 1,575V)
NEPTUNE LTS M17 NEP_QVDD (VCC + 1,875V)
DCS_RX_50 1800 MHz U800 BB_IO_REG_NEP (VCC + 2.775V) (VCC from PCap)

( to PCap )
TX_START
POWER A11
DSP Peripherals C5 VDDA (VCC + 2,775V)
(to U200) (Clock ) MCLK T9 accelerator, encryption H1 AP_IO_REG (VCC + 2,775V)
GSM_RX_50 900 MHz ( Frontend Control (Reset )MS Timer, Interupts M800
W10 SPI V_SIM
and Digital Modulation) (Data In /OUT)MDI
U9 K2 SIM GND
SIM DIO 1+4+5
3

TX_EN (Transmitt Enable)

K3 Connector 9+10

RAMP (PA Power Control)

CELL_RX_50 850 MHz SIM RST
U6 SIM J4 7 1.8 or 3V
DSP DSP VSIM
from Neptune V8 L1 Timer Interface L1 SIM CLK SIM Card
UltraLite Memory 6 2+8
( Frontend Control SIM_PD
104 MHz R1

(Transmitt Enable)
and Digital Modulation)

(Receive Enable)
RX_ANT_EN
M1 VSIM_EN (to Pcap)

(Band select)

TX_START
CNTRL_1
CNTRL_2
CNTRL_3
TXI (NC)
MCLK
DATA BUS D0-15

MDI
MS
Shared Memory
1Mbit RAM
ADDRESS BUS A1-24

G8 E8 E7 D7 C3 D2 B7 D6 G5 E6 C2 U805
W7 External
DAC1 GPIO MCU G17 EB1_B F3
MCU Memory Memory (from Neptune)
A2 SAW/ LNA G12 ARM7 K16 EB0_B C2
Matching
LNA
IIN VoiceBand 52 MHz Interface W18 CS0B K1 FLASH F4 RESET_OUT
RX/TX Sync Anti A13 V17 CS1B
IBIN
ADC Anti Chanel DAC
LPF F8 D6,J1
A3 SAW/ LNA Switch 13 bit Filter Drop Alias Filter 12 bit
ENR N10 J19 R_WB F5,D5
LNA T16 OEB J2,H1 B5... VCC_NEP_MEM
Matching T19 BURSTCLK
F7 C6

Output Mixer
Quadrature Polyphase
Mixer
DC CLKR A4 26 MHz L16 LBAB E5 E4 VBUCK
Filter Correct (100KHz) Serial
A5 SAW/ LNA (100KHz)
F6 Oscillator Clock Generator N18 ECBB G7 ( VCC
LNA Interface from PCap)
Matching FSR 2MB Ram
H7
4 MB Flash
A6 SAW/ LNA
QBIN DRI
LNA RX/TX
MQSPI
ADC Sync Anti Anti Chanel DAC AP_READY ( from U2000)
Matching QIN Switch 13 bit Filter Drop Alias Filter 12 bit
LPF Display M2 ( Bulverde / Neptune Handshake)
Quadrature N1 BP_READY ( to U2000)
1 2 G1 Generator D8 OSCO OSCO_F
U110 Digital TX
PRIME_DIG (VCC)

Clock Generator
Interface G7

Oscilator and
F1 Reference E5 OSCM (Clock enable)
1
EDGE
Devider C5 Y100 2
3 26MHz
U100 GMSK EDGE
FIR C6
Modulator Modulator
GSM/ EDGE Filter U809
1
TRANCEIVER F4 RF_DATA
(Data In /OUT)
V14 BP_OPT1 Switch 5 BB_IO_REG ( VCC)
(Clock ) U8 6
Interface
GMSK/ EDGE Select Serial F5 RF_CLK
(Chip select) V7 SPI W8 BP_OPT2 4 BP_FLASH_MODE_EN
( VCO Feedback ) G4 RF_CS W9 On (from Bulverde -forces Neptune in Flash Mode)
FIN Off
Devider Pre-Distortion Anti LDTO (NC) (U250 Control Bus)
( VCO Tuning) Filter Alias
G3 GPIO
( Lock Detect Out)
One BaseBand UART2
VCO1 (TX_LB) UART / USB Keypad Timer Wire Serial Audio Universal U12 ANT_DETB ( from Mech Antenna Switch)
MQSPI Bus Port Interface
Loop Filter

CP Interface Interface Interface Asynchron. B10 ISENE ( PA_detect from U150)

Phase Det. ADC H3 VCO_REG (rx) (tx)
VCO2 (TX_HB) Voltage B8.. PRIME_DIG Rx /Tx
PA Control Reg.
C1.. RF_REG A16 A17 D15 V12 W12 T10 V13 U13 A12 B13
TX_EN C15 C16 B16 P16 T11 V11 B14 G8 W5 E3 W11 D13 B12
(VCC’s from PCAP)

OSCM

BB_SAP_TX ( RX Audio Data )

Serial Audio for Ringtone BB_SAP_FS ( TX Audio Data )
BB_SAP_CLK (framesync)
(clock)
BP_SLEEP_RQST_1_5V
CLK 13MHZ_1_8V
NEP_ICL_VPOUT

NEP_ICL_TXENB

(from Level Shifter U2006) CLK_32KHz_1_5V

(from U801) NEP_RESET_INB
4

NEP_ICL_XRXD
NEP_ICL_VMIN

(to U805) RESET OUT

(BP-AP Watchdog) BB_WDOG

NEP_ICL_VPIN
(from U900)

BB_SPI_MOSI
NEP_ICL_SE0

BB_SPI_MISO
Inverter

BB_SPI_CLK

AP_SLEEP_RQST
BB_IO_REG

BB_SAP_RX
U804

PCAP_INT
PCAP_CS

One Wire data from Battery OWB

2
BP_SLEEP_RQST

(13 MHz to PCap)

Neptune Bulverde Neptune PCap
USB Communication

(from/ to Neptune

and Voice Audio)

Communication

( Mono )
Revision Overview
2 Rev. 1.0: Initial Block Diagram
Level Rev. 1.1 added ISENSE at U800
Shift Rev. 1.2 added FM_INT at U500, U2000
U803 Rev.1.3 edited arrows, descriptons & Signals
(Sleep Mode Indication to Clock Circuit) (Clock disable/ enable)
4 Rev.1.4 updated BATTP and BATTI inputs at PCap,, updated PCAP_INT
at Neptune, updated I2C Bus, added VCC_PLL at U2000, updated

(Sleep Mode Indication to PCap )

Funlight Driver Circuit, updated Pin8 of J403 to GND,

BP_SLEEP_RQST
Rev. 1.5: Rev. 1.4: Audio Signals routingat U2000, U900

GSM SERVICE SUPPORT GROUP 2006.03.28

A1200
LEVEL 3 AL Block Diagram Rev. 1.5
A1200
Page1of 3
 (13MHz Clock to U900) MMEDIA_13MHz
ESD SD-Card Contact Flip Open/Close Detect
U22 (from PCAP )
A19 MMC_D0 C1 A1 9 1,2
6 U2005 2 U2000

FL2010
CLK_32KHZ_1_5V GND AP_IO_REG
(from Level Shifter U2006) AA22 XTAL D17 MMC_D1 C2 A2 10 8

M2001
GPIO B17 MMC_D2 C3 Hall Efect FLIP_INT A3 Bulverde
AD21 A3 3 11
(VCC from Q907) 13 MHz Y2000 INT. C17 MMC_D3 C4 A4 4 Transistor
VCC_STACKED_MEM AC21 SD Card 12
B18 MMC_CMD C5 A5 5 (forces Neptune in Flash Mode) Generic
B6... BP_FLASH_MODE_EN C18 GPIO
A20 MMC_CLK 7 6 VCC_TRANSFLASH (VCC from PCap)
(VCC from PCap) 1-25 ADDR. BUS
PCUTS_VCC B2,B4,..... GND 8 J403 5 AUDIO_REG (VCC from PCap)
(VCC from PCap)
0-15 DATA BUS VBUCK 3

Connector
H4 SDCLK0 AC4 1 I2C_RESET A14
VBUCK E9 GND 7,8..
23 I2C_SCL D20

Camera
N11 SDCLK2 AD7 B16 CAM_CLK_IN 24
U2001 C6 AD3 21 I2C_SDA A22
SDCLK3 GPIO AB13 CAM_EN 4
AB7 NSDCS0 D1 MEM. U2000 Kamera C15... CAM_DATA(0-7 11... U405
AD6
AA6
NSDCS3
NSDCAS
C1
L1
Int. Bulverde AA11
AA12
CAM_VSYNC
CAM_HSYNC
10
9 20
CAM_CLK_OUT
B1 (I2C Data Bus to FM Receiver
AC7 NSDRAS
(Aplication Processor) A1 & and Funlight Driver) BUL_VCC_IO A12
M1
AD6 SDCKE N1 AA14 CAM_PCLK_GATE C2 BUL_VCC_BB AD12
SDRAM AP_IO_REG BUL_VCC_BATT AB20
AB9 DQM0 E1 (VCC from PCap)
(48MB) C7 LCD_ID0 2
1 BUL_VCC_LCD J24 Power
AB10 DQM1 F1 J400 VBUCK
Y21 B9 LCD_ID1 2 BUL_VCC_MEM A4
NRESET_OUT E4
Flash NCS0
R21 LCD_OE 4 Constant Current AP_CORE A7
B3 G8 R23 LCD_VSYNC 8 Backlight Supply VCC_SRAM A5
(64MB) AC5 NOE J8 CPU LCD

Touchscreen/ Display
P23 LCD_HSYNC 12 VCC_PLL AC20
AB5 NWE E3 Display P22 LCD_MCLK 16 L401
Interface B7 LCD_SD 20 D101 U404

Connector
TB_RL (NC) 22
32 LED+ 1 2 BPLUS ( VCC fromU901) (Backlight Enable)
AP_SLEEP_RQST AP_CLK_RQST Y23 C8 LCD_CM 24
1,4V 4 BLK_PWM A18 Generic
(Bulverde to PCap/Neptune Sleep Indicator) U911 5
Flash G24 LDD1-LDD17 29.... 38 LED- 6 GPIO
AP_READY AC19 32MB C16
( Bulverde / Neptune Handshake) 6 TSY2 (from U500- FM IC interupt) FM_INT

VR400
(ESD)
BP_READY Y22 GND 1,10...
34 TSY1 ( to PCap ) (Interupt from U901) EMU_INT V23
VBUCK
(from PCap) 26 39 TSX2
GPIO AP_IO_REG 28 (Enable to EMU IC) USB_READY AB18
36 TSX1
BT
ANTENNA PAD AC18 KBR0 Side Down- (J405)
BT_TXD AC17 KBR1 Image .......- (J406)
B9 C22
BT_RXD AB17 KBR2 VA ..............(J407)
B8 C21
BT_CTS Keypad AD18 KBR4 Side Up...... .(J408)
BT_ANTENNA RFIO C8 C19
FL301 E1 BT_RTS GPIO KBR2 Side Select...(J409)
C9 B20 USB/ Client USB/ Host
B3,H9.... B4
BT_NRESET A15 SSP2/ SSP3/ SSP1/ M403 Port 2 Port3
(VCC from AP_IO_REG_1 GPIO/
BLUE_WAKEB Codec1 Codec2 POWER/ NC 1- 4 EMU -Bulverde Bulverde Neptun
PCAP) BTRF_REG A4 B5 AC11 (Voice, BT Audio) (Application Aud.) 1nd Serial Timer FAIL DET. AA17 KBR3
BLUE_HOST_WAKEB C10 Interface
5 Keypad (communication) (communication)
(tx) (rx) (rx) (tx) AB16 KBC2 6
B6

AA10
Connector

AB24
W23
W21
AD10 AB12 B15 B13 A17 D14 D19 A21 AB11 F22 C13

C24
Y22
T24 B14 GND 7
Bluetooth D13 C23 AD9 AC14 D16 Y24 AD15
PWR_SW 8 AB14 C14 B19 C12 A13 F23
U300

BP_RESETB
(rx) E8 S401 2 3 1 4 6
Y300 1 J5
(tx) D9
BB_SAP_RX
U L = Left

POWER_FAIL_N

EMU_USB_VPOUT_TXD
(framesync)
26 Mhz

U910
U = Up

BB_WDOG
D8

EMU_USB_VMIN_RXD
(clock) R R = Right
F8 L
5 C

NEP_RESET_INB
KBC1 D = Down

EMU_USB_TXENB
(from Level Shifter U2006)

PCAP_MCU_RESETB

NEP_ICL_VPOUT

NEP_ICL_TXENB
J4

EMU_USB_XRXD
3

EMU_USB_VPIN
C = Center

NEP_ICL_XRXD
CLK_32KHZ_1_5V

NEP_ICL_VMIN
U801
A5 D

NEP_ICL_VPIN
EMU_USB_SE0
Neptune PCap

NEP_ICL_SE0
Communication
(clock) BB_SAP_CLK Navigation Key
HJACK_DET

(from/ to Neptune (framesync) BB_SAP_FS

BB_SPI_MISO
BB_SPI_MOSI
Serial Audio for Ringtone ( TX Audio Data )BB_SAP_RX

SYS_RESTART
BB-SPI_CLK
AP_PCAP_INT
AP_SPI_MOSI
AP_SPI_MISO
and Voice Audio)

AP_PCAP_CS
AP_SAP_CLK

PCAP_INT
AP_SPI_CLK

POWER_FAIL
ST_REF (Bias)
AP_SAP_TX

PCAP CS
( RX Audio Data )BB_SAP_TX

(to U901)
AP_SAP_FS

(to Neptune)
AP_WDOG
BB_SAP_CLK

BB_SAP_TX
BB_SAP_RX

POWER_SW
BB_SAP_FS

RESETB
Bulverde -EMU- IC Bulverde - Neptune
USB USB
( the PCap is Master for Communication Communication
Audio Clock and
Framesync.)
NC

K12
K11
D15

H12
C12

L12
G3
H6

L10

E11
D3
D2

F11
H8
H7

B2
F6

F5

M8
G7
G8

N9
C5

C6

K9
E5

H9
R7
F7

P8

J12
(from U901) AUDIO_IN K7 (tx) (rx) (tx) (rx) A5 ACC_ID (Accesory ID from U901)
USB/RS232 PRI SPI SEC SPI ON
Detect
Stereo

HJACK_DET H5 CODEC CODEC POWER T16 EMU_PWR_ON (External B+ Sense from U901)
13 BIT CNTL. CNTL. TIMER LOGIC AD
R1 16 BIT (communication) LOGIC LOGIC FAIL DET. CONV. M11 BATTI (Battery Current Sense from R921)
INT_MICP PHONE STEREO R17 BATTP (Battery Sense )
MIC_BIAS1 N3 A/D
AUDIO U5 THERM (Thermistor from Battery) M901
HJACK_MIC R2
AMPL.
MIC_BIAS2 M2 4 BATTP R921 BATTI (from R901 - Charger)
(from/ to
Audio Circuit) ALERTM_PAD F1 N8 THERMBIAS THERM 2 (OWB Battery Data to Neptune Interface)
ALERTP_PAD H1 IO 3 OWB
Battery
HJACK_SPKR_L K3 K13 SIM_PD (to Neptune) Connector 1 GND
HJACK_SPKR_R L2
PGA_INR J7 CHARGE
Audio Filter PGA_INL CONTR. R15
L6
C1 A1 HAND_SPKRP
Logic
( to Flip Connector) FL902 HAND_SPKRM
J4
K2
U900 OVER
VOLT. N13
C3 A3 PCAP2 CNTL. NC
A5 LED J16
B4 USB CNTL. J15
NC
B3 INTERF.
BACKl. K17
TSY2 T4 TOUCH CONTR.
(from/ to J400) TSY1 R4 SCREEN
TSX2 T2 INTERF. C2 CLK_13MHZ_1_8V ( from Neptune (Clock Source))
TSX1 T3 MMEDIA_13MHZ ( from Bulverde) (Clock Source))
C1
R12 MEMORY P10 BP_SLEEP_RQST (Sleep Mode Indication) (disables: RF_REG, BB_IO_REG, VCO_REG)
U13 HOLD M9 AP_SLEEP_RQST (Sleep Mode Indication) (disables: AP_CORE,VCC_SRAM, VCC_PLL)
P15 TX_START (from Neptune)
TIMER
B Sense
VHOLD_EXT_EN

U8
Y900
Boost Mode
Switcher 3

Switcher 2

Switcher 1
Buck Mode

Buck Mode
PCUTS_VCC

DRIVE
VSIM
AUX3

U10
to Vibra
VIB

V10 V9 V8 V7 V6 V5 V4 V3 V2 V1
T7 CLK_32KHz CLK_32KHz (to U500 )
( 1,3V )
G12........

(Level Shifter) Revision Overview

T11 2 4
M15
K14

G17

N12

H15

H17

D10
H14

E10

F17

F10

F15

L17

U2006 CLK_32KHz_1_5V (to U2000+U300+U800) Rev. 1.0: Initial Block Diagram

A6

A7

U1
B7

T10 Rev. 1.1 added ISENSE at U800

LCELL_BYP
PCAP_BP

(RTC Batterie) Rev. 1.2 added FM_INT at U500, U2000

E PNP B

Rev.1.3 edited arrows, descriptons & Signals

+ BT900
( 2,80V ) VCC_TRANSFLASH

LICELL
C Q901

2 C962/963 Rev.1.4 updated BATTP and BATTI inputs at PCap,, updated PCAP_INT
Vibrator

- at Neptune, updated I2C Bus, added VCC_PLL at U2000, updated

Motor
M902
( 2,775V ) BB_IO_REG

( 2,775V ) AP_IO_REG
Q907

Funlight Driver Circuit, updated Pin8 of J403 to GND,

( Not used)
VCC_STACKED_MEM

( 2,775V ) VCO_REG

( 2,775V ) AUD_REG

Q990
( 1,275 ) VCC_SRAM
VSIM_EN

( 1,575V ) REF_REG
( 1,275V )VCC_PLL

Rev. 1.5: Rev. 1.4: Audio Signals routingat U2000, U900

RF_REG

( 1,875V ) VBUCK

( 1,2V ) AP_CORE
( 5,5V ) VBOOST
) VSIM

3
)BT_RF_REG
BPLUS

AP_IO_REG
( 2,775V )

GSM SERVICE SUPPORT GROUP 2006.03.28

( 1,8/ 3V
( 1,8V )

BPLUS
(Enable)

A1200
LEVEL 3 AL Block Diagram Rev. 1.5
( 2,775V

( from U900) AP_IO_REG PRIME_DIG (to 100 ) A1200

Page2of 3
 Bulverde -EMU- IC
USB
Communication

EMU_USB_VPOUT_TXD
EMU_USB_VMIN_RXD

EMU_USB_TXENB
EMU_USB_XRXD
EMU_USB_VPIN

EMU_USB_SE0
17
13
14

12
28
16
(from U2000)
I2C_SCL 7
I2C_SDA 9
(Reset from PCap) PCAP_MCU_RESETB 11 EMU IC
U901
(VCC from PCap) AP_IO_REG I2C_ADDRESS 6, 8
4

J902
Audio Circuit (Bias)
AP_IO_REG
(Accesory ID to PCap) ACC_ID
(Interupt to Bulverde) EMU_INT
5
10
(Enable from Bulverde) USB_READY 27
HJACK_DET (from/ to PCap )
(External B+ Sense to U900) EMU_PWR_ON 33
HJACK_MIC (VCC from PCAP) VBOOST_EMU 25
VBOOST
Audio Filter
Stereo Headset HS_SPKR_L C1 A1 HJACK_SPKR_L (from PCap
EXT. MIC to PCap) AUDIO_IN 19
Jack FL901 HJACK_SPKR_L 20
HS_SPKR_R C3 A3 HJACK_SPKR_R and EMU IC) J904 ( from PCAP)
HJACK_SPKR_R 18
G1-G4 GND 3 22 ...
FM_ANT_IN ( to FM Stereo IC)
5 U902
Internal MK901 3 DP_RXD 23

Microphone
1
4
L909 INT_MICP
MIC_BIAS1
Mini USB 2 DM_TXD Filter 21

4 UID ESD VR902 15

ALERTM_PAD VBUS
Alert Pads 1 USB_PWR R967 29
2
ALERTP_PAD
Battery USB Power to CR906
Audio A1 A3 BPLUS Switch
FM 15 PGA_INR (from/ to PCap ) Power to
Filter FL903
B2 Receiver 13
(Stereo Audio to PCap)
PGA_INL BPLUS Q903 BP_FET 34
U500 (VCC) 8 FM_VCCA AUDIO_REG Switch
(from Headset (Main Power Sourse for A1200 BPLUS
FM Radio Connector J902)
17 FM_VCCD AP_IO_REG
to PCap, Q990, Q902.....)
35
11 CLK_32KHZ BATT_FET 36
FM_ANT_IN 6
Q902 Charger Q904_5_EN 30
19 I2C_SDA (Control Bus from U2000 Q904 Q905 (Charge Control)
19 GPIO- Interface)
20 I2C_SCL
20
16 FM_INT (Interupt to U2000 GPIO- Interface) Color definition only for this section !
Main Charge Path (Charge Power Source)
B+ support without Ext Charger CHARGER_INPUT
B+ support with Ext Charger

R901 ISENSE 32
(Charge Current Sense)
(to R921- Charger Source) BATTI BATTI 37

Sign of Live Circuit

CR 926
(Sign of Live Enable)
(VCC to PCap) VBOOST Q925 SOL 38

Flip
Connector

J402
2 VBOOST_FLIP VBOOST (VCC from PCap)
5 HAND_SPKRP
(from FL902)
7 HAND_SPKRM
Flip Connector

U401
6 BLUE1_CATHODE 3 21 AP_IO_REG (VCC from PCap)
4 BLUE2_CATHODE 8
14 RED1_CATHODE 1
8 RED2_CATHODE 6
12 GREEN1_CATHODE 2 19 I2C_SCL (from U2000)
10 GREEN2_CATHODE 7 20 I2C_SDA
1,3,9,11,13 9, 22...
GND GND
Revision Overview
Rev. 1.0: Initial Block Diagram
Funlight Rev. 1.1 added ISENSE at U800
Driver Rev. 1.2 added FM_INT at U500, U2000
Rev.1.3 edited arrows, descriptons & Signals
Rev.1.4 updated BATTP and BATTI inputs at PCap,, updated PCAP_INT
at Neptune, updated I2C Bus, added VCC_PLL at U2000, updated
Funlight Driver Circuit, updated Pin8 of J403 to GND,
Rev. 1.5: Rev. 1.4: Audio Signals routingat U2000, U900

GSM SERVICE SUPPORT GROUP 2006.03.28

LEVEL 3 AL Block Diagram Rev. 1.4

A1200 A1200
Page3of 3