module PCSel1 (PC, Instruction, Zero, Branch,Clk, Jump, nextPC);

input [31:00] Instruction;

input [31:00] PC;
input Jump;
input Clk;
input Branch;
input Zero;
output reg [31:00] nextPC;
wire [31:00]PC1;
wire [3:0]PC11;
wire [31:0] out1,out2;
wire [31:0] out3,op4;
wire [15:0]op;
wire [25:0]op2;
wire [27:0]op3;
wire Select1;
reg [31:0] out4;

assign PC1 = PC+32;

assign op = Instruction[15:0];
assign op2 = Instruction[25:0];
assign op3 = op2 << 2;
assign PC11 = PC1[31:28];
assign op4 = {PC11, op3};
assign out1 = op ; // sign-extends
assign out2 = out1 << 2;
assign out3 = out2 + PC1;
assign Select1 = Branch & Zero;
always @(posedge Clk)
begin
case(Select1)
1'b0 : out4 = PC1;
1'b1 : out4 = out3;
endcase
end
always @(posedge Clk)
begin
case(Jump)
1'b0 : nextPC = out4;
1'b1 : nextPC = op4;
endcase
end
endmodule
module MuxM1 (in1,in2,RegDest,Instruction1); // Mux2x1;
input [31:0] in1;
input [31:0] in2;
input RegDest;
output reg [31:0] Instruction1;
//reg [4:0] Instruction1;
always @(in1 ,in2, RegDest)

begin
case(RegDest)
1'b0 : Instruction1 = in1;
1'b1 : Instruction1 = in2;
endcase
end
endmodule

module DM (writeaddr,writedata,write,clock,readaddr,readdata,RegCell);
input [31:0] writeaddr, readaddr;
input [31:0] writedata;
input write,clock;
output [31:0] readdata;
reg [31:0] RegCellS [0:1024] ;
output reg [31:0] RegCell ;
always @(posedge clock)
begin
if (write == 1 )
begin
RegCellS[writeaddr] = writedata;
RegCell = RegCellS[writeaddr];
end
end
assign readdata = RegCellS[readaddr];
endmodule
module ALU(rs_value,rt_value, zero,clk, instruction, rd_value,operation);
input [31:0] rs_value,rt_value ;
input clk ;
output zero ;
input [31:0] instruction;
output reg [31:0] rd_value;
output reg [3:0] operation;
reg [25:0] target ;
reg zero ;
reg [5:0] funct;
reg [1:0]instruction_type;
reg [15:0] immediate_offset, PC;
reg [31:0] memory[0:4095];
reg [5:0] op;
reg [5:0] op2;
reg [31:0] rt_value1 ;
always @ (posedge clk )
begin
op [5:0] = instruction[31:26];
op2 [5:0] = instruction[10:6];
case(op)
0: /* R-type */
begin

instruction_type = 2'b00;
funct = instruction[5:
0];
end
2: /* J-type */
begin
target = instruction[25:0];
instruction_type = 2'b10;
end
default: /* I-type */
begin
immediate_offset = instruction[15:0];
instruction_type = 2'b01;
end
endcase

case(instruction_type)
2'b00: /* R-type */
begin
case(funct)
6'b100001: /* add rd, rs, rt */
begin
rd_value = rs_value + rt_value;
zero = 0;
operation= 4'b0000;
end
6'b100011: /* sub rd, rs, rt */
begin
rd_value = rs_value - rt_value;
zero = 0;
operation= 4'b0001;
end
6'b100100: /* and rd, rs, rt */
begin
rd_value = rs_value & rt_value;
zero = 0;
operation= 4'b0010;
end
6'b100101: /* or
rd, rs, rt */
begin
rd_value = rs_value | rt_value;
zero = 0;
operation= 4'b0011;
end
6'b101010: /* slt rd, rs, rt */

begin
rd_value = rs_value < rt_value? 1 : 0;
zero = 0;
operation= 4'b0100;
end
6'b000000: /* sl1 rd, rs, rt */
begin
rd_value = rt_value << op2;
zero = 0;
operation= 4'b0101;
end
6'b000010: /* srl rd, rs, rt */
begin
rd_value = rt_value >> op2;
zero = 0;
operation= 4'b0110;
end
endcase
end
2'b01: /* I-type */
begin
case(op)
6'b000100: /* beq rs, rt, offset */
begin
if(rs_value == rt_value) zero = 1;
operation= 4'b0111;
end
6'b001001: /* addi rt, rs, immediate */
begin
rd_value = rs_value + immediate_offset;
zero = 0;
operation= 4'b1000;
end
6'b001100: /* andi rt, rs, immediate */
begin
rd_value = rs_value & immediate_offset;
zer
o = 0;
operation= 4'b1001;
end
6'b001101: /* ori rt, rs, immediate */

begin
rd_value = rs_value | immediate_offset;
zero = 0;
operation= 4'b1010;
end
6'b100011: /* lw
rt, rs[offset] */
begin
rd_value = rs_value + immediate_offset;
zero = 0;
operation= 4'b1011;
end
6'b1010
11: /* sw

rt, rs[offset] */
begin
rd_value = rs_value + immediate_offset;
zero = 0;

operation= 4'b1100;
end
endcase
end

2'b10: /* J-type */
begin
case(op)
6'b000010:
begin
PC = target;
end
endcase
end
endcase
end
endmodule

module MuxM (in1,in2,RegDest,Instruction1); // Mux2x1;

input [31:0] in1;
input [31:0] in2;
input RegDest;
output reg [31:0] Instruction1;
//reg [4:0] Instruction1;
always @(RegDest)
begin

case(RegDest)
1'b0 : Instruction1 = in1;
1'b1 : Instruction1 = in2;
endcase
end
endmodule
module SignExtender(in,out );
input signed [15:0] in;
output signed [31:0] out;
assign out = in; // sign-extends
endmodule

// Mux2:1
module Mux2x11 (in1,in2,RegDest,Instruction1); // Mux2x1;
input [4:0] in1;
input [4:0] in2;
input RegDest;
output reg [4:0] Instruction1;
//reg [4:0] Instruction1;
always @(RegDest )
begin
case(RegDest)
1'b0 : Instruction1 = in1;
1'b1 : Instruction1 = in2;
endcase
end
endmodule
// InstructionDecoder;
module InstructionDecoder ( Instruction,Clk,RegDest, Jump,Branch,MemtoReg,MemRe
ad,
MemWri
te,ALUSrc, RegWrite);
input [5:0]Instruction;
input Clk;
output reg RegDest;
output reg Jump;
output reg Branch;
output reg MemtoReg;
output reg MemWrite;
output reg MemRead;
output reg ALUSrc;
output reg RegWrite;
always @ (posedge Clk)
case(Instruction)
6'b000000: /* R-type */
begin
RegDest =

1;
Jump=
Branch=
MemtoReg=
MemWrite=

x;

0;
0;
0;
1'b

MemRead= 0;
ALUSrc=
RegWrite=

0;
1;

end
6'b101011: /* SW */
begin
RegDest =

1'bx;
Jump=
Branch=
MemtoReg=

0;
0;
1'b

MemWrite=
MemRead=

1;

ALUSrc=

1;

RegWrite=

0;

x;
0;

end
6'b100011: /* LW */
begin
RegDest =

0;
Jump=
Branch=
MemtoReg=
MemWrite=
MemRead=

0;
0;
1;
0;

ALUSrc=
RegWrite=

1;
1;

1;

end
6'b000100: /* BEQ*/
begin
RegDest =

1'bx;
Jump=
Branch=
MemtoReg=

0;
1;
1'b

MemWrite=

1'b

x;
x;
MemRead=
0;
ALUSrc=
RegWrite=

0;

0;

end
6'b000010: /* J-type */
begin
RegDest = 1'bx;
Jump=
Branch=
x;

1;
1'b

MemtoReg=

1'b

MemWrite=

1'b

x;
x;
MemRead=
0;
ALUSrc=

1'b

x;
RegWrite=

0;

end
endcase
endmodule

//ROM
module ROM(
input clk,
input [31:0] PC,
output [31:0] Instruction
);
reg [31:0] Instruction;
always @(posedge clk)
case (PC)
32'b00000000000000000000000000100000:
0001000000100001;
/*add*/
32'b00000000000000000000000001100000:
0001000000100011;
/*sub*/
32'b00000000000000000000000010000000:
0001000000100100;
/*and*/
32'b00000000000000000000000010100000:
0001000000100101;
/*or*/
32'b00000000000000000000000011100000:
0001000000101010;
/*slt*/
32'b00000000000000000000000100000000:
0001000010000000;/*sll*/
32'b00000000000000000000000100100000:
0001000010000010;/*srl*/
32'b00000000000000000000000101000000:
0001000000000010;/*andi*/
32'b00000000000000000000000101000000:
0001000000000010;/*addi*/
32'b00000000000000000000000101100000:
0001000000000010;/*ori*/
32'b00000000000000000000000110000000:
0001000000100100;/*beq*/
32'b00000000000000000000000110100000:
0000000000100000;/*load*/
32'b00000000000000000000000111000000:
0000000000100000;/*store*/
32'b00000000000000000000000111100000:
0000000001000000;/*jump */
endcase
endmodule

Instruction = 32'b0000000000000001
Instruction = 32'b0000000000000001
Instruction = 32'b0000000000000001
Instruction = 32'b0000000000000001
Instruction = 32'b0000000000000001
Instruction = 32'b0000000000000001
Instruction = 32'b0000000000000001
Instruction = 32'b0011000000000001
Instruction = 32'b0010010000000001
Instruction = 32'b0011010000000001
Instruction = 32'b0001000000000001
Instruction = 32'b1000110000000001
Instruction = 32'b1010110000000001
Instruction = 32'b0000100000000000

// RegisterFile
module RegisterFile(writeaddr,writedata,write,clock,readaddr1,readaddr2,readdata
1,readdata2,RegCell);
input [4:0] writeaddr, readaddr1, readaddr2;
input [31:0] writedata;
input write,clock;
output reg [31:0] readdata1,readdata2;
reg [31:0] RegCellS [0:31] ;
output reg [31:0] RegCell ;
always @(posedge clock)
begin
if (write == 1)
begin
RegCellS[writeaddr] = writedata;
RegCell = RegCellS[writeaddr];
end
if (write == 0)
begin
readdata1 = RegCellS[readaddr1];
readdata2 = RegCellS[readaddr2];
end
end
endmodule
module MIPS1(
input [31:0] PC,
input clk,
output [4:0]In11,In21,In31,In61,
output [15:0]In51,
output [25:0]In41,
output [31:0] Instruction
);
wire [31:0] Instruction;
wire [4:0] In11;
wire [4:0] In21,In31;
wire [5:0] In61;
wire [25:0] In41;
wire [15:0] In51;
ROM G1 (clk, PC,Instruction );
assign In11 = Instruction[20:16];
assign In21 = Instruction[15:11];
assign In31 = Instruction[25:21];
assign In41 = Instruction[25:00];
assign In51 = Instruction[15:00];
assign In61 = Instruction[31:26];
// Mux2x11 G2 (In1,In2,RegDest,Instruction1);
//RegisterFile G3 ( In1,In2,In2,writedata,Regwrite,clk,readdata1,readdat
a2);
endmodule
module Decoder (PC1,In111,In211,In311,In411,In511,In611,clk1,RegDest1, Jump1,B
ranch1,MemtoReg1,MemRead1,
Instru
ction1,MemWrite1,ALUSrc1, RegWrite1);

input [31:0]PC1;
input clk1;
output wire [4:0] In111;
output wire[4:0] In211,In311;
output wire[5:0] In611;
output wire[25:0] In411;
output wire[31:0] Instruction1;
output wire[15:0] In511;
output wire RegDest1;
output wire Jump1;
output wire Branch1;
output wire MemtoReg1;
output wire MemWrite1;
output wire MemRead1;
output wire ALUSrc1;
output wire RegWrite1;
MIPS1 instance_name (
.PC(PC1),
.clk(clk1),
.In11(In111),
.In21(In211),
.In31(In311),
.In61(In611),
.In51(In511),
.In41(In411),
.Instruction(Instruction1)
);
InstructionDecoder ID11 (In611,clk1,RegDest1, Jump1,Branch1,MemtoReg1,MemRead1,
MemWrite1,ALUSrc1, Reg
Write1);
endmodule

// Mux module
module a (PC11,clk11,A,B,C,D,E,F,Instructions11,RegDest11, Jump11,Branch11,Memto
Reg11,MemRead11,
Instru
ctionD1,MemWrite11,ALUSrc11, RegWrite11);
input [31:0] PC11;
input clk11;
output wire RegDest11;
output wire Jump11;
output wire Branch11;
output wire MemtoReg11;
output wire MemWrite11;
output wire MemRead11;
output wire ALUSrc11;
output wire RegWrite11;
output wire[5:0] F;
output wire[25:0] D;
output wire[15:0] E;
output wire [4:0]A,B,C;
output wire [4:0] Instructions11;

output wire[31:0] InstructionD1;

Decoder instance_name (
.PC1(PC11),
.In111(A),
.In211(B),
.In311(C),
.In411(D),
.In511(E),
.In611(F),
.clk1(clk11),
.RegDest1(RegDest11),
.Jump1(Jump11),
.Branch1(Branch11),
.MemtoReg1(MemtoReg11),
.MemRead1(MemRead11),
.MemWrite1(MemWrite11),
.ALUSrc1(ALUSrc11),
.RegWrite1(RegWrite11),
.Instruction1(InstructionD1)
);
Mux2x11 M1 (A,B,RegDest11,Instructions11);
endmodule

module RegisterFile1(PC21,,clk21,writeaddr1,writedata1,A1,B1,C1,D1,E1,F1,Instru
ctions21,readdata11,readdata21,RegDest21,
Jump21,Branch21,write,InstructionD11,MemtoReg21,MemRead21,MemWrite21,ALU
Src21, RegWrite21,RegCellD);
input [4:0] writeaddr1;
input [31:0] writedata1;
input [31:0] PC21;
input clk21,write;
output wire [31:0] readdata11,readdata21;
output wire RegDest21;
output wire Jump21;
output wire Branch21;
output wire MemtoReg21;
output wire MemWrite21;
output wire MemRead21;
output wire ALUSrc21;
output wire RegWrite21;
output wire[5:0] F1;
output wire[25:0] D1;
output wire[15:0] E1;
output wire [4:0]A1,B1,C1;
output wire [4:0] Instructions21;
output wire [31:0] RegCellD ;
output wire [31:0] InstructionD11 ;
a instance_name (
.PC11(PC21),
.clk11(clk21),
.A(A1),
.B(B1),

.C(C1),
.D(D1),
.E(E1),
.F(F1),
.Instructions11(Instructions21),
.RegDest11(RegDest21),
.Jump11(Jump21),
.Branch11(Branch21),
.MemtoReg11(MemtoReg21),
.MemRead11(MemRead21),
.MemWrite11(MemWrite21),
.ALUSrc11(ALUSrc21),
.RegWrite11(RegWrite21),
.InstructionD1(InstructionD11)
);
RegisterFile R1(writeaddr1,writedata1,write,clk21,C1,A1,readdata11,read
data21,RegCellD);
//RegisterFile R2(writeaddr1,writedata1,1,clk21,C1,A1,readdata11,readda
ta21);
//RegisterFile R3(writeaddr1,writedata1,0,clk21,C1,A1,readdata11,readda
ta21);
endmodule
module SignExtenderM (PCM,clkM,out1,writeaddrM,writedataM,AM,BM,CM,DM,EM,FM,Ins
tructionsM,readdata1M,readdata2M,RegDestM,
JumpM,BranchM,writeM,InstructionD12,MemtoRegM,MemReadM,MemWriteM,ALUSrcM
, RegWriteM,RegCellDM);

input [4:0] writeaddrM;

input [31:0] writedataM;
input [31:0] PCM;
input clkM,writeM;
output wire [31:0] out1;
output wire [31:0] readdata1M,readdata2M;
output wire RegDestM;
output wire JumpM;
output wire BranchM;
output wire MemtoRegM;
output wire MemWriteM;
output wire MemReadM;
output wire ALUSrcM;
output wire RegWriteM;
output wire[5:0] FM;
output wire[25:0] DM;
output wire[15:0] EM;
output wire [4:0]AM,BM,CM;
output wire [4:0] InstructionsM;
output wire [31:0] RegCellDM ;
output wire[31:0] InstructionD12;

RegisterFile1 instance_name (
.PC21(PCM),

.clk21(clkM),
.writeaddr1(writeaddrM),
.writedata1(writedataM),
.A1(AM),
.B1(BM),
.C1(CM),
.D1(DM),
.E1(EM),
.F1(FM),
.Instructions21(InstructionsM),
.readdata11(readdata1M),
.readdata21(readdata2M),
.RegDest21(RegDestM),
.Jump21(JumpM),
.Branch21(BranchM),
.write(writeM),
.MemtoReg21(MemtoRegM),
.MemRead21(MemReadM),
.MemWrite21(MemWriteM),
.ALUSrc21(ALUSrcM),
.RegWrite21(RegWriteM),
.RegCellD(RegCellM),
.InstructionD11(InstructionD12)
);
SignExtender SE (EM,out1);
endmodule
module mux2 (PCM1,clkM1,outM1,writeaddrM1,writedataM1,AM1,BM1,CM1,DM1,EM1,FM1,I
nstructionsM1,readdata1M1,readdata2M1,RegDestM1,
JumpM1,BranchM1,writeM1,InstructionD13,MemtoRegM1,MemReadM1,MemWriteM1,A
LUSrcM1, RegWriteM1,RegCellDM1,Ali);
input [4:0] writeaddrM1;
input [31:0] writedataM1;
input [31:0] PCM1;
input clkM1,writeM1;
output wire [31:0] outM1;
output wire [31:0] readdata1M1,readdata2M1;
output wire RegDestM1;
output wire JumpM1;
output wire BranchM1;
output wire MemtoRegM1;
output wire MemWriteM1;
output wire MemReadM1;
output wire ALUSrcM1;
output wire RegWriteM1;
output wire[5:0] FM1;
output wire[25:0] DM1;
output wire[15:0] EM1;
output wire [4:0]AM1,BM1,CM1;
output wire [4:0] InstructionsM1;
output wire [31:0] RegCellDM1;
output wire [31:0] Ali;
output wire[31:0] InstructionD13;
// Instantiate the module
SignExtenderM instance_name (
.PCM(PCM1),
.clkM(clkM1),
.out1(outM1),
.writeaddrM(writeaddrM1),

.writedataM(writedataM1),
.AM(AM1),
.BM(BM1),
.CM(CM1),
.DM(DM1),
.EM(EM1),
.FM(FM1),
.InstructionsM(InstructionsM1),
.readdata1M(readdata1M1),
.readdata2M(readdata2M1),
.RegDestM(RegDestM1),
.JumpM(JumpM1),
.BranchM(BranchM1),
.writeM(writeM1),
.MemtoRegM(MemtoRegM1),
.MemReadM(MemReadM1),
.MemWriteM(MemWriteM1),
.ALUSrcM(ALUSrcM1),
.RegWriteM(RegWriteM1),
.RegCellDM(RegCellDM1),
.InstructionD12(InstructionD13)
);
MuxM M2 (readdata2M1,outM1,ALUSrcM1,Ali);
endmodule
module ALUM (PCM2,clkM2,outM2,writeaddrM2,writedataM2,AM2,BM2,CM2,DM2,EM2,FM2,In
structionsM2,
readdata1M2,readdata2M2,RegDestM2, JumpM2,BranchM2,writeM2,MemtoRegM
2,MemReadM2,
MemWriteM2,InstructionD14,ALUSrcM2, RegWriteM2,R
egCellDM2,Ali2,zero2, rd_value2,opr);

input [4:0] writeaddrM2;

input [31:0] writedataM2;
input [31:0] PCM2;
input clkM2,writeM2;
output wire [31:0] outM2;
output wire [31:0] readdata1M2,readdata2M2;
output wire RegDestM2;
output wire JumpM2;
output wire BranchM2;
output wire MemtoRegM2;
output wire MemWriteM2;
output wire MemReadM2;
output wire ALUSrcM2;
output wire RegWriteM2;
output wire[5:0] FM2;
output wire[25:0] DM2;
output wire[15:0] EM2;
output wire [4:0]AM2,BM2,CM2;
output wire [4:0] InstructionsM2;
output wire [31:0] RegCellDM2;
output wire [31:0] Ali2;
output wire zero2 ;
output wire [31:0] rd_value2;
output wire [3:0] opr;

output wire[31:0] InstructionD14;

mux2 instance_name (
.PCM1(PCM2),
.clkM1(clkM2),
.outM1(outM2),
.writeaddrM1(writeaddrM2),
.writedataM1(writedataM2),
.AM1(AM2),
.BM1(BM2),
.CM1(CM2),
.DM1(DM2),
.EM1(EM2),
.FM1(FM2),
.InstructionsM1(InstructionsM2),
.readdata1M1(readdata1M2),
.readdata2M1(readdata2M2),
.RegDestM1(RegDestM2),
.JumpM1(JumpM2),
.BranchM1(BranchM2),
.writeM1(writeM2),
.MemtoRegM1(MemtoRegM2),
.MemReadM1(MemReadM2),
.MemWriteM1(MemWriteM2),
.ALUSrcM1(ALUSrcM2),
.RegWriteM1(RegWriteM2),
.RegCellDM1(RegCellDM2),
.Ali(Ali2),
.InstructionD13(InstructionD14)
);
ALU a (readdata1M2,Ali2, zero2,clkM2, InstructionD14, rd_value2,opr);
endmodule

module DATAM(PCM9,clkM9,outM9,writeaddrM9,writedataM9,AM9,BM9,CM9,DM9,EM9,FM9,
InstructionsM9,readdata1M9,readdata2M9,RegDestM9, JumpM9,BranchM9,w
riteM9,
MemtoRegM9,MemReadM9,MemWriteM9,InstructionDM9,
ALUSrcM9, RegWriteM9,RegCellDM9,
Ali9,zero9, rd_value9,read_data9,mems,opr1);
input [4:0] writeaddrM9;
input [31:0] writedataM9;
input [31:0] PCM9;
input clkM9,writeM9;
output wire [31:0] outM9;
output wire [31:0] readdata1M9,readdata2M9;
output wire RegDestM9;
output wire JumpM9;
output wire BranchM9;
output wire MemtoRegM9;
output wire MemWriteM9;
output wire MemReadM9;
output wire ALUSrcM9;
output wire RegWriteM9;
output wire[5:0] FM9;
output wire[25:0] DM9;

output wire[15:0] EM9;

output wire [4:0]AM9,BM9,CM9;
output wire [4:0] InstructionsM9;
output wire [31:0] RegCellDM9;
output wire [31:0] Ali9;
output wire [3:0] opr1;
output wire zero9 ;
output wire [31:0] rd_value9;
output wire[31:0] InstructionDM9;
output wire [31:0] read_data9,mems;

ALUM instance_name (
.PCM2(PCM9),
.clkM2(clkM9),
.outM2(outM9),
.writeaddrM2(writeaddrM9),
.writedataM2(writedataM9),
.AM2(AM9),
.BM2(BM9),
.CM2(CM9),
.DM2(DM9),
.opr(opr1),
.EM2(EM9),
.FM2(FM9),
.InstructionsM2(InstructionsM9),
.readdata1M2(readdata1M9),
.readdata2M2(readdata2M9),
.RegDestM2(RegDestM9),
.JumpM2(JumpM9),
.BranchM2(BranchM9),
.writeM2(writeM9),
.MemtoRegM2(MemtoRegM9),
.MemReadM2(MemReadM9),
.MemWriteM2(MemWriteM9),
.InstructionD14(InstructionDM9),
.ALUSrcM2(ALUSrcM9),
.RegWriteM2(RegWriteM9),
.RegCellDM2(RegCellDM9),
.Ali2(Ali9),
.zero2(zero9),
.rd_value2(rd_value9)
);
DM dm1 (rd_value9,readdata2M9,MemWriteM9,clkM9,rd_value9,read_data9,mems);
endmodule

module MUXMemtoreg(PCM91,clkM91,outM91,writeaddrM91,writedataM91,AM91,BM
91,CM91,DM91,EM91,FM91,
InstructionsM91,readdata1M91,readdata2M91,RegDestM91, JumpM91,Branc
hM91,writeM91,
MemtoRegM91,MemReadM91,MemWriteM91,InstructionD
M91,ALUSrcM91, RegWriteM91,RegCellDM91,
Ali91,zero91, rd_value91,read_data91,mems, pout
,opr2);

input [4:0] writeaddrM91;

input [31:0] writedataM91;
input [31:0] PCM91;
input clkM91,writeM91;
output wire [31:0] outM91;
output wire [31:0] readdata1M91,readdata2M91;
output wire RegDestM91;
output wire JumpM91;
output wire BranchM91;
output wire MemtoRegM91;
output wire MemWriteM91;
output wire MemReadM91;
output wire ALUSrcM91;
output wire RegWriteM91;
output wire[5:0] FM91;
output wire[25:0] DM91;
output wire[15:0] EM91;
output wire [4:0]AM91,BM91,CM91;
output wire [4:0] InstructionsM91;
output wire [31:0] RegCellDM91;
output wire [31:0] Ali91;
output wire [3:0] opr2;
output wire zero91 ;
output wire [31:0] rd_value91;
output wire[31:0] InstructionDM91;
output wire [31:0] read_data91,mems;
output wire [31:0] pout;
DATAM instance_name (
.PCM9(PCM91),
.clkM9(clkM91),
.outM9(outM91),
.writeaddrM9(writeaddrM91),
.writedataM9(writedataM91),
.opr1(opr2),
.AM9(AM91),
.BM9(BM91),
.CM9(CM91),
.DM9(DM91),
.EM9(EM91),
.FM9(FM91),
.InstructionsM9(InstructionsM91),
.readdata1M9(readdata1M91),
.readdata2M9(readdata2M91),
.RegDestM9(RegDestM91),
.JumpM9(JumpM91),
.BranchM9(BranchM91),
.writeM9(writeM91),
.MemtoRegM9(MemtoRegM91),
.MemReadM9(MemReadM91),
.MemWriteM9(MemWriteM91),
.InstructionDM9(InstructionDM91),
.ALUSrcM9(ALUSrcM91),
.RegWriteM9(RegWriteM91),
.RegCellDM9(RegCellDM91),
.Ali9(Ali91),
.zero9(zero91),
.rd_value9(rd_value91),
.read_data9(read_data91),

.mems(mems)
);
MuxM1 mtr (rd_value91,read_data91,MemtoRegM91,pout);
endmodule
module PCSEL(PCM92,clkM92,writeaddrM92,writedataM92, JumpM92,BranchM92,writeM92,
InstructionDM92,zero92, pout92, nextPC1,opr3);
input [4:0] writeaddrM92;
input [31:0] writedataM92;
input [31:0] PCM92;
input clkM92,writeM92;
output wire JumpM92;
output wire BranchM92;
output wire zero92 ;
output wire[31:0] InstructionDM92;
output wire [31:0] nextPC1;
output wire [31:0] pout92;
output wire [3:0] opr3;
MUXMemtoreg instance_name (
.PCM91(PCM92),
.clkM91(clkM92),
.writeaddrM91(writeaddrM92),
.writedataM91(writedataM92),
.JumpM91(JumpM92),
.BranchM91(BranchM92),
.writeM91(writeM92),
.InstructionDM91(InstructionDM92),
.zero91(zero92),
.opr2(opr3),
.pout(pout92)
);
PCSel1 pcs (PCM92,InstructionDM92,Zero92,BranchM92,clkM92, JumpM92, nextPC1);
endmodule

module PROCESOR(PCM92,clkM92,writeaddrM92,writedataM92, writeM92,

pout92, nextPC1,opr4);
input [4:0] writeaddrM92;
input [31:0] writedataM92;
input [31:0] PCM92;
input clkM92,writeM92;
output wire [31:0] nextPC1;
output wire [31:0] pout92;
output wire [3:0] opr4;
PCSEL instance_name (
.PCM92(PCM92),
.clkM92(clkM92),
.writeaddrM92(writeaddrM92),
.writedataM92(writedataM92),
.writeM92(writeM92),
.pout92(pout92),

.opr3(opr4),
.nextPC1(nextPC1)
);
endmodule