FDCC consists of a differential difference transconductor formed [1], by making

all transistor to be operate at saturation. The symbol of FDCC is constructed a

nd it consists of six terminals, Y1, Y2 are high impedance terminals, while X1 a
nd X2 are low impedance. The differential voltage Vyd applied across Y1 and Y2 t
erminals are conveyed to Z1 and Z2 terminals, that is, (Iz1=Ix1 and Iz2=Ix2). Th
e Z1 and z2 are high impedance nodes suitable of current outputs. The FDCC consi
sts of a differential difference formed from transistor M1 to M16, a current mir
ror formed from M17 to M21 and M37 to M39. Two class AB output stages[5] M22 to
M24. All these transistors operate in saturation mode. In this paper; the propos
ed FDCC structure is based on using differential difference operational floating
amplifier (DDOFA)[2] and a floating current source circuit . The DDOFA circuit
symbol is presented in Fig.1 (b). The DDOFA structure is divided into three sta
ges: the input stage, gain stage and output stage. Where Go is the open loop tra
nsconductance gain of the block. Using negative feedback techniques the two diff
erential difference voltages of the DDOFA are equated as follows V1 - V2 = V3
V4. The CMOS realization of FDCC is shown