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Design Methodology
February 2003, ver. 1.4
Introduction
f
Software
Support &
Licensing
Requirements
f
Design Flow
Altera Corporation
AN-226-1.4
For more information on using the Synplify software with Altera designs,
go to the Synplicity web site at http://www.synplicity.com.
This application note assumes that you have set up, licensed, and are
familiar with the Synplify or Synplify Pro software.
After obtaining and correctly setting up the license file, set the
LM_LICENSE_FILE environment variable to the location of the license
file to enable the software.
To obtain and license the Synplify software, see the Synplicity web site at
http://www.synplicity.com.
The basic steps in a Quartus II design flow using the Synplify software is:
1.
Create HDL design files within the Synplify software or a text editor.
2.
3.
4.
Figure 1 shows the recommended design flow when using the Synplify
and Quartus II software.
Figure 1. Recommended Design Flow
VHDL
Verilog HDL
Functional
simulation
Timing
contraints
RTL
simulation
Synplify
software
Post synthesis
simulation files
(.vhm / .vm )
Technology
specific netlist
(.vqm / .edf )
Forward annotated
timing constraints
( .tcl / .acf )
Gate-level
timing
simulation
Quartus II
software
Post place-and-route
simulation files
(.vho / .vo )
No
Timing
requirements
satisfied?
Yes
Configuration files
( .sof / .pof )
Configure device
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The Synplify and Synplify Pro software tools support both VHDL and
Verilog HDL source files. Synplify Pro also supports mixed synthesis,
allowing a combination of VHDL and Verilog HDL source files. After
synthesis, the Synplify and Synplify Pro software produces several
intermediate and output files. Table 1 lists these files with a short
description of each file.
Table 1. Synplify Intermediate & Output Files
File Extension(s)
File Description
.srs
.srm
.vm/.vhm
.srr (1)
.edf/.vqm (2)
.acf/.tcl (3)
Notes to Table 1:
(1)
(2)
(3)
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This report file includes performance estimates which are often based on pre-placeand-route information. Please use the fMAX reported by the Quartus II software
after place-and-route, as it is the only reliable source of timing information. This
report file includes post-synthesis device resource utilization statistics which may
inaccurately predict resource usage after place-and-route. The Synplify software
does not account for black-box functions nor for logic element (LE) usage reduction
achieved through register packing performed by the Quartus II software. Register
packing combines a single register and look-up table (LUT) into a single logic cell,
reducing the logic cell utilization below the Synplify software estimate. Use the
device utilization reported by the Quartus II software after place-and-route.
An EDIF output file (.edf) is only created for ACEXTM 1K, FLEXR 10K, FLEX 10KA,
FLEX 10KE, FLEX 6000, FLEX 8000, MAXR 7000, MAX 9000, and MAX 3000
devices. A Verilog Quartus Mapping (.vqm) file is created for all other Altera
device families.
An assignment and configuration file (.acf) file is only created for ACEX 1K,
FLEXR 10K, FLEX 10KA, FLEX 10KE, FLEX 6000, FLEX 8000, MAX 7000, MAX
9000, and MAX 3000 devices. The .acf is generated for backward compatibility with
the MAX+PLUSR II software. A tool command language (Tcl) file (.tcl) for the
Quartus II software is created for all devices, which also contains Tcl commands to
create a Quartus II project and, if applicable, the MAX+PLUS II assignments are
imported from the .acf file.
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Design
Planning
Before you begin a new VHDL or Verilog HDL design, you must first
determine your design methodology. For example, you should decide
whether you will use a top-down or hierarchical bottom-up methodology,
and whether you want to use a block-based design flow. For hierarchical
design flows, you should partition your design for the best performance
and easiest optimization. This section describes design planning
considerations, including:
Description
Advantages
One output netlist for the You can perform optimization across design boundaries and
entire design.
hierarchies for the entire design.
Simple to manage.
Bottom-up
(block-based)
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General
Synthesis
Design
Guidelines
Combinatorial Logic
Logic is combinatorial if outputs at a specified time are a function of the
inputs at that time only, regardless of the previous state of the circuit.
Examples of combinatorial logic functions include decoders, multiplexers,
and adders. When applied to combinatorial logic, the techniques
described in the following sections optimize the performance results
during Synplify synthesis.
Latches
Latches are used in digital logic to hold the value of a signal until a new
value is assigned. Altera devices are register-intensive; therefore
designing with latches uses more logic and leads to lower performance
than designing with registers. When designing combinatorial logic, avoid
creating a latch unintentionally due to the HDL design style. For example,
when CASE or IF statements do not cover all possible conditions of the
inputs, combinatorial feedback can generate latches to hold the output in
the case when a new output value is not assigned. When a latch is created,
Synplify issues warnings.
Omitting the final ELSE clause or WHEN OTHERS clause from an IF or
CASE statement can also generate a latch. Don't care assignments on the
default conditions tend to prevent latch generation. Figure 2 shows
sample VHDL code that prevents the unintentional creation of a latch. If
the final ELSE clause is omitted, an unintentional latch is generated as
shown in Figure 3. Figure 4 shows the schematic representation of the
VHDL code from Figure 2 that includes the final ELSE statement,
preventing the latch from being inferred.
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Latch
Q
oput
ENA
sel [1..0]
sel [1..0]
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Sequential Logic
Logic is sequential if the outputs at a specified time are a function of the
inputs at the time and at all preceding times. All sequential circuits must
include one or more registers (flip-flops).
Figure 5 shows sample VHDL code that prevents the unintentional
creation of feedback multiplexer. The final ELSE clause is used to assign
all states and avoid feedback. If the final ELSE clause is omitted, a
feedback multiplexer is generated, and the function requires an extra LE
in the Altera device.
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Gated Clocks
Try to avoid using internally-generated gated clocks because they create
logic delays and clock skew, and may require using additional routing
resources on Altera devices. Internally generated clocks may also
introduce glitches that create functional problems.
If you must use an internally generated clock, use the dedicated global,
regional, or fast pins that feed high-fan-out global routing lines.
To implement an internally generated gated clock in a design, you can
promote the clock signal to the global line through the Quartus II
Assignment Organizer by instantiating a GLOBAL primitive.
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For more information on the Finite State Machine (FSM) Compiler, refer
to the Synplify Optimization Strategies section.
Figure 6. Sample State Machine
32-Bit
Counter
(8-Bit)
4-to-1
Multiplexer
State Machine
Figure 7 shows an inefficient design style, because the counter and the
multiplexer are incorporated into the state machine description. As a
result, two counters may be inferred during synthesis instead of one
up/down counter. In addition, the multiplexer may have additional logic
associated with its control signals.
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Guidelines for
Altera
Megafunctions
& LPM
Functions
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Figure 9 shows the potential ways to use megafunctions in the AlteraSynplify design methodology. Instantiation and inference of specific
functions will be discussed in later sections.
Figure 9. Potential Ways to Use Megafunctions
Megafunctions
Inference
Instantiation
Using
MegaWizard
Plug-In
Directly
embedding
in HDL
When possible, if the black box does not have registered inputs and
outputs, use GRAY box timing to aid in the synthesis results when the
syn_tpd, syn_tsu, and syn_tco attributes are defined. If you do not
use these attributes, it may lead to inaccurate timing estimates during
synthesis. See Figure 10 for a Verilog HDL example.
Figure 10. Verilog HDL Example
module ram32x4(z,d,addr,we,clk);
/* synthesis syn_black_box syn_tco1=clk->z[3:0]=4.0
syn_tpd1=addr[3:0]->z[3:0]=8.0
syn_tsu1=addr[3:0]->clk=2.0
syn_tsu2=we->clk=3.0 */
output[3:0]z;
input[3:0]d;
input[3:0]addr;
input we
input clk
endmodule
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16
Description
Symbol for the megafunction used in the Quartus II
schematic editor
<output file>.inc
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Description
Sample AHDL instantiation of the sub design in the
megafunction wrapper file
Only generated when AHDL output is selected, which is not supported in the
Synplify software.
Only generated when VHDL output is selected.
Only generated when Verilog HDL output is selected.
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q => count
);
END top;
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Inferring
Megafunctions
from HDL Code
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Limitations
Inference
Most efficient use of the memory resource for a Coding style allows for portability
specific technology
Support for all RAM types
Timing/area estimation
No tool dependencies
Inferring RAM
Follow the guidelines below for the Synplify software to successfully infer
RAM in a design:
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These guidelines allow the compiler to extract the RAM and keep it at a
high level until it gets mapped to the technology specific resources. Each
Altera device family has different guidelines for ensuring that memory is
correctly mapped to device resources.
The Stratix, Stratix GX, and Cyclone device families have support for
advanced memory features. Because of the wide variety of functionality,
the process for inferring these memory features requires a more detailed
approach than for the other device families.
For the Stratix, Stratix GX, and Cyclone device families, the minimum
RAM size is 2-bits and the minimum address width is 1-bit.
1
RAM primitive
Stratix / Stratix GX /
Cyclone
FLEX 10KE /
ACEX 1K
ALTSYNCRAM
ALTDPRAM
ALTDPRAM
2-bits
64-bits
128-bits
1-bit
4-bits
5-bits
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When inferring RAM for any of the Altera device families listed above, the
Synplify software generates additional bypass logic. This logic is
generated to resolve a half-cycle read/write behavior difference between
the RTL and post-synthesis simulations. The RTL simulation shows the
memory updating on the positive edge of the clock, and the post-synthesis
simulation shows the memory updating on the negative edge. To
eliminate the bypass logic, the output of the RAM must be registered. By
adding this register, the output of the RAM is seen after a full clock cycle,
by which time the update has occurred thus eliminating the need for the
bypass logic.
Figure 14 shows sample VHDL code preventing bypass logic for inferring
dual-port RAM. The extra latency behavior stems from the inferencing
methodology and is not required when using the instantiation
methodology.
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Figure 14. VHDL Code for Inferred Dual-Port RAM Preventing Bypass Logic
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY dualport_ram IS
PORT ( data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wr_addr, rd_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
we : IN STD_LOGIC;
clk : IN STD_LOGIC);
END dualport_ram;
ARCHITECTURE ram_infer OF dualport_ram IS
TYPE Mem_Type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR (7
DOWNTO 0);
SIGNAL mem : Mem_Type;
SIGNAL addr_reg : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL tmp_out : STD_LOGIC_VECTOR(7 DOWNTO 0); --output
register
BEGIN
tmp_out <= mem (CONV_INTEGER(rd_addr));
PROCESS (clk, we, data_in) BEGIN
IF (clk=1 AND clkEVENT) THEN
IF (we=1) THEN
mem(CONV_INTEGER(wr_addr)) <= data_in;
END IF;
data_out <= tmp_out; --registers output
preventing
-- bypass logic generation.
END IF;
END PROCESS;
END ram_infer;
Inferring ROM
Follow the guidelines below for the Synplify software to successfully infer
ROM in a design:
The Synplify software infers ROMs from HDL source code that uses CASE
statements, or equivalent IF statements, to make 16 or more signal
assignments using constant values. These constants must all be the same
width. Figure 15 shows sample VHDL code that infers ROM.
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Figure 15. VHDL Code for Inferring ROM with a CASE Statement
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY rom IS
PORT (addr_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
attribute syn_romstyle : string;
attribute syn_romstyle of data_out : signal is "block_rom";
END rom;
ARCHITECTURE rom_infer OF rom IS
CONSTANT value_a : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
CONSTANT value_b : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT value_c : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT value_d : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT value_e : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
CONSTANT value_f : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";
CONSTANT value_g : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT value_h : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1110";
CONSTANT value_i : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";
CONSTANT value_j : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";
CONSTANT value_k : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT value_l : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
CONSTANT value_m : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";
CONSTANT value_n : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT value_o : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT value_p : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
BEGIN
PROCESS (addr_in)
BEGIN
CASE addr_in IS
WHEN "0000" => data_out <= value_a;
WHEN "0001" => data_out <= value_b;
WHEN "0010" => data_out <= value_c;
WHEN "0011" => data_out <= value_d;
WHEN "0100" => data_out <= value_e;
WHEN "0101" => data_out <= value_f;
WHEN "0110" => data_out <= value_g;
WHEN "0111" => data_out <= value_h;
WHEN "1000" => data_out <= value_i;
WHEN "1001" => data_out <= value_j;
WHEN "1010" => data_out <= value_k;
WHEN "1011" => data_out <= value_l;
WHEN "1100" => data_out <= value_m;
WHEN "1101" => data_out <= value_n;
WHEN "1110" => data_out <= value_o;
WHEN "1111" => data_out <= value_p;
WHEN others => data_out <= "----";
END CASE;
END PROCESS;
END rom_infer;
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Synplify
Optimization
Strategies
Timing-driven Synthesis
The Synplify software supports timing-driven synthesis through userassigned timing constraints to optimize the performance of the design.
The Synplify software optimizes the design to attempt to meet these
constraints. Actual timing results are only obtained after the design has
gone through full place-and-route in the Quartus II software. Using the
NativeLinkR feature, timing constraints, such as clock frequencies, multicycle paths, and false paths, applied in the Synplify software are forwardannotated to the Quartus II software for timing-driven place-and-route.
Clock Frequencies
Use the SCOPE editor to set global frequency requirements for the entire
design and individual clock settings. Use the Clocks tab in the SCOPE
editor to specify frequency (or period), rise times, fall times, duty cycle,
and other settings. Assigning individual clock settings, rather than overconstraining the global frequency, helps the Quartus II and Synplify
software achieve the fastest clock frequency for the overall design. The
define_clock attribute assigns clock constraints.
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Input/Output Delays
Specify the input and output delays for the ports of a design in the
Input/Output tab of the SCOPE editor or by using the
define_input_delay and define_output_delay attributes. The
Synplify software does not allow you to assign the TCO and TSU values
directly to inputs and outputs. However, a TCO value can be inferred by
setting an external output delay, and a TSU value can be inferred by
setting an external input delay. The following equations illustrate the
relationship between TCO/TSU and the input/output delays:
TCO = Clock period external output delay
TSU = Clock period external input delay
When the syn_forward_io_constraints attribute is set to 1, the
Synplify software passes the external input and output delays to the
Quartus II software through NativeLink integration. The Quartus II
software then uses the external delays to calculate the maximum system
frequency.
Multi-Cycle Paths
Specify any multi-cycle paths in the design in the Multi-Cycle Paths tab
of the SCOPE editor or with the define_multicycle_path attribute. A
multi-cycle path is one that requires more than one clock cycle to
propagate. It is important to specify which paths are multi-cycle to avoid
having the Quartus II and Synplify compilers work excessively on a noncritical path. Not specifying these paths can also result in an inaccurate
critical path being reported during timing analysis.
False Paths
False paths are paths that should not be considered during timing analysis
and/or which should be assigned low (or no) priority during
optimization. Some examples of false paths are slow asynchronous resets
and test logic added to the design. Set these paths in the False Paths tab of
the SCOPE editor or with the define_false_path attribute.
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Description
Sequential
Generates state machines with the fewest possible flip-flops. Sequential, also called binary, state
machines are useful for area-critical designs when timing is not as much of a concern.
Gray
Generates state machines where only one flip-flop changes during each transition. Gray-encoded
state machines tend to be glitchless.
One-hot
Generates state machines containing one flip-flop for each state. One-hot state machines provide
the best performance and shortest clock-to-output delays. However, one-hot implementations are
usually larger than binary implementations.
Safe
Generate extra control logic to force the state machine to the reset state if an invalid state is
reached. The safe value can be used in conjunction with the other three values, which results in
the state machine being implemented with the requested encoding scheme and the generation of
the reset logic.
The default is to optimize state machine logic for speed and area, but this
is potentially undesirable for critical systems. The safe value generates
extra control logic to force the state machine to the reset state if an invalid
state is reached.
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Perform Cliquing
You can only turn on cliquing when the Map Logic to LCELLs option is
turned on. This setting allows the Synplify software to group nodes
together for critical paths. These groups are called cliques. The Synplify
software creates a LogicLock region for the critical paths. Through
NativeLink integration, all LogicLock assignments are passed to the
Quartus II software.
Max Fan-out
When dealing with critical path nets with high fan-outs, you can use the
syn_maxfan attribute to control the fan-out of the net. Setting this
attribute for a specific net results in the replication of the driver of the net
to reduce the overall fan-out. The syn_maxfan attribute takes an integer
value and applies to inputs or registers. (The syn_maxfan attribute
cannot be used to duplicate control signals, and the minimum-allowed
value of the attribute is 4.) Using this attribute may result in increased
logic resource utilization, thus putting a strain on routing resources and
leading to long compile times and difficult fitting.
If you need to duplicate an output register or output enable register, you
can create a register for each output pin by using the syn_useioff
attribute (see Register Packing on page 30).
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Preserving Nets
During synthesis, the compiler maintains ports, registers, and instantiated
components. However, some nets may not be maintained in order to
create an optimized circuit. Applying the syn_keep directive overrides
the optimization of the compiler and preserves the net during synthesis.
The syn_keep directive takes a Boolean value and can be applied to
wires (Verilog HDL) and signals (VHDL). Setting the value to true
preserves the net through synthesis.
Register Packing
Altera devices allow for the packing of registers into I/O cells. Altera
recommends allowing the Quartus II software to make the I/O register
assignments. However, it is possible to control register packing with the
syn_useioff attribute. The syn_useioff attribute takes a Boolean
value and can be applied to ports or entire modules. Setting the value to
1 instructs the compiler to pack the register into an I/O cell. Setting the
value to 0 prevents register packing in both the Synplify and Quartus II
software.
Preserving Hierarchy
The Synplify software performs cross-boundary optimization by default.
This results in the flattening of the design to allow optimization. Use the
syn_hier attribute to over-ride the default compiler settings. The
syn_hier attribute takes a string value and can be applied to
modules/architectures. Setting the value to hard maintains the
boundaries of a module/architecture and prevent cross-boundary
optimization.
By default, the Synplify software generates a hierarchical .vqm. To flatten
the file, set the syn_netlist_hierarchy attribute equal to 0.
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Figure 18 shows VHDL code for making location assignments for Stratix,
Cyclone, APEX 20K, APEX 20KE, APEX 20KC, APEX II, Mercury, and
Excalibur devices. The pin location assignments for these devices are
written to the output Tcl script.
Figure 18. altera_chip_pin_lc with VHDL for APEX 20K, APEX 20KE,
APEX 20KC, APEX II, Mercury, Excalibur, Stratix, and Cyclone Devices
(1)
Note
The @ is used to specify pin locations. For these devices the pin
location assignments are written to the output EDIF.
Figure 19. altera_chip_pin_lc with VHDL for ACEX 1K and FLEX 10KE Devices
ENTITY sample (data_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
ATTRIBUTE altera_chip_pin_lc : STRING;
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Exporting
Designs to the
Quartus II
Software Using
NativeLink
Integration
After a design is synthesized in the Synplify software, a .vqm (or .edf) file
and Tcl files are used to import the design into the Quartus II software for
place-and-route. You can run the Quartus II software from within the
Synplify software or as a standalone application. Once you have imported
the design into the Quartus II software, you can specify different options
to further optimize the design.
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1.
2.
Turn on one of the following options from the Options menu in the
Synplify software:
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a.
Set Options: Opens the Quartus II software GUI and places the
synthesized output file, forward-annotated timing constraints,
and pin assignments in a named Quartus II project. You can
then configure options for the project.
b.
Run Foreground Compile: Allows for interactive place-androute. The Quartus II software GUI is opened and automatically
runs the place-and-route with the project settings from the
synthesis run. You can monitor the progress, observe all
messages generated, and execute other Quartus II software
commands.
c.
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To open the Tcl Console, select Utility Windows > Tcl Console
(View menu) in the Quartus II software.
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2.
2.
Conclusion
Revision
History
Version 1.4
The following changes were made to the AN 226: Synplify & Quartus II
Design Methodology version 1.4:
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Version 1.3
The following changes were made to the AN 226: Synplify & Quartus II
Design Methodology version 1.3:
Version 1.2
The following changes were made to the AN 226: Synplify & Quartus II
Design Methodology version 1.2:
Version 1.1
The following changes were made to the AN 226: Synplify & Quartus II
Design Methodology version 1.1:
Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the
stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their
respective holders. Synplify, Synplify Pro, and HDL Analyst are registered trademarks of Synplicity. Altera
products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights,
and copyrights. Altera warrants performance of its semiconductor products to current specifications in
accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera Corporation. Altera
customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services.
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