CS221:DigitalDesign

Counter & Registers

Counter&Registers

Dr.A.Sahu
Dept of Comp. Sc. & Engg.
DeptofComp.Sc.&Engg.
IndianInstituteofTechnologyGuwahati

Out e
Outline
Counter:SynchronousVsAsynchronous
Counter:FiniteStateMachine
C
t Fi it St t M hi
AregisterandCombinationallogic

Counter&FSMController:
UsingJKFFs,RSFFandTFFs

Up/DownCounter,Clear,LoadCounter
Registers
Preset/Clear,Load,Left/RightShift
CounterBasedonShiftRegisters
C
t B d
Shift R i t

BinaryCounter:Asynchronous
Q0
1

T Q

CLK

Q1

RisingEdge

T Q

Q2
1

T Q

Q3
T Q

FallingEdge

CLK
Q0

Q1

Q2

Q3

Counter:SyncVsAsync
AsynchronousCounter:RippleCounter
ChangeinStateofQi1 isusedtoToggleQi
ClockisappliedatFF0,itpropagatethroughtoFFn
InputClocktoFF1=SkewedversionofClk ofFF0
Clock+PropagationdelayofFF

Rippling:Overalltimedelayofoccurrenceofcount
pulse and when stabilized count appear at O/P
pulseandwhenstabilizedcountappearatO/P
Whencounter:1111..11to0000..00,togglesignal
must propagate through all FFs
mustpropagatethroughallFFs
Wrost caseSettlingtime:nxtpd
where tpd =PropagationdelayofaFF
wheret
=Propagation delay of a FF

SynchronousCounter:OnesingleclocktoallFF

BinaryCounter:Synchronous
Q0
1

Q1
1

Q2
1

Q3
1

CLK

Q0=1
=>10

Q1Q0=11
=>100

Q2Q1Q0
111=>1000

Counter

Exampleof4bitcounter
Countfrom0000to1111andrepeat
Upcounter:0000to1111
p
Downcounter:1111to0000
Mod N counter:
ModNcounter:
Mod10counter:0000to1001(0to9)and
repeat
Mod6counter:000to101(0to5)andrepeat

FSMofCounter:2bit
b
b
Statebits=Outputbits
A
00

Combinational
logic

B
01

C
10

n0
clk

s1
s0
State register

I/P
/

s1
s0
n1

D
11

A
B
C
B

O/P
/

s1

s0

n0 n1

0
0
1
1

0
1
0
1

0
1
1
0

1
0
1
0

FSMController:BinaryCounter
A
00

B
01

C
10

D
11

n1 = s1 xor s0
n0 = s0

I/P
A
B
C
B

s1

O/P

s1

s0

n0 n1

0
0
1
1

0
1
0
1

0
1
1
0

1
0
1
0

s0

s1
clk

s0
State register

n0

n1

Synchronous Counter : Design

SynchronousCounter:Design
Together:CreateFSM,EncodeBit
StateTable
DesignCombinationCircuit
Design Combination Circuit

Mod 10 Counter: BCD Counter

Mod10Counter:BCDCounter
Countfrom0000to1001(09theReset)
FSMwithEncodingdone
A
0000

B
0001

C
0010

D
0011

E
0100

J
1001

I
1000

H
0111

G
0110

F
0101

State
Table Creation
StateTableCreation
S3
0
0
0
0
0
0
0
0
1
1

PresentState
S2 S1 S0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1

NextState
N3 N2 N1 N0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
0
0
0
0

N0=S0
N0
S0
N1=
N3=
N4=

Using other FF in Counter

UsingotherFFinCounter
Takes
TakesbenefitofdualinputstoFF
benefit of dual inputs to FF
CountercanbeimplementedusingSmall
Combinational Circuit
CombinationalCircuit
MoreInputsfromCombinationalCircuit
UseofExcitationTable
HowFFoutchangesfromonetoothers
RequiredFFinputstochangeFFoutput
0to0,0to1,1to0and1to1

DesignofCounter:WithFFs
0,2,3,4,5,1,0
A
000

B
010

C
011

J
001

I
101

H
110

CounterdesignusingJKFF
s2
s1
s0

Combinational
logic
s2 s1
s0
State register

clk

Q1

n0

Q2

Q
Q

FF1
J C K

n1 n2

Q3
Q
Q

FF2
J C K

Q
Q

FF3
J C K
CLK

LogicNetwork

4TypesofFlipFlops
S
0
0
1
1

R
0
1
0
1
D
0
1

Q+
Qt
0
1
U
Q+
0
1

J
0
0
1
1

K
0
1
0
1
T
0
1

Q+
Qt
0
1
Qt
Qt
Q+
Qt
Qt

Characteristic Equations
CharacteristicEquations
A
Adescriptionsofthenextstatetable
descriptions of the next state table
ofaflipflop
ConstructingfromtheKarnaugh map
for Qt+1 intermsofthepresentstate
forQ
in terms of the present state
andinput

Characteristictables

The tables that weve made so far are called

characteristic tables.
They show the next state Q(t+1) in terms of the current
state Q(t) and the inputs.
For simplicity, the control input C is not usually listed.
Again, these tables dont indicate the positive edgetriggered behavior of the flip-flops that well be using.
J

Q+

Qt

Qt

D
0
1

Q+
0
1

T
0
1

Q+
Qt
Qt

Characteristicequations
Wecanalsowritecharacteristicequations,
where the next state Q(t+1) is defined in terms
wherethenextstateQ(t+1)isdefinedinterms
ofthecurrentstateQ(t)andinputs.
J

Q+

Qt

Qt

Q+=KQ+JQ
Q(t+1)=K
Q(t+1)
KQ(t)
Q(t)+JQ
+ JQ(t)
(t)

Characteristicequations
Wecanalsowritecharacteristicequations,
wherethenextstateQ(t+1)isdefinedinterms
h
h
Q( 1) i d fi d i
ofthecurrentstateQ(t)andinputs.
D
0
1

Q+
0
1

T
0
1

Q+
Qt
Qt

Q+=D
Q(t+1)=D
Q+=TQ+TQ=T Q
Q(t+1)=TQ(t)+TQ(t)
=T Q(t)

Characteristic equations
SR

Q+=S+RQ(SR=0)

FlipFlop Characteristic
Type
Equation
SR
Q+= S+RQ(SR=0)
JK

Q+=JQ
= JQ+KQ
+K Q

Q+=D

Q+=TQ+TQ=TQ

Excitation Table for JK Flip Flop

ExcitationTableforJKFlipFlop
ItisdifferentthanCharacteristicEquation
It is different than Characteristic Equation
TablingrequiresInputtochangefromQtoQ+
J

Q+

Qt

Qt

CharacteristicTable

Q
0
0
1
1

Q+
0
1
0
1

J
0
1
X
X

K
X
X
1
0

ExcitationTable

Excitation Table for T Flip Flop

ExcitationTableforTFlipFlop
ItisdifferentthanCharacteristicEquation
It is different than Characteristic Equation
TablingrequiresInputtochangefromQtoQ+
T

Q+

Qt

Qt

CharacteristicTable

Q
0
0
1
1

Q+
0
1
0
1

T
0
1
1
0

ExcitationTable

Excitation Table for D Flip Flop

ExcitationTableforDFlipFlop
ItisdifferentthanCharacteristicEquation
It is different than Characteristic Equation
TablingrequiresInputtochangefromQtoQ+
D

Q+

CharacteristicTable

Q
0
0
1
1

Q+
0
1
0
1

D
0
1
0
1

ExcitationTable

Excitation Table for SR Flip Flop

ExcitationTableforSRFlipFlop
ItisdifferentthanCharacteristicEquation
It is different than Characteristic Equation
TablingrequiresInputtochangefromQtoQ+
S

Q+

Qt

CharacteristicTable

Q
0
0
1
1

Q+
0
1
0
1

S
0
1
0
X

R
X
0
1
0

ExcitationTable

ExcitationTable:SyncCounterUsingJKFF
A
000
J
001

B
010
I
101

PresentState

C
011
H
110

NextState

Q3 Q1+ Q2+ Q3+

Q1

Q2

1
0

Q+

Flip
p FlopInputs
p p
J1

K1

J2

K2

J3

K3

FFInputFunctions
PresentState

Flip FlopInputs

Q1

Q2

Q3

J1

K1

J2

K2

J3

K3

J1=F(Q1,Q2,Q3)

J2=F(Q1,Q2,Q3)

K1=F(Q1,Q2,Q3) K2=F(Q1,Q2,Q3)

J3=F(Q1,Q2,Q3)
K3=F(Q1,Q2,Q3)

SolveEachFunctionUsingKMAP
PresentState

Flip FlopInputs

Q1

Q2

Q3

J1

K1

J2

K2

J3

K3

Q2Q3
Q1 0 0 1

Q1

J1=Q2Q3

J2=Q3

J3=Q2

K1=Q2

K2=Q1

K3=Q1

0
X

CounterLogicDiagram
Q1

Q2

Q3

FF1
J C K

FF2
J C K

FF3
J C K

CLK

L i N t
LogicNetwork
k
Q1
Q

Q2
Q

FF1
J C K

J1 Q2Q3
J1=
Q2Q3
K1=Q2
J2=Q3
K2=Q1
J3=Q2
K3 Q1
K3=Q1

Q3
Q

FF2
J C K

FF3
J C K

CLK

ExcitationTable:SyncCounterUsingDFF
A
000
J
001

B
010
I
101

PresentState

C
011
H
110
NextState

Q2

Q3

1
0

Q+

Flip
p FlopInputs
p p

Q1+ Q2+ Q3+

Q1

D1

D2

D3

ExcitationTable:SyncCounterUsingDFF
A
000
J
001

B
010
I
101

PresentState

C
011
H
110

Q+

Flip
p FlopInputs
p p

Q1

Q2

Q3

D1

D2

D3

D1=Q1Q2+Q2Q3
D2=Q1Q2+Q2Q3
D3=Q1+Q2Q3

CounterImplementationusingDFF
D1=Q1Q2+Q2Q3
Q1

Q
FF1
D C

D2=Q1Q2+Q2Q3

Q2

Q
Q

Q
FF2
D C

Q3

Q
Q

D3=Q1+Q2Q3
Sameas
FSM
Controller

Q
Q

FF3
D C
CLK

Require
Require
moreLogic
asJKFF
Based
Based

ExcitationTable:SyncCounterUsingTFF
A
000
J
001

B
010
I
101

PresentState

C
011
H
110
NextState

Q2

Q3

1
0

Q+

Flip
p FlopInputs
p p

Q1+ Q2+ Q3+

Q1

T1

T2

T3

ExcitationTable:SyncCounterUsingDFF
A
000
J
001

B
010
I
101

PresentState

C
011
H
110

Q+

Flip
p FlopInputs
p p

Q1

Q2

Q3

T1

T2

T3

T1=Q1Q2+Q2Q3
T2=Q1Q2+Q2Q3
T3=Q1+Q1Q3

CounterImplementationusingDFF
Q1

Q
FF1
T C

Q2

Q
FF2
T C

Q3

T1=Q1Q2+Q2Q3
T2=Q1Q2+Q2Q3
T3=Q1+Q1Q3

FF3
T C
CLK

Still
Require
moreLogic
asJKFF
Based

ExcitationTable:SyncCounterUsingRSFF
A
000
J
001

B
010
I
101

PresentState

C
011
H
110

NextState

Q3 Q1+ Q2+ Q3+

Q1

Q2

1
0

Q+

Flip
p FlopInputs
p p
S1

R1

S2

R2

S3

R3

FFInputFunctions
PresentState

Flip FlopInputs

Q1

Q2

Q3

S1

R1

S2

R2

S3

R3

S1=F(Q1,Q2,Q3)

S2=F(Q1,Q2,Q3)

S3=F(Q1,Q2,Q3)

R1=F(Q1,Q2,Q3) R2=F(Q1,Q2,Q3)

R3=F(Q1,Q2,Q3)

SolveEachFunctionUsingKMAP
PresentState

Flip FlopInputs

Q1

Q2

Q3

R1

S1

S2

R2

S3

R3

Q2Q3
Q1 0 0 1

Q1

S1=Q2Q3

S2=Q1Q3

S3=Q2Q3

R1=Q2

R2=Q1

R3=Q1Q3

0
X

CounterLogicDiagram

Q1
Q

Q2
Q

FF1
S C R

Q3
Q

FF2
S C R

FF3
S C R

S1=Q2Q3
R1=Q2
S2=Q
= Q1Q3
R2=Q1
S3=Q
= Q2Q3
R3=Q1Q3
CLK

Thanks