REFERENCES

[1]

D. Sinha, N. Shenoy, and H. Zhou, ``Statistical gate sizing for timing yield
optimization,'' in Proc. IEEE/ACM ICCAD, Nov. 2014,pp. 1037_1041.

[2]

A. Davoodi and A. Srivastava, ``Variability driven gate sizing for binningyield

optimization,'' IEEE Trans. Very Large Scale Integr. (VLSI) Syst.vol. 16, no. 6,
pp. 683_692, Jun. 2008.

[3]

A. Singhee, C. Fang, J. Ma, and R. Rutenbar, ``Probabilistic interval-valued

computation: Toward a practical surrogate for statistics inside cad tools,''inProc.
43rd Annu. DAC, 2006, pp. 167_172.

[4]

V. Khandelwal and A. Srivastava, ``Monte-Carlo driven stochastic optimization

framework for handling fabrication variability,'' in Proc.IEEE/ACM ICCAD,
Nov. 2007, pp. 105_110.

[5]

Z. Li, C. Alpert, S. Hu, T. Muhmud, S. Quay, and P. Villarrubia, ``Fast

interconnect synthesis with layer assignment,'' in Proc. ISPD, 2008,pp. 71_77.

[6]

C.Alpert et al., ``Techniques for fast physical synthesis,'' Proc. IEEE, vol. 95, no.
3, pp. 573_599, Mar. 2007.

[7]

R. M. D. Wu, J. Hu, and M. Zhao, ``Layer assignment for crosstalk risk

minimization,'' in Proc. ASP-DAC, 2004, pp. 159_162.

[8]

G. Xu, L.-D. Huang, D. Z. Pan, and M. D. F. Wong, ``Redundant-via enhanced

maze routing for yield improvement,'' in Proc. ASP-DAC, 2005,pp. 1148_1151.

[9]

C. Buragohain, D. Agrawal, and S. Suri. Distributed navigation algorithms for

sensor networks. In IEEE INFOCOM, 2006.