Lob Report: EEE 454 Department of FEE BueT Lab Report: EEE 454 VLSLIL Group No:07 Lab No: 02 LAB TITLE: Layout Design of a2 input NAND Gate Prepared by: Student Name: MD. AYAZ MASUD Student ID: 0906021 Name(s) of Group Member: TAHMID SAMI RAHMAN Student ID of Group Member: 0906016 Date of Experiment: 7/3/2015 Date of Report: 14/3/2015Lob Report: EEE 454 Department of FEE BueT ABSTRACT In this experiment, we have created a layout view of the basie two input NAND gate from scratch. We have also checked for DRS errors in this layout and removed every error that incurred KEYWORDS 1. Cadence 2. Layout 3. NAND 4, CMOS 5. VirtuosoLob Report: EEE 454 Department of FEE BueT TABLE OF CONTENTS Abstract, 2 Keywords, 2 Table of Contents, 3 List of Tables 4 List of Illustrations, 4 Introduction. 5 Theory 5 Lab Handout Questions 6 Tools Used. 7 Procedures 8 Results 9 Conclusions. 10 References, nLob Report: EEE 454 Department of FEE BueT of Tables: Table 1: Design Rules for NMOS and PMOS, Page & List of IMlustrations: Figure | : NAND Gate Page $ Figure 2: NAND Gate Truth Table Page 5 Figure 3: 2 input NAND Gate Page $ Figure 4: Errors Generated in Layout Design After Running DRC Page 7 Figure 5: 'No DRC Error Notification Page 7 Figure 6: NMOS in series Page 9 Figure 7 : PMOS in parallel Page 9 Figure 8: Zoomed View of the NAND Gate Page 9 Figure 9: Overall View of 2 Input NAND Gate. Page 10Lob Report: EEE 454 Department of FEE BueT Introduction: Design of any gate in layout level requires extraordinary care and abidance of design rules. In this experiment we have designed a simple 2 input NAND gate in layout considering all the design rules in Virtuoso. Theory In digital electronics a NAND gate is one that gives a LOW(0) output only if both the inputs are HIGH(|). It is basically an AND gate followed by an inverter and has extensive use in logic design as it is one of the universal gates. Here is the schematic representation and the truth table for NAND gate. A out B r[o|s a{alo Figure 1 : NAND Gate Jit Figure 2: NAND Gate Truth Table Like any other gate this gate can be fabricated in CMOS technology. As it has two inputs it is evident that it will need two pairs of NMOS and PMOS, The circuit level diagram of a2 input NAND gate in CMOS technology is given below and its operations explained as well. Figure 3: 2 input NAND GateLob Report: EEE 454 Department of FEE BueT Ifboth of the A and B inputs are high, then both the NMOS transistors will be ON, neither of the PMOS transistors will conduct, and a conductive path will be established between the output and ground, bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and Vpn (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vpo, bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a NAND logic gate Lab Handout Questions: 1, Show the print out of the layout, Measure its size. Could you achieve minimum sized layout? 2. What types of error did you received? What are the meanings of the error? Answers: 1. The print of the layout is attached in the Results section (Figure-), Overall design had a size of 87um X 99 ym. If we only consider the P-substrate part of the design then it measured 3.3m X 5.6m It was possible to design a more compact layout by smarter placement of components, But as it was our first attempt in layout design we put more effort in abidance of the design rules rather than the compactness of the design,Lob Report: EEE 454 Department of FEE BueT 2, ‘There were several errors in our frst attempt, All of them generated due to minor violations of design rules. | i | nnn | Figure 4: Errors Generated in Layout Design After Running DRC Keeping a minimum distance between two adjacent component was the most vital rule and ‘was violated in numerous occasions. We discovered some new rules that were not in the lab handout. For example, a maximum 0,3 ym distance between two adjacent Metal 1 to Metal 2 Via is compulsory. After learning about all these errors a quick check in the design produced a completely errorless layout design, Figure 5 :'No DRC Error’ Notification Tools Used: © Virtuoso © CadenceLob Report: EEE 454 Department of FEE BueT Procedure: In our NAND gate we have 2 PMOS transistors in parallel and 2 NMOS transistors in series. We designed our layout keeping this in mind. At first we designed the NMOS and then the PMOS The NMOS consists of Oxide, Nimp, Cont and Poly layers. We drew a contact at first then provided metal layer around it, Once it was done, a polysilicon layer was chosen and we drew the Poly gate layer. The Oxide layer was drawn surrounding the contact, Finally a rectangular \Nimp layer was provided all around. The design rules are listed below together with the design rules of PMOS. The PMOS consists of Oxide, Poly, Pimp, Cont and Nwell layers. It is exactly similar to the NMOS design except here we used Pimp in stead of Nimp and later we designed a N-well around the Pimp. We confined our space within a constant height so that other circuit elements can be added without disturbing ours. It was done by placing two Metal2 rectangles at a distance of 5 mm. They also provided as our Von and GND bus ‘Next we provided the Metall pins for Input and Output and connected wires from the transistor metal contact to Metal2 using via. We also provided bias for P-substrate and N-well by providing Pimp and Nimp layer with oxide and contact, The design rules that we followed throughout the design are listed below. NMOS PMOS: Contact size: 0.12 umX 0.12 um (Fixed) Minimum Nwell width: 0.6 um Poly width Minimum: 0.1 um (Fixed MOS Minimum Nwell spacing to Nwell (same gate length) potential): 0.6 um Contact to Poly spacing (Minimum): 0.1 Minimum Nwell spacing to Nwell um (different potential): 1.2 um Contact to Oxi de spacing (Minimum): 0.06 Minimum Nwell spacing to N+ active um area: 0.3 um Poly extending to Oxi de (Minimum): 0.18 Minimum Nwell spacing to P+ active um 3um imum Nwell enclosure to P+ active 2 0.12 um Nimp (Pimp as well) over lapping Oxide (Minimum): 0.18 um ‘Minimum Metal 1 width: 0.12 um Minimum Nwell enclousere to N+ active ‘Maximum Metal 1 width: 12.0 um area: 0.12 um Minimum Metal 1 to Contact enclosure: Minimum N+ Active Area to P+ Active 0.06 um Area Spacing: 0.15 um Poly to Poly spacing (Minimum): 0.12 um ‘Table 1: Design Rules for NMOS and PMOSLob Report: EEE 454 Department of FEE BueT Resu Inthis experiment we were not asked to take any data, Rather we designed the layout and checked for errors, Here are the figures from our design Figure 6: NMOS in series Figure 7 : PMOS in parallel A zoomed view of the gate is given below Figure 8: Zoomed View of the NAND GateLob Report: EEE 454 Department of FEE BueT ‘And this the final overall view of the 2-input NAND gate Figure 9: Overall View of 2 Input NAND Gate. Conclusion: In this experiment we have had our first experience of layout design. We designed it for a very simple logic gate like NAND gate, but this has laid the foundation for more complex designs in the future. Although error analysis was out of the scope of this experiment we checked for DRC error in order to answer the questions in the lab handout. As we strictly adhered to the design rules we produced no major error and all minor errors were successfully resolved. 10Lob Report: EEE 454 Department of FEE BueT Reference: 1. Douglas A. Pucknell , Kamran Eshraghian, Basic VLSI Design 3rd edition, Chapter 6 Section 3, Subsection 2. 2, Neil H.E. Weste, David Money Harris, CMOS VLSI Design, 4th edition, Chapter 3, Section 3, Subsection 3. 3. Creating Full custom Layouts using Cadence’ Virtuoso Layout Editor {http://www.bioee.ee.columbia.edu/courses/cad/htmi/layout. html) uLob Report: EEE 454 Department of FEE BueT R