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A

KSWAA/KTWAA
Liverpool 10M/10MG
Sunderland 10M/10MG

LA-4982P REV 1.0 Schematic


Intel Penryn/ Cantiga/ ICH9M
2009-07-27 Rev. 1.0

www.masteram.su

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
E

of

45

Compal Confidential
Fan Control

Model Name : KSWAA/KTWAA


File Name : LA-4981P

APL5607

uPGA-478 Package
(Socket P) page

page 4

CRT
page 17
VGA MXM/B
ATI M92XT,64bit with 128M/256MB
ATI M96,128bit with 256M/512MB

EC
SMBUS

HDMI CEC Controller


R5F211A4SP

PCIE-Express 16X

GM45/PM45/GL40
GM47/GM49
uFCBGA-1329

page 18

HDMI Conn.

Level Shifter

page 20

page 20

Intel Cantiga

page 20

H_D#(0..63)

Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2


Dual Channel

1.5V DDR3 800/1066

USB/B

FP/B

USB port 0,1

USB port 8

page 25

PCIeMini Card
WLAN

C-Link

USB

Express Card

Int. Camera

USB port 5

USB port 11

1.5V 2.5GHz(250MB/s)

SATA port 1

Intel ICH9-M

5V 1.5GHz(150MB/s)

page 25

1.5V 2.5GHz(250MB/s)

SATA port 4
5V 1.5GHz(150MB/s)

PCIe 1x

page 28

5V 1.5GHz(150MB/s)

page 32

page 21,22,23,24

Power/B

page 26

page 25

eSATA

USB

page 25

USB port 3
page 25

page 31

HD Audio

3.3V/1.5V 24.576MHz/48Mhz

HDA Codec

MDC 1.5 Conn


Debug Port

page 21

3V 33MHz

ENE KB926 D2

page 34

page 26

page 33

AMP.

ALC272

TPA6017

page 29

page 30

DC/DC Interface CKT.


page 35

Touch Pad

ODD/B for 17"

page 25

5V 480MHz

RTC CKT.
page 25

SATA ODD

USB port 3

PCI

LPC BUS

USB/B

page 25

SATA port 5

5V 480MHz

PCMCIA
OZ601

SATA HDD0

BGA-676

USB

RTS5159E 3IN1
USB port 10

1.5V 2.5GHz(250MB/s)

3.3V 33 MHz

PCIe port 3

page 18

PCIe 1x

RTL8103EL 10/100M

page 28

page 26

5V 480MHz

PCIe 1x [2,4,5]

5V 480MHz

Express Card

BT conn
USB

USB

USB port 4

page 26
2

DMI x 4
5V 480MHz

PCIe port 4
page 27

RJ45

page 14,15

BANK 0, 1, 2, 3

page 7,8,9,10,11,12,13

USB port 7
page 27

PCIe port 1

page 16

4,5,6

PCIeMini Card
WiMax
2

SLG8SP556VTR

page 4

667/800/1066MHz

LCD Conn.

Clock Generator

EMC1402-1

FSB

H_A#(3..35)

page 19

Thermal Sensor

Intel Penryn Processor

page 26

Int.KBD

SPI ROM

page 34

Int.
MIC CONN
page 30

page 33

Power Circuit DC/DC

MIC CONN
page 30

HP CONN
page 30

SPK CONN
page 30
4

page 36,37,38,39
40,41,42

FP/B for 17"

page 25

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
E

of

45

Voltage Rails

SIGNAL

STATE

Power Plane

Description

S1

S3

S5

G3

VIN

Adapter power supply (19V)

ON

ON

ON

OFF

B+

AC or battery power rail for power circuit.

ON

ON

ON

ON

SLP_S1# SLP_S3# SLP_S4# SLP_S5#


HIGH

HIGH

HIGH

HIGH

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

S5 (Soft OFF)

LOW

LOW

LOW

LOW

G3

LOW

LOW

LOW

LOW

Full ON

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

OFF

+0.75VS

0.75V switched power rail for DDR terminator

ON

OFF

OFF

OFF

+1.05VS

1.05V switched power rail

ON

OFF

OFF

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

OFF

+1.8V

1.8V power rail for DDR

ON

ON

OFF

OFF

+1.8VS

1.8V power rail for VRAM

ON

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON

OFF

+3VL

3.3V always on power rail

ON

ON

ON

ON

+3V_SB

3.3V power rail for LAN

ON

ON

OFF

OFF

+3V_LAN

3.3V power rail for LAN

ON

ON

OFF

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

OFF

+3VS_HDP

3.3V power rail for G-sensor

ON

OFF

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON

OFF

+5VL

5V always on power rail

ON

ON

ON

ON

+5V_SB

5V power rail for SB

ON

ON

OFF

OFF

+5VS

5V switched power rail

ON

OFF

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON

OFF

+RTCVCC

RTC power

ON

ON

ON

ON

BTO Option Table


Function
description

DEVICE

PCI DEVICE ID

IDSEL#

CARD BUS

D4

AD20

REQ/GNT#
1

A/B

EC SM Bus1 address

RJ11

Camera

(B)

(R)

(X)

MDC

Camera

Express Card

PCMCIA

Bluetooth

BTO

NEW@

PCM@

BT@

explain

MDC@

3D Sensor
2

(S)
3D Sensor

CAM@

GSENSOR@

HDMI
(Y)

description

PIRQ

Bluetooth

(A)

explain

BTO

Power Device

(E)

Function

External PCI Devices

Express Card/ PCMCIA

Intel(UMA)
IHDMI@

ATI VGA/B
NIHDMI@

HDMI@

COMMON
H@

EC SM Bus2 address
Address

+5VL

EC KB926 D2

+5VL

Smart Battery

0001 011X b

+5VL

HDMI-CEC

0011 010x b

Power Device
+3VS
+3VS
+3VS

Address

EC KB926 D2
CPU THM Sen
SMSC SMC1402
VGA THM Sen
ADM1032ARMZ
VGA on die
thermal sensor

1001 101Xb
1001 100Xb
1001 111Xb
(No used)

ICH9M SM Bus address


Power Device

Address

+3V_SB ICH9M
4

1101 001Xb

+3VS

Clock Generator
(SLG8SP556V)
DDR DIMM0

+3VS

DDR DIMM1

1001 010Xb

+3VS

Express Card

+3VS

1001 000Xb

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
E

of

45

H_A20M#
H_FERR#
H_IGNNE#

22
22
22
22

H_STPCLK#
H_INTR
H_NMI
H_SMI#

H_A20M#
H_FERR#
H_IGNNE#

A6
A5
C4

A20M#
FERR#
IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

D5
C6
B4
A3

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
D2
D22
D3
F6

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

Reserve for
debug
close to South
Bridge

D20
B3

LOCK#

H4

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

C1
F3
F4
G3
G2

HIT#
HITM#

G6
E4

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

H_BR0#
H_IERR#
H_INIT#

R1 1

2 56_0402_5%
H_INIT#
22

+1.05VS

H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7
H_HIT# 7
H_HITM# 7

C2
1

if use XDP,these resistor are 51ohm


+1.05VS
XDP_TDO
XDP_TMS
XDP_TDI
XDP_TCK

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

XDP_TRST#
PAD T13

U1

H_THERMDA

H_LOCK# 7
H_RESET#

C1

H_THERMDC
2
2200P_0402_50V7K
CPU_THERM#

R3
1
2
10K_0402_5%

+3VS

+1.05VS
XDP_DBRESET# 23

THERMTRIP#

H_PROCHOT#
H_THERMDA
H_THERMDC

C7

2
54.9_0402_1%
2
54.9_0402_1%
2
54.9_0402_1%

1
R6
1
R7

2
54.9_0402_1%
2
54.9_0402_1%

DN

THERM#

8
7

ALERT#

GND

EC_SMB_CK2 17,33
D

EC_SMB_DA2 17,33

1
R2

2
10K_0402_5%
@ Reserve

+3VS

for source control

1
R8
1
R9

2
@ 56_0402_5%
2
56_0402_5%

FAN Control Circuit

1A
1SS355_SOD323-2

OCP#

Q6
@ MMBT3904_SOT23

23

1
2
3
4

+FAN1

EN_DFAN1

10mil

H CLK

H_THERMDA, H_THERMDC routing together,


Trace width / Spacing = 10 / 10 mil

JFAN
+FAN1

1
2

U2

PROCHOT# PU: 68Ohm near CPU and MVP6.


56Ohm near CPU if no used.

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16

D1
@

2
C3
10U_0805_10V4Z

H_THERMTRIP# 8,22

A22
A21

SMCLK
SMDATA

EMC1402-1-ACZL-TR_MSOP8

+5VS

33

BCLK[0]
BCLK[1]

DP

Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2

1
R14
1
R4
1
R5

H_PROCHOT#

D21
A24
B25

VDD

THERMAL
PROCHOT#
THERMDA
THERMDC

IERR#
INIT#

F1

0.1U_0402_16V4Z

CONTROL

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

22
22
22

H5
F21
E1

7
7
7

H_ADSTB#1

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

ICH

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

H_ADS#
H_BNR#
H_BPRI#

BR0#

ADDR GROUP_1

H_A#17
Y2
H_A#18
U5
H_A#19
R3
H_A#20 W6
H_A#21
U4
H_A#22
Y5
H_A#23
U1
H_A#24
R4
H_A#25
T5
H_A#26
T3
H_A#27 W2
H_A#28 W5
H_A#29
Y4
H_A#30
U2
H_A#31
V4
H_A#32 W3
H_A#33 AA4
H_A#34 AB2
H_A#35 AA3
V1

DEFER#
DRDY#
DBSY#

H1
E2
G5

EN
VIN
VOUT
VSET

GND
GND
GND
GND

8
7
6
5

D2
@

C4
@ 1000P_0402_25V8J
1

1
2
3

1
2
3

4
5

GND
GND

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#[17..35]

ADS#
BNR#
BPRI#

K3
H2
K2
J3
L1

+3VS

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

XDP/ITP SIGNALS

H_ADSTB#0

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP_0

7
7
7
7
7
7

@
JCPUA

H_A#[3..16]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

ACES_85204-0300N
@

BAS16_SOT23-3

APL5607KI-TRG_SO8
C5
10U_0805_10V4Z

R10

10K_0402_5%
1
+3VS
FAN_SPEED1 33

2
C6
0.01U_0402_16V7K
1 @

RESERVED

Penryn
B

H_FERR#
2
C596

H_SMI#
H_INIT#
H_NMI
H_A20M#
H_INTR
H_IGNNE#
H_STPCLK#

2
C597
2
C598
2
C599
2
C600
2
C601
2
C602
2
C603

1
@ 180P_0402_50V8J

1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J

Reserve for
debug
close to CPU
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

of

45

@
JCPUD

@
JCPUB

7
7
7
7

H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]

+1.05VS Close

7
7
7

H_DSTBN#1
H_DSTBP#1
H_DINV#1

+CPU_GTLREF

+CPU_GTLREF

R11
1K_0402_1%

to
CPU pin
AD26
within
500mils.

R17
2K_0402_1%

8,16 CPU_BSEL0
8,16 CPU_BSEL1
8,16 CPU_BSEL2

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

DATA GRP 1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

H_D#[32..47]

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

DATA GRP 0

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

COMP0
COMP1
COMP2
COMP3

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DPRSTP#
H_DPSLP#

DATA GRP 2

H_D#[0..15]

DATA GRP 3

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

Resistor placed within


0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_PWRGOOD
H_CPUSLP#

COMP0

1
R12
1
R13
COMP2
1
R15
COMP3
1
R18
COMP1

2
27.4_0402_1%
2
54.9_0402_1%
2
27.4_0402_1%
2
54.9_0402_1%

H_DPRSTP# 8,22,43
H_DPSLP# 22
H_DPWR# 7
H_PWRGOOD 22
H_CPUSLP# 7
H_PSI#
43

layout note: Please use "Daisy Chain"


to layout and the signal (H_DPRSTP#)
is routed from ICH9 to power IC,
then to NB and CPU

Penryn

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
B

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0
H_CPUSLP#

166

200

266

2
C650
H_PWRGOOD
2
C651
H_DPRSTP#
2
C652
H_DPSLP#
2
C653

Reserve for
debug
close to CPU

1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

Penryn
.

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

of

45

330U_X_2VM_R6M
1

+CPU_CORE

Near CPU CORE regulator

ESR <= 1.5m ohm


Capacitor > 1980uF

+ C7
@

2
330U_X_2VM_R6M

+CPU_CORE

+ C8
@

+ C9
@

+CPU_CORE

330U_X_2VM_R6M
1

+ C10
@

2
330U_X_2VM_R6M

1
Place these capacitors on L8
(North side,Secondary Layer)

C11
10U_0805_6.3V6M

C12
10U_0805_6.3V6M

C13
10U_0805_6.3V6M

C14
10U_0805_6.3V6M

C15
10U_0805_6.3V6M

C16
10U_0805_6.3V6M

C17
10U_0805_6.3V6M

C18
10U_0805_6.3V6M

+CPU_CORE

+CPU_CORE
@
JCPUC

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

330U_6.3V_M_R15

330U_6.3V_M_R15

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VCCSENSE 43

VSSSENSE

AE7

VSSSENSE

VSSSENSE 43

C79

C80

C81

1
Place these capacitors on L8
(North side,Secondary Layer)

C19
10U_0805_6.3V6M

C20
10U_0805_6.3V6M

C21
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C23
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C25
10U_0805_6.3V6M

C26
10U_0805_6.3V6M

C82

need to change P/N


+CPU_CORE

330U_6.3V_M_R15

330U_6.3V_M_R15

reserve for test


please co-layout with C7~C10

Place these capacitors on L8


(Sorth side,Secondary Layer)

C27
10U_0805_6.3V6M

C28
10U_0805_6.3V6M

C29
10U_0805_6.3V6M

C30
10U_0805_6.3V6M

C31
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

C34
10U_0805_6.3V6M

+CPU_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C35
10U_0805_6.3V6M

C36
10U_0805_6.3V6M

C37
10U_0805_6.3V6M

C38
10U_0805_6.3V6M

C39
10U_0805_6.3V6M

C40
10U_0805_6.3V6M

C41
10U_0805_6.3V6M

C42
10U_0805_6.3V6M

Mid Frequence Decoupling


+1.05VS

4.5A

330U_6.3V_M_R15
1

1
+

+
C43
@

Place these inside socket cavity on L8

+1.05VS (North side Secondary)

C146

330U_X_2VM_R6M

reserve for test

C44
0.1U_0402_10V6K

C45
0.1U_0402_10V6K

C46
0.1U_0402_10V6K

C47
0.1U_0402_10V6K

C48
0.1U_0402_10V6K

C49
0.1U_0402_10V6K

Near pin B26

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

43
43
43
43
43
43
43

+1.5VS

C50
0.01U_0402_16V7K 10U_0805_6.3V6M
2

C51
B

Penryn
.
+CPU_CORE

VCCSENSE

100_0402_1% 2

R19

VSSSENSE

100_0402_1% 2

R20

Close to CPU pin


within 500mils.

Length match within 25 mils.


The trace width/space/other is
14/7/25.

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

of

45

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

Layout Note:
H_RCOMP / +H_VREF / H_SWNG
trace width and spacing is 10/20
within 100 mils from NB

+1.05VS

R22
221_0402_1%

R23
2K_0402_1%

H_SWNG

H_SWING
H_RCOMP

R24
24.9_0402_1%

C52
0.1U_0402_16V4Z
@

H_SWING=0.3125*VCCP

C5
E3

H_RCOMP

+H_VREF

H_SWNG
H_RCOMP

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

R25
100_0402_1%

C53
0.1U_0402_16V4Z

4
5

H_RESET#
H_CPUSLP#

C12
E11

H_CPURST#
H_CPUSLP#

+H_VREF

Near B3 pin

A11
B11

H_AVREF
H_DVREF

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR# 5
H_DRDY# 4
H_HIT#
4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

J8
L3
Y13
Y1

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

L10
M7
AA5
AE6

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

5
5
5
5

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

L9
M8
AA6
AE5

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

5
5
5
5

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

B15
K13
F13
B13
B14

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

4
4
4
4
4

H_RS#_0
H_RS#_1
H_RS#_2

B6
F12
C8

H_RS#0
H_RS#1
H_RS#2

4
4
4

1 2

R21
1K_0402_1%

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6

H_A#[3..35]

U3A

H_D#[0..63]

+1.05VS

HOST

5
5
5
5

CANTIGA ES_FCBGA1329
GM45R3@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

of

45

AY21

Internal pull-up

01
00
10
11

Internal pull-up

0 = Dynamic ODT Disabled


1 = Dynamic ODT Enabled *(Default)

CFG[13:12]

= All Z Mode Enabled


= Reserved
= XOR Mode Enabled
= Normal Operation*(Default)

BG23
BF23
BH18
BF18

CFG19 Internal pull-down

0 = Normal Operation
1 = DMI Lane Reversal Enable

CFG20

0 = Only PCIE or [SDVO/DP/HDMI] is operational.

Internal pull-down

(PCIE/SDVO select)

RSVD20

RSVD22
RSVD23
RSVD24
RSVD25

*(Default)
* (Default)

5,16 CPU_BSEL0
5,16 CPU_BSEL1
5,16 CPU_BSEL2

R46
R47

1
1

2@ 2.21K_0402_1%
2@ 2.21K_0402_1%

MCH_CFG_12
MCH_CFG_13

+3VS

R48

2@ 2.21K_0402_1%

MCH_CFG_16

1
1

T16 PAD
MCH_CFG_19
2 4.02K_0402_1%
MCH_CFG_20
2@ 4.02K_0402_1%

R49
R50
B

+3VS

2 PM_EXTTS#_R
10K_0402_5%

PM_SYNC#

14,15 PM_EXTTS#

1
2 0_0402_5%
5,22,43 H_DPRSTP#

R53

R54
R55
R56

1
1
1

2 0_0402_5%

PM_SYNC#_R

PM_EXTTS#_R
GMCH_PWROK
2 100_0402_5% MCH_RSTIN#
NB_THERMTRIP#
2 0_0402_5%
DPRSLPVR
0_0402_5%
2

R29
B7
N33
P32
AT40
AT11
T20
R32

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

SMRCOMP
SMRCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

BF28
BH28

+SM_RCOMP_VOH
+SM_RCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

AV42
AR36
BF17
BC36

+SM_VREF
SM_PWROK
SM_REXT

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

B38
A38
E41
F41

CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#

PEG_CLK
PEG_CLK#

F43
E43

CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

AE41
AE37
AE47
AH39

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

21
21
21
21

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AE40
AE38
AE48
AH40

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

21
21
21
21

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AE35
AE43
AE46
AH42

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

21
21
21
21

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

AD35
AE44
AF46
AH43

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

21
21
21
21

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

B33
B32
G33
F33
E33

GFX_VR_EN

C34

R29
R30

1
1

1
1

1
2
2

2
C56
0.01U_0402_16V7K

14
14
15
15

+1.5V

2 0_0402_5%
2 499_0402_1%
SM_DRAMRST# 14,15

R31
1K_0402_1%

1
C58
0.1U_0402_16V4Z
2 @

CLK_DREF_96M 16
CLK_DREF_96M# 16
CLK_DREF_SSC 16
CLK_DREF_SSC# 16

2.2U_0603_6.3V6K
C57
R28
1K_0402_1%

+1.5V

2 80.6_0402_1%
2 80.6_0402_1%

20mil
R32
R33

SM_PWROK R101 1

2
0_0402_5%

DDR3_SM_PWROK 42

R34
1K_0402_1%
CLK_DREF_96M
1
R575
CLK_DREF_96M# 1
R576
CLK_DREF_SSC
1
R577
CLK_DREF_SSC# 1
R578

PM@
2
0_0402_5%
PM@
2
0_0402_5%
PM@
2
0_0402_5%
PM@
2
0_0402_5%

Please place these resistors close to related balls


+1.05VS

+3VS
R38
1K_0402_5%

Lane reversal
R41
54.9_0402_1%

R42
1K_0402_5%

MCH_TSATN#

3
1
Q7
MMBT3904_SOT23-3

MCH_TSATN_EC# 33

Strap Pin Table


SDVO_CTRLDATA
(Internal pull-down)

0 = SDVO interface disabled *(Default)


1 = SDVO interface enabled

DDPC_CTRLDATA
(Internal pull-down)

0 = Digital display (iHDMI/DP) interface disabled


1 = Digital display (iHDMI/DP) interface enabled
*(Default)

+1.05VS
2

17,21,27,28,33,34 PLT_RST#
4,22 H_THERMTRIP#
23,43 PM_DPRSLPVR

R51

PM

1
R52

23

BG22
BH21

80 Ohm

MCH_CFG_9
MCH_CFG_10

SM_RCOMP
SM_RCOMP#

2.2U_0603_6.3V6K
C55
R27
3.01K_0402_1%

+SM_RCOMP_VOL

For Cantiga

1
1

2@ 2.21K_0402_1%
2@ 2.21K_0402_1%

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1

14
14
15
15

R44
R45

R39
R40
R43

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

CFG

1
1
1

1 1K_0402_5% MCH_CLKSEL0
1 1K_0402_5% MCH_CLKSEL1
1 1K_0402_5% MCH_CLKSEL2
T14 PAD
T15 PAD
MCH_CFG_5
2@ 2.21K_0402_1%
MCH_CFG_6
2@ 2.21K_0402_1%
MCH_CFG_7
2@ 2.21K_0402_1%

BD17
AY17
BF15
AY13

GRAPHICS VID

2
2
2

SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1

DMI

CLK

1 = PCIE/[SDVO/DP/HDMI] are operating simu.

R35
R36
R37

DDRA_SCS0#
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#

0 = PCIe Loopback Enable


1 = Disable*(Default)

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SM_DRAMRST# would be
needed for DDR3 only

Internal pull-up

RSVD15
RSVD16
RSVD17

BA17
AY16
AV16
AR13

C54
0.01U_0402_16V7K

14
14
15
15

CFG10

B31
B2
M1

DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1

0 = Lane Reversal Enable


1 = Normal Operation *(Default)

BC28
AY28
AY36
BB36

+SM_RCOMP_VOH

Internal pull-up

RSVD

CFG9

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

14
14
15
15

1 = Intel Management Engine Crypto TLS cipher suite with


confidentiality *(Default)

DDRA_CLK0#
DDRA_CLK1#
DDRB_CLK0#
DDRB_CLK1#

Internal pull-up

AR24
AR21
AU24
AV20

0 = Intel Management Engine Crypto Transport Layer Security


(TLS) cipher suite with no confidentiality

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

R26
1K_0402_1%

*(Default)

14
14
15
15

can support disble by SW.

1 = iTPM Host Interface is Disabled

DDRA_CLK0
DDRA_CLK1
DDRB_CLK0
DDRB_CLK1

0 = iTPM Host Interface is enabled

AP24
AT21
AV24
AU20

Internal pull-up

0 = DMI x 2
1 = DMI x 4 *(Default)

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

CFG6

CFG16

+1.5V

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

COMPENSATION

Internal pull-up

M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24

DDR CLK/ CONTROL/

CFG5

CFG7

U3B

011 = FSB667
010 = FSB800
000 = FSB1067

CFG[2:0]

Strap Pin Table

R57
1K_0402_1%

CL_CLK0 23
CL_DATA0 23

ICH_PWROK

Width:Spacing
12mil:12mil

CL_RST#0 23

+CL_VREF

+CL_VREF=0.355V
1

C59
0.1U_0402_16V4Z

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

N28
M28
G36
E36
K36
H36

SDVO_SCLK
SDVO_SDATA

TSATN#

B12

MCH_TSATN#

AH37
AH36
AN36
AJ35
AH34

SDVO_SCLK 20
SDVO_SDATA 20
CLKREQ_3GPLL# 16
MCH_ICH_SYNC# 23

CL_VREF
should be
0.35 V
R60
499_0402_1%

2
+3VS
SDVO_SCLK 2
R61 GM@
SDVO_SDATA 2
R62 IHDMI@

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

B28
B30
B29
C29
A28

AZ_SDIN2_MCH_R

AZ_BITCLK_MCH 22
AZ_RST_MCH# 22
1
R63
AZ_SDOUT_MCH 22
AZ_SYNC_MCH

22

2
33_0402_5%
IHDMI@

1 2.2K_0402_5%

1 GM@ 2
R579
0_0402_5%
1 PM@
2
R580
0_0402_5%

2009/07/22

Compal Electronics, Inc.


2012/07/22

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

AZ_SDIN2_MCH 22

Compal Secret Data

Classification

Issued Date

1 2.2K_0402_5%

the strap pin will impact no IHDMI SKU if mount R62

CANTIGA ES_FCBGA1329
GM45R3@
Security

R61 PM@
0_0402_5%
R62 PM@
0_0402_5%

NC

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

ME

GMCH_PWROK
2
@ 0_0402_5%
2
0_0402_5%

MISC

23,33,43 VGATE
23,33 ICH_PWROK

1
R58
1
R59

HDA

Use VGATE for GMCH_PWROK

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Sheet

Wednesday, December 30, 2009


1

of

45

15 DDR_B_D[0..63]
DDR_A_BS0 14
DDR_A_BS1 14
DDR_A_BS2 14

SA_RAS#
SA_CAS#
SA_WE#

BB20
BD20
AY20

DDR_A_RAS# 14
DDR_A_CAS# 14
DDR_A_WE# 14

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SYSTEM

MEMORY

DDR_A_DM[0..7]

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AJ43 DDR_A_DQS#0
AT43 DDR_A_DQS#1
BA44 DDR_A_DQS#2
BD37 DDR_A_DQS#3
AY12 DDR_A_DQS#4
BD8 DDR_A_DQS#5
AU9 DDR_A_DQS#6
AM8 DDR_A_DQS#7

DDR_A_DQS#[0..7]

DDR_A_MA[0..14]

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

14

DDR_A_DQS[0..7]

U3E
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

14

14

14

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

CANTIGA ES_FCBGA1329
GM45R3@

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SA_BS_0
SA_BS_1
SA_BS_2

BD21
BG18
AT25

SB_BS_0
SB_BS_1
SB_BS_2

BC16
BB17
BB33

DDR_B_BS0 15
DDR_B_BS1 15
DDR_B_BS2 15

SB_RAS#
SB_CAS#
SB_WE#

AU17
BG16
BF14

DDR_B_RAS# 15
DDR_B_CAS# 15
DDR_B_WE# 15

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SYSTEM

U3D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

DDR

14 DDR_A_D[0..63]

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

15
C

DDR_B_DQS#[0..7]

AL46 DDR_B_DQS#0
AV47 DDR_B_DQS#1
BH41 DDR_B_DQS#2
BH37 DDR_B_DQS#3
BG9 DDR_B_DQS#4
BC2 DDR_B_DQS#5
AT2 DDR_B_DQS#6
AN5 DDR_B_DQS#7
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

15

DDR_B_MA[0..14]

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

15

15

CANTIGA ES_FCBGA1329
GM45R3@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

of

45

+3VS

U3C

within 500 mils

L_DDC_DATA

LCTLA_CLK
2
L32
10K_0402_5%
G32
33 UMA_ENBKL
LCTLB_DATA
LCTLA_CLK
GM@
2
M32
10K_0402_5%
LCTLB_DATA
M33
GM@
UMA_LCD_EDID_CLK
UMA_LCD_EDID_CLK K33
2
18 UMA_LCD_EDID_CLK
2.2K_0402_5%
UMA_LCD_EDID_DATAJ33
18 UMA_LCD_EDID_DATA
GM@
UMA_LCD_EDID_DATA
UMA_ENVDD
2
M29
18 UMA_ENVDD
2.2K_0402_5%
R69 1 GM@
2 LVDS_IBG
C44
2.37K_0402_1% Spacing=20mil B43
R501 1 GM@
2 0_0402_5%
E37
R502 1 GM@
2 0_0402_5%
E38
GM@

0 = LFP Disable
*(Default)
1 = LFP Card Present; PCIE disable

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

C41
C40
B37
A37

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

18 UMA_LCD_TXOUT018 UMA_LCD_TXOUT118 UMA_LCD_TXOUT2-

H47
E46
G40
A40

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

18 UMA_LCD_TXOUT0+
18 UMA_LCD_TXOUT1+
18 UMA_LCD_TXOUT2+

H48
D45
F40
B40

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

18 UMA_LCD_TZOUT018 UMA_LCD_TZOUT118 UMA_LCD_TZOUT2-

A41
H38
G37
J37

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

18 UMA_LCD_TZOUT0+
18 UMA_LCD_TZOUT1+
18 UMA_LCD_TZOUT2+

B42
G38
F37
K37

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

18
18
18
18

UMA_LCD_TXCLKUMA_LCD_TXCLK+
UMA_LCD_TZCLKUMA_LCD_TZCLK+

LVDS

R64
PM@
0_0402_5%
R66
PM@
0_0402_5%
R67
PM@
0_0402_5%
R68
PM@
0_0402_5%

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

GRAPHICS

1
2
R500PM@ 0_0402_5%

1
R64
1
R66
1
R67
1
R68

1 GM@
R70
1 GM@
R71
1 GM@
R72

2 TV_COMPS
75_0402_1%
2 TV_LUMA
75_0402_1%
2 TV_CRMA
75_0402_1%

TV_COMPS
TV_LUMA
TV_CRMA

F25
H25
K25
H24

C31
E32
R73
PM@
0_0402_5%
R74
PM@
0_0402_5%
R75
PM@
0_0402_5%

1
R73 GM@
1
R74 GM@
1
R75 GM@

UMA_CRT_B
2
150_0402_1%
UMA_CRT_G
2
150_0402_1%
UMA_CRT_R
2
150_0402_1%

UMA_CRT_B

19

UMA_CRT_G

19

UMA_CRT_R

R78
PM@
0_0402_5%

1
R503 PM@
1
R504 PM@

UMA_CRT_CLK
2
4.7K_0402_5%
UMA_CRT_DATA
2
4.7K_0402_5%

E28

CRT_BLUE

UMA_CRT_G

G28

CRT_GREEN

UMA_CRT_R

UMA_CRT_HSYNC
0_0402_5%
UMA_CRT_VSYNC
2
0_0402_5%

19 UMA_CRT_CLK
19 UMA_CRT_DATA
19 UMA_CRT_HSYNC
2
R78 GM@

UMA_CRT_CLK
UMA_CRT_DATA
UMA_CRT_HSYNC
1UMA_CRT_IREF
1.02K_0402_1%

J28

CRT_RED

G29

CRT_IRTN

H32
J32
J29
E29

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF

UMA_CRT_VSYNC L29

19 UMA_CRT_VSYNC

TV_DCONSEL_0
TV_DCONSEL_1

UMA_CRT_B

+3VS

1
R76 GM@
1
R77 GM@

TV_RTN

PEG_COMP 1
R65

2
49.9_0402_1%

PEG_COMPI
PEG_COMPO

T37
T36

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

VGA

19

TVA_DAC
TVB_DAC
TVC_DAC

TV

R70
PM@
0_0402_5%
R71
PM@
0_0402_5%
R72
PM@
0_0402_5%

PCI-EXPRESS

1
2
R499GM@ 0_0402_5%

CRT_VSYNC

+1.05VS

10mils

PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_N[0..15] 17

PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_P[0..15] 17

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15] 17
PCIE_MTX_C_GRX_P[0..15] 17

C612 1

2 PM@

C614 1

2 PM@

C616 1
C618 1
C620 1
C622 1
C624 1

2 PM@
2 PM@
2 PM@
2 PM@
2 PM@

C626 1

2 PM@

C628 1

2 PM@

C630 1

2 PM@

C632 1

2 PM@

C634 1

2 PM@

C636 1
C638 1

2 PM@
2 PM@

C640 1

2 PM@

C642 1

2 PM@

C611
0.1U_0402_16V7K
C613
0.1U_0402_16V7K
C615
0.1U_0402_16V7K
C617
0.1U_0402_16V7K
C619
0.1U_0402_16V7K
C621
0.1U_0402_16V7K
C623
0.1U_0402_16V7K
C625
0.1U_0402_16V7K

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

C627
0.1U_0402_16V7K
C629
0.1U_0402_16V7K
C631
0.1U_0402_16V7K
C633
0.1U_0402_16V7K
C635
0.1U_0402_16V7K
C637
0.1U_0402_16V7K
C639
0.1U_0402_16V7K
C641
0.1U_0402_16V7K

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

2 PM@

0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

CANTIGA ES_FCBGA1329
GM45R3@
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3

C61 1

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3

C65 1

PCIE_GTX_C_MRX_P3

C63 1

C67 1

C60 1
2 IHDMI@ 0.1U_0402_16V7K
C62 1
2 IHDMI@ 0.1U_0402_16V7K

2 IHDMI@ 0.1U_0402_16V7K

C64 1
2 IHDMI@ 0.1U_0402_16V7K
C66 1
2 IHDMI@ 0.1U_0402_16V7K

2 IHDMI@ 0.1U_0402_16V7K

2 IHDMI@ 0.1U_0402_16V7K

2 IHDMI@ 0.1U_0402_16V7K

1
2
R505 IHDMI@
0_0402_5%

PCIE_MTX_C_GRX_HDMI_N0
PCIE_MTX_C_GRX_HDMI_N1
PCIE_MTX_C_GRX_HDMI_N2
PCIE_MTX_C_GRX_HDMI_N3

20
20
20
20

PCIE_MTX_C_GRX_HDMI_P0
PCIE_MTX_C_GRX_HDMI_P1
PCIE_MTX_C_GRX_HDMI_P2
PCIE_MTX_C_GRX_HDMI_P3

20
20
20
20

PCIE_GTX_C_MRX_HDMI_P3 20

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

10

of

45

U3F

0.1U_0402_16V4Z

BA36
BB24
BD16
BB21
AW16
AW13
AT13

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

9600mA
For layout placement un-mound C123 and mound C84

Int. Graphic
+1.05VS

+NB_VCCAXG
10U_0805_10V4Z

0.47U_0603_10V7K

0.1U_0402_16V4Z

1
1

C225
C85
C86
C87
C88
C89
C90
GM@
GM@
220U_6.3V_M_R15 GM@
GM@
GM@
GM@
2 GM@
2
2
2
2
2
2
10U_0805_10V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z

C86 PM@
0_0805_5%
+NB_VCCAXG
PJ27
1

JUMP_43X39 @
PJ28
1

JUMP_43X39 @
PJ29
1

JUMP_43X39 @
PJ30
1

PJ31
1

AJ14
AH14

VCC_AXG_SENSE
VSS_AXG_SENSE

JUMP_43X39 @

PAD T3
PAD T4

JUMP_43X39 @
PJ32

+
+
C73
GM@
2
2
220U_6.3V_M_R15
C72

0.22U_0402_10V4Z
1

C74

1
C75

0.1U_0402_16V4Z
1

C76

1
C77

2
2
2
10U_0805_10V4Z
0.22U_0402_10V4Z

U3G

NB Core,Intel Management Engine Link


220U_6.3V_M_R15
1

Intel: VCC -- 220U*2, ESR 12mOhm

AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35

+1.05VS

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

GFX

+1.05VS

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

+1.05VS

VCC

Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm


For layout issue to separate 220u*1 to +1.05VS
B

Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14

VCC CORE (Core+IMEL+HSIO)


W/Ext GFX: 3060mA
W/Int GFX: 2400mA

VCC CORE

SM

10U_0805_10V4Z

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

NCTF

1
C71

VCC

2
330U_6.3V_M_R15

C70

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

VCC

C69

GFX NCTF

+
C78

VCC

1
D

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC SM LF

10U_0805_10V4Z

Int. Graphic

AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

POWER

DDR PWR

+NB_VCCAXG

DDR3,1066MHz,4140mA
DDR3,800MHz,3162.5mA
+1.5V

POWER

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

AV44 VCCSM_LF1
BA37 VCCSM_LF2
AM40 VCCSM_LF3
AV21 VCCSM_LF4
AY5 VCCSM_LF5
AM10 VCCSM_LF6
BB13 VCCSM_LF7

C91
0.1U_0402_16V4Z

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

CANTIGA ES_FCBGA1329
GM45R3@
C93
1
0.22U_0603_10V7K

C92
2 0.1U_0402_16V4Z 2

C95
1
0.47U_0603_10V7K

C94
2 0.22U_0603_10V7K

1 C96
1U_0402_6.3V4Z
2

C97
1U_0402_6.3V4Z

2
A

CANTIGA ES_FCBGA1329
GM45R3@

JUMP_43X39 @

2009/07/22

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/22

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Sheet

Wednesday, December 30, 2009


1

11

of

45

+3VS_TVCRT_DACBG

C102
GM@
2
2
0.1U_0402_16V4Z

+1.05VS

+1.05VS_AHPLL

F47

2 0.1U_0402_16V4Z
2

Pin AD1

+1.5VS_PEG_BG

PCIe&DMI
+1.5VS

R87

1
2
0_0603_5%

VCCA_DAC_BG

B25

VSSA_DAC_BG

+1.05VS_DPLLA

F47

VCCA_DPLLA64.8mA

+1.05VS_DPLLB

L48

VCCA_DPLLB64.8mA

AD1

VCCA_HPLL 24mA

+1.05VS_MPLL

AE1

VCCA_MPLL 139.2mA

+1.8V_TXLVDS

J48

VCCA_LVDS

J47

VSSA_LVDS

L48

+1.8V_TXLVDS

LVDS

13.2mA

1
C118
1000P_0402_50V7K
2 GM@
Pin J48

C118 PM@
0_0402_5%

414uA

GND to J47
+1.5VS_PEG_BG

AD48

VCCA_PEG_BG

+1.05VS_PEGPLL

AA48

VCCA_PEG_PLL

50mA

+1.05VS_PEGPLL

DDR3,1066MHz,747.5mA
DDR3,800MHz,575mA

C121
2

Pin AD48

A25

+3VS_TVCRT_DACBG
C112 PM@
0_0805_5%

C122
0.1U_0402_16V4Z

0.1U_0402_16V4Z

PCIe&DMI
Pin AA48

+1.05VS
R88
1
2
1 0_0805_5%
C123
220U_D2_4VM_R15
@

+
2

DDR3

+1.05VS_A_SM

4.7U_0805_10V4Z
1
1
C124

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

C125

C126

2
2
2
10U_0805_10V4Z
1U_0402_6.3V4Z

C135
0.1U_0402_16V4Z

C136
2

Pin B24

Pin AP28

HDMI's HDA

1
2
0_0402_5% 1
IHDMI@
C138
0.1U_0402_16V4Z
IHDMI@ 2

2
2
0.01U_0402_25V4Z

+1.5VS_HDA

A32

VCC_HDA

C142
0.1U_0402_16V4Z

C143

HDA

+1.5VS_TVDAC

M25

VCCD_TVDAC

+1.5VS_QDAC

L28

VCCD_QDAC500uA

157.2mA
AF1

+1.05VS_DHPLL
+1.05VS

+1.05VS_DHPLL
R98

+1.05VS_PEGPLL

AA47

+1.8V_LVDS

M38
L37

VCCD_HPLL

50mA

VCCD_PEG_PLL

60.31mA

1
2
0_0402_5%

C150
0.1U_0402_16V4Z

VCCD_LVDS_1
VCCD_LVDS_2

Pin AF1

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

BF21
BH20
BG20
BF20

VCC_TX_LVDS

+1.05VS

+1.05VS_PEGPLL

PCIe&DMI

L1
2
1
BLM18PG121SN1D_0603

0.1U_0402_16V4Z
1

R100
1_0805_1%

C152
2
2

1 C154
10U_0805_10V4Z

Pin AA47

+1.8V_TXLVDS

C35
B35
A35

+3VS

+1.8V
R91 GM@
1
2
1 0_0603_5%

LVDS
1
+1.8V_TXLVDS

C128
10U_0805_10V4Z
2 @

C130 PM@
0_0402_5%

C130
C131
1000P_0402_50V7K
10U_0805_10V4Z
2 GM@
2 GM@

Pin K47

1
V48
U48
V47
U47
U46

+1.05VS

AH48
AF48
AH47
AG47

+1.05VS

D3
2 R93
1
1
2
+1.05VS
10_0603_5%
CH751H-40PT_SOD323-2
C137
0.1U_0402_16V4Z

Pin C35
B

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

+1.05VS

PCIe&DMI
10U_0805_10V4Z
1

C144

C145

2
10U_0805_10V4Z

Pin V48
VTTLF1
VTTLF2
VTTLF3

VTTLF1
A8
VTTLF2
L1
AB2 VTTLF3
1

PCIe&DMI

+1.05VS

C147
C148
C149
0.47U_0603_10V7K 0.47U_0603_10V7K 0.47U_0603_10V7K
2
2
2

C151
0.1U_0402_16V4Z

Pin AH48

+1.8V_LVDS
+1.8V

R99
2
1
0_0603_5%
GM@

LVDS
1

C153
1U_0402_6.3V4Z GM@
2

Pin M38

C153 PM@
0_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

C129

10U_0805_10V4Z

+3VS

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

R90
1_0805_1%

1
+1.5V_SM_CK

105.3mA
VCC_HV_1
VCC_HV_2
VCC_HV_3

C127
0.1U_0402_16V4Z

Pin BF21

K47

+1.5V
R89
1
2
0_0805_5%
1

DDR2

+1.05VS_AXF

CANTIGA ES_FCBGA1329
GM45R3@

C120
10U_0805_10V4Z
2 @

456mA

35mA

Pin
L282
2

B22
B21
A21

1782mA

50mA

R96
TV
2
1 0.01U_0402_25V4Z
0_0603_5% 1
1

C119
1U_0402_6.3V4Z

TV

VCCA_TV_DAC_1
VCCA_TV_DAC_2

+1.5VS_QDAC

+1.5VS

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

118.8mA

DMI

C141

Pin M25

+3VS_TVCRT_DAC

B24
A24

D TV/CRT

C140

TV

440mA

SM CK

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

LVDS

C139
@ 10U_0805_10V4Z

+1.5VS_TVDAC
0.1U_0402_16V4Z
1
1

+ C103
220U_D2_4VM_R15
2

+1.05VS
R86
1
2
1 0_0603_5%

+1.05VS_AXF

DDR3,1066MHz,149.5mA
DDR3,800MHz,143.75mA

79mA

+1.5VS
R95
2
1
0_0603_5% 1

C107
4.7U_0805_10V4Z

Intel: VTT 270U*1 ESR 12mOhm

+1.5V_SM_CK

Pin A32

1
C106
4.7U_0805_10V4Z

Host Interface I/O and HSIO

HV

C134

2
2.2U_0603_6.3V4Z

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

1
C105
2.2U_0603_6.3V6K

Pin B22

PEG

0.01U_0402_25V4Z
1
1

C133

+1.5VS_HDA
R94

+1.05VS_A_SM_CK

C104
0.47U_0603_10V7K
2

POWER

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

DDR3,1066MHz,37.95mA
DDR3,800MHz,28.75mA

0.1U_0402_16V4Z
1
1

1
1

VTTLF

+1.5VS

TV

DDR3

AGTL+

A CK

+1.05VS
R92
2
11
0_0603_5% 1
C155
1U_0402_6.3V4Z
C132
2
10U_0805_10V4Z 2

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

NB I/O

Pin AR20

+3VS_TVCRT_DAC

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

5mA

+1.05VS_AHPLL

2
1
MBK2012121YZF_0805
1
C117
1
2
C114
R85 0.5_0805_1%
10U_0805_10V4Z
Pin AE12
0.1U_0402_16V4Z

C116

B27
A26

+3VS_TVCRT_DAC

+1.05VS_MPLL
R84

+1.05VS

FSB=1067Mhz,852mA
73mA

+1.05VS_DPLLB

10U_0805_10V4Z
2
1
10U_FLC-453232-100K_0.25A_10%
1
1
1
C109 +
C112
C113
220U_B2_2.5VM
GM@
GM@
@
Pin
2
2
2
0.1U_0402_16V4Z

C110 PM@
0_0805_5%

+1.05VS

2
1
KC FBM-L11-160808-121LMT
0603 1
1

U3H

C98
10U_0805_10V4Z
GM@ 2

R82 GM@

R83

C115
4.7U_0805_10V4Z

GNDtoB25

CRT

R81

Pin A25

+1.05VS

GM@
10U_0805_10V4Z
2
1
10U_FLC-453232-100K_0.25A_10%
1
1
1
C108 +
C110
C111
220U_B2_2.5VM
GM@
GM@
@
Pin
2
2
2
0.1U_0402_16V4Z

R79 GM@
2
1
BLM18PG181SN1D_0603 1

VTT

+1.05VS_DPLLA

C101
GM@

+3VS_TVCRT_DACBG

+3VS

PLL

+1.05VS

TV

0.01U_0402_25V4Z
1
1

A PEG A LVDS

C100 PM@
0_0402_5%
C101 PM@
0_0402_5%

AXF

+3VS_TVCRT_DAC

CRT

R80 1
0.01U_0402_25V4Z
2
0_0603_5% 1
1
GM@
C99
C100
GM@
GM@
Pin B27
2
2
0.1U_0402_16V4Z

A SM

+3VS_TVCRT_DACBG

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

12

of

45

VSS

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233

BA16

VSS_235

AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

CANTIGA ES_FCBGA1329
GM45R3@

VSS

VSS NCTF

U3J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

VSS SCB

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

NC

U3I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

VSS_351
VSS_352
VSS_353
VSS_354

U24
U28
U25
U29

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

BH48
BH1
A48
C1
A3

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

CANTIGA ES_FCBGA1329
GM45R3@
A

2009/07/22

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/22

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

13

of

45

DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

8
C

DDRA_CKE0

+1.5V
9

DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

8
8

DDRA_CLK0
DDRA_CLK0#

DDR_A_D42
DDR_A_D43

RD5
10K_0402_5%
2
1

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

+0.75VS

GND1
GND2

BOSS1
BOSS2

206
208

205
207

2
+V_DDR3_DIMM_REF

DDRA_ODT1 8
+DDR_VREF_CA_DIMMA

RD4
1
0_0402_5%

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5

1
1

+ CD17
@

+ CD45

330U_B2_2.5VM_R15M

reserve for test

close to JDDRH.126

Layout Note:
Place near JDDRL.203 & JDDRL.204

+0.75VS

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

10U_0805_6.3V6M

1
CD6

DDRA_SCS0# 8
DDRA_ODT0 8

CD21

CD5

DDR_A_BS1 9
DDR_A_RAS# 9

CD20

+3VS

390U_2.5V_M_R10

1U_0402_6.3V4Z

DDR_A_D58
DDR_A_D59
RD3 1
2
10K_0402_5%

+1.5V
DDRA_CLK1 8
DDRA_CLK1# 8

CD19

DDR_A_DM7

DDR_A_MA2
DDR_A_MA0

1U_0402_6.3V4Z

DDR_A_D56
DDR_A_D57

Layout Note: Place these 4 Caps near Command


and Control signals of DIMMA

DDR_A_MA6
DDR_A_MA4

CD18

DDR_A_D50
DDR_A_D51

DDR_A_MA11
DDR_A_MA7

1U_0402_6.3V4Z

DDR_A_DQS#6
DDR_A_DQS6

Layout Note:
Place near JDDRL

1U_0402_6.3V4Z

DDR_A_D48
DDR_A_D49

+1.5V

CD16

DDR_A_DM5

2
@ 0_0402_5%

CD15

DDR_A_D40
DDR_A_D41

DDRA_CKE1 8
RD6 1
DDR_A_MA14

0.1U_0402_16V4Z

DDR_A_D34
DDR_A_D35

DDR_A_D30
DDR_A_D31

CD14

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_DQS#3
DDR_A_DQS3

0.1U_0402_16V4Z

1K_0402_1%

DDR_A_D28
DDR_A_D29

CD13

DDR_A_D32
DDR_A_D33

+V_DDR3_DIMM_REF
RD2

0.1U_0402_16V4Z

DDR_A_MA13

DDR_A_D22
DDR_A_D23

10U_0805_6.3V6M

DDRA_SCS1#

RD1
1K_0402_1%

DDR_A_DM2

10U_0805_6.3V6M

DDR_A_D20
DDR_A_D21

10U_0805_6.3V6M

DDR_A_WE#
DDR_A_CAS#

+1.5V

10U_0805_6.3V6M

9
9

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

SM_DRAMRST# 8,15
DDR_A_D14
DDR_A_D15

10U_0805_6.3V6M

DDR_A_BS0

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

DDR_A_DM1

10U_0805_6.3V6M

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

DDR_A_D12
DDR_A_D13

0.1U_0402_16V4Z

DDR_A_MA10

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_A_MA[0..14]

CD12

DDR_A_D18
DDR_A_D19

DDR_A_DM[0..7]

CD22

DDR_A_DQS#2
DDR_A_DQS2

CD11

DDR_A_D16
DDR_A_D17

DDR_A_D[0..63]

DDR_A_D6
DDR_A_D7

DDR_A_D10
DDR_A_D11

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_DQS#1
DDR_A_DQS1

close to JDDRH.1

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

CD10

DDR_A_D8
DDR_A_D9

DDR_A_D4
DDR_A_D5

CD9

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

CD8

DDR_A_DM0

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

CD7

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

CD4
2.2U_0603_6.3V4Z

CD2
2.2U_0603_6.3V4Z

CD1
0.1U_0402_16V4Z

DDR_A_D0
DDR_A_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR3 SO-DIMM A
REVERSE TYPE

JDDRL

+V_DDR3_DIMM_REF

CD3
0.1U_0402_16V4Z

DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS# 8,15
PM_SMBDATA 15,16,23,27
PM_SMBCLK 15,16,23,27
+0.75VS

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FOX_AS0A626-U2RN-7F
@

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

14

of

45

DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27

8
2

DDRB_CKE0

+1.5V
9

DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_DM5
DDR_B_D42
DDR_B_D43

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

205
207

GND1
GND2

BOSS1
BOSS2

206
208

2
+V_DDR3_DIMM_REF

DDRB_ODT1 8
+DDR_VREF_CA_DIMMB

RD7
1
0_0402_5%

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5

1
1

+ CD39
330U_B2_2.5VM_R15M
@
2

close to JDDRL.126

Layout Note:
Place near JDDRH.203 & JDDRH.204

+0.75VS

DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

10U_0805_6.3V6M

1
1
CD25

DDRB_SCS0# 8
DDRB_ODT0 8

CD43

CD26

1 RD9
2
10K_0402_5% +0.75VS

DDR_B_BS1 9
DDR_B_RAS# 9

CD42

+3VS

+1.5V
DDRB_CLK1 8
DDRB_CLK1# 8

1U_0402_6.3V4Z

DDR_B_D58
DDR_B_D59
RD8 1
2
10K_0402_5%

DDR_B_MA2
DDR_B_MA0

CD41

DDR_B_DM7

Layout Note: Place these 4 Caps near Command


and Control signals of DIMMB

DDR_B_MA6
DDR_B_MA4

1U_0402_6.3V4Z

DDR_B_D56
DDR_B_D57

DDR_B_MA11
DDR_B_MA7

CD40

DDR_B_D50
DDR_B_D51

Layout Note:
Place near JDDRH

1U_0402_6.3V4Z

DDR_B_DQS#6
DDR_B_DQS6

+1.5V

1U_0402_6.3V4Z

DDR_B_D48
DDR_B_D49

2
@ 0_0402_5%

CD35

DDR_B_D40
DDR_B_D41

DDRB_CKE1 8
RD10 1
DDR_B_MA14

CD36

DDR_B_D34
DDR_B_D35

DDR_B_D30
DDR_B_D31

0.1U_0402_16V4Z

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_DQS#3
DDR_B_DQS3

CD37

DDR_B_D28
DDR_B_D29

0.1U_0402_16V4Z

DDR_B_D32
DDR_B_D33

DDR_B_D22
DDR_B_D23

CD38

DDR_B_MA13

DDR_B_DM2

0.1U_0402_16V4Z

DDRB_SCS1#

DDR_B_D20
DDR_B_D21

0.1U_0402_16V4Z

SM_DRAMRST# 8,14
DDR_B_D14
DDR_B_D15

10U_0805_6.3V6M

DDR_B_WE#
DDR_B_CAS#

10U_0805_6.3V6M

9
9

DDR_B_MA10

DDR_B_DM1

10U_0805_6.3V6M

DDR_B_BS0

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D12
DDR_B_D13

10U_0805_6.3V6M

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

DDR_B_MA[0..14]

10U_0805_6.3V6M

DDRB_CLK0
DDRB_CLK0#

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

DDR_B_DM[0..7]

DDR_B_D6
DDR_B_D7

10U_0805_6.3V6M

8
8

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CD34

DDR_B_D10
DDR_B_D11

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D[0..63]

CD44

DDR_B_DQS#1
DDR_B_DQS1

close to JDDRL.1

DDR_B_DQS#[0..7]

CD33

DDR_B_DQS[0..7]

CD32

DDR_B_D8
DDR_B_D9

DDR_B_D4
DDR_B_D5

CD31

DDR_B_D2
DDR_B_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

CD30

DDR_B_DM0

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

CD29

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

CD28
2.2U_0603_6.3V4Z

CD24
2.2U_0603_6.3V4Z

CD23
0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR3 SO-DIMM B
REVERSE TYPE

JDDRH

+V_DDR3_DIMM_REF

CD27
0.1U_0402_16V4Z

DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS# 8,14
PM_SMBDATA 14,16,23,27
PM_SMBCLK 14,16,23,27
+0.75VS

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FOX_AS0A626-UARN-7F
@

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
E

15

of

45

FSC

FSB

FSA

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

REF
MHz

266

100

33.3

14.318

96.0

48.0

133

100

33.3

14.318

96.0

48.0

200

100

33.3

14.318

96.0

48.0

DOT_96 USB
MHz
MHz

R108
80mA
0.1U_0402_16V4Z
1
2
0_0805_5% 1
1
C213
C214

+1.05VS

2
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
1
C216
C217
C218

C215

2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

+3VS

+3VS_CK505

+1.05VS_CK505

C219

R107
1
2
0_0805_5% 1

2
0.1U_0402_16V4Z

250mA
0.1U_0402_16V4Z
1
C207

C206

2
10U_0805_10V4Z

0.1U_0402_16V4Z
1
C209

C208

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
C211

C210

2
0.1U_0402_16V4Z

C212
0.1U_0402_16V4Z

+3VS_CK505
U4

SDA

PM_SMBDATA 14,15,23,27

SCL

10

PM_SMBCLK 14,15,23,27

VDD_PCI

CPU_0

71

CLK_CPU_BCLK 4

VDD_CPU

CPU_0#

70

CLK_CPU_BCLK# 4

CPU_1

68

CPU_1#

67

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

55

33.3

100

100

100

333

166

33.3

100

400

14.318
14.318

33.3

100

96.0

14.318

33.3

96.0

96.0

14.318

96.0

48.0

+1.05VS_CK505

48.0

2
2
C220
18P_0402_50V8J

Routing the
trace at
least 10mil

CLK_XTAL_IN

14.31818MHZ_16P

place 22ohm for damping resistor


when loading is two device,
32

C221
18P_0402_50V8J

CLK_48M_CR

23 CLK_48M_ICH

3IN1@2 R131

1 22_0402_5%

3IN1@1 R117

2 22_0402_5% CLK_FSA

FSB
R117 NO3IN1@
33_0402_5%
R111 1

23 CLK_14M_ICH

2
R116

5,8 CPU_BSEL0

CLK_FSA
1
2.2K_0402_5%

23

2
R109

5,8 CPU_BSEL2

CLK_FSC
1
10K_0402_5%

31 CLK_PCI_PCM
33 CLK_PCI_EC
21 CLK_PCI_ICH

0
1
0
1

CLK_EC

=
=
=
=

VDD_48

27

VDD_PLL3
VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

SRC_0#/DOT_96#

REF_0/FS_C/TEST_

REF_1

CLK_96M

25

CLK_96M#

LCDCLK/27M

28

LCDCLK#/27M_SS

29

SRC_1#

CPU
NB

PM@
PM@

2
2 0_0402_5%
0_0402_5%
2
2 0_0402_5%
0_0402_5%

1
R555 1 GM@
R556
GM@

2
2 0_0402_5%
0_0402_5%

21

GM@
GM@

SRC_2

32

CLK_PCIE_ICH

SRC_2#

33

CLK_PCIE_ICH#

CLK_PCIE_SATA 22

36

CLK_PCIE_SATA# 22

39

CLK_WLAN 27

40

CLK_WLAN# 27

CLK_DREF_SSC 8
CLK_DREF_SSC# 8

NB_SSC (100MHz)

SATA

WLAN

CKPWRGD/PD#
NC

23

H_STP_CPU#

53

CPU_STOP#

23

H_STP_PCI#

54

PCI_STOP#

CLK_XTAL_IN

XTAL_IN

CLK_XTAL_OUT

XTAL_OUT

SRC_6

57

CLK_NEW 27

SRC_6#

56

CLK_NEW# 27

ExpressCard

SRC_7

61

CLK_MCH_3GPLL 8

SRC_7#

60

CLK_MCH_3GPLL# 8

SRC_8/CPU_ITP

64

CLK_LAN 28

SRC_8#/CPU_ITP#

63

CLK_LAN# 28

13

PCI_1

SRC_9

44

R115 1

2 33_0402_5%

CLK_DDR

14

PCI_2

SRC_9#

45

R129 1

2 33_0402_5%

CLK_CARDBUS

15

PCI_3

R113 1

2 33_0402_5%

CLK_EC

SRC_10

50

16

PCI_4/SEL_LCDCL

R112 1

2 33_0402_5%

CLK_ICH

SRC_10#

51

17

PCIF_5/ITP_EN

18

VSS_PCI

VSS_REF

3G_PLL

LOM

SRC_11

48

SRC_11#

47

+3VS

22

VSS_48

CLKREQ_3#

37

CLKREQ_SATA#

26

VSS_IO

CLKREQ_4#

41

CLKREQ_WLAN#

CLKREQ_SATA#

69

VSS_CPU

CLKREQ_6#

58

CLKREQ_NEW#

30

VSS_PLL3

CLKREQ_7#

65

CLKREQ_3GPLL#

34

VSS_SRC

CLKREQ_9#

43

CLKREQ_9

CLKREQ_9

59

VSS_SRC

SLKREQ_10#

49

CLKREQ_10

CLKREQ_10

42

VSS_SRC

CLKREQ_11#

46

CLKREQ_11

CLKREQ_11

73

THERMAL_PAD

USB_1/CLKREQ_A#

21

CLKREQ_SATA# 23

CLKREQ_WLAN#

CLKREQ_WLAN# 27

CLKREQ_NEW#

CLKREQ_NEW# 27

CLKREQ_3GPLL#

CLKREQ_3GPLL# 8

2
R125
2
R124
2
R119
2
R118
2
R123
2
R126
2
R120

1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%

SLG8SP556VTR_QFN72_10X10

CLK_EC
R128
10K_0402_5%
GM@

2009/07/22

Deciphered Date

2012/07/22

Title

SCHEMATIC MB A4982

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

VGA (100MHz)

35

SRC_4

NB (96MHz)

CLK_PCIE_VGA 17
CLK_PCIE_VGA# 17

ICH-DMI

SRC_3

SRC_4#

CLK_DREF_96M 8
CLK_DREF_96M# 8

21

SRC_3#

FS_B/TEST_MODE

24

SRC_1

USB_0/FS_A

CK_PWRGD

SRC_0/DOT_96

R509 1
1
R510
1
R511 1
R512

CLK_ICH

CLK_14ICH

R122
10K_0402_5%
PM@

R127
10K_0402_5%

CLK_FSC

2 33_0402_5%

+3VS

R121
10K_0402_5%
@

19

SRC8/SRC8# (100MHz)
ITP/ITP# (266MHz)
Enable DOT96 & SRC1(UMA)
Enable SRC0 & 27MHz(DIS)

+3VS

72

11

34 CLK_PCI_DDR

CLK_ICH

CPU_BSEL1

CPU_BSEL1

5,8 CPU_BSEL1

VDD_REF

12

66

+/-30ppm
Y1

48.0

Reserved

CLK_XTAL_OUT

VDD_SRC

48.0

Document Number

Rev
B

401791
Wednesday, December 30, 2009
G

Sheet

16

of
H

45

10 PCIE_MTX_C_GRX_N[0..15]
10 PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

10 PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

10 PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

JMXMA

1
3
5
7
9
11
13
15
17
19
21
23

+MXM_B+

PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
C

PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4

PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2

25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
GND
GND
GND
GND

PEX_RX15#
PEX_RX15
GND
PEX_RX14#
PEX_RX14
GND
PEX_RX13#
PEX_RX13
GND
PEX_RX12#
PEX_RX12
GND
PEX_RX11#
PEX_RX11
GND
PEX_RX10#
PEX_RX10
GND
PEX_RX9#
PEX_RX9
GND
PEX_RX8#
PEX_RX8
GND
PEX_RX7#
PEX_RX7
GND
PEX_RX6#
PEX_RX6
GND
PEX_RX5#
PEX_RX5
GND
PEX_RX4#
PEX_RX4
GND
PEX_RX3#
PEX_RX3
GND
PEX_RX2#
PEX_RX2
GND

JMXMB

1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
RUNPWROK
5VRUN
GND
GND
GND

PRSNT2#
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
PEX_TX2#
PEX_TX2

2
4
6
8
10
12
14
16
18
20
22
24

PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1

+1.8VS

140mil(3.5A)

PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0

SUSP#

16 CLK_PCIE_VGA#
16 CLK_PCIE_VGA

27,29,33,36,39,41

+5VALW
8,21,27,28,33,34

PLT_RST#

4,33 EC_SMB_DA2
4,33 EC_SMB_CK2

26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108

19 VGA_CRT_HSYNC
19 VGA_CRT_VSYNC
19 VGA_CRT_CLK
19 VGA_CRT_DATA

PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6

20,23 VGA_HDMI_HPD
20 VGA_HDMI_CLK20 VGA_HDMI_CLK+

PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4

20 VGA_HDMI_TX220 VGA_HDMI_TX2+

PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3

20 VGA_HDMI_TX120 VGA_HDMI_TX1+

PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2

20 VGA_HDMI_TX020 VGA_HDMI_TX0+

109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231

QUASA_CA0330-230N20
@

110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232

PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0

VGA_CRT_R 19
VGA_CRT_G 19
VGA_CRT_B 19
LCD_TZCLK- 18
LCD_TZCLK+ 18

LCD_TZOUT2- 18
LCD_TZOUT2+ 18
LCD_TZOUT1- 18
LCD_TZOUT1+ 18
LCD_TZOUT0- 18
LCD_TZOUT0+ 18
LCD_TXCLK- 18
LCD_TXCLK+ 18

LCD_TXOUT2- 18
LCD_TXOUT2+ 18
LCD_TXOUT1- 18
LCD_TXOUT1+ 18
LCD_TXOUT0- 18
LCD_TXOUT0+ 18
LCD_EDID_DATA 18
LCD_EDID_CLK 18
VGA_ENVDD 18
B

VGA_ENBKL 33
VGA_HDMI_DATA 20
VGA_HDMI_CLK 20
+3VS

+MXM_B+
L28 2
1
KC FBM-L11-201209-221LMAT_0805
PM@
L27 2
1
KC FBM-L11-201209-221LMAT_0805
PM@
1
1
C224
C223
PM@
PM@
680P_0402_50V7K 68P_0402_50V8J
2
2

PEX_RX1#
GND
PEX_RX1
PEX_TX1#
GND
PEX_TX1
PEX_RX0#
GND
PEX_RX0
PEX_TX0#
GND
PEX_TX0
PEX_REFCLK#
PRSNT1#
PEX_REFCLK
TV_C/HDTV_Pr
CLK_REQ#
GND
PEX_RST#
TV_Y/HDTV_Y
RSVD
GND
RSVD
TV_CVBS/HDTV_Pb
SMB_DAT
GND
SMB_CLK
VGA_RED
THERM#
GND
VGA_HSYNC
VGA_GRN
VGA_VSYNC
GND
DDCA_CLK
VGA_BLU
DDCA_DAT
GND
IGP_UCLK#
LVDS_UCLK#
IGP_UCLK
LVDS_UCLK
GND
GND
RSVD
LVDS_UTX3#
RSVD
LVDS_UTX3
RSVD
GND
IGP_UTX2#
LVDS_UTX2#
IGP_UTX2
LVDS_UTX2
GND
GND
IGP_UTX1#
LVDS_UTX1#
IGP_UTX1
LVDS_UTX1
GND
GND
IGP_UTX0#
LVDS_UTX0#
IGP_UTX0
LVDS_UTX0
GND
GND
IGP_LCLK#/DVI_B_CLK#
LVDS_LCLK#
IGP_LCLK/DVI_B_CLK
LVDS_LCLK
DVI_B_HPD/GND
GND
RSVD
LVDS_LTX3#
RSVD
LVDS_LTX3
GND
GND
IGP_LTX2#/DVI_B_TX2#
LVDS_LTX2#
IGP_LTX2/DVI_B_TX2
LVDS_LTX2
GND
GND
IGP_LTX1#/DVI_B_TX1#
LVDS_LTX1#
IGP_LTX1/DVI_B_TX1
LVDS_LTX1
GND
GND
IGP_LTX0#/DVI_B_TX0#
LVDS_LTX0#
IGP_LTX0/DVI_B_TX0
LVDS_LTX0
DVI_A_HPD
GND
DVI_A_CLK#
DDCC_DAT
DVI_A_CLK
DDCC_CLK
GND
LVDS_PPEN
DVI_A_TX2#
LVDS_BL_BRGHT
DVI_A_TX2
LVDS_BLEN
GND
DDCB_DAT
DVI_A_TX1#
DDCB_CLK
DVI_A_TX1
2V5RUN
GND
GND
DVI_A_TX0#
3V3RUN
DVI_A_TX0
3V3RUN
GND
3V3RUN
FIX PIN
FIX PIN
QUASA_CA0330-230N20

+5VALW

160mil(4A)

+1.8VS

B+
C222
PM@

160mil(4A)

1
0.1U_0603_25V7K

1
C482
PM@
0.1U_0402_16V4Z
2

C483
PM@
0.1U_0402_16V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

17

of

45

LCD/PANEL BD. Conn.


+LCD_VDD

1
R623

C671
0.01U_0402_25V7K

ENVDD

5
4

2
47K_0402_5%

3
1

Inrush current = 0A

17 LCD_TXCLK+
17 LCD_TXCLK-

W=60mils
1

17 LCD_TZOUT0+
17 LCD_TZOUT0-

C672
4.7U_0805_10V4Z
@ 2

17 LCD_TZOUT2+
17 LCD_TZOUT2-

17 LCD_TZOUT1+
17 LCD_TZOUT1-

C673
0.1U_0402_16V4Z

17 LCD_TZCLK+
17 LCD_TZCLK+5V_LVDS_CAM
+5VS
+5VALW

CAM@
R104 1
2
0_0603_5%
R105 1
2
0_0603_5% @

21
21

USB20_P11
USB20_N11

USB20_P11_R
USB20_N11_R

@ WCM-2012-900T_0805
1
2
R181
0_0402_5%
CAM@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

LCD_TXOUT0+
LCD_TXOUT0LCD_TXOUT1+
LCD_TXOUT1LCD_TXOUT2+
LCD_TXOUT2-

BKOFF#

BKOFF#

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R629
1 R631

UMA_LCD_TXOUT0+ 10
UMA_LCD_TXOUT0- 10

LCD_TXOUT1+
LCD_TXOUT1-

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R633
1 R635

UMA_LCD_TXOUT1+ 10
UMA_LCD_TXOUT1- 10

LCD_TXOUT2+
LCD_TXOUT2-

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R637
1 R639

UMA_LCD_TXOUT2+ 10
UMA_LCD_TXOUT2- 10

LCD_TXCLK+
LCD_TXCLK-

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R641
1 R643

UMA_LCD_TXCLK+ 10
UMA_LCD_TXCLK- 10

LCD_TZOUT0+
LCD_TZOUT0-

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R645
1 R647

UMA_LCD_TZOUT0+ 10
UMA_LCD_TZOUT0- 10

LCD_TZOUT1+
LCD_TZOUT1-

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R649
1 R651

UMA_LCD_TZOUT1+ 10
UMA_LCD_TZOUT1- 10

LCD_TZOUT2+
LCD_TZOUT2-

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R653
1 R655

UMA_LCD_TZOUT2+ 10
UMA_LCD_TZOUT2- 10

LCD_TZCLK+
LCD_TZCLK-

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R657
1 R659

UMA_LCD_TZCLK+ 10
UMA_LCD_TZCLK- 10

LCD_EDID_CLK
LCD_EDID_DATA

0_0402_5%
0_0402_5%

2 GM@
2 GM@

1 R661
1 R663

UMA_LCD_EDID_CLK 10
UMA_LCD_EDID_DATA 10

1.5A
JLVDS

W=20mils

LCD_TZOUT0+
LCD_TZOUT0LCD_TZOUT1+
LCD_TZOUT1LCD_TZOUT2+
LCD_TZOUT233

17 LCD_EDID_CLK
17 LCD_EDID_DATA

0.1U_0402_16V4Z
1
2
C766 CAM@

1 CAM@ 2
R182
0_0402_5%
L23
2 2
1 1

NB side

LCD_TXOUT0+
LCD_TXOUT0-

+LCD_VDD

Q17B
2N7002DW-T/R7_SOT363-6

R626
100K_0402_5%

17 LCD_TXOUT2+
17 LCD_TXOUT2-

Q18
AO3413_SOT23

2
1

6 2

2
GM@ 0_0402_5%
1
2
R625
PM@ 0_0402_5%
R624

VGA_ENVDD

17 LCD_TXOUT1+
17 LCD_TXOUT1-

VGA_ENVDD

UMA_ENVDD

W=60mils

17

UMA_ENVDD

17 LCD_TXOUT0+
17 LCD_TXOUT0-

+3VS

R622
100K_0402_5%

C853
0.1U_0402_16V7K

Q17A
2N7002DW-T/R7_SOT363-6

10

LVDS conn.

VGA side

please link to VGA Conn. then link to LVDS Conn.

+3VS

R621
150_0603_5%

2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
GND GMD

+LCDVDD_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

LCD_TXCLK+
LCD_TXCLK-

1
C674
0.1U_0402_16V4Z

C675
4.7U_0805_10V4Z

LCD_TZCLK+
LCD_TZCLKLCD_EDID_CLK
LCD_EDID_DATA

+3VS

+LCDVDD_R

+LCD_INV
B+

C391
680P_0402_50V7K

Rated Current MAX:3000mA


L17 2
1
FBMA-L11-201209-221LMA30T_0805
C677
68P_0402_50V8J

+LCD_VDD

DAC_BRIG 33
INVT_PWM 33

ACES_87242-4001-09
@

R627
10K_0402_5%

2 L16
1
0_0805_5%

C676
0.1U_0402_16V4Z

For EMI request


1

C678
0.1U_0402_25V4Z

C392
680P_0402_50V7K

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

18

of

45

CRT CONNECTOR

D55

+5VS
D56

D57

D58

2
3

+3VS

If=1A

DAN217_SC59
@

C679
@ 0.1U_0402_16V4Z

DAN217_SC59
@

DAN217_SC59
@

+CRT_VCC_R
+CRT_VCC
F3
30mil
1
1
2
RB491D_SOT23-3
1.1A_6V_MINISMDC110F-2 1

JCRT

CRT_B_L

C680

C681

C682

1
C683

C684

C685

VSYNC
CRT_DDC_CLK

1
L21

2
10_0402_5%

HSYNC

D_CRT_VSYNC

1
L22

2
10_0402_5%

VSYNC

+CRT_VCC

1
2
R683 PM@ 0_0402_5%

17 VGA_CRT_VSYNC

CRT_VSYNC

C688
@

U39
SN74AHCT1G125GW_SOT353-5

1
R674
0_0402_5%

Q19A
10 UMA_CRT_DATA
17 VGA_CRT_DATA
10 UMA_CRT_CLK

17 VGA_CRT_CLK

1
2
R681 GM@ 0_0402_5%

10 UMA_CRT_VSYNC

P
OE#

5
1

C687
@

R685
0_0402_5%

1
R679
1
R680
1
R682
1
R684

2 CRT_DATA
GM@ 0_0402_5%
2
PM@ 0_0402_5%
2 CRT_CLK
GM@ 0_0402_5%
2
PM@ 0_0402_5%

+CRT_VCC

R677
4.7K_0402_5%

R678
4.7K_0402_5%

U38
SN74AHCT1G125GW_SOT353-5

D_CRT_HSYNC

1
Q19B

4
1

C850
33P_0402_50V8K
2
@

10P_0402_50V8J

5
1
P
OE#

1
2
R676 PM@ 0_0402_5%

1
10K_0402_5%

17 VGA_CRT_HSYNC

CRT_HSYNC

1
2
R675 GM@ 0_0402_5%

+3VS

2
R673

10P_0402_50V8J

10 UMA_CRT_HSYNC

2
0.1U_0402_16V4Z

16
17

ALLTO_C10532-11505-L_15P-T
@

+CRT_VCC

1
C686

G
G

R672

R671

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

R670

HSYNC
CRT_B_L
+CRT_VCC

VGA_CRT_B

L20
1
2
NBQ100505T-800Y_0402

CRT_DDC_DAT
CRT_G_L

2.2P_0402_50V8C

17

CRT_B

2.2P_0402_50V8C

UMA_CRT_B

CRT_G_L

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRT_R_L

2.2P_0402_50V8C

VGA_CRT_G

10

L19
1
2
NBQ100505T-800Y_0402

2.2P_0402_50V8C

UMA_CRT_G

17

CRT_G

2.2P_0402_50V8C

10

CRT_R_L

2.2P_0402_50V8C

VGA_CRT_R

L18
1
2
NBQ100505T-800Y_0402

CRT_R

2
GM@ 0_0402_5%
2
PM@ 0_0402_5%
2
GM@ 0_0402_5%
2
PM@ 0_0402_5%
2
GM@ 0_0402_5%
2
PM@ 0_0402_5%

2
1
150_0402_1%

17

1
R664
1
R665
1
R666
1
R667
1
R668
1
R669

2
1
150_0402_1%

UMA_CRT_R

2
1
150_0402_1%

10
1

CRT_DDC_DAT

2N7002DW-T/R7_SOT363-6
CRT_DDC_CLK

2N7002DW-T/R7_SOT363-6

C689
C849
470P_0402_50V8J
@
33P_0402_50V8K
2 @

C690
470P_0402_50V8J
2 @

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
E

19

of

45

OE
+3VS

VGA_DVI_TXC-

2 R164
0_0402_5%

HDMI_R_CK-

L9

4
VGA_DVI_TXC+

2
3

H@ OCE2012120YZF_0805
1
2 R166
@ 0_0402_5%

VGA_DVI_TXD0-

2 R167
0_0402_5%

H@ OCE2012120YZF_0805
1
2 R172
@ 0_0402_5%

VGA_DVI_TXD1-

2 R173
0_0402_5%

R148
R150
R152
R154

1
2 @ 0_0402_5%
3
+3VS
1
2 @ 0_0402_5%
4
0_0402_5%
1 IHDMI@ 2
0_0402_5%
1 IHDMI@ 2
R156
2
1
6
4.12K_0402_1% IHDMI@
7
10 PCIE_GTX_C_MRX_HDMI_P3

Vendor suggest un-mound for these.


R159 1 @
68_0402_5%

2
1
C251

2 VGA_DVI_TXC+
0.5P_0402_50V8B
@

VGA_DVI_TXD2- R160 1 @
68_0402_5%

2
1
C252

2 VGA_DVI_TXD2+
0.5P_0402_50V8B
@

VGA_DVI_TXD1- R161 1 @
68_0402_5%

2
1
C253

2 VGA_DVI_TXD1+
0.5P_0402_50V8B
@

HDMI_R_D0VGA_DVI_TXD0- R162 1 @
68_0402_5%

2
1
C254

4
VGA_DVI_TXD1+

VGA_DVI_TXD2-

30

DDC_EN

32

FUNCTION3
FUNCTION4

34
35

SDA_SOURCE

SDVO_SCLK

SCL_SOURCE

1 IHDMI@ 2
R689 0_0402_5%

10

VGA_DVI_TXC+
VGA_DVI_TXC-

13
14

VGA_DVI_TXD2+
VGA_DVI_TXD2-

16
17

VGA_DVI_TXD1+
VGA_DVI_TXD1-

19
20

2 VGA_DVI_TXD0+
0.5P_0402_50V8B
@

VGA_DVI_TXD0+
VGA_DVI_TXD0-

HDMI_R_D0+
HDMI_R_D1-

2
3

HDMI_HPD_R
R147 2
IHDMI@
R149
R151
R153
R155

HPD_SINK

Q47
BSH111_SOT23-3
HDMI@
1

2
2
1
1

1
1
2
2

1 4.7K_0402_5%

+3VS

0_0402_5% @
0_0402_5% @
0_0402_5% IHDMI@
0_0402_5% IHDMI@

2
1
R570
H@
10K_0402_5%
HDMI_HPD_R

+3VS

2
1
R571 H@
2.2K_0402_5%

+3VL

1
2
D54
CH751H-40PT_SOD323-2
H@

ANALOG2
IN_D4+
IN_D4-

48
47

PCIE_MTX_C_GRX_HDMI_P3 10
PCIE_MTX_C_GRX_HDMI_N3 10

IN_D3+
IN_D3-

45
44

PCIE_MTX_C_GRX_HDMI_P0 10
PCIE_MTX_C_GRX_HDMI_N0 10

OUT_D2+
OUT_D2-

IN_D2+
IN_D2-

42
41

PCIE_MTX_C_GRX_HDMI_P1 10
PCIE_MTX_C_GRX_HDMI_N1 10

22
23

OUT_D1+
OUT_D1-

IN_D1+
IN_D1-

39
38

PCIE_MTX_C_GRX_HDMI_P2 10
PCIE_MTX_C_GRX_HDMI_N2 10

1
5
12
18
24
27
31
36
37
43

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

OUT_D4+
OUT_D4OUT_D3+
OUT_D3-

+3VS

VGA_HDMI_HPD 17,23

1
2
R958 100K_0402_5%

+5VL
HDMI_HPD

THERMAL_PAD

49

2
C658
H@
0.1U_0402_16V4Z
1
2

STHDLS101TQTR QFN 48P HDMI SHIFTER_QFN48_7X7


IHDMI@

HDMI_R_D1+

Q48
BSH111_SOT23-3
HDMI@
D
3
VGA_HDMI_DATA 17

29

HPD_SOURCE

2 R177
0_0402_5%

28

ANALOG1(REXT)

H@ OCE2012120YZF_0805
1
2 R176
@ 0_0402_5%

FUNCTION1
FUCNTION2

SDVO_SDATA

L11

SCL_SINK
SDA_SINK

HDMI_SDATA

HDMI_R_CK+

L10

VGA_DVI_TXD0+

C250
H@
0.1U_0402_16V4Z

VGA_DVI_TXC-

HDMI_SCLK

VGA_HDMI_CLK 17

U37

R572
100K_0402_5%
H@
HDMI_HPD_R

74AHCT1G125GW_SOT353-5
H@

OE

C659
H@

1
0.1U_0402_16V4Z

+HDMI_5V_OUT

25

+5VS

R145
7.5K_0402_1%
IHDMI@

OE*

PCIE_GTX_C_MRX_HDMI_P3

VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V

2
11
15
21
26
33
40
46

+3VS
R141
20K_0402_5%
IHDMI@

PMEG2010AEH_SOD123 H@
F2 H@
2
1
2
1
D53
1.1A_6V_MINISMDC110F-2

+3VS

U7

C242
C243
C244
C245
C246
C247
C248
C249
IHDMI@
IHDMI@
IHDMI@
IHDMI@
IHDMI@
IHDMI@
IHDMI@
IHDMI@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

2 HDMI@ 1
RV67
0_0402_5%

2 R144
1
10K_0402_5%
IHDMI@

OE#

+3VS

HDMI_R_D2-

L12

17
17
17
17

VGA_HDMI_CLKVGA_HDMI_TX0VGA_HDMI_TX1VGA_HDMI_TX2-

17
17
17
17

VGA_HDMI_CLK+
VGA_HDMI_TX0+
VGA_HDMI_TX1+
VGA_HDMI_TX2+

H@ OCE2012120YZF_0805
1
2 R178
@ 0_0402_5%
CV165 1
CV167 1
CV169 1
CV171 1

1 HDMI@ 2
R690 499_0402_1%
HDMI_R_CK- 1 HDMI@ 2
R691 499_0402_1%
HDMI_R_D1- 1 HDMI@ 2
R692 499_0402_1%
HDMI_R_D1+ 1 HDMI@ 2
R693 499_0402_1%
HDMI_R_D0- 1 HDMI@ 2
R694 499_0402_1%
HDMI_R_D0+ 1 HDMI@ 2
R695 499_0402_1%
HDMI_R_D2+ 1 HDMI@ 2
R696 499_0402_1%
HDMI_R_D2- 1 HDMI@ 2
R697 499_0402_1%

HDMI_R_D2+

CV164 1
2 0.1U_0402_16V7K HDMI@
CV166 1
2 0.1U_0402_16V7K HDMI@

2 0.1U_0402_16V7K HDMI@

CV168 1
2 0.1U_0402_16V7K HDMI@
CV170 1
2 0.1U_0402_16V7K HDMI@

2 0.1U_0402_16V7K HDMI@

2 0.1U_0402_16V7K HDMI@

2 0.1U_0402_16V7K HDMI@

VGA_DVI_TXCVGA_DVI_TXD0VGA_DVI_TXD1VGA_DVI_TXD2VGA_DVI_TXC+
VGA_DVI_TXD0+
VGA_DVI_TXD1+
VGA_DVI_TXD2+

JHDMI
HDMI_HPD
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0D

2
G

+5VS

1 @
2
R698 100K_0402_5%

HDMI Connector

HDMI_R_CK+

VGA_DVI_TXD2+

HDMI_R_D0+
HDMI_R_D1Q20
2N7002_SOT23-3
HDMI@

HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

+HDMI_5V_OUT
HDMI_SCLK

20
21
22
23

1 R262
2
H@ 2.2K_0402_5%

HDMI_SDATA 1 R290
2
H@ 2.2K_0402_5%

@ TYCO_1939864-1_19P

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

20

of

45

PCI_CBE#[0..3]
31 PCI_AD[0..31]

PCI_CBE#[0..3]

31

+3VS

U9B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PCI

PCI_REQ#0

F1
G4
B6
A7
F13
F12
E6
F6

C/BE0#
C/BE1#
C/BE2#
C/BE3#

D8
B4
D6
A5

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

PLTRST#
PCICLK
PME#

C14
D4
R2

RP15

PCI_GNT#0 23
PCI_REQ#1 31
PCI_GNT#1 31

PCI_REQ#1
PCI_REQ#2

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

1
2
3
4

PCI_REQ#3

8.2K_0804_8P4R_5%
RP16
1
8
2
7
3
6
4
5

STRAP_A16 23
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_IRDY#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
CLK_PCI_ICH

8
7
6
5

PCI_IRDY#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#

31
31
31
31

8.2K_0804_8P4R_5%
RP17
1
8
2
7
3
6
4
5

PCI_IRDY# 31
PCI_PAR 31
PCI_RST# 31
PCI_DEVSEL# 31

PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

8.2K_0804_8P4R_5%

PCI_STOP# 31
PCI_TRDY# 31
PCI_FRAME# 31
PLT_RST# 8,17,27,28,33,34
CLK_PCI_ICH 16

R179
2
1
@ 10_0402_5%

CLK_PCI_ICH

C257

@ 10P_0402_50V8J

+3VS

+3VS
RP18

1
2
3
4

8
7
6
5

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

31

PCI_PIRQA#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

J5
E1
J6
C4

8.2K_0804_8P4R_5%

RP19

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676
ICH9R3@

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

H4
K6
F2
G2

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

1
2
3
4

8
7
6
5

8.2K_0804_8P4R_5%

27
27
27
27

C258 2
C259 2

1 0.1U_0402_16V7K NEW@
1 0.1U_0402_16V7K NEW@

PCIE_ITX_NEWRX_N1
PCIE_ITX_NEWRX_P1

PERN3
PERP3
PETN3
PETP3

PCIE_ITX_LANRX_N3
PCIE_ITX_LANRX_P3

PCIE_IRX_C_WLANTX_N4
PCIE_IRX_C_WLANTX_P4
PCIE_ITX_C_WLANRX_N4
PCIE_ITX_C_WLANRX_P4

C264 2
C265 2

1 0.1U_0402_16V7K WLAN@ PCIE_ITX_WLANRX_N4


1 0.1U_0402_16V7K WLAN@ PCIE_ITX_WLANRX_P4

G29
G28
H27
H26

PERN4
PERP4
PETN4
PETP4

E29
E28
F27
F26

PERN5
PERP5
PETN5
PETP5

SLP_CHG#
4
3 SLP_CHG_M4
2 USB_OC#11
1 USB_OC#10
10K_0804_8P4R_5%

5
6
7
8

23

SPI_CS#1

23 ICH_SPI_MOSI
USB_OC#0

25,33 USB_OC#0

RP22

5
6
7
8
+3VL

1
R183
1
R184

R277
330K_0402_5%
@

4 SLP_CHG_M3
USB_OC#0
3
USB_OC#8
2
USB_OC#2
1
10K_0804_8P4R_5%

USB_OC#2
USB_OC#3_D
SLP_CHG#
SLP_CHG_M3
SLP_CHG_M4

25 SLP_CHG#
25 SLP_CHG_M3
25 SLP_CHG_M4
27 EXP_CPPE#

USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11

USB_OC#9
2
10K_0402_5%
2 USB_OC#3_D
10K_0402_5%

Within 500 mils


1

PERN2
PERP2
PETN2
PETP2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

RP21

USBBIAS

1
2
R186
22.6_0402_1%

D15 @

L29
L28
M27
M26

C262 2
C263 2

+3V_SB

25,33 USB_OC#3

PERN1
PERP1
PETN1
PETP1

J29
J28
K27
K26

N29
N28
P27
P26

PCIE_IRX_C_LANTX_N3
PCIE_IRX_C_LANTX_P3
PCIE_ITX_C_LANRX_N3
PCIE_ITX_C_LANRX_P3

28
28
28
28

For LAN

For WLAN

PCIE_IRX_C_NEWTX_N1
PCIE_IRX_C_NEWTX_P1
PCIE_ITX_C_NEWRX_N1
PCIE_ITX_C_NEWRX_P1

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

D23
D24
F23

SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6

D25
E23

SPI_MOSI
SPI_MISO

AG2
AG1

2 USB_OC#3_D

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V27
V26
U29
U28

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3

8
8
8
8

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y27
Y26
W29
W28

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2

8
8
8
8

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB27
AB26
AA29
AA28

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1

8
8
8
8

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0

8
8
8
8

T26
T25

CLK_PCIE_ICH# 16
CLK_PCIE_ICH 16

DMI_CLKN
DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP

C29
C28
D27
D26

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3

Direct Media Interface

27
27
27
27

PCI - Express

U9D

For Express
Card

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47

SPI
USB

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

AF29
AF28

DMI_IRCOMP

AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

Lane reversal

Within 500 mils


1
R180

2
24.9_0402_1%

USB20_N0
USB20_P0
USB20_N1
USB20_P1

25
25
25
25

USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

25
25
27
27
26
26

USB20_N7 27
USB20_P7 27

USB20_N10
USB20_P10
USB20_N11
USB20_P11

32
32
18
18

+1.5VS

USB/B-Right
USB/B-Right
eSATA-USB
ExpressCard
BT
WiMax(WLAN)

Card reader(3 IN 1)
Int. Camera

USBRBIAS
USBRBIAS#

ICH9-M ES_FCBGA676
ICH9R3@

CH751H-40PT_SOD323-2

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1 R133
2
0_0402_5%

2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

21

of

45

C13

LAN_RSTSYNC

F14
G13
D14

2
2

29 AZ_RST_HD#
26 AZ_RST_MD#
8 AZ_RST_MCH#

R209 1
R210 1
R211 1

2 33_0402_5%
2 33_0402_5%MDC@
2 33_0402_5%IHDMI@

29 AZ_SDOUT_HD
26 AZ_SDOUT_MD
8 AZ_SDOUT_MCH

R212 1
R213 1
R214 1

2 33_0402_5%
2 33_0402_5%MDC@
2 33_0402_5%IHDMI@

AZ_SYNC

AZ_RST#

AZ_SDOUT

23

AZ_SDOUT

35

SATA_LED#

1ST HDD

25 SATA_IRX_C_DTX_N1
25 SATA_IRX_C_DTX_P1
25 SATA_ITX_DRX_N1
25 SATA_ITX_DRX_P1

GPIO56

B28
B27

GLAN_COMPI
GLAN_COMPO

AZ_SYNC

AF6
AH4

HDA_BIT_CLK
HDA_SYNC

AZ_RST#

AE7

HDA_RST#

AF4
AG4
AH3
AE5

29 AZ_SDIN0_HD
26 AZ_SDIN1_MD
8 AZ_SDIN2_MCH

SATA_LED#
2
10K_0402_5%

GLAN_COMP

B10

AZ_SDOUT

SATA_LED#

DPRSTP#
DPSLP#

AJ25
AE23

FERR#

AJ26

CPUPWRGD

AD22

H_PWRGOOD 5

IGNNE#

AF25

H_IGNNE# 4

INIT#
INTR
RCIN#

AE22
AG25
L3

H_INIT#
4
H_INTR
4
KB_RST# 33

NMI
SMI#

AF23
AF24

STPCLK#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDOUT
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16
AH16
AF17
AG17

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

2 56_0402_5%H_FERR#

KB_RST#

2
@ 10K_0402_5%
1
@ 56_0402_5%
1
56_0402_5%

+3VS
+1.05VS

H_FERR# 4
C

KB_RST#

R197 2 @

1 10K_0402_5%
2

+1.05VS
H_NMI
H_SMI#

AH27

4
4

1
2
R201
56_0402_5%

H_THERMTRIP#

H_STPCLK# 4

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AH11
AJ11
AG12
AF12

SATA_IRX_C_DTX_N4 25
SATA_IRX_C_DTX_P4 25
SATA_ITX_DRX_N4 25
SATA_ITX_DRX_P4 25

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AH9
AJ9
AE10
AF10

SATA_IRX_C_DTX_N5 25
SATA_IRX_C_DTX_P5 25
SATA_ITX_DRX_N5 25
SATA_ITX_DRX_P5 25

SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS

AH18
AJ18
AJ7
AH7

CLK_PCIE_SATA# 16
CLK_PCIE_SATA 16

H_THERMTRIP#
2
54.9_0402_1%

+3VS

1
+1.05VS
R199
330_0402_5%
@

Q10

1 2SC2411K_SOT23
@

H_THERMTRIP# 4,8

T5

D50
DAN202UT106_SC70-3
@

SATA ODD
ENTRIP1 38,40

eSATA
ENTRIP2 38,40
B

SATARBIAS
R216
24.9_0402_1%

10mils width
less than
500mils

ICH9-M ES_FCBGA676
ICH9R3@

H_FERR#

H_DPRSTP# 5,8,43
H_DPSLP# 5
FERR# R195 1

1
R191
2
R192
2
R193

H_DPRSTP#

PAD

TP12

AG7
AE8

GATEA20 33
H_A20M# 4

AG26 THRMTRIP_ICH# 1
R208
TP12
AG27

THRMTRIP#

AG5

AH13
AJ13
AG14
AF14

N7
AJ27

2 33_0402_5%
2 33_0402_5%MDC@
2 33_0402_5%IHDMI@

1 R198
2
24.9_0402_1%

LAN_TXD_0
LAN_TXD_1
LAN_TXD_2

GATEA20
GATEA20

A20GATE
A20M#

29 AZ_SYNC_HD
26 AZ_SYNC_MD
8 AZ_SYNC_MCH

R205 1
R206 1
R207 1

+1.5VS
AZ_BITCLK

D13
D12
E13

LPC_FRAME# 33,34

J3
J1

2 33_0402_5%
2 33_0402_5%MDC@
2 33_0402_5%IHDMI@

LAN_RXD0
LAN_RXD1
LAN_RXD2

K3

LDRQ0#
LDRQ1#/GPIO23

GLAN_CLK

FWH4/LFRAME#

33,34
33,34
33,34
33,34

E25

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

K5
K4
L6
K2

INTVRMEN
LAN100_SLP

2 SM_INTRUDER#

R200 1
R202 1
R203 1

1
R215

B22
A22

23 ICH_INTVRMEN
23 LAN100_SLP

LPC

J2

1
SHORT PADS
C274 1
1U_0402_6.3V6K

29 AZ_BITCLK_HD
26 AZ_BITCLK_MD
8 AZ_BITCLK_MCH

+3VS

RTCRST#
SRTCRST#
INTRUDER#

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

R196 1
1M_0402_5%

A25
F20
C22

RTC

1
SHORT PADS
C273 1
1U_0402_6.3V6K

2ICH_SRTCRST#

RTCX1
RTCX2

ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#

CPU

R194 1
20K_0402_5%

C23
C24

J1

ICH_RTCRST#

ITPM Setting, near DDR Door

U9A
ICH_RTCX1
ICH_RTCX2

LAN / GLAN

CMOS Setting, near DDR Door


2

C272
12P_0402_50V8J
2
1

C271
0.1U_0402_16V4Z

R190 1
20K_0402_5%

IN

IHDA

+CHGRTC

OUT

NC

SATA

32.768KHZ_12.5P_MC-306 X1
3 NC

+RTCVCC

R189
10M_0402_5%
2
1

D10
BAS40-04_SOT23-3
+RTCVCC

C270
12P_0402_50V8J
2
1

+RTCBATT

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

22

of

45

2 4.7K_0402_5%
2 4.7K_0402_5%

for EMI request


ICH_SMBDATA

CLK_14M_ICH

R242 1

+3VS

R244 1
R245 1

M6

PM_SYNC#
EC_LID_OUT#

33 EC_LID_OUT#

10K_0402_5%
2
2 @ 8.2K_0402_5%

R246 1

+3VS

ACIN

R250 1
R251 1

+3V_SB

1 R807

+3VS

SB_WAKE#

16
16

SERIRQ
EC_THERM#

10K_0402_5%

1
2
R248 330K_0402_5%
1
D12

+3VS
33,35,37

1K_0402_5%

OCP#

2
CH751H-40PT_SOD323-2

8.2K_0402_5%
10K_0402_5%

100K_0402_5%

PM_CLKRUN#

31 PM_CLKRUN#

THRM# not
used, 8.2K to 27,33 SB_WAKE#
31,33,34 SERIRQ
10K PU to
33 EC_THERM#
+3VS.

ICH_ACIN

2
2

H_STP_PCI#
H_STP_CPU#

SB_WAKE#
SERIRQ
EC_THERM#
VGATE

8,33,43 VGATE
T6

EC_SMI#
EC_SCI#

OCP#
ICH_ACIN

OCP#

2HDD_DET#
EC_SMI#
EC_SCI#

33
EC_SMI#
33
EC_SCI#
17,20 VGA_HDMI_HPD

+3VS
+3V_SB

R253 1

R255 2
R257 2

1 @ 10K_0402_5%
100K_0402_5%
1

TP11

PAD

8.2K_0402_5%

BT_DET#
26

GPIO57

2HDD_DET#
BT_DET#

BT_DET#

16 CLKREQ_SATA#

+3VS

R809 2 100K_0402_5%

CIR_EN#

CIR_EN#
GPIO57

Assert = iTPM Physical Presence Enable


De-assert = iTPM disable
**Only used in iAMT w/ME Firmware
Desktop Platform used only

CLGPIO5
Mobil Platform
GPIO57

ICH9M Strap Pin


+3VS

1
R258 @

2
1K_0402_5%

SB_SPKR

29
SB_SPKR
8 MCH_ICH_SYNC#

iTPM Physical Presence

ICH_SPI_MOSI 21

T7
T8
T9

PAD
PAD
PAD

ICH_TP3
TP8
TP9
TP10

SMBALERT#/GPIO11

A14
E19

STP_PCI#
STP_CPU#

L4
E20
M5
AJ23

CLKRUN#
WAKE#
SERIRQ
THRM#

D21

VRMPWRGD

A20

TP11

AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8
M7
AJ24
B21
AH20
AJ20
AJ21

SLP_S3#
SLP_S4#
SLP_S5#
S4_STATE#/GPIO26

C10

S4_STATE#

PWROK

G20

ICH_PWROK

PMSYNC#/GPIO0

A17

GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10

DPRSLPVR/GPIO16
BATLOW#

D20

RSMRST#

D22

CLPWROK

1
R261

SB_SPKR
2
1K_0402_5%

SB_SPKR

2
@ 1K_0402_5%

PCI_GNT#0 21

2
@ 1K_0402_5%

SPI_CS#1 21

1
R267

2
@ 1K_0402_5%

0
0
1
1

CL_DATA0
CL_DATA1

F22
C19

CL_DATA0 8

CL_VREF0
CL_VREF1

C25 +CL_VREF0_ICH
A19

CL_RST0#
CL_RST1#

F21
D18

MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9

A16
C18
C11
C20

PCI_GNT#3

Low= A16 swap override Enable


High= Default* (Internal pull-up)

Width:Spacing
12mil:12mil

SUS_PWR_ACK 1
R256

2
10K_0402_5%

SUS_PWR_ACK

ICH_INTVRMEN

R254
453_0402_1%

2
C278
0.1U_0402_16V4Z

+3V_SB

Mobile Platform used only


Desktop Platform used only

ICH8M LAN100 SLP Strap


(Internal VR for VccLAN1.05 and VccCL1.05)
Low = Internal VR Disabled
ICH_LAN100_SLP High = Internal VR Enabled(Default)

Flash Descriptor Security Override Strap


GPIO33

Low= Descriptor Security override


High= Default* (Internal pull-up)

DMI Termination Voltage


GPIO49 Low= Desktop used
High= Mobile* (Internal pull-up)

XOR Chain Entrance Strap


ICH_TP3
(Internal pull-up)
0
+3VS

R266

@ 1K_0402_5%

R268

ICH_TP3
@ 1K_0402_5%

AZ_SDOUT 22

HDA_SDOUT
(Internal pull-down)
0

Description
RSVD

Enter XOR Chain

Normal Operation

Set PCIE port config bit 1

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

(Default)

Compal Electronics, Inc.

Compal Secret Data


2009/07/22

Issued Date

22

LAN100_SLP 22

Security Classification

RSMRST# circuit

Low = Internal VR Disabled


ICH_INTVRMEN High = Internal VR Enabled(Default)
+RTCVCC

1
2
+3V_SB
R243
4.7K_0402_5%
D11A
BAV99DW-7_SOT363

R252
3.24K_0402_1%

CL_RST#0 8

GPIO10

2
330K_0402_5%
2
@ 0_0402_5%

+3V_SB

EC_RSMRST# 33

8,33

Internal VR Enable Strap


(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

1
R259
1
R260

1 R275
2
1K_0402_5%

+3VS
CL_CLK0

RESERVED
SPI
PCI
LPC* (Default)

A16 Swap Override Strap

ICH_PWROK

F24
B19

Low= Disable
High= iTPM enable by MCH strap*

0
1
0
1

STRAP_A16 21

R6

ICH9-M ES_FCBGA676
ICH9R3@

Low= *Default
High= "No Reboot"

2
1
R249
2.2K_0402_5%

CK_PWRGD 16
ICH_PWROK

B16

PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction

1
R265

R5

SLP_M#

Boot BIOS Strap (Internal pull-up)


1
R263

PBTN_OUT# 33

+3V_SB

MMBT3906_SOT23-3

D11B
BAV99DW-7_SOT363

1
2
R247 0_0402_5%
SB_RSMRST#

CL_CLK0
CL_CLK1

No Reboot Strap (Internal pull-up)


+3VS

B13 ICH_LOW_BAT#
R3

2 R239
1
0_0402_5% @
1 Q11 3

SB_RSMRST#
1
2
R241
10K_0402_5%

PM_DPRSLPVR 8,43

PWRBTN#

Internal TPM Strap(Internal pull-down)


SPI_MOSI

M2

LAN_RST#

CK_PWRGD

PM_SLP_S3# 33
PM_SLP_S4# 33
PM_SLP_S5# 33

2
@ 10K_0402_5%
1
8.2K_0402_5%

+3V_SB

1
R235
2
R237

ICH_LOW_BAT#

PM_CLKRUN#

C16
E16
G17

S4_STATE#

2
B

8.2K_0402_5%

P1

SUSCLK

R240 1

clocks

CLK_14M_ICH 16
CLK_48M_ICH 16

2
1
2
C276
@ 4.7P_0402_50V8C
2
1
2
C277
@ 4.7P_0402_50V8C

+3VS

+3V_SB

4 XDP_DBRESET#

SUS_STAT#/LPCPD#
SYS_RESET#

H1 CLK_14M_ICH
AF3 CLK_48M_ICH

EC_LID_OUT#

R4
G19

BIOS need to
set GPIO

BT_PWR# 26
BT_RST# 26

10K_0402_5%

RI#

XDP_DBRESET#

CLK14
CLK48

SPK_SEL 29

F19

AH23
AF19
AE21
AD20

R238 1

ICH_RI#

SMB

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

10K_0402_5%
LINKALERT#
10K_0402_5%
ME_EC_CLK1
10K_0402_5%
ME_EC_DATA1
10K_0402_5%
ICH_RI#
10K_0402_5% XDP_DBRESET#

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

2
2
2
2
2

2N7002DW-T/R7_SOT363-6

G16
A13
E17
C17
B18

1
1
1
1
1

ICH_SMBCLK

3
Q4B

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1

SATA
GPIO

R230
R232
R233
R234
R236

+3V_SB

1
R228
@ 10_0402_5%
CLK_48M_ICH
1
R229
@ 10_0402_5%

U9C

Q4A
2N7002DW-T/R7_SOT363-6 4

14,15,16,27 PM_SMBCLK
D

+3V_SB

14,15,16,27 PM_SMBDATA

R221 1
R224 1

Power MGT

1 R223
1
R226
1

SYS / GPIO

4.7K_0402_5% 2
4.7K_0402_5% 2

MISC
GPIO
Controller Link

2 R225
2 R219
2

0_0402_5% 1
0_0402_5% 1

+3VS

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

23

of

45

U9F

1
C281
0.1U_0402_16V4Z

PJ37

+3VS

+5VS

2N7002DW-T/R7_SOT363-6
1
6
Q16A
STAR@
Q16B
STAR@

1 R594
2
330K_0402_5%
@
1
2
C851
STAR@
0.1U_0402_25V6
SBPWR_EN#

1 R593
2
47K_0402_5%
STAR@

1 R597
2
47K_0402_5%
STAR@

+VSB

D14
CH751H-40PT_SOD323-2
1

+5VALW
+1.5VS_PCIE_ICH
10U_0805_10V4Z

2.2U_0603_6.3V6K

1
1

+
C293
220U_6.3V_M_R15

C294

C295

C296

2 10U_0805_10V4Z
2

+1.5VS

+1.5VS_SATAPLL_ICH

L15 1
2
MBK1608121YZF_0603
C304
10U_0805_10V4Z

1
C305
1U_0402_6.3V4Z
2

AE1
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25

+ICH_V5REF_SUS
2
1
R270
2
100_0402_5%
C289
1U_0402_6.3V4Z
1

+5V_SB

L14 2
1
KC FBM-L11-201209-221LMAT_0805

+1.5VS

+3V_SB

A6

VCCRTC6uA
V5REF

at G3 state

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

23mA VCCDMIPLL

R29

48mA VCC_DMI[1]
VCC_DMI[2]

W23
Y23

2mA

V5REF_SUS 2mA
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]

1634mA

646mA

VCCA3GP

2N7002DW-T/R7_SOT363-6
4

+ICH_V5REF_SUS

+ICH_V5REF
1
R269 1
100_0402_5%
C284
1U_0402_6.3V4Z
2

+5VALW

33,36 SBPWR_EN#

D13
CH751H-40PT_SOD323-2
1

JUMP_43X39 @

+5V_SB

+ICH_V5REF

CORE

1
C280
0.1U_0402_16V4Z

VCCSATAPLL

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]

AB23
AC23

308mAVCC3_3[01]
VCC3_3[02]
VCC3_3[07]

AG29
AJ6
AC10

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

AD19
AF20
AG24
AC20

VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

B9
F9
G3
G6
J2
J7
K7

2mA

11mA
11mA

47mA
AJ19

V_CPU_IO[1]
V_CPU_IO[2]

VCCP_CORE

1
C279
1U_0402_6.3V4Z

PCI

A23

+RTCVCC

1342mA
C307
1U_0402_6.3V4Z

close to AE15

Symbol

S0

S3

close to AF11

S4/S5

VCC_1_05

VCCLAN3_3

VCCLAN3_3

VCCCL1_5

VCC_1_5_A

VCCCL3_3

VCCCL3_3

VCCCL1_05

VCC_1_05

VCCCL3_3

VCCCL3_3

close to AC9

+1.5VS
C314

VCCSUS1_05

VCC_1_5_A

VCCSUS3_3

VCC_1_05

VCCSUS3_3

VCCSUS3_3

C315

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

VCCSUS3_3

Internal voltage regulators power these wells inside the ICH9


and current for this rail is accounted for in the sourcing voltage
rail current requirements.
close to AC7

close to AC14

C317
0.1U_0402_16V4Z

VCCLAN1_05_INT_ICH

1
C318
0.1U_0402_16V4Z

+3VS

+1.5VS

C324
0.1U_0402_16V4Z

+3VS

+1.05VS

+1.05VS

1
C290
0.1U_0402_16V4Z

C291
0.1U_0402_16V4Z

C297

0.1U_0402_16V4Z
1
C298

0.1U_0402_16V4Z
2

close to AG24

0.1U_0402_16V4Z
1

C299
C300
0.1U_0402_16V4Z
2

close to AD19

0.1U_0402_16V4Z
1

C301
C302
0.1U_0402_16V4Z
2
2

close to B9, G6, K7

C303
0.1U_0402_16V4Z
2

close to AJ6

+ICH_HDA
R271

AC8 TP_VCCSUS1_05_ICH_1
F17 TP_VCCSUS1_05_ICH_2

@
@

PAD
PAD

T10
T11

VCCSUS1_5[1]

AD8

VCCSUS1_5[2]

F18

R272
C306
0.1U_0402_16V4Z

NIHDMI@
0_0603_5%
0_0603_5%
IHDMI@

+3VS
+1.5VS

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

A18
D16
D17
E22

VCCSUS3_3[05]

AF1

C310

0.1U_0402_16V4Z

VCC1_5_A[18]
VCC1_5_A[19]

C311
C312
0.022U_0402_16V7K 0.022U_0402_16V7K
2
2

AC21

VCC1_5_A[20]

G10
G9

VCC1_5_A[21]
VCC1_5_A[22]

AC12
AC13
AC14

VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]

AJ5

VCCUSBPLL 11mA

AA7
AB6
AB7
AC6
AC7

VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]

A10
A11

VCCLAN1_05[1]
VCCLAN1_05[2]

A12
B12

VCCLAN3_3[1]
VCCLAN3_3[2] 78mA

23mA

A27

VCCGLANPLL

D28
D29
E26
E27

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]

80mA

1mA

ICH9-M ES_FCBGA676
ICH9R3@

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

+3V_SB

G22
G23

VCCCL3_3[1]
VCCCL3_3[2]

A24
B24

1
C313
0.1U_0402_16V4Z

close to AF1 2

close to T1

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

VCCCL1_05
VCCCL1_5

NIHDMI@
0_0603_5% +3V_SB
+VCCSUS1_5_ICH_INT
R274
0_0603_5%
IHDMI@
C309
0.1U_0402_16V4Z
R273

+VCCSUS1_5_ICH_INT

AC18
AC19

VCCGLAN3_3

C292
4.7U_0805_10V4Z

+3VS

close to AG29

VCCCL1_05_INT_ICH
VCCCL1_5_INT_ICH
1
+3VS

C320
1U_0402_6.3V4Z

1
1

C321
0.1U_0402_16V4Z

C319
0.1U_0402_16V4Z

2009/07/22

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

Title

Date:

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

Compal Electronics, Inc.


2012/07/22

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

ICH9-M ES_FCBGA676
ICH9R3@

Compal Secret Data

Security Classification

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

close to G22

close to G23

Issued Date

C287
4.7U_0805_10V4Z

A26
1

C286
10U_0805_10V4Z

VCC1_5_A[17]

1
C323
0.1U_0402_16V4Z
2

AC9

GLAN POWER

C322
0.1U_0402_16V4Z
2

+1.5VS

1
C285

+1.5VS

L13 1
2
MBK1608121YZF_0603

VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

1
C316
0.1U_0402_16V4Z

+1.5VS_DMIPLL_ICH
0.01U_0402_16V7K

212mA

USB CORE

C283
0.1U_0402_16V4Z

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

close to AJ5

+1.5VS

AJ3

AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29

1
C282
0.1U_0402_16V4Z

+ICH_SUSHDA

ATX

VCCLAN1_05

VCCSUS1_5

C308
1U_0402_6.3V4Z

AJ4

VCCSUS1_05[1]
VCCSUS1_05[2]

ARX

VCCPSUS

VCCPUSB

+1.5VS

VCCHDA

VCCSUSHDA

U9E

+1.05VS

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

24

of

45

SATA HDD Conn.


+5VS

1.2A
1

SATA ODD Conn


+5VS

Place closely JP25 SATA CONN.

C697
10U_0805_10V4Z

C698
0.1U_0402_16V4Z

C699
0.1U_0402_16V4Z

C700
0.1U_0402_16V4Z

C721

C722

C723
@
10U_0805_10V4Z 1U_0402_6.3V4Z
2
2

10U_0805_10V4Z

USB Board

Place component's closely ODD CONN.

1.1A

W=60mils

1
C724
0.1U_0402_16V4Z

1.4A
U42

+5VALW

C725
0.1U_0402_16V4Z

1
2
3
4

33

USB_EN#

GND
IN
IN
EN#

+USB_VCCA

C752
4.7U_0805_10V4Z
2 @

for 17" expansion using

JODD

JHDD

GND
A+
AGND
BB+
GND

24
23

GND
GND

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

1
2
3
4
5
6
7

SATA_ITX_C_DRX_P1 C713 1
SATA_ITX_C_DRX_N1 C715 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_ITX_DRX_P1 22
SATA_ITX_DRX_N1 22

SATA_IRX_DTX_N1
SATA_IRX_DTX_P1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_IRX_C_DTX_N1 22
SATA_IRX_C_DTX_P1 22

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

C717 1
C719 1

15
14

GND
GND

+5VS

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

SATA_ITX_C_DRX_P4_ODD
SATA_ITX_C_DRX_N4_ODD

+5VS

SANTA_19A202-1_22P
@
this is temp. footprint

1
2
3
4
5
6
7
8
9
10
11
12
GND
GND

+5VS

SANTA_206401-1_RV
@

+3VS

JODDB

SATA_IRX_DTX_N4_ODD
SATA_IRX_DTX_P4_ODD

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

USB_OC#0 21,33

G528_SO8

for 16" use

For EMI request


1
1000P_0402_50V7K

2
C693

8
7
6
5

OUT
OUT
OUT
FLG

1
2
3
4
5
6
7
8
9
10
11
12
13
14

+USB_VCCA
SATA_IRX_DTX_P4
SATA_IRX_DTX_N4

2 16@
2 16@

0.01U_0402_25V7K
0.01U_0402_25V7K

SATA_IRX_DTX_N4_ODD
SATA_IRX_DTX_P4_ODD

C735 1
C736 1

2 16@
2 16@

0.01U_0402_25V7K
0.01U_0402_25V7K

SATA_IRX_DTX_P4
SATA_IRX_DTX_N4

C732 1
C731 1

2 17@
2 17@

0.01U_0402_25V7K
0.01U_0402_25V7K

SATA_ITX_C_DRX_N4
SATA_ITX_C_DRX_P4

C730 1
C729 1

2 17@
2 17@

0.01U_0402_25V7K
0.01U_0402_25V7K

1
2
3
4
5
6
7
8
9
10
11
12
13
14

SATA_ITX_C_DRX_N4
SATA_ITX_C_DRX_P4

E&T_6905-E12N-00R
@

SATA_ITX_C_DRX_P4_ODD C733 1
SATA_ITX_C_DRX_N4_ODDC734 1

JUSBB

W=60mils

21
21

USB20_N0
USB20_P0

21
21

USB20_N1
USB20_P1

1
2
3
4
5
6
7
8
9
10
11
12
GND
GND

E&T_6905-E12N-00R
@

SATA_IRX_C_DTX_P4 22
SATA_IRX_C_DTX_N4 22
SATA_ITX_DRX_N4 22
SATA_ITX_DRX_P4 22

eSATA/USB
1

+USB_VCCB

+USB_VCCB

R952
43K_0402_1%
@

R130 1

2 0_0402_5%

USB20_P3_R

USB20_N3

R132 1

2 0_0402_5%

USB20_N3_R

1
2
3
4

+3VALW

U52

21

USB20_P3

21

USB20_N3

21 SLP_CHG_M4
USB20_P3_S
USB20_N3_S

1D+

VCC

USB20_N3_S

1D-

USB20_P3

2D+

D+

USB20_P3_R

USB20_N3

2D-

D-

USB20_N3_R

GND

OE#

+USB_VCCB

2
C354
0.1U_0402_16V4Z
@ 1

1OE#
2OE#
3OE#
4OE#

2
5
9
12

1A
2A
3A
4A

14

VCC

1B
2B
3B
4B
GND

0.1U_0402_16V4Z @
2

U53

1
4
10
13

21 SLP_CHG_M3

C353
1

USB20_P3_S

USB20_P3_S_O
3
USB20_N3_S_O
6
2 100_0402_5% @
8 R114 1
11

10

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

W=60mils
1
USB_OC#3 21,33

C692
1000P_0402_50V7K

0.1U_0402_16V4Z

2
1

eSATA/USB Conn

3
PJDLC05_SOT23-3

JESATA

USB20_N3_R
USB20_P3_R

22 SATA_ITX_DRX_P5
22 SATA_ITX_DRX_N5
22 SATA_IRX_C_DTX_N5
22 SATA_IRX_C_DTX_P5

C739 1
C740

2
1

0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_ITX_C_DRX_P5
SATA_ITX_C_DRX_N5

C742 1
C744

2
1

0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_IRX_DTX_N5
SATA_IRX_DTX_P5

1
2
3
4

VBUS
DD+
GND

5
6
7
8
9
10
11

GND
A+
AGND
BB+
GND

USB

ESATA

SHIELD
SHIELD
SHIELD
SHIELD

12
13
14
15

FOX_3Q318111
@

2009/07/22

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C750

SN74CBT3125PWRG4_TSSOP14
@
OE#
function
A port= B port
H
disconnect
L

+
C749

C743
4.7U_0805_10V4Z
@
2
D62 @

For EMI request

Issued Date

C84

SLP_CHG# 21

TS3USB221RSER_QFN10_2x1P5~D
@
S
OE#
function
X
disconnect
H
L
L
D=1D
H
L
D=2D

1000P_0402_50V7K

220U_6.3V_M_R15

8
7
6
5

G528_SO8

please close to SB under 30mm


R950
51K_0402_1%
@

R951
51K_0402_1%
@

+USB_VCCB

+USB_VCCB

U40

33 USB_CHG_EN#

USB20_P3_S_O
USB20_N3_S_O

W=60mils

1.4A

+5VALW

mount the two resistor


when un-mount USB sleep$charge function

R949
75K_0402_1%
@

USB20_P3

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

25

of

45

BlueTooth Interface

MDC 1.5 Conn.

+3VS

+3VS

C751 BT@
0.1U_0402_16V4Z

3
1

21
USB20_P5
21
USB20_N5
27 WLAN_BT_CLK
23
BT_DET#

10
9
8
7
6
5
4
3
2
1

BT@ 2
1
R721
0_0402_5%

27 WLAN_BT_DATA

1
R723 @

+3VS

2
4.7K_0402_5%

+BT_VCC
(MAX=200mA)
1
C755
4.7U_0805_10V4Z
BT@

C756
0.1U_0402_16V4Z
BT@

10
9
8
7
6
5
4
3
2
1

1
3
5
7
9
11

22 AZ_SDOUT_MD
22 AZ_SYNC_MD

AZ_SDIN1_MD_R

22 AZ_RST_MD#

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

+MDC

2
4
6
8
10
12

1
2
R731 NIHDMI@
1
2
R733 IHDMI@

+3V_SB
0_0603_5%
+VCCSUS1_5_ICH_INT
0_0603_5%

+3V_SB

AZ_BITCLK_MD 22

2BT_RESET#
0_0402_5%

C754
0.1U_0402_16V4Z
@

GND2
GND1
JMDC

+BT_VCC

R736
10_0402_5%
@

GND
GND
GND
GND
GND
GND

1 BT@
R722

BT_RST#

12
11

Q22 BT@
AO3413_SOT23

ACES_87213-1000G
@

22 AZ_SDIN1_MD

2
R737

1 AZ_SDIN1_MD_R
33_0402_5% MDC@

BT@R724
BT@R724
4.7K_0402_5%

13
14
15
16
17
18

23

JBT

Inrush current = 0A

C761
C762
C763
C764
0.1U_0402_16V4Z
1000P_0402_50V7K
0.1U_0402_16V4Z
4.7U_0805_10V4Z
2 MDC@
2 MDC@
2 MDC@
2 MDC@

Bluetooth Connector

ACES_88018-124G
@

C768
10P_0402_50V8J
@

Connector for MDC Rev1.5


2

1
1
2
R719
47K_0402_5% 2
BT@
C847
0.01U_0402_25V7K
BT@
1

BT_PWR#

1
G

23
D

+3V_SB

C753
0.1U_0402_16V7K
BT@

R718
100K_0402_5%
BT@

+MDC

For EMI request

KEYBOARD
KEYBOARD
CONN. for 17" CONN. for 16"
KSI[0..7]
KSO[0..17]

KSI[0..7]

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

KSO16

33

KSO[0..17] 33

JKB2

Touch/B Connector

please close to JKB1

JKB1
JKB34
KSO16
KSO17
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
CAPS_LED#
NUM_LED#

ACES_88170-3400
@

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

JKB34
KSO16

1
2
R755 300_0402_5%

+3VS

KSO17
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
2
1
CAPS_LED# R762 300_0402_5%

+3VS
CAPS_LED# 33

NUM_LED#

NUM_LED# 33

ACES_88170-3400
@

1
C821
KSO17
1
C818
KSO2
1
C789
KSO1
1
C790
KSO0
1
C791
KSO4
1
C792
KSO3
1
C795
KSO5
1
C796
KSO14
1
C797
KSO6
1
C798
KSO7
1
C799
KSO13
1
C800
KSO8
1
C801
KSO9
1
C802
KSO10
1
C803
KSO11
1
C804
KSO12
1
C805
KSO15
1
C807
KSI7
1
C808
KSI2
1
C810
KSI3
1
C811
KSI4
1
C812
KSI0
1
C813
KSI5
1
C814
KSI6
1
C815
KSI1
1
C816
CAPS_LED#
1
C817
NUM_LED#
1
C819

JTOUCH

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

1
2
3
4

+5VS
33
33

TP_CLK
TP_DATA

1
2
3 GND
4 GND

5
6

ACES_85201-0405N
@

2
1
3
D80
@
PJDLC05_SOT23-3

SW/B Connector
JPOWER
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
GND 11
GND 12

ON/OFFBTN#
KSO0

ON/OFFBTN# 33,35
KSO0
33
KSI1
33 EC_PLAYBTN#
KSI3
33 EC_MUTEBTN#
KSI5
33 EC_FRDBTN#
KSI2
33 EC_REVBTN#

ON/OFFBTN#

C691 1

2@ 220P_0402_50V7K

KSI1

C701 1

2@ 220P_0402_50V7K

KSI3

C702 1

2@ 220P_0402_50V7K

KSI5

C710 1

2@ 220P_0402_50V7K

KSI2

C709 1

2@ 220P_0402_50V7K

For EMI request

ACES_85201-1005N
@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

26

of

45

+3V_WLAN

PCIe Mini Card-WLAN/WiMax

Default
PJ18
2
1 1

+3V_WLAN

+3VS

@ JUMP_43X79
+3V_WLAN
+1.5VS

JWLAN
26 WLAN_BT_DATA
26 WLAN_BT_CLK
16 CLKREQ_WLAN#
16
16

CLK_WLAN#
CLK_WLAN

21 PCIE_IRX_C_WLANTX_N4
21 PCIE_IRX_C_WLANTX_P4
21 PCIE_ITX_C_WLANRX_N4
21 PCIE_ITX_C_WLANRX_P4

WLAN/ WiFi
+3V_WLAN

Debug card using

2 0_0402_5% E51_TXD_R
2 0_0402_5% E51_RXD_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

GND1

CM17
WLAN@

+3V_SB

2
0.01U_0402_25V4Z

@ JUMP_43X79

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

CM18
WLAN@

CM19
WLAN@

2
4.7U_0805_10V4Z

+1.5VS

1
XMIT_OFF# 33
PLT_RST# 8,17,21,28,33,34

PLT_RST#

CM20
WLAN@

0.1U_0402_16V4Z
1
CM21
WLAN@

2
0.01U_0402_25V4Z

CM22
WLAN@

2
4.7U_0805_10V4Z

PM_SMBCLK 14,15,16,23
PM_SMBDATA 14,15,16,23
USB20_N7 21
USB20_P7 21

WiMax

R110 1
R106 1

E51_TXD
E51_RXD

R959
100K_0402_5%

FOX_AS0B226-S40N-7F
@

+3VALW_CARD

+3VS_CARD

Imax = 0.275A
1

CN1
10U_0805_10V4Z
NEW@

+3V_SB

RN1

RN2

2 CP_USB#
NEW@ 100K_0402_5%

2EXP_CPPE#
100K_0402_5%
RN3

CN2
0.1U_0402_16V4Z
NEW@

CN3
10U_0805_10V4Z
NEW@

share with USB OC PIN


need always pull high

2 PLT_RST#
100K_0402_5%
33,42

RN4
10K_0402_5%
@

Q23
2N7002_SOT23-3
@

G Vcc

UN2

2
2
1

2
G

17,29,33,36,39,41

CLKREQ#

11
13

+3VS

2
4

3.3Vin
3.3Vin

3.3Vout
3.3Vout

3
5

+3V_SB

17

2
4

CLKREQ_NEW#

AUX_IN
SYSRST#

AUX_OUT
OC#

SYSON

SHDN#

PERST#

SUSP#

STBY#

NC

10

CPPE#

GND

CN7
0.1U_0402_16V4Z
@

CN4
0.1U_0402_16V4Z
NEW@

CN5
10U_0805_10V4Z
NEW@

JEXP
CN6
0.1U_0402_16V4Z
NEW@

+1.5VS_CARD

CP_USB#
RCLKEN

CLKREQ_NEW# 16

9
18

21
21

USB20_N4
USB20_P4

14,15,16,23 PM_SMBCLK
14,15,16,23 PM_SMBDATA
+1.5VS_CARD

40mils

EXP_CPPE#

RN5
10K_0402_5%
@

1.5Vout
1.5Vout

20

+3VS

1.5Vin
1.5Vin

PLT_RST#

+3VS

Imax = 0.75A
1

60mils

12
14

+1.5VS

+3VS

RCLKEN

+1.5VS_CARD

Imax = 1.35A

UN1

33
33

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

0.1U_0402_16V4Z
1

PJ19

CPUSB#

Thermal_Pad

+3VS_CARD

23,33 SB_WAKE#
+3VALW_CARD

40mils
15

+3VALW_CARD

PM_SMBCLK
PM_SMBDATA

PERST#

+3VS_CARD

19
8

CP_USB#

21

PERST#

EXP_CPPE#

CLKREQ#
EXP_CPPE#

16 CLK_NEW#
16 CLK_NEW

16

21 PCIE_IRX_C_NEWTX_N1
21 PCIE_IRX_C_NEWTX_P1

7
21

21 PCIE_ITX_C_NEWRX_N1
21 PCIE_ITX_C_NEWRX_P1

RCLKEN
G577NSR91U_TQFN20_4x4
NEW@

1 NEW@ 2 CLKREQ_NEW#
RN6 0_0402_5%

reserve for test

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
GND
PERn0
GND
PERp0
GND
GND
PETn0
GND
PETp0
GND

27
28

GND
GND

31
32
29
30

SANTA_132862-2_26P
@
this is temp. footprint

NC7SZ32P5X_NL_SC70-5
@

CLKREQ#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet

27

of

45

+LAN_VDD12

Close to Pin10,13,30,36,45
2

CL15

CL2

CL3

CL4

CL5

Place Close to Chip


CL9 1

2 0.1U_0402_16V7K PCIE_IRX_LANTX_P320

HSOP

21 PCIE_IRX_C_LANTX_N3

CL8 1

2 0.1U_0402_16V7K PCIE_IRX_LANTX_N321

HSON

21 PCIE_ITX_C_LANRX_P3

15

HSIP

21 PCIE_ITX_C_LANRX_N3

16

HSIN

17
18

REFCLK_P
REFCLK_M

25

CLKREQB

16
16

LAN_WAKE#
2
100K_0402_5%

1
RL4 @

CLK_LAN
CLK_LAN#

27

PERSTB

2 2.49K_0402_1%

46

RSET

LAN_WAKE#
ISOLATEB

26
28

LANWAKEB
ISOLATEB

8,17,21,27,33,34 PLT_RST#
+3VS

RL3 1

33 LAN_WAKE#

RL5
1K_0402_1%

LAN_X1
LAN_X2

41
42

YL1
1LAN_X2

CKXTAL1
CKXTAL2

25MHz_20pF_6X25000017
CL17

27P_0402_50V8J
2

CL18
27P_0402_50V8J

23
24

NC
NC

7
14
31
47

GND
GND
GND
GND

22

33
34
35
32

LAN_DO
LAN_DI
LAN_SK_LAN_LINK#
LAN_CS

LED0

38

LAN_ACTIVITY#

2
3
5
6
8
9
11
12

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
NC

LAN_X1 2

LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS

RTL8103EL-GR

ISOLATEB

RL6
15K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

UL2

21 PCIE_IRX_C_LANTX_P3

+3V_LAN

0.1U_0402_16V4Z

GNDTX

1
RL1
2
RL2

PAD

T12
2
3.6K_0402_5%
1
1K_0402_5%

+3V_LAN

Close to Pin1,37,29
+3V_LAN

Close to Pin48

CL10
0.1U_0402_16V4Z

CL11
0.1U_0402_16V4Z

CL12
0.1U_0402_16V4Z

VCTRL12A

48

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

19
30
36
13
10

NC

39

NC
VCTRL12D

44
45

VDD33
VDD33

29
37

AVDD33
NC
NC

1
40
43

VCTRL12

VCTRL12

0.1U_0402_16V4Z
1

+EVDD12
+LAN_VDD12

2
CL6

CL7

Close to Pin19

1
@ 10U_0805_10V4Z

+EVDD12

+LAN_VDD12
+3V_LAN

CL13
1U_0402_6.3V4Z

CL14
0.1U_0402_16V4Z

RTL8103EL-GR_LQFP48_7X7

For EMI request

LAN Conn.

CL19 68P_0402_50V8J
2
1
LAN_ACTIVITY#

12
1
150_0402_1%
11
2
1
RL11
150_0402_1%
8

2
RL7

+3V_LAN

2
CL20
2
CL21

1
1

0.01U_0402_16V7K
0.01U_0402_16V7K

Place these components


colsed to UL3

LAN_MDI1+
LAN_MDI1-

TD+
TDCT
NC
NC
CT
RD+
RD-

16
15
14
13
12
11
10
9

TX+
TXCT
NC
NC
CT
RX+
RX-

RJ45_MIDI0+
RJ45_MIDI0CL26 1
1
CL27
RJ45_MIDI1+
RJ45_MIDI1-

2 1000P_0402_50V7-K 1
2
1
1000P_0402_50V7-K

2 75_0402_1%
2
75_0402_1%

PR2-

PR3-

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

PR1+

RJ45_GND

RL9
LAN_SK_LAN_LINK#

2
RL10
2
CL22

DELTA_LFE8456E-R

10

1
150_0402_1%
1
68P_0402_50V8J

RJ45_GND

1
CL23

2
RL12

SHLD2

14

SHLD1

13

Green LEDGreen LED+


TYCO_2068888-1_12P-T
@

For EMI request


+3V_LAN

PR4PR4+

RL8

Yellow LED+

UL3
1
2
3
4
5
6
7
8

Yellow LED-

7
RJ45_MIDI1-

LAN_MDI0+
LAN_MDI0-

JLAN

1
150_0402_1%
LANGND

2 1000P_1808_3KV7K
1

CL24

CL25

Compal Secret Data

Security Classification
2009/07/22

Issued Date

0.1U_0402_16V4Z

2012/07/22

Deciphered Date

Title

Date:

4.7U_0603_6.3V6K

Compal Electronics, Inc.


SCHEMATIC MB A4982

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Rev
B

401791
Sheet

Wednesday, December 30, 2009


E

28

of

45

+3VS_DVDD

30mil

+AVDD

CA57

1
2
2
10U_0805_10V4Z

2
2
0.1U_0402_16V4Z

2
100P_0402_50V8J

CA7

30

MIC2_R

30

MIC1_C_L

30

MIC1_C_R

Ext. Mic

2 MIC@
100P_0402_50V8J

1
CA52
CA51
1

100P_0402_50V8J
2
MIC@

1
CA54

2
100P_0402_50V8J

CA53
1

100P_0402_50V8J
2

1
CA14
C

MONO_IN
2
100P_0402_50V8J

22 AZ_BITCLK_HD
22 AZ_SDOUT_HD

2
1 AZ_SDIN0_HD_R
33_0402_5% RA7

22 AZ_SDIN0_HD

39

LOUT2_R

41

23

LINE1_L

SPDIFO1

48

24

LINE1_R

SPDIFO2

45

21

MIC1_L

HPOUT_L

33

1 RA5

22

MIC1_R

HPOUT_R

32

1 RA6

MONO_OUT

37

SDATA_OUT

DMIC_CLK3/4

44

SDATA_IN

LINE2_VREFO

20

34
47
43
4
7

CA34 @ 100P_0402_50V8J
AZ_BITCLK_HD
1
2
2
1
RA31 @ 100_0402_5%

19

CPVEE

31

CA16 1

VREF

27

AC_VREF

40

AC_JDREF

CA42 @ 100P_0402_50V8J
1
2 AZ_RST_HD#

2
1
+3VS
RA37 4.7K_0402_5%
@

For EMI request

DGND

CBN

30

1
CA17

CBP

29

GPIO0-->SPK_SEL

Sense Pin

SENSE A

Impedance

Codec Signals

39.2K

PORT-A (PIN 39, 41)

20K

PORT-B (PIN 21, 22)

10K

PORT-C (PIN 23, 24)

5.1K

PORT-D (PIN 35, 36)

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

2
2.2U_0603_6.3V6K

10K

PORT-H (PIN 37)

5.1K

PORT-I (PIN 32, 33)

AGND

HIGH:HARMAN
LOW:NO-BRAND

Function

1
2
VIN

GND

SHDN#

BP

CA11
2
1

CA10
1U_0402_6.3V4Z
1 @

SB_SPKR

RA8
1
2
47K_0402_5%

CA15
1
2

RA9
1
2
47K_0402_5%

MONO_IN

0.1U_0402_16V4Z

CardBUS Beep
31

RA19
1
2
47K_0402_5%

PCM_SPK#

1
RA11
10K_0402_5%

CA20
0.1U_0402_16V4Z

For EMI request


For EMI request

CA47 1

2 0.1U_0603_50V7K

CA48 1

2 0.1U_0603_50V7K

CA49 1

2 0.1U_0603_50V7K

CA50 1

2 0.1U_0603_50V7K

RA12 1

2
0_0603_5%

30

MIC_SENSE

30

NBA_PLUG

1 RA18
2
20K_0402_1%

SENSE_A

Ext. MIC

SPK out

1
RA16

2
5.1K_0402_1%

SENSE_B

1 RA17
2
20K_0402_1%
MIC@

Int. MIC

Headphone out

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

VOUT

place close to chip

SENSE B

23

1U_0402_6.3V4Z

RA10 CA55
1

26
42

need to re-link ALC272

EC_BEEP#

CA18 CA19 CA58

ALC272-GR_LQFP48_7X7
B

33

PCI Beep

CA45 MIC@
1
2

2
2.2U_0603_6.3V6K

JDREF

AVSS1
AVSS2

30

1U_0402_6.3V4Z

NC
DVSS
DVSS

30

HP_R

CA46
1
2

10mil
10mil

IF test OK, link direct

MIC2_VREFO

EAPD

HP_L

EC Beep

28

SENSE B

SUSP#

+MIC2_VREFO

MIC1_VREFO

SENSE A

0.22U_0402_10V4Z
APL5151-475BC-TRL_SOT23-5
@
@

+MIC1_VREFO

18

GPIO1/DMIC_DATA3/4

LINE1_VREFO

GPIO0/DMIC_DATA1/2

2
63.4_0402_1%
2
63.4_0402_1%

UA1

Beep sound

13

EAPD#

AMP_SPK_R 30

46

1
0_0402_5%

36

DMIC_CLK1/2

SYNC

RA4

LOUT1_R

BITCLK

10

MUTE#

AMP_SPK_L 30

30

LOUT2_L

MIC2_R

22 AZ_SYNC_HD

SENSE_B

MIC2_L

17

RESET#

SENSE_A

DVDD

16

11

SPK_SEL

DVDD_IO

38

25

LINE2-R

22 AZ_RST_HD#

23

LOUT1_L

35

+VDDA

4.75V
CA9
1U_0402_6.3V4Z
@

17,27,33,36,39,41

LINE2-L

BEEP_IN

+5VALW

For EMI request

15

12

20mil

1
2
FBMA-L11-160808-800LMT_0603
1
IHDMI@
CA56
100P_0402_50V8J
2

MIC2_L

AVDD2

AVDD1
30

14

For EMI request

Int. Mic

CA8

2
0.1U_0402_16V4Z

For EMI request


UA2

10U_0805_10V4Z
1

PJ33
JUMP_43X39
@

100P_0402_50V8J

CA6

0.1U_0402_16V4Z

+5VS

+1.5VS

LA1

10U_0805_10V4Z

10U_0805_10V4Z
1
1
CA4
CA5

2
1
0_0603_5%
CA3

Audio regulator

+3VS

RA2
0_0603_5%
NIHDMI@

20K_0402_1%

+VDDA

2
0.1U_0402_16V4Z
+1.5VS_DVDIO

40mil

0.1U_0402_16V4Z

RA3

2
1
0_0603_5%

10U_0805_10V4Z
1
CA2

CA1

Codec

RA1

100P_0402_50V8J

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

29

of

45

Ext. Mic
TPA6017 Medium Range Amplifier
+5VS
0.1U_0402_16V4Z

29

MIC1_C_L

29

MIC1_C_R

4.7U_0805_10V4Z

CA21
2
1

4.7U_0805_10V4Z

1
CA22

CA24

2 MIC@ 1
4.7K_0402_5%
RA24

CA30

0.033U_0402_25V7K

CA31

LINE_C_OUTL

AMP_SPK_L

CA32

0.033U_0402_25V7K

18

SPKR+

ROUT-

14

SPKR-

LOUT+

SPKL+

LOUT-

F=1/2RC --> -3db

2
1
1K_0402_5%
RA26 MIC@

MIC@

1
2

reserve for test


close to JLVDS

ACES_85204-0200N
@

1 NC1
2 NC2

3
4

RA29
100K_0402_5%
@

Speaker Connector
DA4 PJDLC05_SOT23-3
2

1
3

SPKL-

10

Keep 10 mil width


AMP_BYPASS

90K

10

70K

0 15.6

45K

1 21.6

25K

SPKL+
SPKLSPKR+
SPKR-

LA3 1
LA4 1
LA5 1
LA6 1

FBMA-L11-160808-800LMT_0603
FBMA-L11-160808-800LMT_0603
FBMA-L11-160808-800LMT_0603
FBMA-L11-160808-800LMT_0603

2
2
2
2

DA5 PJDLC05_SOT23-3
3

GND5
GND1
GND2
GND3
GND4

1
2
3
4

C860

1
2

SPK_L1
SPK_L2
SPK_R1
SPK_R2

CA33
0.47U_0603_10V7K

TPA6017A2_TSSOP20

C861

1
@

C862

1
@

1
@

1
2
3
4
ACES_85204-0400N
@

C863

680P_0402_50V7K

12

JSPK

GAIN0 GAIN1 Av(db)Rin(ohm)

680P_0402_50V7K

NC
BYPASS
SHUTDOWN

21
20
13
11
1

1 MIC@ 2INT_MIC_R
RA38
0_0402_5%

RA30
100K_0402_5%

680P_0402_50V7K

19

MUTE#

680P_0402_50V7K

C=0.033U,R=70K,F=68Hz
29

1U_0402_6.3V4Z

LIN+

LIN-

JMIC
INT_MIC
2
CA27
220P_0402_50V7K

ROUT+

1
9

MIC2_R

1U_0402_6.3V4Z

+MIC2_VREFO

2
3

RIN-

29

16
15
6

GAIN1

setting 68Hz

For EMI request

HeadPhone/LINE Out JACK


JLINE

5
29

NBA_PLUG

29

HP_R

29

HP_L

LA7 1
2 HP_R_L
KC FBM-L11-160808-121LMT 0603
LA8 1
2 HP_L_L
KC FBM-L11-160808-121LMT 0603

3
1
2

CA35

DIP

SW_XRE094_3P

2
10K_0402_5%

2
UA4

1
3

1
RA36

2
10K_0402_5%
1

CA37
0.01U_0402_16V7K

A
G

1
RA35

CA36
0.1U_0402_16V4Z

CA38
0.01U_0402_16V7K

Ext.MIC/LINE IN JACK

UA5

74LVC1G14GW_SOT353-5

For EMI request

+3VS

COM

NC

2
A

0.1U_0402_16V4Z
2

+3VS

RA34
10K_0402_5%

FOX_JA6333L-B3T0-7F
@

CA43
0.1U_0402_16V4Z
@

DA6 @
PJDLC05_SOT23-3

RA32
100K_0402_5%

1
5

RA33
10K_0402_5%

DIP

SW2

3
6
2
1
1

+3VS

Volume Control

+3VS

29

0.033U_0402_25V7K

17

MIC2_L

RA25 MIC@
1K_0402_5%
2
1

DA3 @
PSOT24C_SOT23

GAIN0

RIN+

29

CA28
MIC@

LINE_C_OUTR

AMP_SPK_R

RA27
100K_0402_5%

0.033U_0402_25V7K

29

RA28
100K_0402_5%
@

VDD
PVDD1
PVDD2

CA29

MIC@
CA26
2
1

10 dB
+5VS

UA3

+MIC1_VREFO

Int. Mic

CA25

0.1U_0402_16V4Z

Rin =70Kohm

RA23 1
2
1
2
4.7K_0402_5% DA2
CH751H-40PT_SOD323-2

CA23
10U_0805_10V4Z

+MIC1_VREFO

MIC1_R

2
1
1K_0402_5%
RA22

CH751H-40PT_SOD323-2
RA21
2 RA20
1
1
2
1K_0402_5% 4.7K_0402_5%
DA1
MIC1_L
2
1

1
2
3
4
5
6
7

CD1#
D1
CP1
SD1#
Q1
Q1#
GND

VCC
CD2#
D2
CP2
SD2#
Q2
Q2#

14
13
12
11
10
09
08

29
MIC1_R
MIC1_L

74LCX74MTC_TSSOP14

MIC_SENSE
LA9 1
2 MIC1_L_R
KC FBM-L11-160808-121LMT 0603
LA101
2 MIC1_L_L
KC FBM-L11-160808-121LMT 0603

1 CA44
1
1
0.1U_0402_16V4Z
@
CA40
CA41
120P_0402_50V8K @
2
2
@ 2

3
1
2

ENCODER_DIR 33
ENCODER_PULSE 33

3
6
2
1

CA39

0.1U_0402_16V4Z

JEXMIC

DA7 @
PJDLC05_SOT23-3

FOX_JA6333L-B3T0-7F
@

120P_0402_50V8K

For EMI request

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet

30

of

45

21 PCI_AD[0..31]

PCI_AD[0..31]

21 PCI_CBE#[0..3]

PCI_CBE#[0..3]

+3VS
0.1U_0402_16V4Z
+5VS
IDSEL SELECT POWER-ON-STRAPPING
(SEE NOTE & TABLE FOR OPTIONS)

10U_0805_10V4Z

CB1
PCM@

0.1U_0402_16V4Z

+3VS

+3VS

CB8
PCM@

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS
CB9
PCM@

CB10
PCM@

CB13
PCM@

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_AD20
IDSEL
1 PCM@ 2
RB19 100_0402_5% PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

64
77
97
115

4
5
6
7
8
9
10
13
14
15
16
17
18
19
21
22
28
29
30
31
34
35
36
37
38
39
40
41
42
43
44
46
127
11
12
49
50

CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
PCI_VCC
PCI_VCC
PCI_VCC
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VPP_VCC/VPPD1/IDSEL
C/BE3#
C/BE2#
C/BE1#
C/BE0#

16 CLK_PCI_PCM
21 PCI_DEVSEL#
21 PCI_FRAME#
21
PCI_IRDY#
21
PCI_TRDY#
21
PCI_STOP#
21
PCI_PAR

26
27
23
24
25
47
48

PCI_CLK
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PERR#/SPKR_OUT

29

PCM_SPK#

51

21
21

PCI_REQ#1
PCI_GNT#1

2
3

21

PCI_RST#

126
120
2
RB20 @

23 PM_CLKRUN#

1
0_0402_5%

CLK_PCI_PCM

RST#
PME#/RI_OUT#
MF6
MF4
MF3
MF0

32
45
65
96
128

for EMI request

RB21
10_0402_5%
@

55
54
53
52

REQ#
GNT#

GND
GND
GND
GND
GND

23,33,34 SERIRQ
21
PCI_PIRQA#

CB3
PCM@

VCC5#/VCCD0#/SDATA
VCC3#/VCCD1#/SCLK
VPP_PGM/VPPD0/SLATCH

124
125
123

VCC5#
VCC3#

D10/CAD31
D9/CAD30
D1/CAD29
D8/CAD28
D0/CAD27
A0/CAD26
A1/CAD25
A2/CAD24
A3/CAD23
A4/CAD22
A5/CAD21
A6/CAD20
A25/CAD19
A7/CAD18
A24/CAD17
A17/CAD16
IOW#/CAD15
A9/CAD14
IORD#/CAD13
A11/CAD12
OE#/CAD11
CE2#/CAD10
A10/CAD9
D15/CAD8
D7/CAD7
D13/CAD6
D6/CAD5
D12/CAD4
D5/CAD3
D11/CAD2
D4/CAD1
D3/CAD0

103
102
101
100
99
110
109
108
106
105
104
118
95
94
93
75
73
74
71
72
70
69
68
85
84
82
83
80
81
78
79
76

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

A16/CCLK
A23/CFRAME#
A15/CIRDY#
A22/CTRDY#
A21/CDEVSEL#
A20/CSTOP#
A13/CPAR
A14/CPERR#
WAIT#/CSERR#
INPACK#/CREQ#
WE#/CGNT#
RDY/IREQ#/CINT#
A19/CBLOCK#
WP/CCLKRUN#
RESET/CRST#
D2/RFU
D14/RFU
A18/RFU
VS1/CVS1
VS2/CVS2
CD1#/CCD1#
CD2#/CCD2#
BVD2/LED/CAUDIO
BVD1/STSCHG#/RI#/CSTSCHG

107
114
117
116
113
61
58
60
91
89
62
88
59
87
119
98
86
63
57
121
56
122
92
90

S1_A16_R
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A13
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_RDY#
S1_A19
S1_WP
S1_RST
S1_D2
S1_D14
S1_A18
S1_VS1
S1_VS2
S1_CD1#
S1_CD2#
S1_BVD2
S1_BVD1

REG#CCBE3#
A12/CCBE2#
A8/CCBE1#
CE1/CCBE0#

111
112
66
67

S1_REG#
S1_A12
S1_A8
S1_CE1#

CB4
PCM@

+S1_VCC
RB17
33K_0402_5%
PCM@

5
6
7
8

VCC5#
VCC3#

4.7U_0805_10V4Z

UB2

40mil

VCC/VPP +3.3V
VCC/VPP +3.3V
VCC5#
+5V
VCC3#
GND

1
2
3
4

PCMCIA Socket

OZ2210GN-B1_SO8
PCM@
JPCM

PVT

RB22
33K_0402_5%
PCM@

SA000026P10 (S IC OZ2210GN-B1 SO 8P)


VCC5#
(124)

VCC5#
(124)

VPP_PGM

IDSEL SELECT

(123)

VPP_PGM
(125)

IDSEL SELECT

AD18

* AD20

AD25

PIN F4

NOTE: IDSEL SELECTION!


THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME.
IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE
PCI AD LINES OR EXTERNAL IDSEL SIGNAL.

RB18 33_0402_5%
1
2 S1_A16
PCM@

22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE


REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO
SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS.
THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS.

1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68

S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12
S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15
S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11
S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21

+S1_VCC

CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS


FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY
CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST
BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC.

+S1_VCC

0.1U_0402_16V4Z
CB11
PCM@

CB12
PCM@

4.7U_0805_10V4Z
1

S1_A16
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7
S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#
S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#

OZ601TN_TQFP128~D
PCM@

22K TO 47K PULL-UPS MUST BE PLACED


ON INTA#, PME#, SERIRQ# & CLKRUN#.

GND
GND
DATA3
CD1#
DATA4
DATA11
DATA5
DATA12
DATA6
DATA13
DATA7
DATA14
CE1#
DATA15
ADD10
CE2#
OE#
VS1#
ADD11
IORD#
ADD9
IOWR#
ADD8
ADD17
ADD13
ADD18
ADD14
ADD19
WE#
ADD20
READY
ADD21
VCC
VCC
VPP
VPP
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24
ADD7
ADD25
ADD6
VS2#
ADD5
RESET
ADD4
WAIT#
ADD3
INPACK#
ADD2
REG#
ADD1
BVD2
ADD0
BVD1
DATA0
DATA8
DATA1
DATA9 GND
DATA2 GND
DATA10 GND
WP
GND
CD2#
GND
GND

69
70
71
72

SANTA_130675-4_68P
@
this is temp. footprint

RB16
33K_0402_5%
@

UB1

1
20
33

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1
1

CB7
PCM@

CB6
PCM@

CB5
PCM@

CB2
PCM@

CB14
10P_0402_50V8J
@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Deciphered Date

2012/07/22

Title

SCHEMATIC MB A4982

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

401791

Wednesday, December 30, 2009


D

Sheet

31

of

45

+3VS_CR
RC2
1

+3VS
+3VALW

0_0603_5% 3IN1@
2

RC4

2
0_0603_5% @

confirm that whether can be removed

CC1
0.1U_0402_16V4Z
3IN1@

RC7
2
CC6
1

0.1U_0402_16V4Z 3IN1@
2
UC2

+3VS_CR
2

CC4
2
RC8
100K_0402_5%
3IN1@

0.1U_0402_16V4Z
1
3IN1@

1
3
7
9
11
33

AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3

RST#_R
MODE SEL
XTLO
XTLI

8
44
45
47
48

3V3_IN
RST#
MODE_SEL
XTLO
XTLI

CR_LED#

4
5
14

DM
DP
GPIO0

+VCC_3IN1

VREG
MS_D4
NC

+3VS_CR

RC10
0_0402_5%
RST#_R
2
1
3IN1@

RST#
1

CC5
1U_0402_6.3V4Z
3IN1@

CC8
1U_0402_6.3V4Z
3IN1@

+3VS_CR

2
21
21

USB20_N10
USB20_P10

+3VS
MODE SEL
1
RC13
120_0402_5%
3IN1@

1
1

22

RC16
0_0402_5%
3IN1@

Vf=2.0V(typ),2.4V(max)
DC1
HT-110UYG-CT_YEL/GRN
3IN1@
2

RREF

12
32

DGND
DGND

6
46

AGND
AGND

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
SD_DAT6/XD_D7/MS_D3_SP10
MS_INS#_SP9
SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

XTAL_CTR
MS_D5

13
24

EEDO
EECS
EESK
SD_CMD

15
16
17
36

CR_LED#

CC7
1U_0402_6.3V4Z
3IN1@

SD_DATA2
SD_DATA3

SD_MS_CLK
MS_DATA3_SD_DATA6
MSCD#
MS_DATA2_SD_DATA7
SD_MS_DATA0
MS_DATA1
MSBS
SD_DATA1
SDCD#
SDWP#

RC11 1 3IN1@ 2 22_0402_5%

SDCLK

RC12 1 3IN1@ 2 22_0402_5%

MSCLK
C

XTAL_CTR

3 in 1 Card Reader
SDCMD

RTS5159-GR_LQFP48_7X7 3IN1@
RC15
0_0402_5%
3IN1@

confirm all pin define with connector spec.

RC14
6.19K_0402_1%
3IN1@

10
22
30

CC13
0.1U_0402_16V4Z
@

0_0402_5% 3IN1@
1

JREAD
SDWP#
SD_DATA1
SD_MS_DATA0
B

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

MSBS
SDCLK
MS_DATA1
SD_MS_DATA0
+VCC_3IN1

48Mhz
1
2
RC19 0_0402_5%

16 CLK_48M_CR

CC10
1U_0402_6.3V4Z
3IN1@

XTLI

MS_DATA2_SD_DATA7
1

CC11
0.1U_0402_16V4Z
3IN1@

3IN1@
+3VS_CR

SD_DATA3

1
2 XTAL_CTR
RC20 0_0402_5%
3IN1@

12Mhz

USB AUTO DE-LINK MS FORMATTER

NC

YES

NC

47P

YES

NC

NC

6P_0402_50V8D

NC

680P

YC1
12MHZ_16P_6X12000012
@

10K 680P

6P_0402_50V8D

TAITW_R009-125-LR_RV
@

LED ON

10_0402_5%
1
2

MSCLK

@ RC17

LED ON
SDCLK

YES

Compal Secret Data


2009/07/22

Issued Date

2012/07/22

Deciphered Date

Title

10P_0402_50V8J
@ CC15

Compal Electronics, Inc.


SCHEMATIC MB A4982

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

10P_0402_50V8J
@ CC14

10_0402_5%
1
2
@ RC18

22
23

Compatible with RTS5158E


YES

Security Classification

YES

10K 180P

XTLO
CC12
@

SD_DATA2
SDCD#

Description
Recommended

XTLI
CC9
@

MSCD#
MS_DATA3_SD_DATA6
SDCMD
MSCLK

SD-WP
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
SD-DAT2 GND1
SD-CD
GND2

Rev
B

401791
Sheet

Wednesday, December 30, 2009


1

32

of

45

+3VL
+3VL
0.1U_0402_16V4Z
1
2

2
2
0.1U_0402_16V4Z

C773

2
2
0.1U_0402_16V4Z

C769
1
2

C774
C775
1000P_0402_50V7K1000P_0402_50V7K
1
U43

VCC
VCC
VCC
VCC
VCC
VCC

for EMI request

0.1U_0402_16V4Z

67

C772

CLK_PCI_EC

AVCC

0.1U_0402_16V4Z
1 C771
1
C770

9
22
33
96
111
125

R738
@ 10_0402_5%

2
1

CLK_PCI_EC 12
13
ECRST#
37
20
38

16 CLK_PCI_EC
8,17,21,27,28,34 PLT_RST#
R739
47K_0402_5%
2
1

2
C780

23
EC_SCI#
35 WL_BT_LED#

ECRST#

1
0.1U_0402_16V4Z

1
R595
1
R596

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

KSO2

to avoid EC entry ENE test mode

26

KSI[0..7]

26

KSO[0..17]

KSI[0..7]
KSO[0..17]

RP23

1
2
3
4

+3VL
+3VS

8
7
6
5

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

38
38
4,17
4,17

2.2K_8P4R_5%

2
R751

+3VL

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

SLP_S5#

EC_SMI#

CEC_INT#

+3VALW
C781
1
2
0.1U_0402_16V4Z
@
2
23 PM_SLP_S5#

8 MCH_TSATN_EC#

PM_SLP_S4#_R

4 FAN_SPEED1

U44
@

NC7SZ08P5X_NL_SC70-5

SLP_S5#

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

INVT_PWM 18
EC_BEEP# 29
ACOFF
BATT_TEMPA

GPIO
SM Bus

BATT_TEMPA 38
ADP_I
ADP_V

BATT_TEMPA
1
C776
ACIN_D
1
C779

39
39

27
E51_TXD
27
E51_RXD
26,35 ON/OFFBTN#
35 PWR_SUSP_LED#
26 NUM_LED#

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPI

maybe can remove

1
R750

PM_SLP_S4#_R
2
0_0402_5%

XCLK1
XCLK0

R749
CRY1

2CRY2

AGND

PM_SLP_S4#

122
123

SLP_S5#

GND
GND
GND
GND
GND

2
0_0402_5%

11
24
35
94
113

1
R748

69

CRY1
CRY2
PM_SLP_S5#

USB_CHG_EN# 25
USB_EN# 25
ENCODER_DIR 30
ENCODER_PULSE 30
TP_CLK 26
TP_DATA 26

TP_CLK
TP_DATA
VGATE

+5VS
TP_CLK
1
4.7K_0402_5%
TP_DATA
1
4.7K_0402_5%

2
R740
2
R741
+3VALW

VGATE
8,23,43
WOL_EN# 36
SBPWR_EN# 24,36
LID_SW# 34

LID_SW#
2
47K_0402_5%

ACIN_D

FSTCHG 39
BATT_FULL_LED# 35
CAPS_LED# 26
BATT_CHG_LOW_LED# 35
PWR_ON_LED# 35
SYSON
27,42
VR_ON
43

1
100K_0402_5%

2
R742
D64

ACIN_D

PM_PWROK

EC_RSMRST# 23
EC_LID_OUT# 23
EC_ON
35
EC_SWI#
PM_PWROK
BKOFF# 18
XMIT_OFF# 27

ACIN

23,35,37

1
2
R745GM@ 0_0402_5%
1
2
R746PM@ 0_0402_5%
1
2
R747
100K_0402_5%

ENBKL

USB_OC#0_R

USB_OC#3 21,25
EC_THERM# 23
SUSP#
17,27,29,36,39,41
PBTN_OUT# 23

ICH_PWROK

1
R231
1
R264

PM_PWROK
+3VS

+EC_V18R
C782
4.7U_0805_10V4Z

KB926QFD3_LQFP128_14X14

1
C777

VGATE

PM_PWROK

VGA_ENBKL 17

1
R752@

2
10K_0402_5%
2
10K_0402_5%

2
0.1U_0402_16V4Z

ICH_PWROK

8,23

U5
NC7SZ08P5X_NL_SC70-5

2
0_0402_5%

To reduce CMOS dischage fail rate

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

UMA_ENBKL 10

ENBKL

3
2

32.768KHZ_12.5P_1TJS125BJ4A421P

1
R766

+3VALW

1
C785
Y5

15P_0402_50V8J

IN

1
OUT

USB_OC#0 21,25

C784

NC

The circuit is reserve for new design for pre-MP

LAN_WAKE# 28

NC

EC_SWI#
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%

USB_OC#0_R

1
R753@
1
R754
1
R756@
1
R757

SB_WAKE#

15P_0402_50V8J

23,27

EC_SI_SPI_SO 34
EC_SO_SPI_SI 34
SPI_CLK 34
SPI_CS# 34

@ 20M_0603_5%

2
100P_0402_50V8J
2
100P_0402_50V8J

DAC_BRIG 18
EN_DFAN1 4
IREF
39
CHGVADJ 39

SPI Device Interface


SPI Flash ROM

39

CH751H-40PT_SOD323-2

23

23 PM_SLP_S4#

PS2 Interface

1 CEC_INT#
100K_0402_5%
23 PM_SLP_S3#

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

KSO1

2
47K_0402_5%
2
47K_0402_5%

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

21
23
26
27

PWM Output
AD Input

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

+3VL

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

+3VL

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

C778
@ 22P_0402_50V8J

1
2
3
4
5
7
8
10

22
GATEA20
22 KB_RST#
23,31,34 SERIRQ
22,34 LPC_FRAME#
22,34 LPC_AD3
22,34 LPC_AD2
22,34 LPC_AD1
22,34 LPC_AD0

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

33

of

45

LPC Debug Port

Lid SW

SPI Flash (16Mb*1)

Please place the PAD under DDR DIMM.


+3VALW

It's for 16" using

20mils

U46

8
2

VCC

HOLD

1
6

33 EC_SO_SPI_SI

C822
0.1U_0402_16V4Z
2 16@

S
+3VALW

H1

+3VS

LID_SW#

33

PLT_RST# 8,17,21,27,28,33

LPC_AD3

LPC_AD2 22,33

LPC_AD1

LPC_AD0 22,33

10

CLK_PCI_DDR

1
23,31,33 SERIRQ

C823
10P_0402_50V8J
16@ 2

22,33
22,33

33 SPI_CS#
33

SPI_CLK

VSS

VOUT

It's for 17" using

1
2
R761 0_0402_5%

22,33 LPC_FRAME#

U50 17@
APX9132ATI-TRL_SOT23-3

EC_SI_SPI_SO 33

@ DEBUG_PAD

GND

SST25LF080A_SO8-200mil

VDD

VOUT

R764
22_0402_5%

LID_SW#

16

0.1U_0402_16V4Z

VDD

C786

GND

U48 16@
APX9132ATI-TRL_SOT23-3
+3VL

R953 1
2
33_0402_5%

1
1
C852

reserve for EMI, close to U46

2
33P_0402_50V8J

C838
10P_0402_50V8J
17@ 2

SPI_CLK

C836
0.1U_0402_16V4Z
2 17@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Deciphered Date

C820
22P_0402_50V8J

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet

34

of

45

ISPD

Power Button

U3
ZZZ

U3

+3VL

NB_PM_R1

NB_PM_R3

PCB
R765
D

PCB ZKU LA-4982P REV1

CANTIGA PM
PMR3@

PJP1

U3

CANTIGA PM
PMR1@
D

100K_0402_5%

ON/OFFBTN#

ON/OFFBTN# 26,33

TOP side
SMT1-05-A_4P

6
5

2
SW6

NB_GL40_R1

NB_GL40_R3
PJP1
KSWAA45@

Q28A
2N7002DW-T/R7_SOT363-6

CANTIGA GL40
GL40R3@

CANTIGA GL40
GL40R1@

U3

U9

another at page36

EC_ON

U3

PJP1

R767
10K_0402_5%

For EMI request

SMT1-05-A_4P

DC-IN
17

6
5

DC-IN
16

BTM side

33

37

51_ON#

C646
0.1U_0402_16V4Z
@

SW5

NB_GM45_R1
PJP1
KTWAA45@

debug phase using

SB_R1
CANTIGA GM45
GM45R1@

ICH9-M ES
ICH9R1@

Screw Hole

2N7002DW-T/R7_SOT363-6

H13

H14

H21

H22

H15

H23

H16

H17

H24

H18

H26

H19

H27

H20

H28

H_3P0
@

H_3P0
@

H_3P0
@

H_3P0
@

H_3P0
@

H_3P0
@

H_3P0
@

H_3P0N
@

H_3P0N
@

Q30A
1

H29

H_3P0
@
H40

BATT CHARGE/FULL LED

+3VALW

Vf=1.9V(typ),2.4V(max) for amber


Vf=2.0V(typ),2.4V(max) for green
If=30mA(max)

1
R770

2
120_0402_5%

H_3P0
@

H_3P0
@

H_3P0
@

H_3P0
@

H_3P1N
@

H_3P0
@

PWR_ON_LED# 33

H_3P0
@

H_3P0
@

PWR_SUSP_LED# 33

D68

another at page36

H12

POWER/SUSPEND LED
1

D67
2
2
1
120_0402_5%
HT-110UYG-CT_YEL/GRN

1
R768

H11

23,33,37

+3VALW

ACIN

Vf=2.0V(typ),2.4V(max)
If=30mA(max)

DC-IN LED

H_4P1X3P1N
@

HT-210UD/UYG_AMB/GRN

H38

H39

D70

BATT_FULL_LED# 33

1
H32

H33

H34

H35

H_3P7
@

H_3P7
@

H_3P7
@

WL&BT LED

H_3P7
@
B

D74
2
2
1
120_0402_5%
HT-110UD_1204_AMBER
WLAN@
WLAN@

1
R777

H30

WL_BT_LED# 33

H31

MDC
1

+3VS

H_3P7
@

CPU

HT-210UD/UYG_AMB/GRN
B

H_3P7
@

2
120_0402_5%

H_3P2
@

H36

MINI CARD

1
R773

H_3P2
@

H37
H_3P7
@

+3VALW

BATT_CHG_LOW_LED# 33

VGA
1

H_3P7
@

PCB Fedical Mark PAD

+3VS

1
R780

D76
2
2
1
120_0402_5%
HT-110UYG-CT_YEL/GRN

FD3
@

FD4
@

2 R779
1
10K_0402_5%

+3VS

HDD LED

FD2
@

FD1

SATA_LED# 22
A

1
Q31A
2N7002DW-T/R7_SOT363-6

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Q31B 2N7002DW-T/R7_SOT363-6

2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

35

of

45

+3VALW TO +3VS

+5VALW TO +5VS

+3VALW

+5VALW

+1.5V

Q36B

FDS6676AS
C834

R783

1U_0402_6.3V4Z

R789
820K_0402_5%

1 R786
2
+VSB
220K_0402_5%

470_0805_5%

C829

SI4856ADY_SO8

Q36A
SUSP 5
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

1
2
3
4

3 1

R788
200K_0402_5%
@

S
S
S
G

2
C833

3 1

+VSB

D
D
D
D

C832

1 R785
2
47K_0402_5%

470_0805_5%

1U_0402_6.3V4Z

C828

Q34

8
7
6
5

Q37A
Q37B
SUSP 5
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

Q35B

R782

SI4800BDY_SO8

Q35A
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

Vgs=10V,Id=14.5A,Rds=6mohm

4.7U_0805_10V4Z

1
2
3
4

S
S
S
G

R787
330K_0402_5%

+VSB

D
D
D
D

C831

0.022U_0402_25V7K

4.7U_0805_10V4Z

C830

1 R784
2
47K_0402_5%

8
7
6
5

C827

1U_0402_6.3V4Z

SI4800BDY_SO8

R781

C826

0.01U_0402_25V7K

4.7U_0805_10V4Z

1
2
3
4

+1.5VS
4.7U_0805_10V4Z

Q33

S
S
S
G

1
4.7U_0805_10V4Z

3 1

D
D
D
D

C825

8
7
6
5

C824

470_0805_5%

Q32

Inrush current = 0A

Vgs=10V,Id=9A,Rds=18.5mohm

+1.5V to +1.5VS
+5VS
4.7U_0805_10V4Z

Inrush current = 0A

0.1U_0402_25V6

+3VS

C835

+3VALW TO +3V_LAN

+3VALW TO +3V_SB
+3VALW
+3VALW

D
G

1U_0402_6.3V4Z
STAR@
SBPWR_EN#

2N7002DW-T/R7_SOT363-6

6 1
R805
200K_0402_5%
STAR@

Q46B
STAR@

C845
0.1U_0402_25V6
STAR@

Q46A
STAR@

2
1

C841

2
1
R804 20K_0402_5%
STAR@

R803
470_0805_5%
STAR@

C840
4.7U_0805_10V4Z
@

C844
STAR@

+VSB

1U_0402_6.3V4Z
1

1
C843
4.7U_0805_10V4Z
STAR@
STAR@
2
SI3456BDV-T1-E3_TSOP6

Inrush current = 0A
4

current = 0A

@ JUMP_43X79

6
5
2
1

1
1

C842
10U_0805_10V4Z
STAR@

2
2

3
1

WOL_EN#

Q44

Vgs=10V,Id=6A,Rds=35mohm
PJ35
JUMP_43X79
@
+3V_LAN

33

2
C839
Q41
0.1U_0402_16V7K
AO3413_SOT23
STAR@
STAR@
1
1
2
2
R795
47K_0402_5% 2
STAR@
C837
0.01U_0402_25V7K
STAR@
Inrush
1
D

+3V_SB
PJ36

Vgs=-4.5V,Id=3A,Rds<97mohm

+3VALW
R793
100K_0402_5%
STAR@

SBPWR_EN#

SBPWR_EN# 24,33

2N7002DW-T/R7_SOT363-6

SUSP

SUSP

17,27,29,33,39,41

SUSP#

SUSP

42
Q30B
2N7002DW-T/R7_SOT363-6

Q28B
2N7002DW-T/R7_SOT363-6

SUSP

another at page35
4

another at page35

2
G
3

R796
100K_0402_5%

R802
470_0805_5%

R801
470_0805_5%

Q21
2N7002_SOT23-3

+5VALW

+0.75VS

+1.5VS

R799
10K_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
E

36

of

45

VS
VIN

1
PR3
5.6K_0402_5%

PC6
.1U_0402_16V7K

23,33,35

PACIN

LM393DG_SO8

PACIN

39

ACIN

PU1A

PD1
GLZ4.3B_LL34-2

PR7
10K_0402_1%

1
PR8
10K_0402_1%

RTCVREF

Vin Detector

3.3V

VIN

PC5
0.068U_0402_10V6K

PR6
20K_0402_1%

@ SINGA_2DW-0005-B03

PR4
10K_0402_1%
1
2

2
8

PR5
22K_0402_1%
1
2

PC4
100P_0402_50V8J

PC3
1000P_0402_50V7K

N1
PR2
84.5K_0402_1%

PC2
100P_0402_50V8J

PC1
1000P_0402_50V7K

+
1

DC_IN_S2

10A_125V_451010MRL

DC_IN_S1

PJP1

PF1

DC301001M80

PR1
1M_0402_1%
1
2

VIN

PL1
SMB3025500YA_2P
1
2

High 18.384 17.901 17.430


Low 17.728 17.257 16.976

PD3
RLS4148_LL34-2

CHGRTCP

PR11
200_0603_5%
1
2

PR10
68_1206_5%

N1

VS

PD4
2

VIN

N3

2
PR15
22K_0402_1%

B+

PR14
1K_1206_5%

RLS4148_LL34-2

2
1

RTC Battery

PR16
1K_1206_5%

RTCVREF

SP093MX0000

LM393DG_SO8

+3VALW

+1.5VP

@ JUMP_43X118

+1.5V

OCP(min)=7.7A

+5VL

PC12
1000P_0402_50V7K

PR23
10K_0402_1%
@ PR25
@PR25
66.5K_0402_1%

(100mA,40mils ,Via NO.= 2)

@ JUMP_43X118

(11A,440mils ,Via NO.= 22)


1

+3VL

(100mA,40mils ,Via NO.= 2)

PJ9
1

+5VALWP

@ JUMP_43X118

PJ8
2

@ JUMP_43X39

PJ6
2

+VSBP

+3VLP

OCP(min)=7.9A

PACIN

PJ7

+5VALW

@ JUMP_43X118

(5A,200mils ,Via NO.= 10)

OCP(min)=12.97A
1

PC11
1000P_0402_50V7K

PR27
47K_0402_1%
PQ2
2
2
1
SSM3K7002FU_SC70-3
G

+1.05VSP
+VSB

Precharge detector
15.97V/14.84V FOR
ADAPTOR

PJ11
1

+1.05VS

+1.8VP

+1.8VSP

@ JUMP_43X118

+1.8V

@ JUMP_43X79

@ JUMP_43X39

(10A,400mils ,Via NO.=20)

(120mA,40mils ,Via NO.= 1)

OCP(min)=12.16A

PQ3
DTC115EUA_SC70-3

PR24
499K_0402_1%
PR26
191K_0402_1%

PJ5
2

+5VALWP

RTCVREF

@ JUMP_43X39

@ JUMP_43X118
PJ4
2 2
1 1

(5A,200mils ,Via NO.= 10)

VL

PC13
1000P_0402_50V7K

+3VALWP

PJ3

PJ2

PJ1

ACON

39

PU1B

1U_0805_25V4Z

EN0

40

PD5
RB715F_SOT323-3

@ MAXEL_ML1220T10
PC10

N2

PR18
499K_0402_1%

PC9
10U_0805_10V4Z

+RTCBATT

PR20
2.2M_0402_5%
2
1

IN
GND

VL

OUT

+RTCBATT

PR19
100K_0402_1%
1
2

PBJ1
2

3.3V

G920AT24U_SOT89-3

PU2

+CHGRTC

PR22
560_0603_5%
1
2

PR17
200_0603_5%
PR21
560_0603_5%
1
2

51_ON#

35

PC8
0.1U_0603_25V7K

PC7
0.22U_1206_25V7K

PR13
100K_0402_1%

PR12
1K_1206_5%

PR9
68_1206_5%
PQ1
TP0610K-T1-E3_SOT23-3

N1

BATT+

PD2
RLS4148_LL34-2

PJ12
2

+1.8VS

@ JUMP_43X79

(2A,100mils ,Via NO.=6)

PJ10
2

+0.75VSP

OCP(min)=2.55A

+0.75VS

@ JUMP_43X79

(2A,80mils ,Via NO.= 4)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009
D

Sheet

37

of

45

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 56 degree C
VMB

1
3

PQ4
SSM3K7002FU_SC70-3

O
4

ENTRIP2

22,40

PD6
RLS4148_LL34-2

LM393DG_SO8

PU3A

VL

PQ5
SSM3K7002FU_SC70-3

PR38
100K_0402_1%
1

1
2

PR39
1K_0402_1%

PR40
100K_0402_1%
2

@ SUYIN_200045MR009G171ZR

2
G

2
G

PC18
1000P_0402_50V7K

1
2

+3VLP

PR37
15.8K_0402_1%

PR36
6.49K_0402_1%
2
1

BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA

22,40

2
1
TM_REF1

PC17
0.22U_0805_16V7K

BATT_S1

PR30
47K_0402_1%
PR32
47K_0402_1%
1
2

PR33
12.4K_0402_1%
1
2

1
2
3
4
5
6
7
8
9

PC16
0.1U_0603_25V7K

PC15
0.01U_0402_25V7K

ENTRIP1

VL

1
2

PC14
1000P_0402_50V7K

2
2

BATT+

+3VLP

PJP3

GND
GND
GND
GND

2
PR29
47K_0402_1%

PR35
100_0402_1%
1

PR34
100_0402_1%

For 17"

10
11
12
13

PR31
1K_0402_1%

@ SUYIN_200045MR009G171ZR

1
2
3
4
5
6
7
8
9

2
PR28
1K_0402_1%

GND
GND
GND
GND

BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA

VL

10
11
12
13

BATT_S1

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9

VL
PL2
SMB3025500YA_2P
1
2

PF2
15A_65V_451015MRL
1
2

PJP2

PH1
100K_0402_1%_TSM0B104F4251RZ

For 16"

BATT_TEMPA 33

EC_SMB_DA1 33
EC_SMB_CK1 33

PH2 near main Battery CONN :


BAT. thermal protection at 90 degree C
Recovery at 53 degree C

VL

VL

PQ6
TP0610K-T1-E3_SOT23-3

PR41
47K_0402_1%

8
+

PU3B
O

PR46
16.9K_0402_1%

LM393DG_SO8

PD7
RLS4148_LL34-2

2
1

PR48
0_0402_5%
2

PQ7
SSM3K7002FU_SC70-3

2
G

PC22
@ .1U_0402_16V7K

1
POK

1
PC21
0.22U_0805_16V7K

PR47
100K_0402_1%

40

TM_REF1

1
2
2

1
2

PR44
13.7K_0402_1%
1
2

PR45
22K_0402_1%
1
2

PR42
47K_0402_1%
1
2

100K_0402_1%_TSM0B104F4251RZ
PC20
@ 0.1U_0603_25V7K

VL

PC19
@ 0.22U_1206_25V7K

2
1
PR43
100K_0402_1%

+VSBP

PH2
3

B+

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009
D

Sheet

38

of

45

B+

1
CSIN
CSIP

21

ICOMP

CSIN

20

VCOMP

CSIP

19

ICM

PHASE

18

VREF

UGATE

17

CHLIM

BOOT

16

10

ACLIM

VDDP

15

11

VADJ

LGATE

14

GND

PGND

13

PR71
100K_0402_1%

1
PR60
20_0603_5%
1
2
PC33
0.047U_0603_16V7K
1
2
PR61
20_0603_5%
2
1
PR62
20_0603_5%
PC36
0.1U_0603_25V7K
1
2

CSON

PQ18
AO4466_SO8

PR72
20K_0402_1%

12

DL_CHG

PL3
10U_LF919AS-100M-P3_4.5A_20%
CHG
1
2

26251VDD

PR73
4.7_0603_5%
PC43
4.7U_0805_6.3V6K

2
1

PD12
RB751V-40TE17_SOD323-2
1

2 PACIN
G
PQ17
SSM3K7002FU_SC70-3
2

PC39
0.1U_0603_25V7K
BST_CHGA 2
1

6251VDDP

5
6
7
8
6251aclim

PR70
75K_0402_1%
6251VREF 1
2

DH_CHG
PR69
0_0603_5%
BST_CHG 1

D
PC31
0.1U_0603_25V7K

CSOP

PR64
2.2_0603_5%

LX_CHG

IREF

6251VREF

PR66
0.02_2512_1%
4

BATT+
PC41
10U_1206_25V6M
2
1

CSOP

CELLS

PD11
2

PR56
200K_0402_1%
1
2 VIN

PC40
10U_1206_25V6M
2
1

22

ACOFF

CSON

1SS355_SOD323-2

EN

VIN

1SS355_SOD323-2

5
6
7
8

PD8

PQ15
DTC115EUA_SC70-3

23

PC30
0.1U_0603_25V7K
2
1

ACSET ACPRN

PR65 47K_0402_1%
2
7

33

PR68
33
154K_0402_1%
2
1

PC42
0.01U_0402_25V7K
2
1

ACOFF

@PC37
@
PC37 100P_0402_50V8J
1
2
PC38
.1U_0402_16V7K
ADP_I

ACOFF

DCIN

0.01U_0402_25V7K

PQ21
DTC115EUA_SC70-3

33

6.81K_0402_1%
2

24

VDD

3
ACON

PR63

DCIN

PR67
22K_0402_5%
PACIN 1
2

PACIN

37

PC35
1
2

PU5
1

PQ19
SSM3K7002FU_SC70-3

6800P_0402_25V7K
2

SUSP# 17,27,29,33,36,41

RB715F_SOT323-3

PR52
10K_0402_1%

2 1

PC34
1

2
G

6251_EN

@ PC32
@PC32
680P_0402_50V7K
1
2

CSON

1
2

PC29
.1U_0402_16V7K

PR59
150K_0402_1%

FSTCHG

2
3

PC28
2.2U_0603_6.3V6K
2
1

FSTCHG

PQ16
SSM3K7002FU_SC70-3
3

PR57
10K_0402_1%
2
1

PR51
47K_0402_1%
1
2

PD9

6251VDD

PR58
100K_0402_1%

33

2
G

37

PR55
100K_0402_1%
2
1

2
1

PQ14
DTC115EUA_SC70-3

PQ13
DTC115EUA_SC70-3

PQ10
FDS4435BZ_SO8
1 S
D 8
2 S
D 7
3 S
D 6
4 G
D 5

PR54
100K_0402_1%

PD10
1SS355_SOD323-2
1
2

DCIN

1
2

P3

PR53
47K_0402_1%

PC23
5600P_0402_25V7K

PC27
0.1U_0603_25V7K

PQ12 TP0610K-T1-E3_SOT23-3
PR167 10_0603_5%
3
1
1
2

PR50
200K_0402_1%

PQ11
DTA144EUA_SC70-3

8
7
6
5

PC130
PR152
@ 680P_0603_50V8J @ 4.7_1206_5%

D
D
D
D

AO4466_SO8

S
S
S
G

PQ20

1
2
3
4

PC26
4.7U_1206_25V6K
2
1

1
2
3
4

3
2
1

S
S
S
G

@PQ42
@
PQ42
FDS4435BZ_SO8
1 S
D 8
2 S
D 7
3 S
D 6
4 G
D 5

CHG_B+

3
2
1

D
D
D
D

PL19
HCB4532KF-800T90_1812

8
7
6
5

B+

PR49
0.02_2512_1%

P3

PC25
4.7U_1206_25V6K
2
1

VIN

PQ9
FDS4435BZ_SO8

P2

PC24
4.7U_1206_25V6K
2
1

PQ8
FDS4435BZ_SO8

ISL6251AHAZ-T_QSOP24

Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.63A


Iada=0~3.42A(65W)

CP= 92%*Iada; CP=3.147A

33 CHGVADJ

PR75
31.6K_0402_1%

VIN

PR74
18.2K_0402_1%
1
2
1

Iada=0~4.737A(90W) CP= 92%*Iada; CP=4.36A

CP mode
PR70=53.6k

PR49=0.015

Vaclim=1.08V(75W)

PR70=24.9k

PR49=0.02

Vaclim=1.08V65W)

PR70=75k

PR216
309K_0402_1%
PR166
10K_0402_1%
1
2

Vaclim=0.736V(90W)

CHGVADJ=(Vcell-4)/0.10627

IREF=1.016*Icharge

Vcell

IREF=0.254V~3.048V

4V

VCHLIM need over 95mV

4.2V

1.882V

4.35V

3.2935V

CELLS
CELL number

PC162
.1U_0402_16V7K

CC=0.25A~3A

33

PR217
47K_0402_1%

@PD14
@
PD14
GLZ4.3B_LL34-2

ADP_V

PR49=0.02

VDD

GND

Float

CHGVADJ
0V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009
D

Sheet

39

of

45

PC44
0.22U_0603_10V7K

2VREF_51125

2
G

VL

DRVL2

DRVL1

19

LG_5V

3
2
1
5
6
7
8
PQ25
AO4712_SO8

VCLK

VL

22,38

B++

2VREF_51125

PC56
4.7U_0805_10V6K

PR88
@ 0_0402_5%

TPS51125RGER_QFN24_4X4

3
2
1

18

17

16

GND

EN0
13

PL5
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2

1
+

+5VALWP

PC53
220U_6.3V_M

12

38

LG_3V

PQ23
AO4466_SO8

PC55
PR85
@ 680P_0603_50V8J @ 4.7_1206_5%

LX_5V

5
6
7
8

1
2

20

POK

PC48
10U_1206_25V6M

LL1

PQ27
SSM3K7002FU_SC70-3

24
23

LL2

2
G

VO1
PGOOD

PC47
2200P_0402_50V7K

11

2
D
PQ26
SSM3K7002FU_SC70-3

ENTRIP2

LX_3V

2
1
PC57
0.1U_0603_25V7K

22,38

ENTRIP1

ENTRIP1

2
VFB1

21

VREF

22

DRVH1

VREG5

VBST1

DRVH2

VIN

VBST2

10

15

8
7
6
5

B+

PR86
499K_0402_1%
1
2

UG_3V

EN0

PR87
100K_0402_5%

37

VFB2

BST_3V

PC51
.1U_0402_16V7K
PR83
BST_5V 1
2 1
2
0_0603_5%
UG_5V

SKIPSEL

VREG3

PC131
1U_0402_6.3V6K

1
2
3

PQ24
AO4712_SO8

1
2
3

PC54
PR84
@ 680P_0603_50V8J @ 4.7_1206_5%
2
1
2
1

Ipeak=5A
Imax=3.5A
F=305KHz
Total Capacitor 220u,
ESR 15mohm

PC52
220U_6.3V_M

+3VALWP

PC50
.1U_0402_16V7K

VO2

14

PR82
2 1
2
0_0603_5%

PR81
150K_0402_1%
2

B++

PL4
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2

P PAD

TONSEL

PU6

25
2

PC49
4.7U_0805_10V6K

1
2

1
2

PQ22
AO4466_SO8

ENTRIP1

PR79
19.1K_0402_1%
1
2

PR80
150K_0402_1%
1
2

8
7
6
5

PR78
20K_0402_1%
1
2

ENTRIP2

PR77
30K_0402_1%
1
2

+3VLP

1
PC46
10U_1206_25V6M

PC45
2200P_0402_50V7K

B+

PR76
13K_0402_1%
1
2

ENTRIP2

B++
PL20
HCB4532KF-800T90_1812

Ipeak=5A
Imax=3.5A
F=245KHz
Total Capacitor 220u,
ESR 15mohm

1
PR90
100K_0402_1%

PQ28
SSM3K7002FU_SC70-3

2
G
1

PC58
@ 0.01U_0402_16V7K

2
1
PR91
49.9K_0402_1%

VS

PR89
100K_0402_1%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Issued Date

Deciphered Date

2012/07/22

Title

SCHEMATIC MB A4982

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

40

of

45

PL21
HCB4532KF-800T90_1812

1
2

PC60
4.7U_1206_25V6K

1
3
2
1

PR97
14.7K_0402_1%

DL_1.05V

DRVL

PQ30
FDS6670AS_NL_SO8
4 G

PC67
4.7U_0805_10V6K

+1.05VSP

1
+
2

Ipeak=10A
Imax=7A
F=315KHz
Total Capacitor 1430u,
ESR 2.5mohm

PC63
220U_6.3V_M

10

+5VALW

V5DRV

11

PR95
4.7_1206_5%

14

12

TPS51117RGYR_QFN14_3.5x3.5

@ PC66
@PC66
47P_0402_50V8J
1
2

LX_1.05V

LL
TRIP

PGND

PGOOD

GND

PC64
4.7U_0603_6.3V6K

0.1U_0603_25V7K

VFB

B+

PC65
680P_0603_50V8J

DH_1.05V

5
6
7
8

V5FILT

13

D
D
D
D

VOUT

DRVH

S
S
S

VBST

15
TP

TON

3
2
1

PR96
100_0603_1%
1
2

PL6
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

PC62
BST_1.05V-1

+5VALW

PU7

EN_PSV

@PC61
@PC61
.1U_0402_16V7K

PR94
2.2_0603_1%
BST_1.05V1
2

17,27,29,33,36,39 SUSP#

PR92
255K_0402_1%
1
2

PR93
0_0402_5%
1
2

PQ29
AO4466_SO8

5
6
7
8

PC59
4.7U_1206_25V6K

1.05V_B+

PR98
8.25K_0402_1%
1
2

PR99
20.5K_0402_1%

PL22
HCB4532KF-800T90_1812

PR100
255K_0402_1%
1
2

V5DRV

10

PR105
3K_0402_1%

DL_1.8V

+5VALW

PQ32
AO4712_SO8

+1.8VSP

1
+
2

TPS51117RGYR_QFN14_3.5x3.5

PC76
4.7U_0805_10V6K

Ipeak=2A
Imax=1.4A
F=315KHz
Total Capacitor 220u,
ESR 15mohm

PC72
220U_6.3V_M

11

PGND
8

@PC75
@
PC75
47P_0402_50V8J
1
2

3
2
1

12

DRVL

PGOOD

LX_1.8V

LL
TRIP

PR103
4.7_1206_5%

GND

PC73
4.7U_0603_6.3V6K

0.1U_0603_25V7K

VFB

DH_1.8V

13

V5FILT

DRVH

5
6
7
8

VOUT

VBST

14

15
TP

TON

PL7
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

PC71
BST_1.8V-1

3
2
1

PR104
100_0603_1%
1
2

+5VALW

PU8

EN_PSV

PC70
.1U_0402_16V7K

B+

PR102
2.2_0603_1%
BST_1.8V 1
2

17,27,29,33,36,39 SUSP#

PR101
220K_0402_5%
1
2

PC74
680P_0603_50V8J

2
PC69
4.7U_1206_25V6K

1
PQ31
AO4466_SO8

5
6
7
8

For Discrete

PC68
4.7U_1206_25V6K

1.8V_B+

PR106
28.7K_0402_1%
1
2

PR107
20.5K_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/22

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009
D

Sheet

41

of

45

PL23
HCB4532KF-800T90_1812

PQ33
3
2
1

TPS51117RGYR_QFN14_3.5x3.5

1
2

B+

PC78
4.7U_1206_25V6K

PC85
4.7U_0805_10V6K

1
+
2

+1.5VP

Ipeak=11A
Imax=7.7A
F=315KHz
Total Capacitor 940u,
ESR 4.286mohm

PC81
220U_6.3V_M

DL_1.5V
1

PR112
3.9K_0402_1%

15
TP
8

PC84
@ 47P_0402_50V8J
1
2

DRVL

PGND

PGOOD

GND

PC82
4.7U_0603_6.3V6K

+5VALW

PR113
4.7_1206_5%

10

V5DRV

LX_1.5V
1

TRIP

11

VFB

12

0.1U_0603_25V7K

PC83
680P_0603_50V8J

V5FILT

LL

DH_1.5V

PQ34

VOUT

13

TPCA8028-H_SOP-ADVANCE8-5

DRVH

TON

PL8
1.0UH_PCMC104T-1R0MN_20A_20%
1
2

PC80
BST_1.5V-1

3
2
1

PR111
100_0603_1%
1
2

+5VALW

PU9

EN_PSV

@PC79
@PC79
.1U_0402_16V7K

14

SYSON

PR110
2.2_0603_1%
BST_1.5V 1
2

VBST

PR109
0_0402_5%
1
2
1

27,33

PR108
255K_0402_1%
1
2

TPCA8030-H_SOP-ADV8-5

PC77
4.7U_1206_25V6K

1.5V_B+

PR114
20.5K_0402_1%
1
2

PR257
100K_0402_5%
1
2

DDR3_SM_PWROK

+3VALW

+1.5V

2
1

PR115
20.5K_0402_1%

+5VALW

@PJ34
@
PJ34
JUMP_43X79

@PC132
@
PC132 .1U_0402_16V7K

For UMA

@ PC199
@PC199
4.7U_0805_6.3V6K

@PC198
@
PC198
1U_0603_6.3V6M

@PJ17
@
PJ17
JUMP_43X79

APL5915KAI-TRL_SO8

TP

PC201
22U_0805_6.3V6M

FB

PC90
10U_0805_6.3V6M

EN

+0.75VSP

PR118
1K_0402_1%

PC88
PQ35
.1U_0402_16V7K
SSM3K7002FU_SC70-3

3
2

@ PC89
@PC89
.1U_0402_16V7K

2
G

PC200
0.01U_0402_25V7K

2
1

PR117
0_0402_5%
1
2

SUSP

36

SYSON

@ PC202
@PC202
0.01U_0402_25V7K

APL5331KAC-TRL_SO8

27,33

+1.8VP
@ PR255
@PR255
3K_0402_1%

TP

NC

VOUT

VOUT

0_0402_5%
1
2

5
4

PR256
2.4K_0402_1%

VCNTL

NC

VIN
VOUT

GND

VREF

POK

@PR254
@
PR254

NC

GND

+3VALW
1

6
5

VIN

PR116
1K_0402_1%

PC86
4.7U_0805_6.3V6K

@PU16
@
PU16
VCNTL

PC87
1U_0603_6.3V6M

PU10
1

+1.5V

2009/07/22

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/22

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Sheet

Wednesday, December 30, 2009


1

42

of

45

PR164 1K_0402_1%

VCC_PRM
PC123
0.22U_0603_10V7K

3
2
1

PC99
3300P_0402_50V7K

1
2

PC98
680P_0603_50V8J
2
1

@ PC97
220U_25V_M

PR136
10K_0402_1%
2
1

1
PR135
2

@ PR134
4.7_1206_5%

3.65K_0805_1%

2
1

PR149
1_0402_5%

PC115
0.22U_0603_10V7K

+CPU_B+

VCC_PRM
ISEN2

PR165 3.9K_0402_1%
PC122 .1U_0402_16V7K
1
2
2

2.61K_0402_1%

PR162
20_0402_5%

1
2
PR161 0_0402_5%
PC121 180P_0402_50V8J
1
2

PR163

VSSSENSE

20_0402_5%

PH4
10KB_0603_5%_ERTJ1VR103J
1

VSUM
PC120
0.01U_0603_50V7K

PR159

PC119
330P_0603_50V8

+CPU_CORE

PC118 330P_0603_50V8
1
2

2
0_0402_5%

PR158

VCCSENSE

VCC_PRM

PR154 @ 0_0603_5%
1
2

VSUM

PC117
0.1U_0603_25V7K

PR157 1K_0402_1%
6

PR156
10_0603_5%
2

PR160

ISEN2
1
2
+5VS
PR150 1_0603_5%
PC113
1U_0402_6.3V6K

PC116 2200P_0402_50V7K
1
2
1

PC94
10U_1206_25V6M
2
1
1

3
2
1

100P_0402_50V8J

11K_0402_1%

PC114

PR155 100_0402_1%
1

PR153
1K_0402_5%

2
2

1 2

PQ40
TPCA8028-H_SOP-ADVANCE8-5
4
ISEN1

PR151 97.6K_0402_1% PC112 270P_0402_50V7K


1
2
2
1

49

PR137 @ 0_0603_5%
1
2

PR148
10K_0402_1%
2
1

TP

BOOT_CPU2
1
2
1
2
PR144
2.2_0603_1%
PC108
0.22U_0603_10V7K

PR147

25

PR141
1_0402_5%

PL11
0.36UH_PCMC104T-R36MN1R17_30A_20%

26

NC

+CPU_CORE

+CPU_B+

3.65K_0805_1%

BOOT2

27

PC106
10U_1206_25V6M

UGATE2

UGATE_CPU2

ISEN1 PC103
0.22U_0603_10V7K

PHASE_CPU2

1 2

28

ISEN1

PHASE2

LGATE_CPU2

24

ISEN2
23

VDD
22

GND
21

13

VIN

PC110 1000P_0402_50V7K

20

FB2
VSUM

FB

12

19

11

VO

COMP

18

10

29

VW

30

PGND2

PC104
10U_1206_25V6M
2
1

PVCC
LGATE2

OCSET

3
2
1

ISL6266AHRZ-T_QFN48_7X7

SOFT

VDIFF

1
2
1000P_0402_50V7K PC109
PR145 8.25K_0402_1%
1
2

NTC

PC93
10U_1206_25V6M
2
1

LGATE_CPU1
PC129
330P_0402_50V7K
2
1

32
31

@ PQ41
TPCA8028-H_SOP-ADVANCE8-5

LGATE1

VR_TT#

@ PC102
680P_0603_50V8J

VSUM

@ PR146
4.7_1206_5%

PHASE_CPU1

33

@ PC111
680P_0603_50V8J

34

PGND1

@ PQ38
TPCA8028-H_SOP-ADVANCE8-5

PHASE1

RBIAS

3
2
1

PMON

PC95
0.01U_0402_25V7K

3
2
1
5

37
VID0

38
VID1

39
VID2

40
VID3

41
VID4

42
VID5

PC92
2.2U_0603_6.3V6K
2
1

PR131

PR130

PR126

PR125

PR124

1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2

43
VID6

45

44

46
DPRSTP#

DFB

13K_0402_1%
1
2

UGATE_CPU1

17

@ 100K_0603_1%_TH11-4H104FT
1
2
@PC105
@
PC105 0.015U_0402_16V7K
0.022U_0603_25V7K PC107
1
2
PR143

35

PH3
2

UGATE1

DROOP

VR_TT#
@PR142
@
PR142 4.22K_0402_1%
1
2 1

BOOT1

PSI#

RTN

PGOOD

PQ39
TPCA8023-H_SO8
PC128
330P_0402_50V7K
2
1

1
2
PR139 147K_0402_1%

PQ37
TPCA8028-H_SOP-ADVANCE8-5
4

16

PMON

PC125 .1U_0402_16V7K
2
1

4.99K_0402_1%
2

B+

PL10
0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1

PR138
1

15

H_PSI#

DPRSLPVR

VGATE

PQ36
TPCA8023-H_SO8

2.2_0603_1% 0.22U_0603_10V7K
PR140
PC101
1
2 1
2
BOOT_CPU1

36

VSEN

PL9
HCB4532KF-800T90_1812
1
2
1

14

8,23,33

47

48
3V3

PU11

CLK_EN#

1
PR132

2
PR133
499_0402_1%

1.91K_0402_1%

+3VS

0_0402_5%
2

0_0402_5%
2
PC100
1U_0603_6.3V6M
2
1

PR127
1

VR_ON

PR122
1

CLK_ENABLE#

0_0402_5%
2

PR123

PR121
1

5,8,22 H_DPRSTP#

+3VS

0_0402_5%
2
PR129

PR128

PR120
8,23 PM_DPRSLPVR

PC91
0.022U_0402_16V7K
2
1

PC127
330P_0402_50V7K
2
1

PC126
330P_0402_50V7K
2
1

+CPU_B+

PR119
1_0603_5%

PC96
220U_25V_M

6
CPU_VID2
6
CPU_VID1
6
CPU_VID0
6

33
CPU_VID3

CPU_VID4

CPU_VID5

CPU_VID6

VR_ON

+5VS

PC124 0.22U_0402_6.3V6K
2
1

2009/07/22

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/22

Deciphered Date

Title

SCHEMATIC MB A4982

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Wednesday, December 30, 2009
Date:

Rev
B

401791

Sheet
1

43

of

45

NO DATE
PAGE
MODIFICATION LIST
PURPOSE
------------------------------------------------------------------------------------------------------------EVT

P42-+CPU_CORE

change PU11 ISL6262 to ISL6266

change CPU_CORE IC

Change PR145 6.81k to 8.25k

modify the parameter for ISL6266

Change PC112 470P to 270P


Change PC114 220P to 100P
Change PC116 1000P to 2200P
Change PR155 255 to 100
Change PC118 0.018U to 330P
Change PC119 0.018U to 330P
Change PC120 0.018U to 0.01U
Change upop component PC96 to PC97
EVT

P40-1.05V/1.5V

Change PR97 13.7k to 14.7k

Modify trip resistor for ocp

EVT

P41-1.8VP/0.9VSP

Change PR112 15.4k to 18k

Modify trip resistor for ocp

EVT

P38-CHARGER

Add PC162 0.1U

Add detect adapter function

Add PR216 309k


Add PR217 47k
Add PD14 GLZ4.3B
EVT

P38-CHARGER

Change PR49 0.02 to 0.015

Set CP for 90W(X6366051L02)

Change PR70 24k to 53.6k


Change PQ8,PQ9,PQ10,PQ42 FDS4435 to AO4407A

For 90W(X6366051L02)

Change PR69 2.2 to 0


EVT

P38-CHARGER

Change PR70 24k to 24.9k

Set CP for 75W(X6366051L01)

DVT

P36-DCIN/DECTOR

Delete PD13

Precharge detector circuit modify

ENTRIP1 signal change to EN0


ENTRIP2 signal change to ACON
Change PR23 34k to 10k
Add

@ lable to PR25 66.5k

DVT

P39-3VALWP/5VALWP

Add EN0 signal from PU6 pin 13

Precharge detector circuit modify

DVT

P38-CHARGER

Change PR70 24k to 75k

Set CP for 65W(X6366051L03)

DVT

P42-+CPU_CORE

Add PC126,PC127,PC128,PC129 330PF

For EMI solution

Add PR134,PR146 4.7 ohm


Add PC102,PC111 680PF
Change PR140,PR144 0ohm to 2.2ohm
DVT

P38-CHARGER

Change PR71 100k to 120k

DVT

P42-+CPU_CORE

Change PR145 8.25k to 11.3k

Modify charging current for 12 cell


Modify switching frequency

PVT

P38-CHARGER

Change PL3 Part NO SH000003080 to SH162100M10

SH000003080

PVT

P36-DCIN/DECTOR

Change PU1 8 pin connect to N1

For precharge function

Change PL3 16U to 10U


footprint is wrong

PVT

P38-CHARGER

Add PR166 10k Ohm

Modify

PVT

P38-CHARGER

Remove PD14

Modify ADP_V circuit(2009/02/18)

ADP_V

circuit(2009/02/18)

PVT

P38-CHARGER

Change PR74 18.2k to 15.4k

Change CHGVADJ voltage dividers value(2009/02/18)

PVT

P42-+CPU_CORE

Change PC126,PC127,PC128,PC129
(SE068331K80) to (SE00000FD80)

Change temperature tolerance K(10%) to J(5%)(2009/02/23)

PREMP

P38-CHARGER

Add PR167 10_0603_5%

Add 10 Ohm to DCIN circuit(2009/03/12)

PREMP

P38-CHARGER

Add PL19 HCB4532KF-800T90_1812 and delete PJ12

Add bead on B+ node(2009/03/12)

PREMP

P39-3VALWP/5VALWP

Add PL20 HCB4532KF-800T90_1812 and delete PJ13

Add bead on B+ node(2009/03/12)

PREMP

P40-1.05V/1.5V

Add PL21 HCB4532KF-800T90_1812 and delete PJ14

Add bead on B+ node(2009/03/12)

Add PL22 HCB4532KF-800T90_1812 and delete PJ15

Add bead on B+ node(2009/03/12)

PREMP

P41-1.8VP/0.9VSP

Add PL23 HCB4532KF-800T90_1812 and delete PJ16

Add bead on B+ node(2009/03/12)

PREMP

P39-3VALWP/5VALWP

Change PR79 19.6k to 19.1k

Modify 5V to 5.14V(2009/04/08)

PREMP

P38-CHARGER

Change PR65 100 to 47k

For CPU throtting setting(2009/04/08)

Change PR82,PR83,PR94,PR102,PR110 SD014000080


(0 +-1% 0603) to SD013000080 (0 +-5% 0603)

Component not haven 0_+-1%, change to 0_5%(2009/04/08)

PREMP
PREMP

P42-+CPU_CORE

Change PC126,PC127,PC128,PC129
(SE0000FD80) to (SE074331K80)

Change property NPO to X7R(2009/04/08)

PREMP

P41-1.05VSP/1.8VP

Change PR96 422 ohm to 100 ohm

Avoid 2nd source RT8209B can not power on(2009/07/27)

Change PC64 1U to 4.7U


PREMP

P42-1.5VP/0.75VSP

Change PR111 422 ohm to 100 ohm

Avoid 2nd source RT8209B can not power on(2009/07/27)

Change PC82 1U to 4.7U


PREMP

P42-1.5VP/0.75VSP

Change PR112 14.7k to 3.9k

Set 1.5V OCP to 13.25A(2009/07/27)

PREMP

P40-3VALWP/5VALWP

Change PC52, PC53 SF22001M200 to SF000001H00

SF22001M200 is forbids to use (2009/08/04)

PREMP

P41-1.05VSP/1.8VP

Change PC63, PC72 SF22001M200 to SF000001H00

SF22001M200 is forbids to use (2009/08/04)

PREMP

P42-1.5VP/0.75VSP

Change PC81 SF22001M200 to SF000001H00

SF22001M200 is forbids to use (2009/08/04)

MP

P42-1.5VP/0.75VP

Change High,Low side Mosfet and Choke.

(2009/06/18)

Add bead on B+ node


MP

P38-BATTERY CONN /
OTP

Change PR33 13.7k to 12.4k

Change resistor for OTP (2009/09/01)

Change PR37 15.4k to 15.8k

Compal Secret Data

Security Classification
Issued Date

2009/07/22

Deciphered Date

2012/07/22

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet

44

of

45

PIR (Product Improve Record)


KSWAA LA-4982P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 1.0
NO DATE
PAGE MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------1
7/22
15
delete C604~C610,C643~C645
Change reference plane of control from VCC to GND
2
7/24
35
change PCB P/N to DAZ07300200
For load BOM
3
7/27
14
add CD45 and un-mount CD17,CD39 on DDR 1.5V
design change
D

2009/07/22

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/22

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC MB A4982
Document Number

Rev
B

401791
Wednesday, December 30, 2009

Sheet
1

45

of

45