Vi Dieu Khien PIC PDF

MUC LUC
CHNG 1 TONG QUAN VE VI IEU KHIEN PIC

1.1 PIC LA G ??
1.2 TAI SAO LA PIC MA KHONG LA CAC HO VI IEU KHIEN KHAC??
1.3 KIEN TRUC PIC
1.4 RISC VA CISC
1.5 PIPELINING
1.6 CAC DONG PIC VA CACH LA CHON VI IEU KHIEN PIC
1.7 NGON NG LAP TRNH CHO PIC
1.8 MACH NAP PIC
1.9 BOOTLOADER VA ICP (In Circuit Programming)
CHNG 2 VI IEU KHIEN PIC16F877A
2.1 S O CHAN VI IEU KHIEN PIC16F877A
2.2 MOT VAI THONG SO VE VI IEU KHIEN PIC16F877A
2.3 S O KHOI VI IEU KHIEN PIC16F877A
2.4 TO CHC BO NH
2.4.1 BO NH CHNG TRNH
2.4.2 BO NH D LIEU
2.4.2.1 THANH GHI CHC NANG AC BIET SFR
2.4.2.2 THANH GHI MUC CH CHUNG GPR
2.4.3 STACK
2.5 CAC CONG XUAT NHAP CUA PIC16F877A
2.5.1 PORTA
2.5.2 PORTB
2.5.3 PORTC
2.5.4 PORTD
2.5.5 PORTE
2.6 TIMER 0
2.7 TIMER1
2.8 TIMER2
2.9 ADC
2.10 COMPARATOR
2.10.1 BO TAO IEN AP SO SANH
2.11 CCP
2.12 GIAO TIEP NOI TIEP
1.12.1 USART
2.12.1.1 USART BAT ONG BO
2.12.1.1.1 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART BAT ONG BO
2.12.1.1.2 NHAN D LIEU QUA CHUAN GIAO TIEP USART BAT ONG BO
2.12.1.1.2 USART ONG BO
2.12.1.2.1 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART ONG BO MASTER
MODE
2.12.1.2.2 NHAN D LIEU QUA CHUAN GIAO TIEP USART ONG BO MASTER
MODE
2.12.1.2.3 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART ONG BO SLAVE
MODE
2.12.1.2.4 NHAN D LIEU QUA CHUAN GIAO TIEP USART ONG BO SLAVE MODE
2.12.2 MSSP
2.12.2.1 SPI
2.12.2.1.1 SPI MASTER MODE
2.12.2.1.2 SPI SLAVE MODE
2.12.2.2 I2C
2.12.2.2.1 I2C SLAVE MODE
2.12.2.2.2 I2C MASTER MODE
2.13 CONG GIAO TIEP SONG SONG PSP (PARALLEL SLAVE PORT)
2.14 TONG QUAN VE MOT SO AC TNH CUA CPU.
2.14.1 CONFIGURATION BIT
2.14.2 CAC AC TNH CUA OSCILLATOR
2.14.3 CAC CHE ORESET
2.14.4 NGAT (INTERRUPT)
2.14.4.1 NGAT INT
2.14.4.2 NGAT DO S THAY OI TRANG THAI CAC PIN TRONG PORTB
2.14.5 WATCHDOG TIMER (WDT)
2.14.6 CHE O SLEEP
2.14.6.1 ANH THC VI IEU KHIEN
CHNG 3 TAP LENH CUA VI IEU KHIEN PIC
3.1 VAI NET S LC VE TAP LENH CUA VI IEU KHIEN PIC
3.2 TAP LENH CUA VI IEU KHIEN PIC
3.3 CAU TRUC CUA MOT CHNG TRNH ASSEMBLY VIET CHO VI IEU KHIEN
PIC
CHNG 4 MOT SO NG DUNG CU THE CUA PIC16F877A

4.1 IEU KHIEN CAC PORT I/O
4.1.1 CHNG TRNH DELAY
4.1.2 MOT SO NG DUNG VE AC TNH I/O CUA CAC PORT IEU KHIEN
4.2 VI IEU KHIEN PIC16F877A VA IC GHI DCH 74HC595
4.3 PIC16F877A VA LED 7 OAN
4.4 NGAT VA CAU TRUC CUA MOT CHNG TRNH NGAT
4.5 TIMER VA NG DUNG
4.5.1 TIMER VA HOAT ONG NH THI
PHU LUC 1 S O KHOI CAC PORT CUA VI IEU KHIEN PIC16F877A
PHU LUC 2 THANH GHI SFR (SPECIAL FUNCTION REGISTER)
CHNG 1 TONG QUAN VE VI IEU KHIEN PIC

1.1 PIC LA G ??
PIC la viet tat cua Programable Intelligent Computer, co the tam dch la may tnh thong
minh kha trnh do hang Genenral Instrument at ten cho vi ieu khien au tien cua ho:
PIC1650 c thiet ke e dung lam cac thiet b ngoai vi cho vi ieu khien CP1600. Vi ieu
khien nay sau o c nghien cu phat trien them va t o hnh thanh nen dong vi ieu
khien PIC ngay nay.
1.2 TAI SAO LA PIC MA KHONG LA CAC HO VI IEU KHIEN KHAC??
Hien nay tren th trng co rat nhieu ho vi ieu khien nh 8051, Motorola 68HC, AVR,
ARM,... Ngoai ho 8051 c hng dan mot cach can ban moi trng ai hoc, ban than
ngi viet a chon ho vi ieu khien PIC e m rong von kien thc va phat trien cac ng
dung tren cong cu nay v cac nguyen nhan sau:
Ho vi ieu khien nay co the tm mua de dang tai th trng Viet Nam.
Gia thanh khong qua at.
Co ay u cac tnh nang cua mot vi ieu khien khi hoat ong oc lap.
La mot s bo sung rat tot ve kien thc cung nh ve ng dung cho ho vi ieu khien
mang tnh truyen thong: ho vi ieu khien 8051.
So lng ngi s dung ho vi ieu khien PIC. Hien nay tai Viet Nam cung nh tren
the gii, ho vi ieu khien nay c s dung kha rong rai. ieu nay tao nhieu thuan li trong
qua trnh tm hieu va phat trien cac ng dung nh: so lng tai lieu, so lng cac ng dung
m a c phat trien thanh cong, de dang trao oi, hoc tap, de dang tm c s ch dan khi
gap kho khan,
S ho tr cua nha san xuat ve trnh bien dch, cac cong cu lap trnh, nap chng trnh
t n gian en phc tap,
Cac tnh nang a dang cua vi ieu khien PIC, va cac tnh nang nay khong ngng c
phat trien.
1.3 KIEN TRUC PIC
Cau truc phan cng cua mot vi ieu khien c thiet ke theo hai dang kien truc: kien truc
Von Neuman va kien truc Havard.
Hnh 1.1: Kien truc Havard va kien truc Von-Neuman

To chc phan cng cua PIC c thiet ke theo kien truc Havard. iem khac biet gia kien
truc Havard va kien truc Von-Neuman la cau truc bo nh d lieu va bo nh chng trnh.
oi vi kien truc Von-Neuman, bo nh d lieu va bo nh chng trnh nam chung trong mot
bo nh, do o ta co the to chc, can oi mot cach linh hoat bo nh chng trnh va bo nh d
lieu. Tuy nhien ieu nay ch co y ngha khi toc o x l cua CPU phai rat cao, v vi cau truc
o, trong cung mot thi iem CPU ch co the tng tac vi bo nh d lieu hoac bo nh
chng trnh. Nh vay co the noi kien truc Von-Neuman khong thch hp vi cau truc cua
mot vi ieu khien.
oi vi kien truc Havard, bo nh d lieu va bo nh chng trnh tach ra thanh hai bo nh
rieng biet. Do o trong cung mot thi iem CPU co the tng tac vi ca hai bo nh, nh vay
toc o x l cua vi ieu khien c cai thien ang ke.
Mot iem can chu y na la tap lenh trong kien truc Havard co the c toi u tuy theo yeu
cau kien truc cua vi ieu khien ma khong phu thuoc vao cau truc d lieu. V du, oi vi vi
ieu khien dong 16F, o dai lenh luon la 14 bit (trong khi d lieu c to chc thanh tng
byte), con oi vi kien truc Von-Neuman, o dai lenh luon la boi so cua 1 byte (do d lieu
c to chc thanh tng byte). ac iem nay c minh hoa cu the trong hnh 1.1.
1.4 RISC va CISC
Nh a trnh bay tren, kien truc Havard la khai niem mi hn so vi kien truc VonNeuman. Khai niem nay c hnh thanh nham cai tien toc o thc thi cua mot vi ieu khien.
Qua viec tach ri bo nh chng trnh va bo nh d lieu, bus chng trnh va bus d lieu,
CPU co the cung mot luc truy xuat ca bo nh chng trnh va bo nh d lieu, giup tang toc
o x l cua vi ieu khien len gap oi. ong thi cau truc lenh khong con phu thuoc vao cau
truc d lieu na ma co the linh ong ieu chnh tuy theo kha nang va toc o cua tng vi ieu
khien. Va e tiep tuc cai tien toc o thc thi lenh, tap lenh cua ho vi ieu khien PIC c
thiet ke sao cho chieu dai ma lenh luon co nh (v du oi vi ho 16Fxxxx chieu dai ma lenh
luon la 14 bit) va cho phep thc thi lenh trong mot chu k cua xung clock ( ngoai tr mot so
trng hp ac biet nh lenh nhay, lenh goi chng trnh con can hai chu k xung ong ho).
ieu nay co ngha tap lenh cua vi ieu khien thuoc cau truc Havard se t lenh hn, ngan hn,
n gian hn e ap ng yeu cau ma hoa lenh bang mot so lng bit nhat nh.
Vi ieu khien c to chc theo kien truc Havard con c goi la vi ieu khien RISC
(Reduced Instruction Set Computer) hay vi ieu khien co tap lenh rut gon. Vi ieu khien
c thiet ke theo kien truc Von-Neuman con c goi la vi ieu khien CISC (Complex
Instruction Set Computer) hay vi ieu khien co tap lenh phc tap v ma lenh cua no khong
phai la mot so co nh ma luon la boi so cua 8 bit (1 byte).
1.5 PIPELINING
ay chnh la c che x l lenh cua cac vi ieu khien PIC. Mot chu k lenh cua vi ieu khien
se bao gom 4 xung clock. V du ta s dung oscillator co tan so 4 MHZ, th xung lenh se co
tan so 1 MHz (chu k lenh se la 1 us). Gia s ta co mot oan chng trnh nh sau:
1. MOVLW
55h
2. MOVWF
PORTB
3. CALL
SUB_1
4. BSF
PORTA,BIT3
5. instruction @ address SUB_1
ay ta ch ban en qui trnh vi ieu khien x l oan chng trnh tren thong qua
tng chu k lenh. Qua trnh tren se c thc thi nh sau:
Hnh 1.2: C che pipelining
TCY0: oc lenh 1
TCY1: thc thi lenh 1, oc lenh 2
TCY2: thc thi lenh 2, oc lenh 3
TCY3: thc thi lenh 3, oc lenh 4.
TCY4: v lenh 4 khong phai la lenh se c thc thi theo qui trnh thc thi cua chng
trnh (lenh tiep theo c thc thi phai la lenh au tien tai label SUB_1) nen chu k thc thi
lenh nay ch c dung e oc lenh au tien tai label SUB_1. Nh vay co the xem lenh 3
can 2 chu k xung clock e thc thi.
TCY5: thc thi lenh au tien cua SUB_1 va oc lenh tiep theo cua SUB_1.
Qua trnh nay c thc hien tng t cho cac lenh tiep theo cua chng trnh.
Thong thng, e thc thi mot lenh, ta can mot chu k lenh e goi lenh o, va mot chu k
xung clock na e giai ma va thc thi lenh. Vi c che pipelining c trnh bay tren, moi
lenh xem nh ch c thc thi trong mot chu k lenh. oi vi cac lenh ma qua trnh thc thi
no lam thay oi gia tr thanh ghi PC (Program Counter) can hai chu k lenh e thc thi v phai
thc hien viec goi lenh a ch thanh ghi PC ch ti. Sau khi a xac nh ung v tr lenh
trong thanh ghi PC, moi lenh ch can mot chu k lenh e thc thi xong.
1.6 CAC DONG PIC VA CACH LA CHON VI IEU KHIEN PIC
Cac k hieu cua vi ieu khien PIC:
PIC12xxxx: o dai lenh 12 bit
C: PIC co bo nh EPROM (ch co 16C84 la EEPROM)
F: PIC co bo nh flash
LF: PIC co bo nh flash hoat ong ien ap thap
LV: tng t nh LF, ay la k hieu cu
Ben canh o mot so vi ieu khien co k hieu xxFxxx la EEPROM, neu co them ch A
cuoi la flash (v du PIC16F877 la EEPROM, con PIC16F877A la flash).
Ngoai ra con co them mot dong vi ieu khien PIC mi la dsPIC.
Viet Nam pho bien nhat la cac ho vi ieu khien PIC do hang Microchip san xuat.
Cach la chon mot vi ieu khien PIC phu hp:
Trc het can chu y en so chan cua vi ieu khien can thiet cho ng dung. Co nhieu
vi ieu khien PIC vi so lng chan khac nhau, tham ch co vi ieu khien ch co 8 chan,
ngoai ra con co cac vi ieu khien 28, 40, 44, chan.
Can chon vi ieu khien PIC co bo nh flash e co the nap xoa chng trnh c
nhieu lan hn.
Tiep theo can chu y en cac khoi chc nang c tch hp san trong vi ieu khien,
cac chuan giao tiep ben trong.
Sau cung can chu y en bo nh chng trnh ma vi ieu khien cho phep.
Ngoai ra moi thong tin ve cach la chon vi ieu khien PIC co the c tm thay trong
cuon sach Select PIC guide do nha san xuat Microchip cung cap.
1.7 NGON NG LAP TRNH CHO PIC
Ngon ng lap trnh cho PIC rat a dang. Ngon ng lap trnh cap thap co MPLAB (c cung
cap mien ph bi nha san xuat Microchip), cac ngon ng lap trnh cap cao hn bao gom C,
Basic, Pascal, Ngoai ra con co mot so ngon ng lap trnh c phat trien danh rieng cho
PIC nh PICBasic, MikroBasic,
1.8 MACH NAP PIC
ay cung la mot dong san pham rat a dang danh cho vi ieu khien PIC. Co the s dung cac
mach nap c cung cap bi nha san xuat la hang Microchip nh: PICSTART plus, MPLAB
ICD 2, MPLAB PM 3, PRO MATE II. Co the dung cac san pham nay e nap cho vi ieu
khien khac thong qua chng trnh MPLAB. Dong san pham chnh thong nay co u the la
nap c cho tat ca cac vi ieu khien PIC, tuy nhien gia thanh rat cao va thng gap rat
nhieu kho khan trong qua trnh mua san pham.
Ngoai ra do tnh nang cho phep nhieu che o nap khac nhau, con co rat nhieu mach nap c
thiet ke danh cho vi ieu khien PIC. Co the s lc mot so mach nap cho PIC nh sau:
JDM programmer: mach nap nay dung chng trnh nap Icprog cho phep nap cac vi
ieu khien PIC co ho tr tnh nang nap chng trnh ien ap thap ICSP (In Circuit Serial
Programming). Hau het cac mach nap eu ho tr tnh nang nap chng trnh nay.
WARP-13A va MCP-USB: hai mach nap nay giong vi mach nap PICSTART PLUS
do nha san xuat Microchip cung cap, tng thch vi trnh bien dch MPLAB, ngha la ta co
the trc tiep dung chng trnh MPLAB e nap cho vi ieu khien PIC ma khong can s dung
mot chng trnh nap khac, chang han nh ICprog.
P16PRO40: mach nap nay do Nigel thiet ke va cung kha noi tieng. Ong con thiet ke
ca chng trnh nap, tuy nhien ta cung co the s dung chng trnh nap Icprog.
Mach nap Universal cua Williem: ay khong phai la mach nap chuyen dung danh cho
PIC nh P16PRO40.
Cac mach nap ke tren co u iem rat ln la n gian, re tien, hoan toan co the t lap rap
mot cach de dang, va moi thong tin ve s o mach nap, cach thiet ke, thi cong, kiem tra va
chng trnh nap eu de dang tm c va download mien ph thong qua mang Internet. Tuy
nhien cac mach nap tren co nhc iem la han che ve so vi ieu khien c ho tr, ben canh
o moi mach nap can c s dung vi mot chng trnh nap thch hp.
1.9 BOOTLOADER VA ICP (In Circuit Programming)
CHNG 2 VI IEU KHIEN PIC16F877A

2.1 S O CHAN VI IEU KHIEN PIC16F877A
Hnh 2.1 Vi ieu khien PIC16F877A/PIC16F874A va cac dang s o chan
2.2 MOT VAI THONG SO VE VI IEU KHIEN PIC16F877A

ay la vi ieu khien thuoc ho PIC16Fxxx vi tap lenh gom 35 lenh co o dai 14 bit.
Moi lenh eu c thc thi trong mot chu k xung clock. Toc o hoat ong toi a cho phep la
20 MHz vi mot chu k lenh la 200ns. Bo nh chng trnh 8Kx14 bit, bo nh d lieu 368x8
byte RAM va bo nh d lieu EEPROM vi dung lng 256x8 byte. So PORT I/O la 5 vi 33
pin I/O.
Cac ac tnh ngoai vi bao gomcac khoi chc nang sau:
Timer0: bo em 8 bit vi bo chia tan so 8 bit.
Timer1: bo em 16 bit vi bo chia tan so, co the thc hien chc nang em da vao
xung clock ngoai vi ngay khi vi ieu khien hoat ong che o sleep.
Timer2: bo em 8 bit vi bo chia tan so, bo postcaler.
Hai bo Capture/so sanh/ieu che o rong xung.
Cac chuan giao tiep noi tiep SSP (Synchronous Serial Port), SPI va I2C.
Chuan giao tiep noi tiep USART vi 9 bit a ch.
Cong giao tiep song song PSP (Parallel Slave Port) vi cac chan ieu khien RD, WR,
CS ben ngoai.
Cac ac tnh Analog:
8 kenh chuyen oi ADC 10 bit.
Hai bo so sanh.
Ben canh o la mot vai ac tnh khac cua vi ieu khien nh:
Bo nh flash vi kha nang ghi xoa c 100.000 lan.
Bo nh EEPROM vi kha nang ghi xoa c 1.000.000 lan.
D lieu bo nh EEPROM co the lu tr tren 40 nam.
Kha nang t nap chng trnh vi s ieu khien cua phan mem.
Nap c chng trnh ngay tren mach ien ICSP (In Circuit Serial Programming)
thong qua 2 chan.
Watchdog Timer vi bo dao ong trong.
Chc nang bao mat ma chng trnh.
Che o Sleep.
Co the hoat ong vi nhieu dang Oscillator khac nhau.
2.3 S O KHOI VI IEU KHIEN PIC16F877A
Hnh 2.2 S o khoi vi ieu khien PIC16F877A.
2.4 TO CHC BO NH
Cau truc bo nh cua vi ieu khien PIC16F877A bao gom bo nh chng trnh (Program
memory) va bo nh d lieu (Data Memory).
2.4.1 BO NH CHNG TRNH
Bo nh chng trnh cua vi ieu khien
PIC16F877A la bo nh flash, dung lng bo
nh 8K word (1 word = 14 bit) va c phan
thanh nhieu trang (t page0 en page 3) .
Nh vay bo nh chng trnh co kha nang
cha c 8*1024 = 8192 lenh (v mot lenh
sau khi ma hoa se co dung lng 1 word (14
bit).
e ma hoa c a ch cua 8K word
bo nh chng trnh, bo em chng trnh co
dung lng 13 bit (PC<12:0>).
Khi vi ieu khien c reset, bo em
chng trnh se ch en a ch 0000h (Reset
vector). Khi co ngat xay ra, bo em chng
trnh se ch en a ch 0004h (Interrupt
vector).
Bo nh chng trnh khong bao gom
bo nh stack va khong c a ch hoa bi
bo em chng trnh. Bo nh stack se c
e cap cu the trong phan sau.
2.4.2 BO NH D LIEU
Hnh 2.3 Bo nh chng trnh PIC16F877A
Bo nh d lieu cua PIC la bo nh EEPROM c chia ra lam nhieu bank. oi vi

PIC16F877A bo nh d lieu c chia ra lam 4 bank. Moi bank co dung lng 128 byte, bao
gom cac thanh ghi co chc nang ac biet SFG (Special Function Register) nam cac vung
a ch thap va cac thanh ghi muc ch chung GPR (General Purpose Register) nam vung
a ch con lai trong bank. Cac thanh ghi SFR thng xuyen c s dung (v du nh thanh
ghi STATUS) se c at tat ca cac bank cua bo nh d lieu giup thuan tien trong qua
trnh truy xuat va lam giam bt lenh cua chng trnh. S o cu the cua bo nh d lieu
PIC16F877A nh sau:
Hnh 2.4 S o bo nh d lieu PIC16F877A
2.4.2.1 THANH GHI CHC NANG AC BIET SFR

ay la cac thanh ghi c s dung bi CPU hoac c dung e thiet lap va ieu khien cac
khoi chc nang c tch hp ben trong vi ieu khien. Co the phan thanh ghi SFR lam hai
loai: thanh ghi SFR lien quan en cac chc nang ben trong (CPU) va thanh ghi SRF dung e
thiet lap va ieu khien cac khoi chc nang ben ngoai (v du nh ADC, PWM, ). Phan nay se
e cap en cac thanh ghi lien quan en cac chc nang ben trong. Cac thanh ghi dung e thiet
lap va ieu khien cac khoi chc nang se c nhac en khi ta e cap en cac khoi chc nang
o. Chi tiet ve cac thanh ghi SFR se c liet ke cu the trong bang phu luc 2.
Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi cha ket qua thc hien phep
toan cua khoi ALU, trang thai reset va cac bit chon bank can truy xuat trong bo nh d lieu.
Thanh ghi OPTION_REG (81h, 181h): thanh ghi nay cho phep oc va ghi, cho phep
ieu khien chc nang pull-up cua cac chan trong PORTB, xac lap cac tham so ve xung tac
ong, canh tac ong cua ngat ngoai vi va bo em Timer0.
Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh):thanh ghi cho phep oc va ghi, cha cac
bit ieu khien va cac bit c hieu khi timer0 b tran, ngat ngoai vi RB0/INT va ngat interrputon-change tai cac chan cua PORTB.
Thanh ghi PIE1 (8Ch): cha cac bit ieu khien chi tiet cac ngat cua cac khoi chc
nang ngoai vi.
Thanh ghi PIR1 (0Ch) cha c ngat cua cac khoi chc nang ngoai vi, cac ngat nay
c cho phep bi cac bit ieu khien cha trong thanh ghi PIE1.
Thanh ghi PIE2 (8Dh): cha cac bit ieu khien cac ngat cua cac khoi chc nang
CCP2, SSP bus, ngat cua bo so sanh va ngat ghi vao bo nh EEPROM.
Thanh ghi PIR2 (0Dh): cha cac c ngat cua cac khoi chc nang ngoai vi, cac ngat
nay c cho phep bi cac bit ieu khien cha trong thanh ghi PIE2.
Thanh ghi PCON (8Eh): cha cac c hieu cho biet trang thai cac che o reset cua vi
ieu khien.
2.4.2.2 THANH GHI MUC CH CHUNG GPR

Cac thanh ghi nay co the c truy xuat trc tiep hoac gian tiep thong qua thanh ghi
FSG (File Select Register). ay la cac thanh ghi d lieu thong thng, ngi s dung co the
tuy theo muc ch chng trnh ma co the dung cac thanh ghi nay e cha cac bien so, hang
so, ket qua hoac cac tham so phuc vu cho chng trnh.
2.4.3 STACK
Stack khong nam trong bo nh chng trnh hay bo nh d lieu ma la mot vung nh
ac biet khong cho phep oc hay ghi. Khi lenh CALL c thc hien hay khi mot ngat xay ra
lam chng trnh b re nhanh, gia tr cua bo em chng trnh PC t ong c vi ieu khien
cat vao trong stack. Khi mot trong cac lenh RETURN, RETLW hat RETFIE c thc thi, gia
tr PC se t ong c lay ra t trong stack, vi ieu khien se thc hien tiep chng trnh theo
ung qui trnh nh trc.
Bo nh Stack trong vi ieu khien PIC ho 16F87xA co kha nang cha c 8 a ch va
hoat ong theo c che xoay vong. Ngha la gia tr cat vao bo nh Stack lan th 9 se ghi e
len gia tr cat vao Stack lan au tien va gia tr cat vao bo nh Stack lan th 10 se ghi e len
gia tri6 cat vao Stack lan th 2.
Can chu y la khong co c hieu nao cho biet trang thai stack, do o ta khong biet c
khi nao stack tran. Ben canh o tap lenh cua vi ieu khien dong PIC cung khong co lenh
POP hay PUSH, cac thao tac vi bo nh stack se hoan toan c ieu khien bi CPU.
2.5 CAC CONG XUAT NHAP CUA PIC16F877A

Cong xuat nhap (I/O port) chnh la phng tien ma vi ieu khien dung e tng tac
vi the gii ben ngoai. S tng tac nay rat a dang va thong qua qua trnh tng tac o,
chc nang cua vi ieu khien c the hien mot cach ro rang.
Mot cong xuat nhap cua vi ieu khien bao gom nhieu chan (I/O pin), tuy theo cach bo
tr va chc nang cua vi ieu khien ma so lng cong xuat nhap va so lng chan trong moi
cong co the khac nhau. Ben canh o, do vi ieu khien c tch hp san ben trong cac ac
tnh giao tiep ngoai vi nen ben canh chc nang la cong xuat nhap thong thng, mot so chan
xuat nhap con co them cac chc nang khac e the hien s tac ong cua cac ac tnh ngoai vi
neu tren oi vi the gii ben ngoai. Chc nang cua tng chan xuat nhap trong moi cong hoan
toan co the c xac lap va ieu khien c thong qua cac thanh ghi SFR lien quan en chan
xuat nhap o.
Vi ieu khien PIC16F877A co 5 cong xuat nhap, bao gom PORTA, PORTB, PORTC,
PORTD va PORTE. Cau truc va chc nang cua tng cong xuat nhap se c e cap cu the
trong phan sau.
2.5.1 PORTA
PORTA (RPA) bao gom 6 I/O pin. ay la cac chan hai chieu (bidirectional pin),
ngha la co the xuat va nhap c. Chc nang I/O nay c ieu khien bi thanh ghi TRISA
(a ch 85h). Muon xac lap chc nang cua mot chan trong PORTA la input, ta set bit ieu
khien tng ng vi chan o trong thanh ghi TRISA va ngc lai, muon xac lap chc nang
cua mot chan trong PORTA la output, ta clear bit ieu khien tng ng vi chan o trong
thanh ghi TRISA. Thao tac nay hoan toan tng t oi vi cac PORT va cac thanh ghi ieu
khien tng ng TRIS (oi vi PORTA la TRISA, oi vi PORTB la TRISB, oi vi PORTC
la TRISC, oi vi PORTD la TRISD vaoi vi PORTE la TRISE). Ben canh o PORTA con
la ngo ra cua bo ADC, bo so sanh, ngo vao analog ngo vao xung clock cua Timer0 va ngo
vao cua bo giao tiep MSSP (Master Synchronous Serial Port). ac tnh nay se c trnh bay
cu the trong phan sau.
Cau truc ben trong va chc nang cu the cua tng chan trong PORTA se c trnh bay
cu the trong Phu luc 1.
Cac thanh ghi SFR lien quan en PORTA bao gom:
PORTA (a ch 05h)
TRISA (a ch 85h)
CMCON (a ch 9Ch)
CVRCON (a ch 9Dh)
: cha gia tr cac pin trong PORTA.

: ieu khien xuat nhap.
: thanh ghi ieu khien bo so sanh.
: thanh ghi ieu khien bo so sanh ien ap.
ADCON1 (a ch 9Fh)
: thanh ghi ieu khien bo ADC.
Chi tiet ve cac thanh ghi se c trnh bay cu the trong phu luc 2.
2.5.2 PORTB
PORTB (RPB) gom 8 pin I/O. Thanh ghi ieu khien xuat nhap tng ng la TRISB.
Ben canh o mot so chan cua PORTB con c s dung trong qua trnh nap chng trnh cho
vi ieu khien vi cac che o nap khac nhau. PORTB con lien quan en ngat ngoai vi va bo
Timer0. PORTB con c tch hp chc nang ien tr keo len c ieu khien bi chng
trnh.
Cau truc ben trong va chc nang cu the cua tng chan trong PORTB se c trnh bay
Cac thanh ghi SFR lien quan en PORTB bao gom:
PORTB (a ch 06h,106h)
: cha gia tr cac pin trong PORTB
TRISB (a ch 86h,186h)
: ieu khien xuat nhap
OPTION_REG (a ch 81h,181h) : ieu khien ngat ngoai vi va bo Timer0.
2.5.3 PORTC
PORTC (RPC) gom 8 pin I/O. Thanh ghi ieu khien xuat nhap tng ng la TRISC.
Ben canh o PORTC con cha cac chan chc nang cua bo so sanh, bo Timer1, bo PWM va
cac chuan giao tiep noi tiep I2C, SPI, SSP, USART.
Cau truc ben trong va chc nang cu the cua tng chan trong PORTC se c trnh bay
Cac thanh ghi ieu khien lien quan en PORTC:
PORTC (a ch 07h)
: cha gia tr cac pin trong PORTC
TRISC (a ch 87h)
2.5.4 PORTD
PORTD (RPD) gom 8 chan I/O, thanh ghi ieu khien xuat nhap tng ng la TRISD.
PORTD con la cong xuat d lieu cua chuan giao tiep PSP (Parallel Slave Port).
Cau truc ben trong va chc nang cu the cua tng chan trong PORTD se c trnh bay
Cac thanh ghi lien quan en PORTD bao gom:
Thanh ghi PORTD : cha gia tr cac pin trong PORTD.
Thanh ghi TRISD
Thanh ghi TRISE
: ieu khien xuat nhap PORTE va chuan giao tiep PSP.
2.5.5 PORTE
PORTE (RPE) gom 3 chan I/O. Thanh ghi ieu khien xuat nhap tng ng la TRISE.
Cac chan cua PORTE co ngo vao analog. Ben canh o PORTE con la cac chan ieu khien
cua chuan giao tiep PSP.
Cau truc ben trong va chc nang cu the cua tng chan trong PORTE se c trnh bay
Cac thanh ghi lien quan en PORTE bao gom:
PORTE : cha gia tr cac chan trong PORTE.
TRISE
: ieu khien xuat nhap va xac lap cac thong so cho chuan giao tiep PSP.
ADCON1 : thanh ghi ieu khien khoi ADC.
2.6 TIMER 0
ay la mot trong ba bo em hoac bo nh thi cua vi ieu khien PIC16F877A. Timer0
la bo em 8 bit c ket noi vi bo chia tan so (prescaler) 8 bit. Cau truc cua Timer0 cho
phep ta la chon xung clock tac ong va canh tch cc cua xung clock. Ngat Timer0 se xuat
hien khi Timer0 b tran. Bit TMR0IE (INTCON<5>) la bit ieu khien cua Timer0.
TMR0IE=1 cho phep ngat Timer0 tac ong, TMR0IF= 0 khong cho phep ngat Timer0 tac
ong. S o khoi cua Timer0 nh sau:
Hnh 2.5 S o khoi cua Timer0.
Muon Timer0 hoat ong che o Timer ta clear bit TOSC (OPTION_REG<5>), khi
o gia tr thanh ghi TMR0 se tang theo tng chu k xung ong ho (tan so vao Timer0 bang
tan so oscillator). Khi gia tr thanh ghi TMR0 t FFh tr ve 00h, ngat Timer0 se xuat hien.
Thanh ghi TMR0 cho phep ghi va xoa c giup ta an nh thi iem ngat Timer0 xuat hien
mot cach linh ong.
Muon Timer0 hoat ong che o counter ta set bit TOSC (OPTION_REG<5>). Khi
o xung tac ong len bo em c lay t chan RA4/TOCK1. Bit TOSE (OPTION_REG<4>)
cho phep la chon canh tac ong vao bot em. Canh tac ong se la canh len neu TOSE=0 va
canh tac ong se la canh xuong neu TOSE=1.
Khi thanh ghi TMR0 b tran, bit TMR0IF (INTCON<2>) se c set. ay chnh la c
ngat cua Timer0. C ngat nay phai c xoa bang chng trnh trc khi bo em bat au
thc hien lai qua trnh em. Ngat Timer0 khong the anh thc vi ieu khien t che o
sleep.
Bo chia tan so (prescaler) c chia se gia Timer0 va WDT (Watchdog Timer). ieu
o co ngha la neu prescaler c s dung cho Timer0 th WDT se khong co c ho tr cua
prescaler va ngc lai. Prescaler c ieu khien bi thanh ghi OPTION_REG. Bit PSA
(OPTION_REG<3>) xac nh oi tng tac ong cua prescaler. Cac bit PS2:PS0
(OPTION_REG<2:0>) xac nh t so chia tan so cua prescaler. Xem lai thanh ghi
OPTION_REG e xac nh lai mot cach chi tiet ve cac bit ieu khien tren.
Cac lenh tac ong len gia tr thanh ghi TMR0 se xoa che o hoat ong cua prescaler.
Khi oi tng tac ong la Timer0, tac ong len gia tr thanh ghi TMR0 se xoa prescaler
nhng khong lam thay oi oi tng tac ong cua prescaler. Khi oi tng tac ong la WDT,
lenh CLRWDT se xoa prescaler, ong thi prescaler se ngng tac vu ho tr cho WDT.
Cac thanh ghi ieu khien lien quan en Timer0 bao gom:
TMR0 (a ch 01h, 101h) : cha gia tr em cua Timer0.
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep ngat hoat ong (GIE va PEIE).
OPTION_REG (a ch 81h, 181h): ieu khien prescaler.
2.7 TIMER1
Timer1 la bo nh thi 16 bit, gia tr cua Timer1 se c lu trong hai thanh ghi
(TMR1H:TMR1L). C ngat cua Timer1 la bit TMR1IF (PIR1<0>). Bit ieu khien cua
Timer1 se la TMR1IE (PIE<0>).
Tng t nh Timer0, Timer1 cung co hai che o hoat ong: che o nh thi (timer)
vi xung kch la xung clock cua oscillator (tan so cua timer bang tan so cua oscillator) va
che o em (counter) vi xung kch la xung phan anh cac s kien can em lay t ben ngoai
thong qua chan RC0/T1OSO/T1CKI (canh tac ong la canh len). Viec la chon xung tac
ong (tng ng vi viec la chon che o hoat ong la timer hay counter) c ieu khien
bi bit TMR1CS (T1CON<1>). Sau ay la s o khoi cua Timer1:
Hnh 2.6 S o khoi cua Timer1.

Ngoai ra Timer1 con co chc nang reset input ben trong c ieu khien bi mot
trong hai khoi CCP (Capture/Compare/PWM).
Khi bit T1OSCEN (T1CON<3>) c set, Timer1 se lay xung clock t hai chan
RC1/T1OSI/CCP2 va RC0/T1OSO/T1CKI lam xung em. Timer1 se bat au em sau canh
xuong au tien cua xung ngo vao. Khi o PORTC se bo qua s tac ong cua hai bit
TRISC<1:0> va PORTC<2:1> c gan gia tr 0. Khi clear bit T1OSCEN Timer1 se lay xung
em t oscillator hoac t chan RC0/T1OSO/T1CKI.
Timer1 co hai che o em la ong bo (Synchronous) va bat ong bo (Asynchronous).
Che o em c quyet nh bi bit ieu khien
(T1CON<2>).
=1 xung em lay t ben ngoai se khong c ong bo hoa vi xung clock
Khi
ben trong, Timer1 se tiep tuc qua trnh em khi vi ieu khien ang che o sleep va ngat do
Timer1 tao ra khi b tran co kha nang anh thc vi ieu khien. che o em bat ong bo,
Timer1 khong the c s dung e lam nguon xung clock cho khoi CCP
(Capture/Compare/Pulse width modulation).
=0 xung em vao Timer1 se c ong bo hoa vi xung clock ben trong.
Khi
che o nay Timer1 se khong hoat ong khi vi ieu khien ang che o sleep.
Cac thanh ghi lien quan en Timer1 bao gom:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep ngat hoat ong (GIE va PEIE).
PIR1 (a ch 0Ch): cha c ngat Timer1 (TMR1IF).
PIE1( a ch 8Ch): cho phep ngat Timer1 (TMR1IE).
TMR1L (a ch 0Eh): cha gia tr 8 bit thap cua bo em Timer1.
TMR1H (a ch 0Eh): cha gia tr 8 bit cao cua bo em Timer1.
T1CON (a ch 10h): xac lap cac thong so cho Timer1.
2.8 TIMER2
Timer2 la bo nh thi 8 bit va c ho tr bi hai bo chia tan so prescaler va
postscaler. Thanh ghi cha gia tr em cua Timer2 la TMR2. Bit cho phep ngat Timer2 tac
ong la TMR2ON (T2CON<2>). C ngat cua Timer2 la bit TMR2IF (PIR1<1>). Xung ngo
vao (tan so bang tan so oscillator) c a qua bo chia tan so prescaler 4 bit (vi cac t
so chia tan so la 1:1, 1:4 hoac 1:16 va c ieu khien bi cac bit T2CKPS1:T2CKPS0
(T2CON<1:0>)).
Hnh 2.7 S o khoi Timer2.

Timer2 con c ho tr bi thanh ghi PR2. Gia tr em trong thanh ghi TMR2 se tang
t 00h en gia tr cha trong thanh ghi PR2, sau o c reset ve 00h. Kh I reset thanh ghi
PR2 c nhan gia tr mac nh FFh.
Ngo ra cua Timer2 c a qua bo chia tan so postscaler vi cac mc chia t 1:1 en
1:16. Postscaler c ieu khien bi 4 bit T2OUTPS3:T2OUTPS0. Ngo ra cua postscaler
ong vai tro quyet nh trong viec ieu khien c ngat.
Ngoai ra ngo ra cua Timer2 con c ket noi vi khoi SSP, do o Timer2 con ong
vai tro tao ra xung clock ong bo cho khoi giao tiep SSP.
Cac thanh ghi lien quan en Timer2 bao gom:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep toan bo cac ngat (GIE va PEIE).
PIR1 (a ch 0Ch): cha c ngat Timer2 (TMR2IF).
PIE1 (a ch 8Ch): cha bit ieu khien Timer2 (TMR2IE).
TMR2 (a ch 11h): cha gia tr em cua Timer2.
T2CON (a ch 12h): xac lap cac thong so cho Timer2.
PR2 (a ch 92h): thanh ghi ho tr cho Timer2.

Ta co mot vai nhan xet ve Timer0, Timer1 va Timer2 nh sau:
Timer0 va Timer2 la bo em 8 bit (gia tr em toi a la FFh), trong khi Timer1 la bo
em 16 bit (gia tr em toi a la FFFFh).
Timer0, Timer1 va Timer2 eu co hai che o hoat ong la timer va counter. Xung
clock co tan so bang tan so cua oscillator.
Xung tac ong len Timer0 c ho tr bi prescaler va co the c thiet lap nhieu
che o khac nhau (tan so tac ong, canh tac ong) trong khi cac thong so cua xung tac ong
len Timer1 la co nh. Timer2 c ho tr bi hai bo chia tan so prescaler va postcaler oc
lap, tuy nhien canh tac ong van c co nh la canh len.
Timer1 co quan he vi khoi CCP, trong khi Timer2 c ket noi vi khoi SSP.
Mot vai so sanh se giup ta de dang la chon c Timer thch hp cho ng dung.
2.9 ADC
ADC (Analog to Digital Converter) la bo chuyen oi tn hieu gia hai dang tng t va so.
PIC16F877A co 8 ngo vao analog (RA4:RA0 va RE2:RE0). Hieu ien the chuan VREF co the
c la chon la VDD, VSS hay hieu ien the chuan c xac lap tren hai chan RA2 va RA3.
Ket qua chuyen oi t tn tieu tng t sang tn hieu so la 10 bit so tng ng va c lu
trong hai thanh ghi ADRESH:ADRESL. Khi khong s dung bo chuyen oi ADC, cac thanh
ghi nay co the c s dung nh cac thanh ghi thong thng khac. Khi qua trnh chuyen oi
hoan tat, ket qua se c lu vao hai thanh ghi ADRESH:ADRESL, bit
(ADCON0<2>) c xoa ve 0 va c ngat ADIF c set.
Qui trnh chuyen oi t tng t sang so bao gom cac bc sau:
1. Thiet lap cac thong so cho bo chuyen oi ADC:
Chon ngo vao analog, chon ien ap mau (da tren cac thong so cua thanh ghi
ADCON1)
Chonh kenh chuyen oi AD (thanh ghi ADCON0).
Chonh xung clock cho kenh chuyen oi AD (thanh ghi ADCON0).
Cho phep bo chuyen oi AD hoat ong (thanh ghi ADCON0).
2. Thiet lap cac c ngat cho bo AD
Clear bit ADIF.
Set bit ADIE.
Set bit PEIE.
Set bit GIE.
3. i cho ti khi qua trnh lay mau hoan tat.

).
4. Bat au qua trnh chuyen oi (set bit
5. i cho ti khi qua trnh chuyen oi hoan tat bang cach:
Kiem tra bit
. Neu
=0, qua trnh chuyen oi a hoan tat.
Kiem tra c ngat.
6. oc ket qua chuyen oi va xoa c ngat, set bit
(neu can tiep tuc chuyen
oi).
7. Tiep tuc thc hien cac bc 1 va 2 cho qua trnh chuyen oi tiep theo.
Hnh 2.8 S o khoi bo chuyen oi ADC.

Can chu y la co hai cach lu ket qua chuyen oi AD, viec la chon cach lu c ieu khien
bi bit ADFM va c minh hoa cu the trong hnh sau:
Hnh 2.9 Cac cach lu ket qua chuyen oi AD.

Cac thanh ghi lien quan en bo chuyen oi ADC bao gom:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep cac ngat (cac bit GIE, PEIE).
PIR1 (a ch 0Ch): cha c ngat AD (bit ADIF).
PIE1 (a ch 8Ch): cha bit ieu khien AD (ADIE).
ADRESH (a ch 1Eh) va ADRESL (a ch 9Eh): cac thanh ghi cha ket qua chuyen
oi AD.
ADCON0 (a ch 1Fh) va ADCON1 (a ch 9Fh): xac lap cac thong so cho bo
chuyen oi AD.
PORTA (a ch 05h) va TRISA (a ch 85h): lien quan en cac ngo vao analog
PORTA.
PORTE (a ch 09h) va TRISE (a ch 89h): lien quan en cac ngo vao analog
PORTE.
Chi tiet ve cac thanh ghi se c trnh bay cu the phu luc 2.
2.10 COMPARATOR
Bo so sanh bao gom hai bo so so sanh tn hieu analog va c at PORTA. Ngo vao
bo so sanh la cac chan RA3:RA0, ngo ra la hai chan RA4 va RA5. Thanh ghi ieu khien bo
so sanh la CMCON. Cac bit CM2:CM0 trong thanh ghi CMCON ong vai tro chon la cac
che o hoat ong cho bo Comparator (hnh 2.10).
C che hoat ong cua bo Comparator nh sau:
Tn hieu analog chan VIN + se c so sanh vi ien ap chuan chan VIN- va tn

hieu ngo ra bo so sanh se thay oi tng ng nh hnh ve. Khi ien ap chan VIN+ ln hn
ien ap chan VIN+ ngo ra se mc 1 va ngc lai.
Da vao hnh ve ta thay ap ng tai ngo ra khong phai la tc thi so vi thay oi tai
ngo vao ma can co mot khoang thi gian nhat nh e ngo ra thay oi trang thai (toi a la 10
us). Can chu y en khoang thi gian ap ng nay khi s dung bo so sanh.
Cc tnh cua cac bo so sanh co the thay oi da vao cac gia tr at vao cac bit C2INV
va C1INV (CMCON<4:5>).
Hnh 2.10 Nguyen l hoat ong cua mot bo so sanh n gian.
Hnh 2.11 Cac che o hoat ong cua bo comparator.

Cac bit C2OUT va C1OUT (CMCON<7:6>) ong vai tro ghi nhan s thay oi tn hieu analog
so vi ien ap at trc. Cac bit nay can c x l thch hp bang chng trnh e ghi nhan
s thay oi cua tn hieu ngo vao. C ngat cua bo so sanh la bit CMIF (thanh ghi PIR1). C
ngat nay phai c reset ve 0. Bit ieu khien bo so sanh la bit CMIE (Tranh ghi PIE).
Cac thanh ghi lien quan en bo so sanh bao gom:

CMCON (a ch 9Ch) va CVRCON (a ch 9Dh): xac lap cac thong so cho bo so
sanh.
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cac bit cho phep cac ngat
(GIE va PEIE).
Thanh ghi PIR2 (a ch 0Dh): cha c ngat cua bo so sanh (CMIF).
Thanh ghi PIE2 (a ch 8Dh): cha bit cho phep bo so sanh (CNIE).
Thanh ghi PORTA (a ch 05h) va TRISA (a ch 85h): cac thanh ghi ieu khien
PORTA.
2.10.1 BO TAO IEN AP SO SANH
Bo so sanh nay ch hoat ong khi bo Comparator c nh dang hoat ong che o 110.
Khi o cac pin RA0/AN0 va RA1/AN1 (khi CIS = 0) hoac pin RA3/AN3 va RA2/AN2 (khi
CIS = 1) se la ngo vao analog cua ien ap can so sanh a vao ngo VIN- cua 2 bo so sanh C1
va C2 (xem chi tiet hnh 2.10). Trong khi o ien ap a vao ngo VIN+ se c lay t mot
bo tao ien ap so sanh. S o khoi cua bo tao ien ap so sanh c trnh bay trong hnh ve
sau:
Hnh 2.12 S o khoi bo tao ien ap so sanh.

Bo tao ien ap so sanh nay bao gom mot thang ien tr 16 mc ong vai tro la cau phan ap
chia nho ien ap VDD thanh nhieu mc khac nhau (16 mc). Moi mc co gia tr ien ap khac
nhau tuy thuoc vao bit ieu khien CVRR (CVRCON<5>). Neu CVRR mc logic 1, ien tr
8R se khong co tac dung nh mot thanh phan cua cau phan ap (BJT dan manh va dong ien
khong i qua ien tr 8R), khi o 1 mc ien ap co gia tr VDD/24. Ngc lai khi CVRR
mc logic 0, dong ien se qua ien tr 8R va1 mc ien ap co gia tr VDD/32. Cac mc ien
ap nay c a qua bo MUX cho phep ta chon c ien ap a ra pin
RA2/AN2/VREF-/CVREF e a vao ngo VIN+ cua bo so sanh bang cach a cac gia tr thch
hp vao cac bit CVR3:CVR0.
Bo tao ien ap so sanh nay co the xem nh mot bo chuyen oi D/A n gian. Gia tr
ien ap can so sanh ngo vao Analog se c so sanh vi cac mc ien ap do bo tao ien ap
tao ra cho ti khi hai ien ap nay at c gia tr xap x bang nhau. Khi o ket qua chuyen
oi xem nh c cha trong cac bit CVR3:CVR0.
Cac thanh ghi lien quan en bo tao ien ap so sanh nay bao gom:
Thanh ghi CVRCON (a ch 9Dh): thanh ghi trc tiep ieu khien bo so sanh
ien ap.
Thanh ghi CMCON (a ch 9Ch): thanh ghi ieu khien bo Comparator.
2.11 CCP
CCP (Capture/Compare/PWM) bao gom cac thao tac tren cac xung em cung cap bi cac bo
em Timer1 va Timer2. PIC16F877A c tch hp san hai khoi CCP : CCP1 va CCP2.Moi
CCP co mot thanh ghi 16 bit (CCPR1H:CCPR1L va CCPR2H:CCPR2L), pin ieu khien dung
cho khoi CCPx la RC2/CCP1 va RC1/T1OSI/CCP2. Cac chc nang cua CCP bao gom:
Capture.
So sanh (Compare).
ieu che o rong xung PWM (Pulse Width Modulation).
Ca CCP1 va CCP2 ve nguyen tac hoat ong eu giong nhau va chc nang cua tng khoi la
kha oc lap. Tuy nhien trong mot so trng hp ngoai le CCP1 va CCP2 co kha nang phoi
hp vi nhau e e tao ra cac hien tng ac biet (Special event trigger) hoac cac tac ong
len Timer1 va Timer2. Cac trng hp nay c liet ke trong bang sau:
CCPx
Capture
Capture
Compare
PWM
CCPy
Capture
Compare
Compare
PWM
PWM
PWM
Capture
Compare
Tac ong
Dung chung nguon xung clock t TMR1
Tao ra hien tng ac biet lam xoa TMR1
Tao ra hien tng ac biet lam xoa TMR1
Dung chung tan so xung clock vacung chu tac ong cua ngat
TMR2.
Hoat ong oc lap
Hoat ong oc lap
Khi hoat ong che o Capture th khi co

mot hien tng xay ra tai pin RC2/CCP1
(hoac RC1/T1OSI/CCP2), gia tr cua thanh
ghi TMR1 se c a vao thanh ghi CCPR1
(CCPR2). Cac hien tng c nh ngha
bi
cac
bit
CCPxM3:CCPxM0
(CCPxCON<3:0>) va co the la mot trong
cac hien tng sau:
Moi khi co canh xuong tai cac pin
CCP.
Moi khi co canh len.
Moi canh len th 4.
Moi canh len th 16.
Hnh 2.13 S o khoi CCP (Capture mode).
Sau khi gia tr cua thanh ghi TMR1 c a vao thanh ghi CCPRx, c ngat CCPIF c set
va phai c xoa bang chng trnh. Neu hien tng tiep theo xay ra ma gia tr trong thanh
ghi CCPRx cha c x l, gia tr tiep theo nhan c se t ong c ghi e len gia tr cu.
Mot so iem can chu y khi s dung CCP nh sau:
Cac pin dung cho khoi CCP phai c an nh la input (set cac bit tng ng trong
thanh ghi TRISC). Khi an nh cac pin dung cho khoi CCP la output, viec a gia tr vao
PORTC cung co the gay ra cac hien tng tac ong len khoi CCP do trang thai cua pin
thay oi.
Timer1 phai c hoat ong che o Timer hoac che o em ong bo.
Tranh s dung ngat CCP bang cach clear bit CCPxIE (thanh ghi PIE1), c ngat CCPIF
nen c xoa bang phan mem moi khi c set e tiep tuc nhan nh c trang thai hoat
ong cua CCP.
CCP con c tch hp bo chia tan so prescaler c ieu khien bi cac bit
CCPxM3:CCPxM0. Viec thay oi oi tng tac ong cua prescaler co the tao ra hoat ong
ngat. Prescaler c xoa khi CCP khong hoat ong hoac khi reset.
Xem cac thanh ghi ieu khien khoi CCP (phu luc 2 e biet them chi tiet).
Khi hoat ong che o Compare, gia tr trong thanh ghi CCPRx se thng xuyen c so
sanh vi gia tr trong thanh ghi TMR1. Khi hai thanh ghi cha gia tr bang nhau, cac pin cua
CCP c thay oi trang thai (c a len mc cao, a xuong mc thap hoac gi nguyen
trang thai), ong thi c ngat CCPIF cung se c set. S thay oi trang thai cua pin co the
c ieu khien bi cac bit CCPxM3:CCPxM0 (CCPxCON <3:0>).
Hnh 2.14 S o khoi CCP (Compare mode).

Tng t nh che o Capture, Timer1 phai c an nh che o hoat ong la timer
hoac em ong bo. Ngoai ra, khi che o Compare, CCP co kha nang tao ra hien tng ac
biet (Special Event trigger) lam reset gia tr thanh ghi TMR1 va khi ong bo chuyen oi
ADC. ieu nay cho phep ta ieu khien gia tr thanh ghi TMR1 mot cach linh ong hn.
Khi hoat ong che o PWM (Pulse

Width Modulation _ khoi ieu che o rong
xung), tn hieu sau khi ieu che se c
a ra cac pin cua khoi CCP (can an nh
cac pin nay la output). e s dung chc
nang ieu che nay trc tien ta can tien
hanh cac bc cai at sau:
1. Thiet lap thi gian cua 1 chu k
cua xung ieu che cho PWM
(period) bang cach a gia tr
thch hp vao thanh ghi PR2.
2. Thiet lap o rong xung can ieu
che (duty cycle) bang cach a
gia tr vao thanh ghi CCPRxL
va cac bit CCP1CON<5:4>.
3. ieu khien cac pin cua CCP la
output bang cach clear cac bit
tng ng trong thanh ghi
TRISC.
4. Thiet lap gia tr bo chia tan so
prescaler cua Timer2 va cho
phep Timer2 hoat ong bang
cach a gia tr thch hp vao
thanh ghi T2CON.
5. Cho phep CCP hoat ong che
o PWM.
Hnh 2.15 S o khoi CCP (PWM mode).
Hnh 2.16 Cac tham so cua PWM
Trong o gia tr 1 chu k (period) cua xung ieu che c tnh bang cong thc:
PWM period = [(PR2)+1]*4*TOSC*(gia tr bo chia tan so cua TMR2).
Bo chia tan so prescaler cua Timer2 ch co the nhan cac gia tr 1,4 hoac 16 (xem lai Timer2
e biet them chi tiet). Khi gia tr thanh ghi PR2 bang vi gia tr thanh ghi TMR2 th qua trnh
sau xay ra:
Thanh ghi TMR2 t ong c xoa.
Pin cua khoi CCP c set.
Gia tr thanh ghi CCPR1L (cha gia tr an nh o rong xung ieu che duty cycle)
c a vao thanh ghi CCPRxH.
o rong cua xung ieu che (duty cycle) c tnh theo cong thc:
PWM duty cycle = (CCPRxL:CCPxCON<5:4>)*TOSC*(gia tr bo chia tan so TMR2)
Nh vay 2 bit CCPxCON<5:4> se cha 2 bit LSB. Thanh ghi CCPRxL cha byte cao cua gia
tr quyet nh o rong xung. Thanh ghi CCPRxH ong vai tro la buffer cho khoi PWM. Khi
gia tr trong thanh ghi CCPRxH bang vi gia tr trong thanh ghi TMR2 va hai bit
CCPxCON<5:4> bang vi gia tr 2 bit cua bo chia tan so prescaler, pin cua khoi CCP lai
c a ve mc thap, nh vay ta co c hnh anh cua xung ieu che tai ngo ra cua khoi
PWM nh hnh 2.14.
Mot so iem can chu y khi s dung khoi PWM:
Timer2 co hai bo chia tan so prescaler va postscaler. Tuy nhien bo postscaler khong
c s dung trong qua trnh ieu che o rong xung cua khoi PWM.
Neu thi gian duty cycle dai hn thi gian chu k xung period th xung ngo ra tiep tuc
c gi mc cao sau khi gia tr PR2 bang vi gia tr TMR2.
2.12 GIAO TIEP NOI TIEP
1.12.1 USART
USART (Universal Synchronous Asynchronous Receiver Transmitter) la mot trong
hai chuan giao tiep noi tiep.USART con c goi la giao dien giao tiep noi tiep noi tiep SCI
(Serial Communication Interface). Co the s dung giao dien nay cho cac giao tiep vi cac
thiet b ngoai vi, vi cac vi ieu khien khac hay vi may tnh. Cac dang cua giao dien
USART ngoai vi bao gom:
Bat ong bo (Asynchronous).
ong bo_ Master mode.
ong bo_ Slave mode.
Hai pin dung cho giao dien nay la RC6/TX/CK va RC7/RX/DT, trong o RC6/TX/CK
dung e truyen xung clock (baud rate) va RC7/RX/DT dung e truyen data. Trong trng
hp nay ta phai set bit TRISC<7:6> va SPEN (RCSTA<7>) c0e cho phep giao dien USART.
PIC16F877A c tch hp san bo tao toc o baud BRG (Baud Rate Genetator) 8 bit
dung cho giao dien USART. BRG thc chat la mot bo em co the c s dung cho ca hai
dang ong bo va bat ong bo va c ieu khien bi thanh ghi PSBRG. dang bat ong bo,
BRG con c ieu khien bi bit BRGH ( TXSTA<2>). dang ong bo tac ong cua bit
BRGH c bo qua. Toc o baud do BRG tao ra c tnh theo cong thc sau:
Trong o X la gia tr cua thanh ghi RSBRG ( X la so nguyen va 0<X<255).
Cac thanh ghi lien quan en BRG bao gom:

TXSTA (a ch 98h): chon che o ong bo hay bat ong bo ( bit SYNC) va chon mc
toc o baud (bit BRGH).
RCSTA (a ch 18h): cho phep hoat ong cong noi tiep (bit SPEN).
RSBRG (a ch 99h): quyet nh toc o baud.
Chi tiet ve cac thanh ghi se c trnh bat cu the trong phu luc 2.
2.12.1.1 USART BAT ONG BO
che o truyen nay USART hoat ong theo chuan NRZ (None-Return-to-Zero), ngha la
cac bit truyen i se bao gom 1 bit Start, 8 hay 9 bit d lieu (thong thng la 8 bit) va 1 bit
Stop. Bit LSB se c truyen i trc. Cac khoi truyen va nhan data oc lap vi nhau se
dung chung tan so tng ng vi toc o baud cho qua trnh dch d lieu (toc o baud gap 16
hay 64 lan toc o dch d lieu tuy theo gia tr cua bit BRGH), va e am bao tnh hieu qua
cua d lieu th hai khoi truyen va nhan phai dung chung mot nh dang d lieu.
2.12.1.1.1 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART BAT ONG BO
Thanh phan quan trong nhat cua khoi truyen d lieu la thanh ghi dch d lieu TSR (Transmit
Shift Register). Thanh ghi TSR se lay d lieu t thanh ghi em dung cho qua trnh truyen d
lieu TXREG. D lieu can truyen phai c a trc vao thanh ghi TXREG. Ngay sau khi bit
Stop cua d lieu can truyen trc o c truyen xong, d lieu t thanh ghi TXREG se c
a vao thanh ghi TSR, thanh ghi TXREG b rong, ngat xay ra va c hieu TXIF (PIR1<4>)
c set. Ngat nay c ieu khien bi bit TXIE (PIE1<4>). C hieu TXIF van c set bat
chap trang thai cua bit TXIE hay tac ong cua chng trnh (khong the xoa TXIF bang
chng trnh) ma ch reset ve 0 khi co d lieu mi c a vao thanhh ghi TXREG.
Hnh 2.17 S o khoi cua khoi truyen d lieu USART.
Trong khi c hieu TXIF ong vai tro ch th trang thai thanh ghi TXREG th c hieu TRMT
(TXSTA<1>) co nhiem vu the hien trang thai thanh ghi TSR. Khi thanh ghi TSR rong, bit
TRMT se c set. Bit nay ch oc va khong co ngat nao c gan vi trang thai cua no.
Mot iem can chu y na la thanh ghi TSR khong co trong bo nh d lieu va ch c ieu
khien bi CPU.
Khoi truyen d lieu c cho phep hoat ong khi bit TXEN (TXSTA<5>) c set. Qua trnh
truyen d lieu ch thc s bat au khi a co d lieu trong thanh ghi TXREG va xung truyen
baud c tao ra. Khi khoi truyen d lieu c khi ong lan au tien, thanh ghi TSR rong.
Tai thi iem o, d lieu a vao thanh ghi TXREG ngay lap tc c load vao thanh ghi
TSR va thanh ghi TXREG b rong. Luc nay ta co the hnh thanh mot chuoi d lieu lien tuc
cho qua trnh truyen d lieu. Trong qua trnh truyen d lieu neu bit TXEN b reset ve 0, qua
trnh truyen ket thuc, khoi truyen d lieu c reset va pin RC6/TX/CK chuyen en trang
thai high-impedance.
Trong trng hp d lieu can truyen la 9 bit, bit TX9 (TXSTA<6>) c set va bit d lieu th
9 se c lu trong bit TX9D (TXSTA<0>). Nen ghi bit d lieu th 9 vao trc, v khi ghi 8
bit d lieu vao thanh ghi TXREG trc co the xay ra trng hp noi dung thanh ghi TXREG
se c load vao thanh ghi TSG trc, nh vay d lieu truyen i se b sai khac so vi yeu
cau.
Tom lai, e truyen d lieu theo giao dien USART bat ong bo, ta can thc hien tuan t cac
bc sau:
1. Tao xung truyen baud bang cach a cac gia tr can thiet vao thanh ghi RSBRG va
bit ieu khien mc toc o baud BRGH.
2. Cho phep cong giao dien noi tiep noi tiep bat ong bo bang cach clear bit SYNC
va set bit PSEN.
3. Set bit TXIE neu can s dung ngat truyen.
4. Set bit TX9 neu nh dang d lieu can truyen la 9 bit.
5. Set bit TXEN e cho phep truyen d lieu (luc nay bit TXIF cung se c set).
6. Neu nh dang d lieu la 9 bit, a bit d lieu th 9 vao bit TX9D.
7. a 8 bit d lieu can truyen vao thanh ghi TXREG.
8. Neu s dung ngat truyen, can kiem tra lai cac bit GIE va PEIE (thanh ghi
INTCON).
Cac thanh ghi lien quan en qua trnh truyen d lieu bang giao dien USART bat ong bo:
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep tat ca cac ngat.
Thanh ghi PIR1 (a ch 0Ch): cha c hieu TXIF.
Thanh ghi PIE1 (a ch 8Ch): cha bit cho phep ngat truyen TXIE.
Thanh ghi RCSTA (a ch 18h): cha bit cho phep cong truyen d lieu (hai pin
RC6/TX/CK va RC7/RX/DT).
Thanh ghi TXREG (a ch 19h): thanh ghi cha d lieu can truyen.
Thanh ghi TXSTA (a ch 98h): xac lap cac thong so cho giao dien.
Thanh ghi SPBRG (a ch 99h): quyet nh toc o baud.
2.12.1.1.2 NHAN D LIEU QUA CHUAN GIAO TIEP USART BAT ONG BO
D lieu c a vao t chan RC7/RX/DT se kch hoat khoi phuc hoi d lieu. Khoi phuc hoi
d lieu thc chat la mot bo dch d lieu ctoc o cao va co tan so hoat ong gap 16 lan hoac
64 lan tan so baud. Trong khi o toc o dch cua thanh thanh ghi nhan d lieu se bang vi tan
so baud hoac tan so cua oscillator.
Hnh 2.18 S o khoi cua khoi nhan d lieu USART.

Bit ieu khien cho phep khoi nhan d lieu la bit RCEN (RCSTA<4>). Thanh phan quan trong
nhat cua khoi nhan d lieu la thsnh ghi nhan d lieu RSR (Receive Shift Register). Sau khi
nhan dien bit Stop cua d lieu truyen ti, d lieu nhan c trong thanh ghi RSR se c a
vao thanh ghi RCGER, sau o c hieu RCIF (PIR1<5>) se c set va ngat nhan c kch
hoat. Ngat nay c ieu khien bi bit RCIE (PIE1<5>). Bit c hieu RCIF la bit ch oc va
khong the c tac ong bi chng trnh. RCIF ch reset ve 0 khi d lieu nhan vao thanh
ghi RCREG a c oc va khi o thanh ghi RCREG rong. Thanh ghi RCREG la thanh ghi
co bo em kep (double-buffered register) va hoat ong theo c che FIFO (First In First Out)
cho phep nhan 2 byte va byte th 3 tiep tuc c a vao thanh ghi RSR. Neu sau khi nhan
c bit Stop cua byte d lieu th 3 ma thanh ghi RCREG van con ay, c hieu bao tran d
lieu (Overrun Error bit) OERR(RCSTA<1>) se c set, d lieu trong thanh ghi RSR se b
mat i va qua trnh a d lieu t thanh ghi RSR vao thanh ghi RCREG se b gian oan.
Trong trng hp nay can lay het d lieu thanh ghi RSREG vao trc khi tiep tuc nhan
byte d lieu tiep theo. Bit OERR phai c xoa bang phan mem va thc hien bang cach
clear bit RCEN roi set lai. Bit FERR (RCSTA<2>) se c set khi phat hien bit Stop dua d
lieu c nhan vao. Bit d lieu th 9 se c a vao bit RX9D (RCSTA<0>). Khi oc d
lieu t thanh ghi RCREG, hai bit FERR va RX9D se nhan cac gia tr mi. Do o can oc d
lieu t thanh ghi RCSTA trc khi oc d lieu t thanh ghi RCREG e tranh b mat d lieu.
Tom lai, khi s dung giao dien nhan d lieu USART bat ong bo can tien hanh tuan t cac
bc sau:
1. Thiet lap toc o baud (a gia tr thch hp vao thanh ghi SPBRG va bit BRGH.
2. Cho phep cong giao tiep USART bat ong bo (clear bit SYNC va set bit SPEN).
3. Neu can s dung ngat nhan d lieu, set bit RCIE.
4. Neu d lieu truyen nhan co nh dang la 9 bit, set bit RX9.
5. Cho phep nhan d lieu bang cach set bit CREN.
6. Sau khi d lieu c nhan, bit RCIF se c set va ngat c kch hoat (neu bit
RCIE c set).
7. oc gia tr thanh ghi RCSTA e oc bit d lieu th 9 va kiem tra xem qua trnh
nhan d lieu co b loi khong.
8. oc 8 bit d lieu t thanh ghi RCREG.
9. Neu qua trnh truyen nhan co loi xay ra, xoa loi bang cach xoa bit CREN.
10. Neu s dung ngat nhan can set bit GIE va PEIE (thanh ghi INTCON).
Cac thanh ghi lien quan en qua trnh nhan d lieu bang giao dien USART bat ong bo:
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cac bit cho phep toan bo
cac ngat (bit GIER va PEIE).
Thanh ghi PIR1 (a ch 0Ch): cha c hieu RCIE.
Thanh ghi PIE1 (a ch 8Ch): cha bit cho phep ngat RCIE.
Thanh ghi RCSTA (a ch 18h): xac nh cac trang thai trong qua trnh nhan d lieu.
Thanh ghi RCREG (a ch 1Ah): cha d lieu nhan c.
Thanh ghi TXSTA (a ch 98h): cha cac bit ieu khien SYNC va BRGH.
Thanh ghi SPBRG (a ch 99h): ieu khien toc o baud.
2.12.1.1.2 USART ONG BO

Giao dien USART ong bo c kch hoat bang cach set bit SYNC. Cong giao tiep noi tiep
van la hai chan RC7/RX/DT, RC6/TX/CK va c cho phep bang cach set bit SPEN. USART
cho phep hai che o truyen nhan d lieu la Master mode va Slave mode. Master mode c
kch hoat bang cach set bit CSRC (TXSTA<7>), Slave mode c kch hoat bang cach clear
bit CSRC. iem khac biet duy nhat gia hai che o nay la Master mode se lay xung clock
ong bo t bo tao xung baud BRG con Slave mode lay xung clock ong bo t ben ngoai qua
chan RC6/TX/CK. ieu nay cho phep Slave mode hoat ong ngay ca khi vi ieu khien ang
che o sleep.
2.12.1.2.1 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART ONG BO MASTER
MODE
Tng t nh giao dien USART bat ong bo, thanh phan quan trong nhat cua hoi truyen d
lieu la thanh ghi dch TSR (Transmit Shift Register). Thanh ghi nay ch c ieu khien bi
CPU. D lieu a vao thanh ghi TSR c cha trong thanh ghi TXREG. C hieu cua khoi
truyen d lieu la bit TXIF (ch th trang thai thanh ghi TXREG), c hieu nay c gan vi
mot ngat va bit ieu khien ngat nay la TXIE. C hieu ch th trang thai thanh ghi TSR la bit
TRMT. Bit TXEN cho phep hay khong cho phep truyen d lieu.
Cac bc can tien hanh khi truyen d lieu qua giao dien USART ong bo Master mode:
1. Tao xung truyen baud bang cach a cac gia tr can thiet vao thanh ghi RSBRG va
bit ieu khien mc toc o baud BRGH.
2. Cho phep cong giao dien noi tiep noi tiep ong bo bang cach set bit SYNC, PSEN
va CSRC.
3. Set bit TXIE neu can s dung ngat truyen.
4. Set bit TX9 neu nh dang d lieu can truyen la 9 bit.
5. Set bit TXEN e cho phep truyen d lieu.
6. Neu nh dang d lieu la 9 bit, a bit d lieu th 9 vao bit TX9D.
7. a 8 bit d lieu can truyen vao thanh ghi TXREG.
8. Neu s dung ngat truyen, can kiem tra lai cac bit GIE va PEIE (thanh ghi
INTCON).
Cac thanh ghi lien quan en qua trnh truyen d lieu bang giao dien USART ong bo Master
mode:
2.12.1.2.2 NHAN D LIEU QUA CHUAN GIAO TIEP USART ONG BO MASTER
MODE
Cau truc khoi truyen d lieu la khong oi so vi giao dien bat ong bo, ke ca cac c hieu,
ngat nhan va cac thao tac tren cac thanh phan o. iem khac biet duy nhat la giao dien nay
cho phep hai che o nhan s lieu, o la ch nhan 1 word d lieu (set bit SCEN) hay nhan mot
chuoi d lieu (set bit CREN) cho ti khi ta clear bit CREN. Neu ca hai bit eu c set, bit
ieu khien CREN se c u tien.
Cac bc can tien hanh khi nhan d lieu bang giao dien USART ong bo Master mode:
1.
2.
3.
4.
5.
6.
Thiet lap toc o baud (a gia tr thch hp vao thanh ghi SPBRG va bit BRGH).
Cho phep cong giao tiep USART bat ong bo (set bit SYNC, SPEN va CSRC).
Clear bit CREN va SREN.
Neu can s dung ngat nhan d lieu, set bit RCIE.
Neu d lieu truyen nhan co nh dang la 9 bit, set bit RX9.
Neu ch nhan 1 word d lieu, set bit SREN, neu nhan 1 chuoi word d lieu, set bit
CREN.
RCIE c set).
Cac thanh ghi lien quan en qua trnh nhan d lieu bang giao dien USART ong bo Master
mode:
2.12.1.2.3 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART ONG BO SLAVE
MODE
Qua trnh nay khong co s khac biet so vi Master mode khi vi ieu khien hoat ong che
o bnh thng. Tuy nhien khi vi ieu khien ang trang thai sleep, s khac biet c the
hien ro rang. Neu co hai word d lieu c a vao thanh ghi TXREG trc khi lenh sleep
c thc thi th qua trnh sau se xay ra:
1.
2.
3.
4.
Word d lieu au tien se ngay lap tc c a vao thanh ghi TSR e truyen i.
Word d lieu th hai van nam trong thanh ghi TXREG.
C hieu TXIF se khong c set.
Sau khi word d lieu au tien a dch ra khoi thanh ghi TSR, thanh ghi TXREG
tiep tuc truyen word th hai vao thanh ghi TSR va c hieu TXIF c set.
5. Neu ngat truyen c cho phep hoat ong, ngat nay se anh thc vi ieu khien va
neu toan bo cac ngat c cho phep hoat ong, bo em chng trnh se ch ti a
ch cha chng trnh ngat (0004h).
Cac bc can tien hanh khi truyen d lieu bang giao dien USART ong bo Slave mode:
1.
2.
3.
4.
5.
6.
7.
8.
Set bit SYNC, SPEN va clear bit CSRC.

Clear bit CREN va SREN.
Neu can s dung ngat, set bit TXIE.
Neu nh dang d lieu la 9 bit, set bit TX9.
Set bit TXEN.
a bit d lieu th 9 vao bit TX9D trc (neu nh dang d lieu la 9 bit).
a 8 bit d lieu vao thanh ghi TXREG.
Neu ngat truyen c s dung, set bit GIE va PEIE (thanh ghi INTCON).
Cac thanh ghi lien quan en qua trnh truyen d lieu bang giao dien USART ong bo Slave
mode:
2.12.1.2.4 NHAN D LIEU QUA CHUAN GIAO TIEP USART ONG BO SLAVE
MODE
S khac biet cua Slave mode so vi Master mode ch the hien ro rang khi vi ieu khien hoat
ong che o sleep. Ngoai ra che o Slave mode khong quan tam ti bit SREN.
Khi bit CREN (cho phep nhan chuoi d lieu) c set trc khi lenh sleep c thc thi, 1
word d lieu van c tiep tuc nhan, sau khi nhan xong bit thanh ghi RSR se chuyen d lieu
vao thanh ghi RCREG va bit RCIF c set. Neu bit RCIE (cho phep ngat nhan) a c set
trc o, ngat se c thc thi va vi ieu khien c anh thc, bo em chng trnh se ch
en a ch 0004h va chng trnh ngat se c thc thi.
Cac bc can tien hanh khi nhan d lieu bang giao dien USART ong bo Slave mode:
1. Cho phep cong giao tiep USART bat ong bo (set bit SYNC, SPEN clear bit
CSRC).
2. Neu can s dung ngat nhan d lieu, set bit RCIE.
3. Neu d lieu truyen nhan co nh dang la 9 bit, set bit RX9.
4. Set bit CREN e cho phep qua trnh nhan d lieu bat au.
RCIE c set).
Cac thanh ghi lien quan en qua trnh nhan d lieu bang giao dien USART ong bo Slave
mode:

2.12.2 MSSP
MSSP ( Master Synchronous Serial
Port) la giao dien ong bo noi tiep dung e
giao tiep vi cac thiet b ngoai vi (EEPROM,
ghi dch, chuyen oi ADC,) hay cac vi ieu
khien khac. MSSP co the hoat ong di hai
dang giao tiep:
SPI (Serial Pheripheral Interface).
I2C (Inter-Intergrated Circuit).
Cac thanh ghi ieu khien giao chuan giao
tiep nay bao gom thanh ghi trang thai
SSPSTAT va hai thanh ghi ieu khien
SSPSON va SSPSON2. Tuy theo chuan giao
tiep c s dung (SPI hay I2C) ma chc
nang cac thanh ghi nay c the hien khac
nhau.
2.12.2.1 SPI
Chuan giao tiep SPI cho phep truyen
nhan ong bo. Ta can s dung 4 pin cho
chuan giao tiep nay:
Hnh 2.19 S o khoi MSSP (giao dien SPI)
RC5/SDO: ngo ra d lieu dang noi
tiep (Serial Data output).
RC4/SDI/SDA: ngo vao d lieu dang
noi tiep (Serial Data Input).
RC3/SCK/SCL: xung ong bo noi tiep (Serial Clock).
RA5/AN4/SS/C2OUT: chon oi tng giao tiep (Serial Select) khi giao tiep che o
Slave mode.
Cac thanh ghi lien quan en MSSP khi hoat ong chuan giao tiep SPI bao gom:
Thanh ghi ieu khien SSPCON, thanh ghi nay cho phep oc va ghi.
Thanh ghi trang thai SSPSTAT, thanh ghi nay ch cho phep oc va ghi 2 bit tren, 6
bit con lai ch cho phep oc.
Thanh ghi ong vai tro la buffer truyen nhan SSPBUF, d lieu truyen i hoac nhan
c se c a vao tranh ghi nay. SSPBUF khong co cau truc em hai lp (doubledbuffer), do o d lieu ghi vao thanh ghi SSPBUF se lap tc c ghi vao thanh ghi SSPSR.
Thanh ghi dch d lieu SSPSR dung e dch d lieu vao hoac ra. Khi 1 byte d lieu
c nhan hoan chnh, d lieu se t thanh ghi SSPSR chuyen qua thanh ghi SSPBUF va c
hieu c set, ong thi ngat se xay ra.
Khi s dung chuan giao tiep SPI trc tien ta can thiet lap cac che o cho giao dien
bang cach a cac gia tr thch hp vao hai thanh ghi SSPCON va SSPSTAT. Cac thong so
can thiet lap bao gom:
Master mode hay Slave mode. oi vi Master mode, xung clock ong bo se i ra t
chan RC3/SCK/SCL. oi vi Slave mode, xung clock ong bo se c nhan t ben ngoai qua
chan RC3/SCK/SCL.
Cac che o cua Slave mode.
Mc logic cua xung clock khi trang thai tam ngng qua trnh truyen nhan (Idle).
Canh tac ong cua xung clock ong bo (canh len hay canh xuong).
Toc o xung clock (khi hoat ong Master mode).
Thi iem xac nh mc logic cua d lieu ( gia hay cuoi thi gian 1 bit d lieu
c a vao).
Master mode, Slave mode va cac che o cua Slave mode c ieu khien bi cac bit
SSPM3:SSPM0 (SSPCON<3:0>). Xem chi tiet phu luc 2.
MSSP bao gom mot thanh ghi dch d lieu SSPSR va thanh ghi em d lieu SSPBUF.
Hai thanh ghi nay tao thanh bo em d lieu kep (doubled-buffer). D lieu se c dch vao
hoac ra qua thanh ghi SSPSR, bit MSB c dch trc. ay la mot trong nhng iem khac
biet gi hai giao dien MSSP va USART (USART dch bit LSB trc).
Trong qua trnh nhan d lieu, khi d lieu a vao t chan RC4/SDI/SDA trong thanh
ghi SSPSR a san sang (a nhan u 8 bit), d lieu se c a vao thanh ghi SSPBUF, bit ch
th trang thai bo em BF (SSPSTAT<0>) se c set e bao hieu bo em a ay, ong thi
c ngat SSPIF (PIR1<3>) cung c set. Bit BF se t ong reset ve 0 khi d lieu trong thanh
ghi SSPBUF c oc vao. Bo em kep cho phep oc tiep byte tiep theo trc khi byte d
lieu trc o c oc vao. Tuy nhien ta nen oc trc d lieu t thanh ghi SSPBUF trc
khi nhan byte d lieu tiep theo.
Qua trnh truyen d lieu cung hoan toan tng t nhng ngc lai. D lieu can truyen
se c a vao thanh ghi SSPBUF ong thi a vao thanh ghi SSPSR, khi o c hieu BF
c set. D lieu c dch t thanh ghi SSPSR va a ra ngoai qua chan RC5/SDO. Ngat se
xay ra khi qua trnh dch d lieu hoan tat. Tuy nhien d lieu trc khi c a ra ngoai phai
c cho phep bi tn hieu t chan
. Chan nay ong vai tro chon oi tng
giao tiep khi SPI che o Slave mode.
Khi qua trnh truyen nhan d lieu ang dien ra, ta khong c phep ghi d lieu vao
thanh ghi SSPBUF. Thao tac ghi d lieu nay se set bit WCON (SSPCON<7>). Mot ieu can
chu y na la thanh ghi SSPSR khong cho phep truy xuat trc tiep ma phai thong qua thanh
ghi SSPBUF.
Cong giao tiep cua giao dien SPI c ieu khien bi bit SSPEN (SSPSON<5>). Ben
canh o can ieu khien chieu xuat nhap cua PORTC thong qua thanh ghi TRISC sao cho phu
hp vi chieu cua giao dien SPI. Cu the nh sau:
RC4/SDI/SDA se t ong c ieu khien bi khoi giao itep SPI.
RS5/SDO la ngo ra d lieu, do o can clear bit TRISC<5>.
Khi SPI dang Master mode, can clear bit TRISC<3> e cho phep a xung clock
ong bo ra chan RC3/SCK/SCL.
Khi SPI dang Slave mode, can set bit TRISC<3> e cho phep nhan xung clock
ong bo t ben ngoai qua chan RC3/SCK/SCL.
nhan tn hieu ieu khien truy
Set bit TRISC<4> e cho phep chan
xuat d lieu khi SPI che o Slave mode.
S o ket noi cua chuan giao tiep SPI nh sau:
Hnh 2.20 S o ket noi cua chuan giao tiep SPI.

Theo s o ket noi nay, khoi Master se bat au qua trnh truyen nhan d lieu bang
cach gi tn hieu xung ong bo SCK. D lieu se dch t ca hai thanh ghi SSPSR a ra ngoai
neu co mot canh cua xung ong bo tac ong va ngng dch khi co tac ong cua canh con lai.
Ca hai khoi Master va Slave nen c an nh chung cac qui tac tac ong cua xung clock
ong bo e d lieu co the dch chuyen ong thi.
2.12.2.1.1 SPI MASTER MODE.
che o Master mode, vi ieu khien co quyen an nh thi iem trao oi d lieu (va
oi tng trao oi d lieu neu can) v no ieu khien xung clock ong bo. D lieu se c
truyen nhan ngay thi iem d lieu c a vao thanh ghi SSPBUF. Neu ch can nhan d
lieu, ta co the an nh chan SDO la ngo vao (set bit TRISC<5>). D lieu se c dch vao
thanh ghi SSPSR theo mot toc o c nh san cho xung clock ong bo. Sau khi nhan c
mot byte d lieu hoan chnh, byte d lieu se c a dao thanh ghi SSPBUF, bit BF c set
va ngat xay ra.
Khi lenh SLEEP c thc thi trong qua trnh truyen nhan, trang thai cua qua trnh se
c gi nguyen va tiep tuc sau khi vi ieu khien c anh thc.
Gian o xung cua Master mode va cac tac ong cua cac bit ieu khien c trnh bay
trong hnh ve sau:
Hnh 2.21 Gian o xung SPI che o Master mode.
2.12.2.1.2 SPI SLAVE MODE

che o nay SPI se truyen va nhan d lieu khi co xung ong bo xuat hien chan SCK. Khi
truyen nhan xong bit d lieu cuoi cung, c ngat SSPIF se c set. Slave mode hoat ong
ngay ca khi vi ieu khien ang che o sleep, va ngat truyen nhan cho phep anh thc vi
ieu khien. Khi ch can nhan d lieu, ta co the an nh RC5/SDO la ngo vao (set bit
TRISC<5>).
Slave mode cho phep s tac ong cua chan ieu khien
(SSPCON<3:0> =
0100). Khi chan
mc thap, chan RC5/SDO c cho phep xuat d lieu va
khi
mc cao, d lieu ra chan RC5/SDO b khoa, ong thi SPI c
reset (bo em bit d lieu c gan gia tr 0).
Hnh 2.22 Gian o xung chuan giao tiep SPI (Slave mode).
Cac thanh ghi lien quan en chuan giao tiep SPI bao gom:
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha bit cho phep toan bo cac
ngat (GIE va PEIE).
Thanh ghi PIR1 (a ch 0Ch): cha ngat SSPIE.
Thanh ghi PIE1 (a ch 8Ch): cha bit cho phep ngat SSPIE.
Thanh ghi TRISC (a ch 87h): ieu khien xuat nhap PORTC.

Thanh ghi SSPBUF (a ch 13h): thanh ghi em d lieu.
Thanh ghi SSPCON (a ch 14h): ieu khien chuan giao tiep SPI.
Thanh ghi SSPSTAT (a ch 94h): cha cac bit ch th trang thai chuan giao tiep SPI.
Thanh ghi TRISA (a ch 85h):ieu khien xuat nhap chan
.
2.12.2.2 I2C
ay la mot dang khac cua MSSP.
Chuan giao tiep I2C cung co hai che o
Master, Slave va cung c ket noi vi ngat.
I2C se s dung 2 pin e truyen nhan d lieu:
RC3/SCK/SCL: chan truyen dan
xung clock.
RC4/SDI/SDA: chan truyen dan d
lieu.
Cac khoi c ban trong s o khoi cua
I2C khong co nhieu khac biet so vi SPI.
Tuy nhien I2C con co them khoi phat hien
bit Start va bit Stop cua d lieu (Start and
Stop bit detect) va khoi xac nh a ch
(Match detect).
Cac thanh ghi lien quan en I2C bao gom:
Thanh ghi SSPCON va SSPCON2:
Hnh 2.23 S o khoi MSSP (I2Cslave
ieu khien MSSP.
mode).
Thanh ghi SSPSTAT: thanh ghi cha
cac trang thai hoat ong cua MSSP.
Thanh ghi SSPBUF: buffer truyen nhan noi tiep.
Thanh ghi SSPSR: thanh ghi dch dung e truyen nhan d lieu.
Thanh ghi SSPADD: thanh ghi cha a ch cua giao dien MSSP.
Cac thanh ghi SSPCON, SSPCON2 cho phep oc va ghi. Thanh ghi SSPSTAT ch cho
phep oc va ghi 2 bit au, 6 bit con lai ch cho phep oc.
Thanh ghi SSPBUF cha d lieu se c truyen i hoac nhan c va ong vai tro
nh mot thanh ghi em cho thanh ghi dch d lieu SSPSR.
Thanh ghi SSPADD cha a ch cua thiet b ngoai vi can truy xuat d lieu cua I2C
khi hoat ong Slave mode. Khi hoat ong Master mode, thanh ghi SSPADD cha gia tr
tao ra toc o baud cho xung clock dung e truyen nhan d lieu.
Trong qua trnh nhan d lieu, sau khi nhan c 1 byte d lieu hoan chnh, thanh ghi
SSPSR se chuyen d lieu vao thanh ghi SSPBUF. Thanh ghi SSPSR khong oc va ghi c,
qua trnh truy xuat thanh ghi nay phai thong qua thanh ghi SSPBUF.
Trong qua trnh truyen d lieu, d lieu can truyen khi c a vao thanh ghi
SSPBUF cung se ong thi a vao thanh ghi SSPSR.
I2C co nhieu che o hoat ong va c ieu khien bi cac bit SSPCON<3:0>, bao gom:
I2C Master mode, xung clock = fosc/4*(SSPADD+1).
I2C Slave mode, 7 bit a ch.
I2C Slave mode, 10 bit a ch.
I2C Slvae mode, 7 bit a ch, cho phep ngat khi phat hien bit Start va bit Stop.
I2C Slave mode, 10 bit a ch, cho phep ngat khi phat hien bit Start va bit Stop.
I2C Firmware Control Master mode.
a ch truyen i se bao gom cac bit a ch va mot bit
hay ghi d lieu) vi oi tng can truy xuat d lieu.
e xac nh thao tac (oc
Khi la chon giao dien I2C va khi set bit SSPEN, cac pin SCL va SDA se trang thai
cc thu h. Do o trong trng hp can thiet ta phai s dung ien tr keo len ben ngoai vi
ieu khien, ben canh o can an nh cac gia tr phu hp cho cac bit TRISC<4:3> (bit ieu
khien xuat nhap cac chan SCL va SDA).
2.12.2.2.1 I2C SLAVE MODE.
Viec trc tien la phai set cac pin SCL va SDA la input (set bit TRISC<4:3>). I2C cua
vi ieu khien se c ieu khien bi mot vi ieu khien hoac mot thiet b ngoai vi khac thong
qua cac a ch. Khi a ch nay ch en vi ieu khien, th tai thi iem nay va tai thi iem
e bao hieu ket
d lieu a c truyen nhan xong sau o, vi ieu khien se tao ra xung
thuc d lieu, gia tr trong thanh ghi SSPSR se c a vao thanh ghi SSPBUF. Tuy nhien
se khong c tao ra neu mot trong cac trng hp sau xay ra:
xung
Bit BF (SSPSTAT<0>) bao hieu buffer ay a c set trc khi qua trnh truyen
nhan xay ra.
Bit SSPOV (SSPCON<6>) c set trc khi qua trnh truyen nhan xay ra (SSPOV
c set trong trng hp khi mot byte khac c nhan vao trong khi d lieu trong thanh ghi
SSPBUF trc o van cha c lay ra).
Trong cac trng hp tren, thanh ghi SSPSR se khong a gia tr vao thanh ghi SSPBUF,
nhng bit SSPIF (PIR1<3>)se c set. e qua trnh truyen nhan d lieu c tiep tuc, can
oc d lieu t thanh ghi SSPBUF vao trc, khi o bit BF se t ong c xoa, con bit
SSPOV phai c xoa bang chng trnh.
Khi MSSP c kch hoat, no se ch tn hieu e bat au hoat ong. Sau khi nhan c
tn hieu bat au hoat ong (canh xuong au tien cua pin SDA), d lieu 8 bit se c dch vao
thanh ghi SSPSR. Cac bit a vao se c lay mau tai canh len cua xung clock. Gia tr nhan
c t thanh ghi SSPSR se c so sanh vi gia tr trong thanh ghi SSPADD tai canh xuong
cua xung clock th 8. Neu ket qua so sanh bang nhau, tc la I2C Master ch nh oi tng
giao tiep la vi ieu khien ang che o Slave mode (ta goi hien tng nay la address
match), bit BF va SSPOV se c xoa ve 0 va gay ra cac tac ong sau:
1.
2.
3.
4.
Gia tr trong thanh ghi SSPSR c a vao thanh ghi SSPBUF.

Bit BF t ong c set.
Mot xung
c tao ra.
C ngat SSPIF c set (ngat c kch hoat neu c cho phep trc o) tai canh
xuong cua xung clock th 9.
Khi MSSP che o I2C Slave mode 10 bit a ch, vi ieu khien can phai nhan vao
(SSPSTAT<2>) phai c xoa ve 0 e cho phep nhan 2
10 bit a ch e so sanh. Bit
byte a ch. Byte au tien co nh dang la 11110 A9 A8 0 trong o A9, A8 la hai bit MSB
cua 10 bit a ch. Byte th 2 la 8 bit a ch con lai.
Quatrnh nhan dang a ch cua MSSP che o I2C Slave mode 10 bit a ch nh sau:
1. au tien 2 bit MSB cua 10 bit a ch c nhan trc, bit SSPIF, BF va UA
(SSPSTAT<1>) c set (byte a ch au tien co nh dang la 11110 A9 A8 0) .
2. Cap nhat vao 8 bit a ch thap cua thanh ghi SSPADD, bit UA se c xoa bi vi
ieu khien e khi tao xung clock pin SCL sau khi qua trnh cap nhat hoan tat.
3. oc gia tr thanh ghi SSPBUF (bit BF se c xoa ve 0) va xoa c ngat SSPIF.
4. Nhan 8 bit a ch cao, bit SSPIF, BF va UA c set.
5. Cap nhat 8 bit a ch a nhan c vao 8 bit a ch cao cua thanh ghi SSPADD,
neu a ch nhan c la ung (address match), xung clock chan SCL c khi
tao va bit UA c set.
6. oc gia tr thanh ghi SSPBUF (bit BF se c xoa ve 0) va xoa c ngat SSPIF.
7. Nhan tn hieu Start.
8. Nhan byte a ch cao (bit SSPIF va BF c set).
9. oc gia tr thanh ghi SSPBUF (bit BF c xoa ve 0) va xoa c ngat SSPIF.
Trong o cac bc 7,8,9 xay ra trong qua trnh truyen d lieu che o Slave mode.
Xem gian o xung cua I2C e co c hnh anh cu the hn ve cac bc tien hanh trong qua
trnh nhan dang a ch.
Xet qua trnh nhan d lieu che o Slave mode, cac bit a ch se c I2C Master
a vao trc. Khi bit
trong cac bit a ch co gia tr bang 0 (bit nay c nhan dang sau
khi cac bit a ch a c nhan xong) va a ch c ch nh ung (address match), bit
cua thanh ghi SSPSTAT c xoa ve 0 va ng d lieu SDI c a ve mc logic thap
(xung
). Khi bit SEN (SSPCON<0>) c set, sau khi 1 byte d lieu c nhan, xung
clock t chan RC3/SCK/SCL se c a xuong mc thap, muon khi tao lai xung clock ta
set bit CKP (SSPCON<4>). ieu nay se lam cho hien tng tran d lieu khong xay ra v bit
SEN cho phep ta ieu khien c xung clock dch d lieu thong qua bit CKP (tham khao gian
o xung e biet them chi tiet). Khi hien tng tran d lieu xay ra, bit BF hoac bit SSPOV se
c set. Ngat se xay ra khi mot byte d lieu c nhan xong, c ngat SSPIF se c set va
phai c xoa bang chng trnh.
Hnh 2.24 Gian o xung cua I2C Slave mode 7 bit a ch trong qua trnh nhan d lieu (bit
SEN = 0).
SEN = 0).
SEN = 1).
SEN = 1).
Xet qua trnh truyen d lieu, khi bit
trong cac bit d lieu mang gia tr 1 va a ch
cua thanh ghi SSPSTAT se c set. Cac bit a
c ch nh ung (address match), bit
c tao ra, xung clock
ch c nhan trc va a vao thanh ghi SSPBUF. Sau o xung
chan RC3/SCK/SCL c a xuong mc thap bat chap trang thai cua bit SEN. Khi o I2C
Master se khong c a xung clock vao I2C Slave cho en khi d lieu thanh ghi SSPSR
trang thai wsan sang cho qua trnh truyen d lieu (d lieu a vao thanh ghi SSPBUF se
ong thi c a vao thanh ghi SSPSR). Tiep theo cho phep xung pin RC3/SCK/SCL
bang cach set bit CKP (SSPCON<4>). Tng bit cua byte d lieu se c dch ra ngoai tai moi
canh xuong cua xung clock. Nh vay d lieu se san sang ngo ra khi xung clock mc logic
cao, giup cho I2C Master nhan c d lieu tai moi canh len cua xung clock. Nh vay trong
qua trnh truyen d lieu bit SEN khong ong vai tro quan trong nh trong qua trnh nhan d
lieu.
Tai canh len xung clock th 9, d lieu a c dch hoan toan vao I2C Master, xung
se c tao ra I2C Master, ong thi pin SDA se c gi mc logic cao. Trong
trng hp xung
c chot bi I2C Slave, thanh ghi SSPSTAT se c reset. I2C Slave
se ch tn hieu cua bit Start e tiep tuc truyen byte d lieu tiep theo (a byte d lieu tiep
theo vao thanh ghi SSPBUF va set bit CKP.
Ngat MSSP xay ra khi mot byte d lieu ket thuc qua trnh truyen, bit SSPIF c set
tai canh xuong cua xung clock th 9 va phai c xoa bang chng trnh e am bao se c
set khi byte d lieu tiep theo truyen xong.
Hnh 2.28 Gian o xung cua I2C Slave mode 7 bit a ch trong qua trnh truyen d
lieu.
Hnh 2.29 Gian o xung cua I2C Slave mode 10 bit a ch trong qua trnh truyen d lieu.
Qua trnh truyen nhan cac bit a ch cho phep I2C Master chon la oi tng I2C
Slave can truy xuat d lieu. Ben canh o I2C con cung cap them mot a ch GCA (General
Call Address) cho phep chon tat ca cac I2C Slave. ay la mot trong 8 a ch ac biet cua
protocol I2C. a ch nay c nh dang la mot chuoi 0 vi
=0 va c cho phep bang
cach set bit GCEN (SSPCON2<7>). Khi o a ch nhan vao se c so sanh vi thanh ghi
SSPADD va vi a ch GCA.
Hnh 2.30 Gian o xung cua I2C Slave khi nhan a ch GCA.
Qua trnh nhan dang a ch GCA cung tng t nh khi nhan dang cac a ch khac
va khong co s khac biet ro rang khi I2C hoat ong che o a ch 7 bit hay 10 bit.
2.12.2.2.2 I2C MASTER MODE
I2C Master mode c xac lap bang cach a cac gia tr thch hp vao cac bit SSPM
cua thanh ghi SSPCON va set bit SSPEN. che o Master, cac pin SCK va SDA se c
ieu khien bi phan cng cua MSSP.
Hnh 2.31 S o khoi MSSP (I2C Master mode).

I2C Master ong vai tro tch cc trong qua trnh giao tiep va ieu khien cac I2C Slave thong
qua viec chu ong tao ra xung giao tiep va cac ieu kien Start, Stop khi truyen nhan d lieu.
Mot byte d lieu co the c bat au bang ieu kien Start, ket thuc bang ieu kien Stop hoac
bat au va ket thuc vi cung mot ieu kien khi ong lap lai (Repeated Start Condition).
Xung giao tiep noi tiep se c tao ra t BRG (Baud Rate Generator), gia tr an nh tan so
xung clock noi tiep c lay t 7 bit thap cua thanh ghi SSPADD. Khi d lieu c a vao
thanh ghi SSPBUF, bit BF c set va BRG t ong em ngc ve 0 va dng lai, pin SCL
c gi nguyen trang thai trc o.Khi d lieu tiep theo c a vao, BRG se can mot
khoang thi gian TBRG t ong reset lai gia tr e tiep tuc qua trnh em ngc. Moi vong
lenh (co thi gian TCY ) BRG se giam gia tr 2 lan.
Hnh 2.32 S o khoi BRG (Baud Rate Benerator) cua I2C Master mode.
Cac gia tr cu the cua tan so xung noi tiep do BRG tao ra c liet ke trong bang sau:
Trong o gia tr BRG la gia tr c lay t 7 bit thap cua thanh ghi SSPADD. Do I2C
che o Master mode, thanh ghi SSPADD se khong c s dung e cha a ch, thay vao
o chc nang cua SSPADD la thanh ghi cha gia tr cua BRG.
e tao c ieu kien Start, trc het can a hai pin SCL va SDA len mc logic cao
va bit SEN (SSPCON2<0>) phai c set. Khi o BRG se t ong oc gia tr 7 bit thap cua
thanh ghi SSPADD va bat au em. Sau khoang thi gian TBRG, pin SDA c a xuong
mc logic thap. Trang thai pin SDA mc logic thap va pin SCL mc logic cao chnh la
ieu kien Start cua I2C Master mode. Khi o bit S (SSPSTAT<3>) se c set. Tiep theo
BRG tiep tuc lay gia tr t thanh ghi SSPADD e tiep tuc qua trnh em, bit SEN c t
ong xoa va c ngat SSPIF c set.
Trong trng hp pin SCL va SDA trang thai logic thap, hoac la trong qua trnh tao
ieu kien Start, pin SCL c a ve trang thai logic thap trc khi pin SDA c a ve
trang thai logic thap, ieu kien Start se khong c hnh thanh, c ngat BCLIF se c set va
I2C se trang thai tam ngng hoat ong (Idle).
Hnh 2.33 Gian o xung I2C Master mode trong qua trnh tao ieu kien Start.
Tn hieu Stop se c a ra pin SDA khi ket thc d lieu bang cach set bit PEN
(SSPCON2<2>). Sau canh xuong cua xung clock th 9 va vi tac ong cua bit ieu khien
PEN, pin SDA cung c a xuong mc thap, BRG lai bat au qua trnh em. Sau mot
khoang thi gian TBRG, pin SCL c a len mc logic cao va sau mot khoang thi gian
TBRG na pin SDA cung c a len mc cao. Ngay tai thi iem o bit P (SSPSTAT<4>)
c set, ngha la ieu kien Stop a c tao ra. Sau mot khoang thi gian TBRG na, bit PEN
t ong c xoa va c ngat SSPIF c set.
Hnh 2.34 Gian o xung I2C Master mode trong qua trnh tao ieu kien Stop.
e tao c dieu kien Start lap lai lien tuc trong qua trnh truyen d lieu, trc het
can set bit RSEN (SSPCON2<1>). Sau khi set bit RSEN, pin SCL c a xuong mc logic
thap, pin SDA c a len mc logic cao, BRG lay gia tr t thanh ghi SSPADD vao e baty
au qua trnh em. Sau khoang thi gian TBRG, pin SCL cung c a len mc logic cao
trong khoang thi gian TBRG tiep theo. Trong khoang thi gian TBRG ke tiep, pin SDA lai c
a xuong mc logic thap trong khi SCL van c gi mc logic cao. Ngay thi iem o bit
S (SSPSTAT<3>) c set e bao hieu ieu kien Start c hnh thanh, bit RSEN t ong
c xoa va c ngat SSPIF se c set sau mot khoang thi gian TBRG na. Luc nay a ch
cua I2C Slave co the c a vao thanh ghi SSPBUF, sau o ta ch viec a tiep a ch
hoac d lieu tiep theo vao thanh ghi SSPBUF moi khi nhan c tn hieu
t I2C Slave,
I2C Master se t ong tao tn hieu Start lap lai lien tuc cho qua trnh truyen d lieu lien tuc.
Can chu y la bat c mot trnh t nao sai trong qua trnh tao ieu kien Start lap lai se
lam cho bit BCLIF c set va I2C c a ve trang thai Idle.
Hnh 2.35 Gian o xung I2C Master mode trong qua trnh tao ieu kien Start lien tuc.
Xet qua trnh truyen d lieu, xung clock se c a ra t pin SCL va d lieu c
a ra t pin SDA. Byte d lieu au tien phai la byte a ch xac nh I2C Slave can giao tiep
va bit
(trong trng hp nay
= 0). au tien cac gia tr a ch se c a vao thanh
ghi SSPBUF, bit BF t ong c set len 1 va bo em tao xung clock noi tiep BRG (Baud
Rate Generator) bat au hoat ong. Khi o tng bit d lieu (hoac a ch va bit
) se c
dch ra ngoai theo tng canh xuong cua xung clock sau khi canh xuong au tien cua pin SCL
c nhan dien (ieu kien Start), BRG bat au em ngc ve 0. Khi tat ca cac bit cua byte
d lieu c a c a ra ngoai, bo em BRG mang gia tr 0. Sau o, tai canh xuong cua
xung clock th 8, I2C Master se ngng tac ong len pin SDA e ch i tn hieu t I2C
). Tai canh xuong cua xung clock th 9, I2C Master se lay mau tn
Slave (tn hieu xung
hieu t pin SDA e kiem tra xem a ch a c I2C Slave nhan dang cha, trang thai
c a vao bit ACKSTAT (SSPCON2<6>). Cung tai thi iem canh xuong cua xung clock
th 9, bit BF c t ong clear, c ngat SSPIF c set va BRG tam ngng hoat ong cho
ti khi d lieu hoac a ch tiep theo c a vao thanh ghi SSPBUF, d lieu hoac a ch se
tiep tuc c truyen i tai canh xuong cua xung clock tiep theo.
Hnh 2.36 Gian o xung I2C Master mode trong qua trnh truyen d lieu.
Xet qua trnh nhan d lieu che o I2C Master mode. Trc tien ta can set bit cho
phep nhan d lieu RCEN (SSPCON2<3>). Khi o BRG bat au qua trnh em, d lieu se
c dch vao I2C Master qua pin SDA tai canh xuong cua pin SCL. Tai canh xuong cua
xung clock th 8, bit c hieu cho phep nhan RCEN t ong c xoa, d lieu trong thanh ghi
SSPSR c a vao thanh ghi SSPBUF, c hieu BF c set, c ngat SSPIF c set, BRG
ngng em va pin SCL c a ve mc logic thap. Khi o MSSP trang thai tam ngng
hoat ong e ch i lenh tiep theo. Sau khi oc gia tr thanh ghi SSPBUF, c hieu BF t
bang cach set bit ACKEN (SSPCON2<4>).
ong c xoa. Ta con co the gi tn hieu
Hnh 2.37 Gian o xung I2C Master mode trong qua trnh nhan d lieu.
2.13 CONG GIAO TIEP SONG SONG PSP (PARALLEL SLAVE PORT)
Ngoai cac cong noi tiep va cac giao ien noi tiep c trnh bay phan tren, vi ieu
khien PIC16F877A con c ho tr mot cong giao tiep song song va chuan giao tiep song
song thong qua PORTD va PORTE. Do cong song song ch hoat ong che o Slave mode
nen vi ieu khien khi giao tiep qua giao dien nay se chu s ieu khien cua thiet b ben ngoai
thong qua cac pin cua PORTE, trong khi d lieu se c oc hoac ghi theo dang bat ong bo
thong qua 8 pin cua PORTD.
Bit ieu khien PSP la PSPMODE (TRISE<4>). PSPMODE c set se thiet lap chc
nang cac pin cua PORTE la cac pin cho phep oc d lieu
(
), cho phep ghi d
lieu
(
) va pin chon vi ieu khien
(
) phuc vu cho viec truyen
nhan d lieu song song thong qua bus d lieu 8 bit cua PORTD. PORTD luc nay ong vai tro
la thanh ghi chot d lieu 8 bit, ong thi tac ong cua thanh ghi TRISD cung se c bo qua
do PORTD luc nay chu s ieu khien cua cac thiet b ben ngoai. PORTE van chu s tac
ong cua thanh ghi TRISE, do o can xac lap trang thai cac pin PORTE la input bang cach
set cac bit TRISE<2:0>. Ngoai ra can a gia tr thch hp cac bit PCFG3:PCFG0 (thanh ghi
ADCON1<3:0>) e an nh cac pin cua PORTE la cac pin I/O dang digital (PORTE con la
cac pin chc nang cua khoi ADC).
Khi cac pin
va
cung mc
thap, d lieu t ben ngoai se c ghi len
PORTD. Khi mot trong hai pin tren chuyen
len mc logic cao, c hieu bao d lieu trong
buffer a ay BIF (TRISE<7>) c set va
c ngat PSPIF (PIR1<7>) c set e bao
hieu ket thuc ghi d lieu. Bit BIF ch c
xoa ve 0 khi d lieu va nhan c
PORTD c oc vao. Bit bao hieu d lieu
nhan c trong buffer b tran IBOV
(TRISE<5>) se c set khi vi ieu khien
nhan tiep d lieu tiep theo trong khi cha
oc vao d lieu a nhan c trc o.
Khi cac pin
va
cung mc logic
thap, bit bao hieu buffer truyen d lieu a
ay BOF (TRISE<6>) se c xoa ngay lap
tc e bao hieu PORTD a san sang cho qua
trnh oc d lieu. Khi mot trong hai pin tren
chuyen sang mc logic cao, c ngat PSPIF
Hnh 2.38 S o khoi cua PORTD va

PORTE khi hoat ong che o PSP Slave
mode.
se c set e bao hieu qua trnh oc d lieu hoan tat. Bit BOF van c gi mc logic 0
cho en khi d lieu tiep theo c a vao PORTD.
Can chu y la ngat SSPIF c ieu khien bi bit PSPIE (PIE1<7>) va phai c xoa
bang chng trnh.
Cac thanh ghi lien quan en PSP bao gom:
Thanh ghi PORTD (a ch 08h): cha d lieu can oc hoac ghi.
Thanh ghi PORTE (a ch 09h): cha gia tr cac pin PORTE.
Thanh ghi TRISE (a ch 89h): cha cac bit ieu khien PORTE va PSP.
Thanh ghi PIR1 (a ch 0Ch): cha c ngat PSPIF.
Thanh ghi PIE1 (a ch 8Ch): cha bit cho phep ngat PSP.
Thanh ghi ADCON1 (a ch 9Fh): ieu khien khoi ADC tai PORTE.
2.14 TONG QUAN VE MOT SO AC TNH CUA CPU.

2.14.1 CONFIGURATION BIT
ay la cac bit dung e la chon cac ac tnh cua CPU. Cac bit nay c cha trong
bo nh chng trnh tai a ch 2007h va ch co the c truy xuat trong qua trnh lap trnh
cho vi ieu khien. Chi tiet ve cac bit nay nh sau:
Bit 13 CP: (Code Protection)

1: tat che o bao ve ma chng trnh.
0: bat che o bao ve ma chng trnh.
Bit 12, 5, 4: khong quan tam va c mac nh mang gia tr 0.
Bit 11 DEBUG (In-circuit debug mode bit)
1:khong cho phep, RB7 va RB6 c xem nh cac pin xuat nhap bnh thng.
0:cho phep, RB7 va RB6 la cac pin c s dung cho qua trnh debug.
Bit 10-9 WRT1:WRT0 Flash Program Memory Write Enable bit
11: Tat chc nang chong ghi, EECON se ieu khien qua trnh ghi len toan bo
nh chng trnh.
10: ch chong t a ch 0000h:00FFh.
01: ch chong ghi t a ch 0000h:07FFh.
00: ch chong ghi t a ch 0000h:0FFFh.
Bit 8 CPD Data EEPROM Memory Write Protection bit
1: Tat chc nang bao ve ma cua EEPROM.
0: Bat chc nang bao ve ma.
Bit 7 LVP Low-Voltage (Single supply) In-Circuit Serial Programming Enable bit
1: Cho phep che o nap ien ap thap, pin RB3/PGM c s dung cho che o
nay.
0: Khong cho phep che o nap ien ap thap, ien ap cao c a vao t pin
, pin RB3 la pin I/O bnh thng.
Bit 6 BODEN Brown-out Reset Enable bit
1: cho phep BOR (Brown-out Reset)
0: khong cho phep BOR.
Bit 3
Power-up Timer Enable bit
1: khong cho phep PWR.
0: cho phep PWR.
Bit 2 WDTEN Watchdog Timer Enable bit
1: cho phep WDT.
0: khong cho phep WDT.
Bit 1-0 FOSC1:FOSC0 la chon loai oscillator

11: s dung RC oscillator.
10: s dung HS oscillator.
01: s dung XT oscillator.
00: s dung LP oscillator.
Chi tiet ve cac ac tnh se c e cap cu the trong cac phan tiep theo.
2.14.2 CAC AC TNH CUA OSCILLATOR
PIC16F877A co kha nang s dung mot trong 4 loai oscillator, o la:
LP: (Low Power Crystal).
XT: Thach anh bnh thng.
HS: (High-Speed Crystal).
RC: (Resistor/Capacitor) dao ong do mach RC tao ra.
oi vi cac loai oscillator LP, HS, XT, oscillator c gan vao vi ieu khien thong
qua cac pin OSC1/CLKI va OSC2/CLKO.
oi vi cac ng dung khong can cac
loai oscillator toc o cao, ta co the s dung
mach dao ong RC lam nguon cung cap
xung hoat ong cho vi vi ieu khien. Tan so
tao ra phu thuoc vao cac gia tr ien ap, gia
tr ien tr va tu ien, ben canh o la s anh
hng cua cac yeu to nh nhiet o, chat
Hnh 2.39 RC oscillator.
lng cua cac linh kien.
Cac linh kien s dung cho mach RC oscillator phai bao am cac gia tr sau:
3 K < REXT < 100 K
CEXT >20 pF
2.14.3 CAC CHE ORESET
Co nhieu che o reset vi ieu khien, bao gom:
Power-on Reset POR (Reset khi cap nguon hoat ong cho vi ieu khien).
reset trong qua trnh hoat ong.
t che o sleep.
WDT reset (reset do khoi WDT tao ra trong qua trnh hoat ong).
WDT wake up t che o sleep.
Brown-out reset (BOR).
Ngoai tr reset POR trang thai cac thanh ghi la khong xac nh vaWDT wake up
khong anh hng en trang thai cac thanh ghi, cac che o reset con lai eu a gia tr cac
va
ch th trang thai hoat ong,
thanh ghi ve gia tr ban au c an nh san. Cac bit
trang thai reset cua vi ieu khien va c ieu khien bi CPU.
reset: Khi pin
mc logic thap,
vi ieu khien se c reset. Tn hieu reset
c cung cap bi mot mach ngoai vi vi
cac yeu cau cu the sau:
Khong noi pin
trc tiep len
nguon VDD.
R1 phai nho hn 40 K e am bao
cac ac tnh ien cua vi ieu khien.
R2 phai ln hn 1 K e han dong i
Hnh 2.40 Mach reset qua pin
.
vao vi ieu khien.
reset con c chong nhieu bi mot bo loc e tranh cac tn hieu nho tac ong
len pin
.
Power-on reset (POR): ay la xung reset do vi ieu khien tao ra khi phat hien nguon
cung cap VDD. Khi hoat ong che o bnh thng, vi ieu khien can c am bao cac
thong so ve dong ien, ien ap e hoat ong bnh thng. Nhng neu cac tham so nay khong
c am bao, xung reset do POR tao ra se a vi ieu khien ve trang thai reset va ch tiep
tuc hoat ong khi nao cac tham so tren c am bao.
Power-up Timer (PWRT): ay la bo nh thi hoat ong da vao mach RC ben trong
vi ieu khien. Khi PWRT c kch hoat, vi ieu khien se c a ve trang thai reset.
PWRT se tao ra mot khoang thi gian delay (khoang 72 ms) e VDD tang en gia tr thch
hp.
Oscillator Start-up Timer (OST): OST cung cap mot khoang thi gian delay bang 1024
chu k xung cua oscillator sau khi PWRT ngng tac ong (vi ieu khien a u ieu kien hoat
ong) e am bao s on nh cua xung do oscillator phat ra. Tac ong cua OST con xay ra
oi vi POR reset va khi vi ieu khien c anh thc t che sleep. OST ch tac ong oi
vi cac loai oscillator la XT, HS va LP.
Brown-out reset (BOR): Neu VDD ha xuong thap hn gia tr VBOR (khoang 4V) va keo
dai trong khoang thi gian ln hn TBOR (khoang 100 us), BOR c kch hoat va vi ieu
khien c a ve trang thai BOR reset. Neu ien ap cung cap cho vi ieu khien ha xuong
thap hn VBOR trong khoang thi gian ngan hn TBOR, vi ieu khien se khong c reset. Khi
ien ap cung cap u cho vi ieu khien hoat ong, PWRT c kch hoat e tao ra mot
khoang thi gian delay (khoang 72ms). Neu trong khoang thi gian nay ien ap cung cap cho
vi ieu khien lai tiep tuc ha xuong di mc ien ap VBOR, BOR reset se lai c kch hoat
khi vi ieu khien u ien ap hoat ong. Mot iem can chu y la khi BOR reset c cho phep,
PWRT cung se hoat ong bat chap trang thai cua bit PWRT.
Tom lai e vi ieu khien hoat ong c t khi cap nguon can trai qua cac bc sau:
POR tac ong.
PWRT (neu c cho phep hoat ong) tao ra khoang thi gian delay TPWRT e on nh
nguon cung cap.
OST (neu c cho phep) tao ra khoang thi gian delay bang 1024 chu k xung cua
oscillator e on nh tan so cua oscillator.
en thi iem nay vi ieu khien mi bat au hoat ong bnh thng.
Thanh ghi ieu khien va ch th trang thai nguon cung cap cho vi ieu khien la thanh ghi
PCON (xem phu luc 2 e biet them chi tiet).
Hnh 2.41 S o cac che o reset cua PIC16F877A.

2.14.4 NGAT (INTERRUPT)
PIC16F877A co en 15 nguon tao ra hoat ong ngat c ieu khien bi thanh ghi
INTCON (bit GIE). Ben canh o moi ngat con co mot bit ieu khien va c ngat rieng. Cac c
ngat van c set bnh thng khi thoa man ieu kien ngat xay ra bat chap trang thai cua bit
GIE, tuy nhien hoat ong ngat van phu thuoc vao bit GIE va cac bit ieu khien khac. Bit ieu
khien ngat RB0/INT va TMR0 nam trong thanh ghi INTCON, thanh ghi nay con cha bit cho
phep cac ngat ngoai vi PEIE. Bit ieu khien cac ngat nam trong thanh ghi PIE1 va PIE2. C
ngat cua cac ngat nam trong thanh ghi PIR1 va PIR2.
Trong mot thi iem ch co mot chng trnh ngat c thc thi, chng trnh ngat
c ket thuc bang lenh RETFIE. Khi chng trnh ngat c thc thi, bit GIE t ong c
xoa, a ch lenh tiep theo cua chng trnh chnh c cat vao trong bo nh Stack va bo em
chng trnh se ch en a ch 0004h. Lenh RETFIE c dung e thoat khoi chng trnh
ngat va quay tr ve chng trnh chnh, ong thi bit GIE cung se c set e cho phep cac
ngat hoat ong tr lai. Cac c hieu c dung e kiem tra ngat nao ang xay ra va phai c
xoa bang chng trnh trc khi cho phep ngat tiep tuc hoat ong tr lai e ta co the phat
hien c thi iem tiep theo ma ngat xay ra.
oi vi cac ngat ngoai vi nh ngat t chan INT hay ngat t s thay oi trang thai cac
pin cua PORTB (PORTB Interrupt on change), viec xac nh ngat nao xay ra can 3 hoac 4
chu k lenh tuy thuoc vao thi iem xay ra ngat.
Can chu y la trong qua trnh thc thi ngat, ch co gia tr cua bo em chng trnh c
cat vao trong Stack, trong khi mot so thanh ghi quan trong se khong c cat va co the b
thay oi gia tr trong qua trnh thc thi chng trnh ngat. ieu nay nen c x l bang
chng trnh e tranh hien tng tren xay ra.
Hnh 2.42 S o logic cua tat ca cac ngat trong vi ieu khien PIC16F877A.
2.14.4.1 NGAT INT

Ngat nay da tren s thay oi trang thai cua pin RB0/INT. Canh tac ong gay ra ngat
co the la canh len hay canh xuong va c ieu khien bi bit INTEDG (thanh ghi OPTION_
REG <6>). Khi co canh tac ong thch hp xuat hien tai pin RB0/INT, c ngat INTF c set
bat chap trang thai cac bit ieu khien GIE va PEIE. Ngat nay co kha nang anh thc vi ieu
khien t che o sleep neu bit cho phep ngat c set trc khi lenh SLEEP c thc thi.
2.14.4.2 NGAT DO S THAY OI TRANG THAI CAC PIN TRONG PORTB
Cac pin PORTB<7:4> c dung cho ngat nay va c ieu khien bi bit RBIE
(thanh ghi INTCON<4>). C ngat cua ngat nay la bit RBIF (INTCON<0>).
2.14.5 WATCHDOG TIMER (WDT)
Watchdog timer (WDT) la bo em oc lap dung nguon xung em t bo tao xung c
tch hp san trong vi ieu khien va khong phu thuoc vao bat k nguon xung clock ngoai vi
nao. ieu o co ngha la WDT van hoat ong ngay ca khi xung clock c lay t pin
OSC1/CLKI va pin OSC2/CLKO cua vi ieu khien ngng hoat ong (chang han nh do tac
ong cua lenh sleep). Bit ieu khien cua WDT la bit WDTE nam trong bo nh chng trnh
a ch 2007h (Configuration bit).
WDT se t ong reset vi ieu khien (Watchdog Timer Reset) khi bo em cua WDT b
tran (neu WDT c cho phep hoat ong), ong thi bit
t ong c xoa. Neu vi ieu
khien ang che o sleep th WDT se anh thc vi ieu khien (Watchdog Timer Wake-up)
khi bo em b tran. Nh vay WDT co tac dung reset vi ieu khien thi iem can thiet ma
khong can en s tac ong t ben ngoai, chang han nh trong qua trnh thc thi lenh, vi ieu
khien b ket mot cho nao o ma khong thoat ra c, khi o vi ieu khien se t ong
c reset khi WDT b tran e chng trnh hoat ong ung tr lai. Tuy nhien khi s dung
WDT cung co s phien toai v vi ieu khien se thng xuyen c reset sau mot thi gian
nhat nh, do oi can tnh toan thi gian thch hp e xoa WDT (dung lenh CLRWDT). Va
e viec an nh thi gian reset c linh ong, WDT con c ho tr mot bo chia tan so
prescaler c ieu khien bi thanh ghi OPTION_REG (prescaler nay c chia xe vi
Timer0).
Mot iem can chu y na la lenh sleep se xoa bo em WDT va prescaler. Ngoai ra
lenh xoa CLRWDT ch xoa bo em ch khong lam thay oi oi tng tac ong cua prescaler
(WDT hay Timer0).
Xem lai Timer0 va thanh ghi OPTION_REG (phu luc 2) e biet them chi tiet.
2.14.6 CHE O SLEEP

ay la che o hoat ong cua vi ieu khien khi lenh SLEEP c thc thi. Khi o neu
c cho phep hoat ong, bo em cua WDT se b xoa nhng WDT van tiep tuc hoat ong,
(STATUS<3>) c reset ve 0, bit
c set, oscillator ngng tac ong va cac
bit
PORT gi nguyen trang thai nh trc khi lenh SLEEP c thc thi.
Do khi che o SLEEP, dong cung cap cho vi ieu khien la rat nho nen ta can thc hien cac
bc sau trc khi vi ieu khien thc thi lenh SLEEP:
a tat ca cac pin ve trang thai VDD hoac VSS
Can bao am rang khong co mach ngoai vi nao c ieu khien bi dong ien cua vi
ieu khien v dong ien nho khong u kha nang cung cap cho cac mach ngoai vi hoat ong.
Tam ngng hoat ong cu khoi A/D va khong cho phep cac xung clock t ben ngoai
tac ong vao vi ieu khien.
e y en chc nang keo len ien tr PORTB.
Pin
phai mc logic cao.
2.14.6.1 ANH THC VI IEU KHIEN
Vi ieu khien co the c anh thc di tac ong cua mot trong so cac hien tng sau:
1. Tac ong cua reset ngoai vi thong qua pin
.
2. Tac ong cua WDT khi b tran.
3. Tac ong t cac ngat ngoai vi t PORTB (PORTB Interrupt on change hoac pin
INT).
Cac bit
va
c dung e the hien trang thai cua vi ieu khien va e phat hien nguon
tac ong lam reset vi ieu khien. Bit
c set khi vi ieu khien c cap nguon va c
reset ve 0 khi vi ieu khien che o sleep. Bit
c reset ve 0 khi WDT tac ong do bo
em b tran.
Ngoai ra con co mot so nguon tac ong khac t cac chc nang ngoai vi bao gom:
1. oc hay ghi d lieu thong qua PSP (Parallel Slave Port).
2. Ngat Timer1 khi hoat ong che o em bat ong bo.
3. Ngat CCP khi hoat ong che o Capture.
4. Cac hien tng ac biet lam reset Timer1 khi hoat ong che o em bat ong
bo dung nguon xung clock ben ngoai).
5. Ngat SSP khi bit Start/Stop c phat hien.
6. SSP hoat ong che o Slave mode khi truyen hoac nhan d lieu.
7. Tac ong cua USART t cac pin RX hay TX khi hoat ong che o Slave mode
ong bo.
8. Khoi chuyen oi A/D khi nguon xung clock hoat ong dang RC.
9. Hoan tat qua trnh ghi vao EEPROM.
10. Ngo ra bo so sanh thay oi trang thai.
Cac tac ong ngoai vi khac khong co tac dung anh thc vi ieu khien v khi che o
sleep cac xung clock cung cap cho vi ieu khien ngng hoat ong. Ben canh o can cho phep
cac ngat hoat ong trc khi lenh SLEEP c thc thi e bao am tac ong cua cac ngat.
Viec anh thc vi ieu khien t cac ngat van c thc thi bat chap trang thai cua bit GIE.
Neu bit GIE mang gia tr 0, vi ieu khien se thc thi lenh tiep theo sau lenh SLEEP cua
chng trnh (v chng trnh ngat khong c cho phep thc thi). Neu bit GIE c set trc
khi lenh SLEEP c thc thi, vi ieu khien se thc thi lenh tiep theo cua chng trnh va sau
o nhay ti a ch cha chng trnh ngat (0004h). Trong trng hp lenh tiep theo khong
ong vai tro quan trong trong chng trnh, ta can at them lenh NOP sau lenh SLEEP e bo
qua tac ong cua lenh nay, ong thi giup ta de dang hn trong viec kiem soat hoat ong cua
chng trnh ngat. Tuy nhien cung co mot so iem can lu y nh sau:
Neu ngat xay ra trc khi lenh SLEEP c thc thi, lenh SLEEP se khong c thc
thi va thay vao o la lenh NOP, ong thi cac tac ong cua lenh SLEEP cung se c bo
qua.
Neu ngat xay ra trong khi hay sau khi lenh SLEEP c thc thi, vi ieu khien lap tc
c anh thc t che o sleep, va lenh SLEEP se c thc thi ngay sau khi vi ieu khien
c anh thc.
. Neu bit
e kiem tra xem lenh SLEEP a c thc thi hay cha, ta kiem tra bit
van mang gia tr 1 tc la lenh SLEEP a khong c thc thi va thay vao o la lenh NOP.
Ben canh o ta can xoa WDT e chac chan rang WDT a c xoa trc khi thc thi lenh
SLEEP, qua o cho phep ta xac nh c thi iem vi ieu khien c anh thc do tac
ong cua WDT.
CHNG 3 TAP LENH CUA VI IEU KHIEN PIC

3.1 VAI NET S LC VE TAP LENH CUA VI IEU KHIEN PIC
Nh a trnh bay chng 1, PIC la vi ieu khien co tap lenh rut gon RISC (Reduced
Instruction Set Computer), bao gom 35 lenh va co the c phan ra thanh 3 nhom c ban:
Nhom lenh thao tac tren bit.
Nhom lenh thao tac tren byte.
Nhom lenh ieu khien.
oi vi dong vi ieu khien
PIC16Fxxx, moi lenh c ma hoa thanh 14
bit word, bao gom cac bit opcode (dung e
xac nh lenh nao c ma hoa) va cac bit
mo ta mot hay vai tham so cua lenh.
oi vi nhom lenh thao tac tren byte,
ta co 2 tham so f (xac nh a ch byte can
thao tac) va d (xac nh ni cha ket qua
thc thi lenh). Neu d = 0, ket qua se c
a vao thanh ghi W. Neu d = 1, ket qua
c a vao thanh ghi c mo ta bi tham
so f.
oi vi nhom lenh thao tac tren bit,
ta co hai tham so b (xac nh bit can thao
tac) va f (xac nh a ch byte d lieu can
thao tac).
Hnh 3.1 C che ma hoa lenh cua

PIC16Fxxx.
oi vi nhom lenh ieu khien ch co mot tham so duy nhat la k (k co the la 8 bit trong
trng hp cac lenh bnh thng hay 11 bit trong trng hp la lenh CALL va lenh GOTO)
dung e mo ta oi tng tac ong cua vi ieu khien (mot label, mot hang so nao o).
Moi lenh se c vi ieu khien thc thi xong trong vong mot chu k lenh, ngoai tr
cac lenh lam thay oi gia tr bo em chng trnh PC can 2 chu k lenh. Mot chu k lenh gom
4 xung clock cua oscillator. V du ta s dung oscillator co tan so 4 MHz th tan so thc thi
lenh se la 4MHz/4 = 1 MHz, nh vay mot chu k lenh co thi gian 1 uS.
Cac lenh thao tac tren mot thanh ghi bat k eu thc hien c che Read-Modify-Write,
tc la thanh ghi se c oc, d lieu c thao tac va ket qua c a vao thanh ghi cha
ket qua (ni cha ket qua tuy thuoc vao lenh thc thi va tham so d). V du nh khi thc thi
lenh CLRF PORTB, vi ieu khien se oc gia tr thanh ghi PORTB, xoa tat ca cac bit va ghi
ket qua tr lai thanh ghi PORTB.
Sau ay ta se i sau vao cau truc, cu phap va tac ong cu the cua tng lenh.
3.2 TAP LENH CUA VI IEU KHIEN PIC

3.2.1 Lenh ADDLW
3.2.5 Lenh BCF
Cu phap: ADDLW k (0 k255)

Tac dung: cong gia tr k vao thanh ghi W,
ket qua c cha trong thanh ghi W.
Bit trang thai: C, DC, Z
Cu phap: BCF f,b (0f127, 0b7)

Tac dung: xoa bit b trong thanh ghi f ve
gia tr 0.
Bit trang thai: khong co.
3.2.2 Lenh ADDWF
3.2.6 Lenh BSF
Cu phap: ADDWF
f,d
(0f255, d[0,1]).
Tac dung: cong gia tr hai thanh ghi W va
thanh ghi f. Ket qua c cha trong thanh
ghi W neu d = 0 hoac thanh ghi f neu d =1.
Cu phap: BSF f,b

(0f127, 0b7)
Tac dung: set bit b trong trnh ghi f.
Bit trang thai: khong co
3.2.7 Lenh BTFSS
Cu phap: ANDLW k (0k255)

Tac dung: thc hien phep toan AND gia
thanh ghi va gia tr k, ket qua c cha
trong thanh ghi W.
Bit trang thai: Z
Cu phap: BTFSS f,b

(0f127, 0b7)
Tac dung: kiem tra bit b trong thanh ghi f.
Neu bit b bang 0, lenh tiep theo c thc
thi. Neu bit b bang 1, lenh tiep theo c
bo qua va thay vao o la lenh NOP.
3.2.4 Lenh ANDWF
3.2.8 Lenh BTFSC
3.2.3 Lenh ANDLW
Cu phap: ANDWF
f,d
(0f127, d [0,1]).
Tac dung: thc hien phep toan AND gia
cac gia tr cha trong hai thanh ghi W va f.
Ket qua c a vao thanh ghi W neu
d=0 hoac thanh ghi f neu d = 1.
Bit trang thai: Z
Cu phap: BTFSC f,b

(0f127, 0b7)
Tac dung: kiem tra bit b trong thanh ghi f.
Neu bit b bang 1, lenh tiep theo c thc
thi. Neu bit b bang 0, lenh tiep theo c
bo qua va thay vao o la lenh NOP.
3.2.9 Lenh CALL

Cu phap: CALL k (0k2047)
Tac dung: goi mot chng trnh con. Trc
het a ch quay tr ve t chng trnh con
(PC+1) c cat vao trong Stack, gia tr
a ch mi c a vao bo em gom 11
bit cua bien k va 2 bit PCLATH<4:3>.
3.2.14 Lenh DECF

Cu phap: DECF f,d
(0f127, d[0,1]).
Tac dung: gia tr thanh ghi f c giam i
1 n v. Ket qua c a vao thanh ghi
W neu d = 0 hoac thanh ghi f neu d = 1.
Bit trang thai: Z
3.2.10 Lenh CLRF

Cu phap CLRF f (0f127)
Tac dung: xoa thanh ghi f va bit Z c
set.
Bit trang thai: Z
3.2.15 Lenh DECFSZ

Cu phap: DECFSZ f,d
Cu phap CLRW
Tac dung: xoa thanh ghi W va bit Z c
set.
Bit trang thai: Z
(0f127, d[0,1])
Tac dung: ga tr thanh ghi f c giam 1
n v. Neu ket qua sau khi giam khac 0,
lenh tiep theo c thc thi, neu ket qua
bang 0, lenh tiep theo khong c thc thi
va thay vao o la lenh NOP. Ket qua c
a vao thanh ghi W neu d = 0 hoac thanh
ghi f neu d = 1.
3.2.12 Lenh CLRWDT
3.2.16 Lenh GOTO
Cu phap: CLRWDT
Tac dung: reset Watchdog Timer, ong
thi prescaler cung c reset, cac bit
c set len 1.
va
Bit trang thai:
,
Cu phap: GOTO k (0k2047)

Tac dung: nhay ti mot label c nh
ngha bi tham so k va 2 bit PCLATH
<4:3>.
3.2.13 Lenh COMF

Cu phap: COMF f,d
3.2.17 Lenh INCF
(0f127, d[0,1]).
Tac dung: ao cac bit trong thanh ghi f.
Ket qua c a vao thanh ghi W neu
d=0 hoac thanh ghi f neu d=1.
Bit trang thai: Z
Cu phap: INCF f,d
3.2.11 Lenh CLRW
(0f127, d [0,1])
Tac dung: tang gia tr thanh ghi f len 1 n
v. Ket qua c a vao thanh ghi W neu
d = 0 hoac thanh ghi f neu d = 1.
Bit trang thai: Z
3.2.18 Lenh INCFSZ

Cu phap: INCFSZ f,d
(0f127, d[0,1])
Tac dung: tang gia tr thanh ghi f len 1 n
v. Neu ket qua khac 0, lenh tiep theo
c thc thi, neu ket qua bang 0, lenh
tiep theo c thay bang lenh NOP. Ket
qua se c a vao thanh ghi f neu d=1
hoac thanh ghi W neu d = 0.
3.2.19 Lenh IORLW

Cu phap: IORLW k (0k255)
Tac dung: thc hien phep toan OR gia
thanh ghi W va gia tr k. Ket qua c
cha trong thanh ghi W.
Bit trang thai: Z
3.2.20 Lenh IORWF
Cu phap: IORWF f,d
(0f127, d[0,1])
Tac dung: thc hien phep toan OR gia
hai thanh ghi W va f. Ket qua c a
vao thanh ghi W neu d=0 hoac thanh ghi f
neu d=1.
Bit trang thai: Z
3.2.22 Lenh RETURN

Cu phap: RETURN
Tac dung: quay tr ve chng trnh chnh
t mot chng trnh con
Bit trang thai:khong co
3.2.23 Lenh RRF
Cu phap: RRF f,d
(0f127, d[0,1])
Tac dung: dch phai cac bit trong thanh ghi
f qua c carry. Ket qua c lu trong
thanh ghi W neu d=0 hoac thanh ghi f neu
d=1.
Bit trang thai: C
3.2.24 Lenh SLEEP

Cu phap: SLEEP
Tac dung: a vi ieu khien ve che o
sleep. Khi o WDT b xoa ve 0, bit
c set len 1 va
c xo ve 0, bit
oscillator khong c cho phep hoat ong.
,
.
Bit trang thai:
3.2.21 Lenh RLF
3.2.25 Lenh SUBLW
Cu phap: RLF f,d
Cu phap: SUBLW k
Tac dung: lay gia tr k tr gia tr trong
thanh ghi W. Ket qua c cha trong
thanh ghi W.
(0f127, d[0,1])
Tac dung: dch trai cac bit trong thanh ghi f
qua c carry. Ket qua c lu trong thanh
ghi W neu d=0 hoac thanh ghi f neu d=1.
Bit trang thai: C
3.2.26 Lenh SUBWF

Cu phap: SUBWF f,d
(0f127, d[0,1])
Tac dung: lay gia tr trong thanh ghi f em
tr cho thanh ghi W. Ket qua c lu
trong thanh ghiaW neu d=0 hoac thanh ghi
f neu d=1.
3.2.27 Lenh SWAP
Cu phap: SWAP f,d
(0f127, d[0,1])
Tac dung: ao 4 bit thap vi 4 bit cao trong
thanh ghi f. Ket qua c cha trong thanh
ghiaW neu d=0 hoac thanh ghi f neu d=1.
3.2.28 Lenh XORLW

Cu phap: XORLW k (0k255)
Tac dung: thc hien phep toan XOR gia
gia tr k va gia tr trong thanh ghi W. Ket
qua c lu trong thanh ghi W.
Bit trang thai: Z
3.2.29 Lenh XORWF
Cu phap: XORWF f,d
Tac dung: thc hien phep toan XOR gia
hai gia tr cha trong thanh ghi W va thanh
ghi f. Ket qua c lu vao trong thanh ghi
W neu d=0 hoac thanh ghi f neu d=1.
Bit trang thai: Z
Ngoai cac lenh tren con co mot so lenh dung trong chng trnh nh:
3.2.30 Lenh #DIFINE
Cu phap: #DEFINE <text1> <text2>
Tac dung: thay the mot chuoi k t nay bang mot chuoi k t khac, co ngha la moi khi
chuoi k t text1 xuat hien trong chng trnh, trnh bien dch se t ong thay the chuoi k t
o bang chuoi k t <text2>.
3.2.31 Lenh INCLUDE
Cu phap: #INCLUDE <filename> hoac #INCLUDE filename
Tac dung: nh kem mot file khac vao chng trnh, tng t nh viec ta copy file o
vao v tr xuat hien lenh INCLUDE. Neu dung cu phap <filename> th file nh kem la file
he thong (stem file), neu dung cu phap filename th file nh kem la file cua ngi s
dung.
Thong thng chng trnh c nh kem theo mot header file cha cac thong tin
nh ngha cac bien (thanh ghi W, thanh ghi F,..) va cac a ch cau cac thanh ghi chc nang
ac biet trong bo nh d lieu. Neu khong co header file, chng trnh se kho oc va kho hieu
hn.
3.2.32 Lenh CONSTANT

Cu phap: CONSTANT <name>=<value>
Tac dung: khai bao mot hang so, co ngha la khi phat hien chuoi k t name trong
chng trnh, trnh bien dch se t ong thay bang chuoi k t bang gia tr value a c
nh ngha trc o.
3.2.33 Lenh VARIABLE
Cu phap: VARIABLE <name>=<value>
Tac dung: tng t nh lenh CONSTANT, ch co iem khac biet duy nhat la gia tr
value khi dung lenh VARIABLE co the thay oi c trong qua trnh thc thi chng trnh
con lenh CONSTANT th khong.
3.2.34 Lenh SET
Cu phap: <name variable> SET <value>
Tac dung: gan gia tr cho mot ten bien. Ten cua bien co the thay oi c trong qua
trnh thc thi chng trnh.
3.2.35 Lenh EQU
Cu phap: <name constant> EQU <value>
Tac dung: gan gia tr cho ten cua ten cua hang so. Ten cua hang so khong thay oi
trong qua trnh thc thi chng trnh.
3.2.36 Lenh ORG
Cu phap: ORG <value>
Tac dung: nh ngha mot a ch cha chng trnh trong bo nh chng trnh cua vi
ieu khien.
3.2.37 Lenh END
Cu phap: END
Tac dung: anh dau ket thuc chng trnh.
3.2.38 Lenh __CONFIG
Cu phap:
Tac dung: thiet lap cac bit ieu khien cac khoi chc nang cua vi ieu khien c cha
trong bo nh chng trnh (Configuration bit).
3.2.39 Lenh PROCESSOR
Cu phap: PROCESSOR <processor type>
Tac dung: nh ngha vi ieu khien nao s dung chng trnh.
3.3 CAU TRUC CUA MOT CHNG TRNH ASSEMBLY VIET CHO VI IEU
KHIEN PIC
Mot chng trnh Assembly bao gom nhieu thanh phan nh chng trnh chnh,
chng trnh ngat, chng trnh con, ay ch trnh bay cau truc mot chng trnh n gian
nhat khi mi bat au lam quen vi viec lap trnh cho vi ieu khien PIC.
Hnh 3.2 Cau truc mot chng trnh Asembly viet cho vi ieu khien PIC.
Ta nhan thay rang khong co s khac biet ln trong cau truc cua mot chng trnh
Assembly viet cho vi ieu khien PIC so vi vi ieu khien khac, ch co s khac biet ve cac
lenh s dung trong chng trnh. Dau ; c dung e a mot ghi chu vao chng trnh va
ch co hieu lc tren mot hang cua chng trnh. Hnh tren la v du ve mot chng trnh n
gian vi cac bc khi tao c ban ban au, ngoai ra neu can thiet ta van co the khai bao
them cac bien, hang va cac tham so khac trc chng trnh chnh (label Main).
Trong trng hp can s dung en chng trnh ngat, ta can mot cau truc chng trnh
phc tap hn vi nhieu bc khi tao phc tap va phai tuan theo mot th t lenh nhat nh.
Tuy nhien neu s dung trnh bien dch MPLAB, cau truc cua chng trnh danh cho mot vi
ieu khien PIC nhat nh a c viet san, ta ch viec viet oan chng trnh ieu khien vao
cac v tr thch hp tren mau chng trnh c viet trc o. ay la mot li the rat ln khi s
dung MPLAB e soan thao cac chng trnh viet cho vi ieu khien PIC.
CHNG 4
MOT SO NG DUNG CU THE CUA PIC16F877A
Trong chng nay ta se i sau vao mot so ng dung cu the cua vi ieu khien
PIC16F877A. Cac ng dung nay c xay dng da tren cac chc nang ngoai vi c tch
hp san ben trong vi ieu khien, qua o giup ta nam ro hn va ieu khien c cac khoi
chc nang o. Tuy nhien trc tien se la mot so ng dung n gian giup ta bc au lam
quen vi tap lenh va cach viet chng trnh cho vi ieu khien PIC.
4.1 IEU KHIEN CAC PORT I/O.
ay la mot trong nhng ng dung n gian nhat giup ta lam quen vi vi ieu khien.
Trong ng dung nay ta se xuat mot gia tr nao o ra mot PORT cua vi ieu khien, chang han
nh PORTB. Gia tr nay se c kiem tra bang cach gan vao cac pin cua PORTB cac LED.
Khi o pin mang gia tr mc logic 1 se lam cho LED sang va pin mang gia tr mc logic 0 se
lam cho LED tat.
Sau ay la mot vai iem can chu y cho ng dung nay:
e LED sang bnh thng th ien ap at len LED vao khoang 1.8 en 2.2
Volt tuy theo mau sac cua LED, trong khi ien ap tai ngo ra cua 1 pin trong PORTB neu
mc logic 1 thng la 5 volt. Do o ta can co them ien tr mac noi tiep vi LED e han
dong (co the dung ien tr 0.33 K).
e xuat c gia tr ra PORTB, trc het ta can khi tao cac pin cua PORTB
la output. ieu nay c thc hien bang cach clear cac bit trong thanh ghi TRISB. Tuy nhien
hai thanh ghi PORTB va TRISB nam hai bank khac nhau trong bo nh d lieu. Do o trc
khi muon truy xuat gia tr trong mot thanh ghi nao o can chon bank d lieu cha thanh ghi
o bang cach a cac gia tr thch hp vao 2 bit RP1:RP0 cua thanh ghi STATUS (xem phu
luc 2 va s o bo nh d lieu).
Do trong tap lenh cua vi ieu khien PIC khong co lenh nao cho phep a mot
byte vao mot thanh ghi cho trc, do o can s dung mot thanh ghi trung gian (thanh ghi W)
va dung hai lenh MOVLW (a byte vao thanh ghi W) va lenh MOVWF (a gia tr trong
thanh ghi W vao thanh ghi f nao o ma ta muon).
Ngoai ra can dung lenh ORG e ch ra a ch bat au chng trnh khi vi ieu
khien c reset. Thong thng a ch bat au chng trnh se la a ch 0000h.
Trong trng hp can dung en che o reset cua pin MCLR, ta co the thiet ke them
mot mach reset ngoai vi (vi ieu khien se c reset khi pin MCLR chuyen t mc logic 1
xuong mc logic 0).
Sau ay la s o mach cua ng dung tren:

HI
5V
0.33 K
R1
R
U1
2
3
4
5
6
7
SW1
5V
HI
8
9
10
11
12
13
14
4 MHz
XTAL
15
16
17
18
19
20
MCLR/VPP
RB7/PGD
RB6/PGC
RB5
RA0/AN0
RB4
RA1/AN1
RA2/AN2/VREF-/CVREFRB3/PGM
RB2
RA3/AN3/VREF+
RB1
RA4/T0CLK/C1OUT
RB0/INT
RA5/AN4/SS/C20UT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
40
39
38
37
36
35
34
33
0.33 K
0.33 K
0.33 K
5V
VDD
GND
32
31
HI
0.33 K
0.33 K
0.33 K
VDD
GND
OSC1/CLK
OSC2/CLKOUT
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC0/T1OSO/T1CLK RC7/RX/DT
RC1/T1OSI/CCP2
RC6/TX/CK
RC2/CCP1
RC5/SDO
RC3/SCK/SCL
RC4/SDI/SDA
RD0/PSP0
RD1/PSP1
RD3/PSP3
RD2/PSP2
30
29
28
27
0
0.33 K
26
25
24
23
22
21
PIC16F877A
Hnh 4.1 Mach nguyen l cua ng dung ieu khien cac PORT cua vi ieu khien.
Mot iem can chu y la vi ieu khien PIC16F877A co en 2 pin VDD va 2 pin GND.
Trong trng hp nay ta phai cap nguon vao tat ca cac pin tren, khi o vi ieu khien mi co
u ien ap e hoat ong.
Chng trnh viet cho ng dung tren nh sau:

;chng trnh 4.1.1
;PORTBTEST.ASM
processor
include
16f877a
<p16f877a.inc>
; khai bao vi ieu khien

; header file nh kem
__CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON &

_XT_OSC & _WRT_OFF & _LVP_OFF & _CPD_OFF
; khai bao cac Configuration bits
ORG
GOTO
Start
; a ch bat au chng trnh

; chng trnh chnh bat au tai ay
BCF
BCF
STATUS,RP1
STATUS,RP0
CLRF
BSF
PORTB
STATUS,RP0
; xoa PORTB
; chon BANK1
MOVLW
MOVWF
0x00
TRISB
; PORTB <- outputs
BCF
STATUS,RP0
; chon BANK0
MOVLW
MOVWF
0x8F
PORTB
; gia tr can a ra PORTB

; PORTB <- 8Fh
loop
END
0x000
start
GOTO
loop
; chon BANK0
; vong lap vo han

; ket thuc chng trnh
Cac bc tiep theo e hoan tat ng dung tren la bien dch chng trnh tren bang mot
trnh bien dch Assembly danh cho vi ieu khien PIC (trnh bien dch MPLAB chang han),
sau o dung mach nap e nap chng trnh vao vi ieu khien PIC va kiem tra ket qua. Neu
khong co loi nao xay ra, LED gan vao cac pin RB7, RB3, RB2, RB1, RB0 se sang, LED gan
vao cac pin con lai se tat (do gia tr ta a ra PORTB la 8Fh).
Hoan toan tng t ta co the viet chng trnh a mot gia tr bat k vao cac PORT
cua vi ieu khien PIC16F877A. Tuy nhien co mot ieu can chu y la oi vi PORTA, do pin
RA4 co cc thu e h (xem phu luc 1) nen muon PORTA hien th ket qua mot cach chnh xac
ta can dung mot ien tr keo len gan them vao ben ngoai pin RA4.
4.1.1 CHNG TRNH DELAY
Chng trnh tren giup ta a gia tr ra cac PORT cua vi ieu khien va cac LED se
sang hay tat tuy theo mc logic a ra cac PORT. Bay gi ta lai muon cac LED se chp tat
sau mot khoang thi gian nh trc. Muon vay ta dung them mot oan chng trnh
DELAY. Thc chat cua chng trnh DELAY la cho vi ieu khien lam mot cong viec vo
ngha nao o trong mot khoang thi gian nh trc. Khoang thi gian nay c tnh toan da
tren qua trnh thc thi lenh, hay cu the hn la da vao thi gian cua mot chu k lenh. Co the
viet chng trnh DELAY da tren oan chng trnh sau:
loop
MOVLW
MOVWL
DECFSZ
GOTO
0X20
delay-reg
delay-reg
loop
; gia tr 20h
; a vao thanh ghi delay
; giam gia tr thanh ghi delay-reg 1 n v
; nhay ti label loop neu thanh ghi delay-reg
;sau khi giam 1 n v cha gia tr khac 0.
; lenh nay c thc thi khi delay-reg bang 0
Neu dung oan chng trnh nay th thi gian delay c tnh gan ung nh sau:
td = 3(1+tv)ti
Trong o td la thi gian delay, tv la gia tr a vao thanh ghi delay-reg va ti la thi
gian cua mot chu k lenh va c tnh theo cong thc:
ti = 4/f0
Vi f0 la tan so cua oscillator. S d co cong thc nay la v mot chu k lenh bao gom 4
xung clock. Cong thc nay ch gan ung v ta a bo qua thi gian thc thi cac lenh trc label
loop va mot chu k lenh phat sinh khi thanh ghi delay-reg mang gia tr 0 (trng hp nay
can hai chu k lenh e thc thi lenh DECFSZ).
Do thanh ghi delay-reg ch mang gia tr ln nhat la FFh nen thi gian delay ch gii
han mot khoang thi gian nhat nh tuy thuoc vao xung clock s dung e cap cho vi ieu
khien. Muon tang thi gian delay ta co the goi chng trnh delay nhieu lan hoac tang so
lng vong lap cua chng trnh delay nh sau:
MOVLW
0Xff
MOVWF
delay-reg1
loop DECFSZ
delay-reg1
GOTO
loop1
; thc thi dng lenh nay neu delay-reg khac 0
GOTO
exit
; thc thi dng lenh nay neu delay-reg bang 0
Loop1 MOVLW
0Xff
MOVWF
delay-reg2
DECFSZ
delay-reg2
Exit
MOVWF
GOTO
loop1
loop
; thc thi dng lenh nay neu delay-reg khac 0

; thc thi dng lenh nay neu delay-reg bang 0
; lenh tiep theo sau thi gian delay
Vi oan chng trnh tren thi gian delay ch ket thuc khi ca hai thanh ghi delay-reg1
va delay-reg2 eu mang gia tr 0.
Sau ay la mot v du cu the. Yeu cau at ra la cho cac LED trong chng trnh 4.1
chp tat sau moi 100 miligiay. Gia s ta ang s dung oscillator 4MHz. Khi o thi gian cua
mot chu k lenh la:
ti = 4/4 MHz = 1 uS.
Vi thi gian can delay la td bang 1s th gia tr can a vao thanh ghi delay-reg la:
tv = (td/3ti) 1 = 33332.
Nh vay ta a vao thanh ghi delay-reg2 gia tr 255 (FFh) va thanh ghi delay-reg1 gia
tr 33332/255 = 131 (83h).
Chng trnh c viet nh sau:
;chng trnh 4.1.2
;PORTBTESTANDDELAY.ASM
;Version 1.1
processor
include
16f877a
<p16f877a.inc>

__CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC &
_WRT_OFF & _LVP_OFF & _CPD_OFF
delay_reg1
delay_reg2
start
EQU 0x20
EQU 0x21
; khai bao a ch cac o nh cha cac thanh ghi

; delay-reg1 va delay-reg2
ORG
GOTO
0x000
start
BCF
BCF
STATUS,RP1
STATUS,RP0
; chon BANK0
CLRF
BSF
PORTB
STATUS,RP0
; xoa PORTB
; chon BANK1
MOVLW
0x00
MOVWF
TRISB
; PORTB <- outputs
BCF
STATUS,RP0
; chon BANK0
MOVLW
MOVWF
0x8F
PORTB
; gia tr can a ra PORTB

; PORTB <- 8Fh
MOVLW
MOVWF
MOVLW
MOVWF
0x83
delay_reg1
0xFF
delay_reg2
loop1 DECFSZ
GOTO
GOTO
loop2 DECFSZ
GOTO
GOTO
delay_reg1
loop2
exit1
delay_reg2
loop2
loop1
; delay 100 ms
exit1 CLRF
PORTB
; xoa PORTB
loop
MOVLW
MOVWF
MOVLW
MOVWF
0x83
delay_reg1
0xFF
delay_reg2
loop3 DECFSZ
GOTO
GOTO
loop4 DECFSZ
GOTO
GOTO
exit2
GOTO
delay_reg1
loop4
exit2
delay_reg2
loop4
loop3
; delay 100 ms
loop
; vong lap vo han
END
Vi chng trnh nay cac pin cua PORTB se thay oi trang thai sau moi khoang thi
gian delay la 100 ms. ieu nay cho phep ta nhan thay bang mat thng v trong mot giay cac
pin cua PORTB se thay oi trang thai 10 lan.
Tuy nhien ta de dang nhan thay mot nhc iem cua chng trnh tren la can ti hai
oan chng trnh delay vi cau truc chng trnh, thuat toan va chc nang hoan toan giong
nhau. ieu nay lam cho chng trnh tr nen phc tap va ton nhieu dung lng bo nh cua vi
ieu khien. ieu nay can c chu trong v dung lng bo nh chng trnh cua mot vi ieu
khien thng nho (oi vi PIC16F877A dung lng bo nh chng trnh la 8K word vi mot
word la 14 bit). Mot phng phap e khac phuc nhc iem nay la s dung chng trnh con
va dung lenh CALL e goi chng trnh con o. Chng trnh con co the c at tai bat
c v tr nao trong chng trnh chnh. Chng trnh 4.2 khi o c viet lai nh sau:
;chng trnh 4.1.3
;PORTBTESTANDDELAY.ASM
;Version 1.2
processor
include
16f877a
<p16f877a.inc>

delay_reg1
delay_reg2
start
loop
EQU 0x20
EQU 0x21
; khai bao a ch cac o nh cha cac thanh ghi

; delay-reg1 va delay-reg2
ORG
GOTO
0x000
start
BCF
BCF
STATUS,RP1
STATUS,RP0
CLRF
BSF
PORTB
STATUS,RP0
; xoa PORTB
; chon BANK1
MOVLW
MOVWF
0x00
TRISB
; PORTB <- outputs
BCF
STATUS,RP0
; chon BANK0
MOVLW
MOVWF
0x8F
PORTB
; gia tr bat k can a ra PORTB

; PORTB <- 8Fh
CALL
delay100ms
; goi chng trnh con delay100ms

; chon BANK0
CLRF
CALL
GOTO
PORTB
delay100ms
loop
; xoa PORTB
; vong lap vo han
Delay100ms
MOVLW
MOVWF
MOVLW
MOVWF
0x83
delay_reg1
0xFF
delay_reg2
loop1 DECFSZ
GOTO
GOTO
loop2 DECFSZ
GOTO
GOTO
Exit
RETURN
delay_reg1
loop2
exit
delay_reg2
loop2
loop1
; delay 100 ms
; tr ve chng trnh chnh
END
Vi cach viet chng trnh s dung chng trnh con, cau truc chng trnh se tr nen
gon gang de hieu hn, linh hoat hn va tiet kiem c nhieu dung lng bo nh chng trnh.
Bay gi ta se ban en mot thuat toan khac e viet chng trnh delay. Ve nguyen tac
th thuat toan mi nay khong co nhieu khac biet so vi thuat toan cu, tuy nhien lenh s dung
trong chng trnh va cach tnh toan thi gian delay th khac nhau. Chng trnh con
delay100ms vi oscillator 4 MHz co the c viet lai nh sau:
delay100ms
MOVLW
MOVWF
d1
MOVLW
MOVWF
MOVLW
MOVWF
delay_0
DECFSZ
GOTO
d100
count1
0xC7
counta
0x01
countb
counta,1
$+2
END
DECFSZ
GOTO
DECFSZ
GOTO
RETLW
countb,1
delay_0
count1,1
d1
0x00
Trc tien ta xet oan chng trnh ke t label delay_0. Lenh DECFSZ mat mot
chu k lenh (tr trng hp thanh ghi counta mang gia tr 0 th can 2 chu k lenh), lenh GOTO
$+2 mat hai chu k lenh. Lenh nay co tac dung cong vao bo em chng trnh gia tr 2, khi o
chng trnh se nhay ti lenh co a ch (PC+2), tc la lenh GOTO delay_0, lenh nay cung
ton hai chu k lenh. Nh vay ta can tong cong 5 chu k lenh e giam gia tr trong thanh ghi
counta 1 n v. Thanh ghi counta mang gia tr 199 (C7h), do o oan chng trnh nay se tao
ra mot khoang thi gian delay:
td = 5(counta+1)*ti = 5(199+1)*1 uS = 1 mS
Muon tao ra thi gian delay 100 mS, ta ch viec a gia tr 100 vao thanh ghi count1.
Vi giai thuat nay thi gian delay tao ra se dai hn so vi giai thuat ma ta s dung
chng trnh 4.2. Ben canh o ta co the viet mot chng trnh con co tac dung delay mot
khoang thi gian bat k la boi so cua 1 mS mot cach de dang.
Trong chng trnh tren ta con s dung them mot lenh kha la la lenh RETLW. Lenh
nay co tac dung tr ve v tr ma chng trnh con c goi va thanh ghi W khi o mang gia tr
la tham so cua lenh RETLW (00h). Trong trng hp nay thanh ghi W khong can mang mot
gia tr cu the khi quay tr ve chng trnh chnh nen lenh RETLW ch co tac dung nh lenh
RETURN.
4.1.2 MOT SO NG DUNG VE AC TNH I/O CUA CAC PORT IEU KHIEN
Da vao chng trnh delay va thao tac a d l ieu ra cac PORT, ta phat trien them
mot so chng trnh nho vi muc ch lam quen vi cach viet chng trnh cho vi ieu khien
PIC16F877A.
ng dung 4.1:
Da vao mach nguyen l hnh 4.1 viet chng trnh ieu khien LED chay. Cu the la
sau thi gian delay 250 ms, LED tiep theo se sang mot cach tuan t t tren xuong di.
Chng trnh nay c viet da vao chng trnh 4.3 vi mot vai thay oi nho. Thay
v a mot gia tr bat k ra PORT, ta a ra PORB gia tr 80h, sau o dch phai gia tr 80h sau
moi khoang thi gian delay (dung lenh RRF).
; Chng trnh 4.1.4
; Chng trnh ieu khien LED chay
processor
16f877a
include
<p16f877a.inc>
;-------------------------------------------------------------------------------------------------------------;Khai bao bien
;-------------------------------------------------------------------------------------------------------------count1
EQU 0x20
; dung cho chng trnh delay
counta
EQU 0x21
countb
EQU 0x22
start
loop
ORG
GOTO
0x000
start
BCF
BCF
CLRF
BSF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
CALL
RRF
GOTO
STATUS,RP1
STATUS,RP0
PORTB
STATUS,RP0
0x00
TRISB
STATUS,RP0
0x8F
PORTB
delay100ms
PORTB,1
loop
delay100ms
MOVLW
MOVWF
d1
MOVLW
MOVWF
MOVLW
d100
count1
0xC7
counta
0x01

; chon BANK0
; xoa PORTB
; chon BANK1
; PORTB <- outputs
; chon BANK0
; gia tr bat k can a ra PORTB
; PORTB <- 8Fh
; dch phai PORTB
; vong lap vo han
MOVWF
delay_0
DECFSZ
GOTO
DECFSZ
GOTO
DECFSZ
GOTO
RETLW
END
countb
counta,1
$+2
countb,1
delay_0
count1,1
d1
0x00
; delay 100ms
Nh vay da tren mot so chng trnh c ban, ta ch can thay oi mot so chi tiet la co
the tao ra mot ng dung mi.
Mot phng phap khac e viet chng trnh tren la dung bang d lieu. Phng phap
bang d lieu c a ra ay khong mang tnh chat toi u hoa giai thuat chng trnh ma
ch mang tnh chat lam quen vi mot giai thuat mi, qua o tao ieu kien thuan li hn trong
viec viet cac chng trnh ng dung phc tap hn sau nay. Ta co the viet lai chng trnh
tren theo phng phap bang d lieu nh sau:
; Chng trnh 4.1.5
; Chng trnh ieu khien LED chay dung bang d lieu
processor
16f877a
include
<p16f877a.inc>
count1
EQU 0x20
counta
EQU 0x21
countb
EQU 0x22
count
EQU 0x23
; dung e tra bang d lieu
ORG
GOTO
start
BCF
BCF
CLRF
BSF
MOVLW
MOVWF
0x000
start
STATUS,RP1
STATUS,RP0
PORTB
STATUS,RP0
0x00
TRISB

; chon BANK0
; xoa PORTB
; chon BANK1
; PORTB <- outputs
Loop1
Loop2
BCF
STATUS,RP0
; chon BANK0
CLRF
count
; reset thanh ghi cha gia tr em
MOVF
CALL
MOVWF
CALL
INCF
count, 0
Table
PORTB
delay100ms
count, 0
XORLW
BTFSC
GOTO
INCF
GOTO
d8
STATUS,Z
Loop1
count, 1
Loop2
; a gia tr em vao thanh ghi W

; goi chng trnh con Table
; xuat gia tr cha trong thanh ghi W ra PORTB
; tang gia tr than ghi count va cha ket qua trong
; thanh ghi W
; so sanh thanh ghi W vi gia tr 8
; kiem tra bit Z (Zero)
; nhay ve label Loop1 neu W = 0
; thc thi lenh nay neu W khac 0
ADDWF
PCL,1
Table
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
delay100ms
MOVLW
MOVWF
d1
MOVLW
MOVWF
MOVLW
MOVWF
delay_0
DECFSZ
GOTO
DECFSZ
GOTO
DECFSZ
GOTO
; cong g tr thanh ghi W vao thanh ghi PCL, ket

; qua cha trong thanh ghi PCL
b10000000
b01000000
b00100000
b00010000
b00001000
b00000100
b00000010
b00000001
d100
count1
0xC7
counta
0x01
countb
counta,1
$+2
countb,1
delay_0
count1,1
d1
; delay 100ms
END
RETURN

phan trc ta a tng e cap en lenh RETLW nhng khi o lenh nay ch co tac
dung nh lenh RETURN. Tuy nhien trong trng hp nay lenh RETLW co mot vai tro cu the
hn la mang d lieu t bang d lieu tr ve chng trnh chnh va xuat ra PORTB d lieu va
mang ve o. Sau moi lan mang d lieu ve bien count se tang gia tr em len. Gia tr em
c a vao thanh ghi W e cong vao thanh ghi PCL. Thanh ghi PCL la thanh ghi cha gia
tr bo em chng trnh, gia tr t bien count c cong vao thanh ghi PCL thong qua thanh
ghi W se ieu khien chng trnh nhay ti ung a ch can lay d lieu t bang d lieu vao
thanh ghi W va thanh ghi W mang d lieu o tr ve chng trnh chnh trong qua lenh
RETLW.
e e phong trng hp gia tr bien count cong vao thanh ghi PCL se ieu khien
chng trnh en v tr vt qua v tr cua bang d lieu (trng hp nay xay ra khi bien count
mang gia tr ln hn 8, khi o v tr lenh can thc thi do bo em chng trnh ch en khong
con ung na), ta so sanh bien count vi gia tr 8. Neu bien count mang gia tr 8 th phep toan
XOR gia bien cao va gia tr se co ket qua bang 0 va c Z trong thanh ghi STATUS se c
set. Luc nay ta can reset lai bien count bang cach nhay ve label Loop1.
Viec dung bang d lieu trong trng hp nay lam cho chng trnh tr nen dai hn,
qua trnh thc thi chng trnh lau hn v bo em chng trnh lien tuc b thay oi gia tr, tuy
nhien ta cung thay c mot u iem cua viec dung bang d lieu la cho phep ta sap xep bo
tr d lieu mot cach linh hoat. Dieu nay the hien qua viec ch can thay oi d lieu trong bang
d lieu, ta se co c nhieu cach ieu khien cac LED sang hay tat theo nhieu qui luat khac
nhau ch khong ch n thuan la dch LED sang sang trai hoac sang phai. ng dung sau ay
cho ta thay ro hn hieu qua cua bang d lieu.
ng dung4 2: Tng t nh ng dung 1, nhng lan nay ta cho LED chay t v tr gia
sang hai pha sau moi khoang thi gian delay 100 ms.
Chng trnh cho ng dung nay hoan toan tng t nh trong ng dung, ta ch can thay
oi bang d lieu mot cach thch hp.
; Chng trnh 4.1.6
; Chng trnh ieu khien hien th LED
processor
16f877a
include
<p16f877a.inc>

;----------------------------------------------------------------------------------------------;Khai bao bien
;----------------------------------------------------------------------------------------------count1
EQU 0x20
counta
EQU 0x21
countb
EQU 0x22
count
EQU 0x23
; dung e tra bang d lieu
start
Loop1
Loop2
Table
ORG
GOTO
0x000
start
BCF
BCF
CLRF
BSF
MOVLW
MOVWF
BCF
STATUS,RP1
STATUS,RP0
PORTB
STATUS,RP0
0x00
TRISB
STATUS,RP0
; PORTB <- outputs

; chon BANK0
CLRF
count
; reset thanh ghi cha gia tr em
MOVF
CALL
MOVWF
CALL
INCF
count, 0
Table
PORTB
delay100ms
count, 0
XORLW
BTFSC
GOTO
INCF
GOTO
d8
STATUS,Z
Loop1
count, 1
Loop2
; a gia tr em vao thanh ghi W

; goi chng trnh con Table
; xuat gia tr cha trong thanh ghi W ra PORTB
; tang gia tr than ghi count va cha ket qua trong
; thanh ghi W
; so sanh thanh ghi W vi gia tr 8
; kiem tra bit Z (Zero)
; nhay ve label Loop1 neu W = 0
; thc thi lenh nay neu W khac 0
ADDWF
PCL,1
RETLW
RETLW
RETLW
b00011000
b00100100
b01000010

; chon BANK0
; xoa PORTB
; chon BANK1
; cong g tr thanh ghi W vao thanh ghi PCL, ket

; qua cha trong thanh ghi PCL
RETLW
RETLW
RETLW
RETLW
RETLW
b10000001
b01000010
b00100100
b00011000
b00100100
delay100ms
MOVLW
MOVWF
d1
MOVLW
MOVWF
MOVLW
MOVWF
delay_0
DECFSZ
GOTO
DECFSZ
GOTO
DECFSZ
GOTO
RETURN
END
d100
count1
0xC7
counta
0x01
countb
counta,1
$+2
countb,1
delay_0
count1,1
d1
; delay 100ms
ng dung 4.3: Test chc nang Input/Output cua cac pin cua vi ieu khien.
cac ng dung trc ta ch lam mot viec la xuat tn hieu ieu khien ra cac PORT
theo mot so qui tac nh san nao o. Trong ng dung nay ta se phat trien them mot chc
nang na cua cac PORT la kha nang nhan tn hieu ieu khien t ben ngoai. Vi ieu khien se
oc tn hieu 0 (ien ap 0 V) va 1 (ien ap 5 V) c tao ra bang cach s dung cac cong tac
an t cac pin RB0:RB3 cua PORTB , sau o kiem tra xem cong tac nao c an va bat LED
tng ng vi cong tac o (cac LED nay c bo tr cac pin RB7:RB4) sang len. e kiem
tra c ng dung nay ta can xay dng s o mach nh sau:
HI
HI
R8 R7 R6 R5
R9
U1
2
3
4
5
6
7
SW5
8
9
10
HI
0
4 MHz
11
12
13
14
15
16
17
18
19
20
RB7/PGD
RB6/PGC
RB5
RA0/AN0
RB4
RA1/AN1
RB2
RA3/AN3/VREF+
RB1
RA4/T0CLK/C1OUT
RB0/INT
RA5/AN4/SS/C20UT
MCLR/VPP
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
GND
OSC1/CLK
OSC2/CLKOUT
VDD
GND
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC1/T1OSI/CCP2
RC6/TX/CK
RC2/CCP1
RC5/SDO
RC3/SCK/SCL
RC4/SDI/SDA
RD0/PSP0
RD1/PSP1
RD3/PSP3
RD2/PSP2
R1
40
39
38
37
36
35
34
33
32
31
R2
D1
D2
D3
R3
D4
R4
HI
SW1
30
29
28
27
0
SW2
SW3
26
25
24
23
SW4
22
21
PIC16F877A
Hnh 4.2 Mach test chc nang I/O cho ng dung 3.

Chng trnh viet cho ng dung nay nh sau:
;Chng trnh 4.1.7
processor
16f877a
include
<p16f877a.inc>
;-------------------------------------------------------------------------------------------------------------;Khai bao hang
;-------------------------------------------------------------------------------------------------------------SW1
EQU
0
SW2
EQU
1
SW3
EQU
2
SW4
EQU
3
LED1
EQU
4
LED2
EQU
5
LED3
LED4
start
loop
EQU
EQU
ORG
GOTO
6
7
0x000
start
BCF
STATUS,RP1
BCF
STATUS,RP0
CLRF PORTB
BSF
STATUS,RP0
MOVLW
b'00001111'
MOVWF
BCF
TRISB
STATUS,RP0
BTFSS
CALL
BTFSS
PORTB,SW1
switch1
PORTB,SW2
CALL
BTFSS
CALL
BTFSS
CALL
GOTO
switch1
CLRF
BSF
RETURN
switch2
CLRF
BSF
RETURN
switch3
CLRF
BSF
RETURN
switch4
CLRF
switch2
PORTB,SW3
switch3
PORTB,SW4
switch4
loop
PORTB
PORTB,LED1
PORTB
PORTB,LED2
PORTB
PORTB,LED3
PORTB
; thiet lap chc nang I/O cho tng pin trong

;PORTB
; kiem tra cong tac 1

; thc thi lenh nay neu cong tac 1 c an
; neu cong tac ; 1 khong c an, kiem tra cong
; tac 2
; tiep tuc qua trnh oi vi cac cong tac con lai
BSF
RETURN
PORTB,LED4
END
Trong chng trnh tren ta ng dung thuat toan hoi vong thong qua vong lap loop
trong phan chng trnh chnh. Khi cong tac khong c nhan, mc logic tai cac pin noi vi
cong tac la mc 1. Khi cong tac c an, cac pin tren sem nh noi at va mang mc logic 0.
Ta ch viec kiem tra lien tuc trang thai logic cua cac pin o va bat LED tng ng vi cong
tac thong qua cac chng trnh con switch1, switch2, switch3 va swtich4 khi phat hien mot
cong tac nao o c an. Tuy nhien can chu y la phai thiet lap trang thai I/O thch hp cho
tng pin trong PORTB (thiet lap RB3:RB0 la input, RB7:RB4 la output).
Mot iem quan trong can lu y la cac cong tac an thng b doi, tc la khi an xuong
hoac tha ra, ien ap tai cac cong tac se phai trai qua mot giai oan qua o, ien ap se dao
ong khong on nh trong mot khoang thi gian nao o, ngoai ra trang thai logic cua pin cung
se thay oi do mot tac ong tc thi t mot trng ben ngoai ma khong phai do ta an cong
tac. Cac yeu to tren se lam anh hng ti hoat ong cua vi ieu khien. e khac phuc nhc
iem tren ta co hai phng phap:
Phng phap chong doi bang phan cng: ta them cac tu ien vao cac cong tac e
loc bt cac tn hieu nho gay nhieu va cac tn hieu khong on nh trong thi gian qua o.
Phng phap nay cung hieu qua nhng gay ton kem ve linh kien va mach nguyen l tr nen
phc tap.
Phng phap chong doi bang phan mem: ta cho vi ieu khien delay trong mot thi
gian ngan va kiem tra xem cong tac con c an khong, neu cong tac thc s con c an
th mi tien hanh cac thao tac tng ng vi cong tac o.
Chng trnh cai tien e khac phuc nhc iem tren co the c viet nh sau:
;Chng trnh 4.1.8
processor
16f877a
include
<p16f877a.inc>
;-------------------------------------------------------------------------------------------------------------;Khai bao hang
;-------------------------------------------------------------------------------------------------------------SW1
EQU
0
SW2
EQU
1
SW3
EQU
2
SW4
EQU
3
LED1
EQU
4
LED2
EQU
5
LED3
EQU
6
LED4
EQU
7
;-------------------------------------------------------------------------------------------------------------;Khai bao bien
;-------------------------------------------------------------------------------------------------------------count1
EQU
0x20
counta
EQU
0x21
countb
EQU
0x22
;-------------------------------------------------------------------------------------------------------------;Cac khai bao khac
;-------------------------------------------------------------------------------------------------------------SWdel
SET
del150
; gan SWdel vi label del150
;-------------------------------------------------------------------------------------------------------------;Chng trnh
;-------------------------------------------------------------------------------------------------------------ORG
0x000
GOTO
start
start
; v tr bat au chng trnh chnh
BCF
STATUS,RP1
BCF
STATUS,RP0
; chon BANK0
CLRF
PORTB
BSF
STATUS,RP0
; chon BANK1
MOVLW
b'00001111'
MOVWF
TRISB
BCF
STATUS,RP0
; chon BANK0
loop
; vong lap kiem tra cong tac nao c an
BTFSS
PORTB,SW1
; kiem tra SW1
CALL
switch1
; nhay ti chng trnh con switch1 neu
; SW1 c an
BTFSS
PORTB,SW2
; neu SW1 khong c an tiep tuc kiem tra
; SW2
CALL
switch2
; thao tac tng t nh SW1
BTFSS
PORTB,SW3
CALL
switch3
BTFSS
PORTB,SW4
CALL
switch4
GOTO
loop
switch1
CLRF
CALL
BTFSC
RETURN
led1_ON
BSF
BTFSC
RETURN
GOTO
switch2
CLRF
CALL
BTFSC
RETURN
led2_ON
BSF
BTFSC
RETURN
GOTO
switch3
CLRF
CALL
BTFSC
RETURN
led3_ON
BSF
BTFSC
RETURN
GOTO
switch4
CLRF
CALL
BTFSC
RETURN
led4_ON
BSF
PORTB
SWdel
PORTB,SW1
; xoa PORTB
; goi chng trnh delay del150
; kiem tra cong tac 1 con nhan hay khong
; neu khong con nhan th tr ve chng
; trnh chnh
PORTB,LED1
PORTB,SW1
; bat LED1 sang

; xac nhan lai trang thai cong tac 1
; tr ve chng trnh chnh neu cong tac
; khong con an
; tiep tuc gi LED1 sang neu cong tac con
; c an
; thao tac tng t vi cac cong tac con lai
led1_ON
PORTB
SWdel
PORTB,SW2
PORTB,LED2
PORTB,SW2
led2_ON
PORTB
SWdel
PORTB,SW3
PORTB,LED3
PORTB,SW3
led3_ON
PORTB
SWdel
PORTB,SW4
PORTB,LED4
BTFSC
PORTB,SW4
RETURN
GOTO
led4_ON
;--------------------------------------------------------------------------------------------------------------;Chng trnh delay cai tien cho phep nhieu khoang thi gian delay khac nhau
;--------------------------------------------------------------------------------------------------------------del0
RETURN
del1
MOVLW
d'1'
GOTO
delay
del5
MOVLW
d'5'
GOTO
delay
del10
MOVLW
d'10'
GOTO
delay
del20
MOVLW
d'20'
GOTO
delay
del50
MOVLW
d'50'
GOTO
delay
del100
MOVLW
d'100'
GOTO
delay
del150
MOVLW
d'150'
GOTO
delay
del200
MOVLW
d'200'
GOTO
delay
delay
MOVWF
count1
d1
; tao thi gian delay 1 mS
MOVLW
0xC7
MOVWF
counta
MOVLW
0x01
MOVWF
countb
delay_0
DECFSZ
counta,1
END
GOTO $+2
DECFSZ
GOTO
DECFSZ
GOTO
RETURN
countb,1
delay_0
count1,1
d1
Vi chng trnh tren, thi gian an cong tac phai lau hn thi gian delay c ch nh
bi hang so SWdel do cong tac se c kiem tra lai trang thai sau thi gian delay . Neu thi
gian an cong tac khong at yeu cau, thao tac bat LED tng ng vi cong tac o sang len se
khong c thc hien va vi ieu khien se tiep tuc qua trnh kiem tra trang thai cac cong tac
con lai.
Thi gian delay can c kiem nh bang thc nghiem va c an nh mot cach thch
hp e chong doi mot cach hieu qua, ong thi cung khong c lau qua, nh vay se gay
s kho chu trong viec s dung cong tac do phai an cong tac trong mot khoang thi gian u
lau.
Viec thay oi thi gian delay trong chng trnh co the c thc hien n gian bang
cach thay oi label cua chng trnh delay gan cho tham so SWdel. Thc ra ta co the trc
tiep a tham so thi gian delay trc tiep vao thanh ghi count1 ma khong can thong qua tham
so SWdel, ieu o lam cho chng trnh tr nen dai va phc tap hn. Tuy nhien chng trnh
tren cung a cho ta thay c mot iem khac biet gia lenh EQU va lenh SET, giup ta
hieu ro hn va s dung mot cach thch hp cac lenh tren trong cac ng dung khac.
ng dung 4. 4: ng dung tong hp.
Trong ng dung nay ta se tap hp lai tat ca cac k nang c s dung trong cac ng
dung trc. Yeu cau at ra cung nh ng dung 3, tuy nhien ben canh viec bat LED tng ng
vi cong tac sang len, ta phai tiep tuc thc hien mot thao tac na la ra lenh cho vi ieu khien
hien th 8 LED c gan vao PORTD theo mot th t tng ng. Cu the nh sau:
An SW1: LED1 sang, 8 LED PORTD chay t trai sang phai (LED sang chay).
An SW2: LED2 sang, 8 LED PORTD chay t trai sang phai (LED tat chay).
An SW3: LED3 sang, 8 LED PORTD chay t trai sang phai (2 LED sang chay).
An SW4: LED4 sang, 8 LED PORTD chay t trai sang phai (2 LED tat chay).
e test c ng dung nay, ta can phat trien them mach test cua ng dung 3 bang
cach them vao 8 LED PORTD thong qua cac ien tr. Cu the nh sau:
HI
HI
R9
R8 R7 R6 R5
U1
2
3
4
5
6
7
SW5
8
9
10
HI
0
4 MHz
11
12
13
14
15
16
17
18
19
20
MCLR/VPP
RB7/PGD
RB6/PGC
RA0/AN0
RB5
RA1/AN1
RB4
RA3/AN3/VREF+
RB2
RA4/T0CLK/C1OUT
RB1
RA5/AN4/SS/C20UT
RB0/INT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
GND
OSC1/CLK
OSC2/CLKOUT
VDD
GND
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC1/T1OSI/CCP2
RC6/TX/CK
RC2/CCP1
RC5/SDO
RC3/SCK/SCL
RC4/SDI/SDA
RD0/PSP0
RD1/PSP1
RD3/PSP3
RD2/PSP2
R1
40
39
38
37
36
35
34
33
D1
R2
D2
R3
D3
R4
D4
SW1
32
31
SW2
HI
SW3
30
29
28
27
SW4
26
25
24
23
22
21
PIC16F877A
0.33 K
D5
0.33 K
D6
0.33 K
D7
0.33 K
D8
0.33 K
D9
0.33 K
D10
0.33 K
D11
0.33 K
D12
Hnh 4.3 Mach test ng dung 4.

Chng trnh viet cho mach test nay cung tng t nh ng dung 3 nhng c them
vao phan hien th LED PORTD. Ta s dung thuat toan bang d lieu e hien th LED.
Chng trnh cu the nh sau:
;Chng trnh 4.1.9
processor
16f877a
include
<p16f877a.inc>
;--------------------------------------------------------------------------------------------------------------;Khai bao cac hang so
;--------------------------------------------------------------------------------------------------------------SW1
EQU
0
SW2
EQU
1
SW3
EQU
2
SW4
EQU
3
LED1
EQU
4
LED2
EQU
5
LED3
EQU
6
LED4
EQU
7
;---------------------------------------------------------------------------------------------------------------;Khai bao bien
;---------------------------------------------------------------------------------------------------------------count
EQU
0x20
; bien dung cho qua trnh dch LED
count1
EQU
0x21
; cac bien dung cho chng trnh delay
counta
EQU
0x22
countb
EQU
0x23
;---------------------------------------------------------------------------------------------------------------;Chng trnh
;---------------------------------------------------------------------------------------------------------------ORG
0x000
GOTO
start
start
; v tr bat au chng trnh chnh
BCF
STATUS,RP1
BCF
STATUS,RP0
; chon BANK0
CLRF
PORTB
CLRF
PORTD
BSF
STATUS,RP0
; chon BANK1
MOVLW
b'00001111'
MOVWF
TRISB
MOVLW
0x00
MOVWF
TRISD
BCF
STATUS,RP0
; chon BANK0
loop1
CLRF
count
; reset bien count
CALL
check_key
; goi chng trnh con check_key
loop2
MOVF
count,W
; a ga tr bien count vao thanh ghi W
BTFSC
PORTB,LED1
; kiem tra trang thai bit LED1
CALL
table1
; goi chng trnh con table1 neu bit
; LED1 mang gia tr bang 1
BTFSC
PORTB,LED2
; tiep tuc kiem tra bit LED2 neu bit LED1 bang 0
CALL
table2
; thao tac tng t vi cac bit ch th trang thai cac
; SW con lai
BTFSC
PORTB,LED3
CALL
table3
table1
BTFSC
CALL
MOVWF
PORTB,LED4
table4
PORTD
CALL
INCF
XORLW
BTFSC
GOTO
delay
count,0
d'14'
STATUS,Z
loop1
INCF
count,1
GOTO
loop2
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
PCL,f
b'10000000'
b'01000000'
b'00100000'
b'00010000'
b'00001000'
b'00000100'
b'00000010'
b'00000001'
b'00000010'
b'00000100'
b'00001000'
b'00010000'
b'00100000'
b'01000000'
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
PCL,f
b'01111111'
b'10111111'
b'11011111'
b'11101111'
b'11110111'
b'11111011'
b'11111101'
b'11111110'
table2
; a gia tr t thanh ghi W sau khi quay tr ve t

; bang d lieu ra PORTD
; goi chng trnh con delay
; tang gia tr bien count e kiem tra
; so sanh bien count vi gia tr 14
; kiem tra c Z (Zero)
; nhay ti label loop1 neu Z bang 1 (gia tr
; bien count bang 14)
; tang gia tr bien count neu Z bang 0 (gia tr
; bien count khong bang 14)
; sau o nhay ti label loop2
; cac bang d lieu dung cho phan dch LED
table3
table4
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
b'11111101'
b'11111011'
b'11110111'
b'11101111'
b'11011111'
b'10111111'
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
PCL,f
b'11000000'
b'01100000'
b'00110000'
b'00011000'
b'00001100'
b'00000110'
b'00000011'
b'00000011'
b'00000110'
b'00001100'
b'00011000'
b'00110000'
b'01100000'
b'11000000'
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
PCL,f
b'00111111'
b'10011111'
b'11001111'
b'11100111'
b'11110011'
b'11111001'
b'11111100'
b'11111100'
b'11111001'
b'11110011'
b'11100111'
b'11001111'
b'10011111'
check_key
; chng trnh con check_key kiem tra trang thai
BTFSS
CALL
BTFSS
CALL
BTFSS
CALL
BTFSS
CALL
RETURN
switch1
CLRF
BSF
RETURN
switch2
CLRF
BSF
RETURN
switch3
CLRF
BSF
RETURN
switch4
CLRF
BSF
RETURN
delay
PORTB,SW1
switch1
PORTB,SW2
switch2
PORTB,SW3
switch3
PORTB,SW4
switch4
PORTB
PORTB,LED1
PORTB
PORTB,LED2
PORTB
PORTB,LED3
PORTB
PORTB,LED4
MOVLW
MOVWF
d'250'
count1
MOVLW
MOVWF
MOVLW
MOVWF
delay_0
DECFSZ
GOTO
DECFSZ
GOTO
0xC7
counta
0x01
countb
d1
; cac SW, sau o bat LED tng ng vi SW o

; sang neu SW o c an. Trang thai cac LED
; co tac dung nh cac bit c hieu khi xac nh thao
; tac dch LED tng ng vi SW c an
counta,1
$+2
countb,1
delay_0
; chng trnh delay mot khoang thi gian 250 ms
END
DECFSZ
GOTO
RETURN
count1,1
d1
Trong chng trnh nay ta li dung cac bit trang thai cua cac LED e dung nh cac c
hieu e xac nh thao tac dch LED tng ng vi SW c nhan trong vong lap loop1 va
loop2. Cac thuat toan nh bang d lieu, kiem tra trang thai cong tac, eu a c e cap
en cac phan trc, van e at ra trong chng trnh nay ch la sap xep va to chc hp l
th t cac thao tac va cac thuat toan. Tuy nhien neu oc k chng trnh tren ta se phat hien
mot iem bat hp l v tr at lenh CALL check_key. Neu at v tr nh chng trnh
tren, vi ieu khien se ch kiem tra cac SW ngay tai thi iem ket thuc qua trnh dch LED.
Nh vay muon thay oi thao tac quet LED ta phai an SW ung ngay tai thi iem o, ieu
nay gay nhieu kho khan va tao s bat hp l so vi thc te. e khac phuc ta ch viec at lenh
o vao trong vong lap loop2, khi o trang thai cac SW se c cap nhat thng xuyen hn
sau moi lan dch LED ma khong phai ch cho en khi ket thuc mot qua trnh dch LED.
Ti giai oan nay xem nh ta ket thuc nhng thao tac n gian nhat khi s dung vi
ieu khien PIC16F877A. Trong phan nay ta ch s dung duy nhat vi ieu khien PIC va cac
PORT I/O e xay dng cac ng dung. Ke t phan sau ta se ket hp vi ieu khien PIC vi cac
thiet b ngoai vi khac e phat huy toi a kha nang cua vi ieu khien.
4.2 VI IEU KHIEN PIC16F877A VA IC GHI DCH 74HC595
Muc ch s dung IC 74HC595 la nang cao so lng pin output cua vi ieu khien.
Thay v phai truy xuat trc tiep mot gia tr nao o ra cac PORT I/O, ta co the truy xuat gian
tiep thong qua IC 74HC595. Tuy nhien viec trc tien la phai tm hieu xem IC 74HC595 hoat
ong nh the nao va cach ieu khien no ra sao. Hnh sau la s o khoi cua IC:
Hnh 4.4 S o khoi IC 74HC595

Thc chat ay la IC ghi dch vi 8 bit ngo ra QH:QA vi chot d lieu 8 bit. D lieu ch
c a vao qua 1 pin SER va c ieu khien bi cac pin RCK (pin ieu khien chot d
lieu), SCK (pin ieu khien viec dch d lieu vao IC thong qua cac xung clock),
(pin tac
ong mc thap dung e xoa d lieu) va pin QH (pin a d lieu noi tiep ra ngoai, pin nay
dung e noi nhieu IC 74HC595 lai vi nhau) va pin
(pin cho phep ngo ra). Ta co the ieu
khien mot IC 74HC595 hoac nhieu IC ghep vi nhau thong qua 4 pin RCK, SCK, SER va
. ieu nay cho phep m rong mot cach vo han so lng pin output cho vi ieu khien,
tat nhien vi mot nhc iem la thi gian truy xuat cham do d lieu phai c dch tng bit
vao IC thong qua tng canh dng tac ong vao pin SCK trc khi a d lieu ra ngoai
thong qua cac pin QH:QA. Sau ay la s o chan va bang s that cua IC 74HC595:
Hnh 4.6 S o chan va bang s that cua 74HC595

Hnh sau the hien cach noi nhieu IC 74HC595 lai vi nhau:
DATA IN
RCK
SCK
VCC
DATA OUT
Hnh 4.7 Cach noi nhieu IC 74HC595
14
9
7
6
5
4
3
2
1
15
0
7
6
5
4
3
2
1
15
SDI
11
12
74HC595
QH
QG
QF
QE
QD
QC
QB
QA
GND
SDO
74HC595
SRCLK
RCLK
13
10
G
CLR
11
12
14
SDI
16
SDO
GND
SRCLK
RCLK
VCC
QH
QG
QF
QE
QD
QC
QB
QA
G
CLR
16
HI
HI
13
10
CLR
Nh ta thay trong hnh tren, cac pin SCK, RCK va

c noi chung lai vi nhau,
trong khi pin SDO cua IC trc se noi vi pin SDI cua IC sau. Tat ca cac IC nay se c ieu
khien thong qua 4 pin SCK,RCK,
va SDI, nh vay ta co the tiet kiem c mot so
lng ang ke so lng pin ieu khien cua vi ieu khien.
Cach ieu khien IC c the hien thong qua bang s that hnh 4.6. Trc tien a 1
bit d lieu vao pin SDI, tao ra mot canh dng pin SCK e dch bit d lieu o vao, qau
trnh nay lap i lap lai lien tuc cho en khi toan bo d lieu c dch vao cac IC 74HC595
(IC tiep theo cung se dch d lieu c a ra thong qua pin SDO cua vi ieu khien trc).
Sau o tao mot canh dng pin RCK e a d lieu t chot d lieu ra cac pin output. ng
dung sau giup ta hieu ro hn cach ieu khien cac IC 74HC595.
ng dung 4.5: IC 74HC595 va cach ieu khien.
Trong ng dung nay ta se a d mot lieu 8 bit bat k ra thong qua IC 47HC595. D
lieu se c kiem tra thong qua cac LED c gan vao cac pin output cua IC. Cac pin ieu
khien cua 74HC595 c gan vao cac pin RB3:RB0 cua PORTB. Cu the nh sau:
Pin RB0: noi vi pin SDI
Pin RB1: noi vi pin SCK
Pin RB2: noi vi pin
Pin RB3: noi vi pin RCLK
Cac th t nay khong bat buoc phai c tuan thu mot cach nghiem ngat, tuy theo
mach phan cng ma ta co s ieu chnh tng ng trong phan mem. Ngoai ra ta co the s
dung bat c pin nao cua PORT I/O nao e ieu khien IC nay.
Mach test cho ng dung nay c thiet ke nh sau:
HI
10 K
U1
HI
0
4 MHz
11
12
13
14
15
16
17
18
19
20
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
GND
PIC16F877A
OSC1/CLK
OSC2/CLKOUT
VDD
GND
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC1/T1OSI/CCP2
RC6/TX/CK
RC2/CCP1
RC5/SDO
RC3/SCK/SCL
RC4/SDI/SDA
RD0/PSP0
RD1/PSP1
RD3/PSP3
RD2/PSP2
14
32
31
12
11
10
13
30
29
28
27
26
25
24
23
16
U3
VCC
8
9
10
40
39
38
37
36
35
34
33
SDI
RCLK
SRCLK
SDO
QA
QB
QC
QD
CLR
G 74HC595 QE
QF
QG
QH
GND
RB7/PGD
RB6/PGC
RA0/AN0
RB5
RA1/AN1
RB4
RA3/AN3/VREF+
RB2
RA4/T0CLK/C1OUT
RB1
RA5/AN4/SS/C20UT
RB0/INT
0.33 K
D1
0.33 K
D2
9
15
1
2
3
4
5
6
7
0.33 K
D3
0.33 K
D4
0.33 K
D5
0.33 K
D6
0.33 K
D7
0.33 K
D8
SW5
MCLR/VPP
HI
2
3
4
5
6
7
HI
22
21
Hnh 4.8 Mach test vi ieu khien PIC16F877A va IC 74HC595.
Sau ay la chng trnh viet cho ng dung nay:

; Chng trnh 4.2.1
;Chng trnh test IC ghi dch 74HC595
;----------------------------------------------------processor
16f877a
include
<p16f877a.inc>
;------------------------------------------------------------------------------------------------------------; Khai bao bien
;------------------------------------------------------------------------------------------------------------sendreg
EQU
0X20
; cha d lieu can xuat ra IC 74HC595
count
EQU
0X21
; dung e em so bit d lieu c gi ra
;------------------------------------------------------------------------------------------------------------;nh ngha phan cng
;------------------------------------------------------------------------------------------------------------#define
data PORTB,0
#define
clock PORTB,1
#define
clear PORTB,2
#define
latch PORTB,3
;------------------------------------------------------------------------------------------------------------; Chng trnh chnh
;------------------------------------------------------------------------------------------------------------ORG
0x000
GOTO
start
start
; chng trnh chnh
BCF
STATUS,RP1
BCF
STATUS,RP0
; chon BANK0
CLRF
PORTB
BSF
STATUS,RP0
; chon BANK1
MOVLW
0xF0
; cac pin RB3:RB0 la output
MOVWF
TRISB
; cac pin RB7:RB4 la input
BCF
STATUS,RP0
; chon BANK0
MOVLW
0x04
MOVWF
BCF
NOP
PORTB
clear
len mc logic cao

; a pin
; reset d lieu trong IC 74HC595
; clear tac ong canh xuong
BSF
MOVLW
clear
0xCA
; a pin
tr ve mc logic cao
; d lieu can a ra IC 74HC595
CALL
BSF
NOP
BCF
GOTO
serout
MOVWF
MOVLW
MOVWF
testbit
END
serout
latch
; goi chng trnh con serout

; tao canh dng tai pin RCK e a d
; lieu ra cac pin output cua IC 74HC595
; a pin RCK tr ve mc logic thap
; chng trnh b treo tai ay
latch
$
sendreg
0x08
count
BCF
BTFSC
BSF
BSF
NOP
data
sendreg,7
data
clock
BCF
RLF
MOVWF
DECFSZ
GOTO
clock
sendreg,0
sendreg
count,1
testbit
RETURN
; a d lieu vao thanh ghi sendreg

; em 8 bit d lieu
; d lieu mac nh bang 0

; sendreg,7 == 0 ??
; neu khong bang 0, set d lieu t 0 -> 1
; tao canh dng tai pin SCK e dch d
; lieu vao IC 74HC595
; a pin SCK ve lai mc logic thap
; dch trai thanh ghi sendreg
; giam bien count 1 n v
; neu bien count cha bang 0, tiep tuc qua
; trnh dch d lieu
; tr ve chng trnh chnh neu count = 0
iem ang chu y nhat cua chng trnh tren la thuat toan xac nh gia tr bit d lieu
can dich vao IC 74HC595. Ban au ng d lieu (SDI) se c mac nh la mc logic 0, sau
o ta kiem tra bit d lieu o (bit th 7 trong thanh ghi sendreg) xem co thc s bang 0 hay
khong. Neu bang 1 th ta set ng d lieu len mc logic 1. Nh vay ta lan lt kiem tra mc
logic cua cac bit d lieu can a vao IC 74HC595 va set/clear ng d lieu SDI tng ng
vi bit d lieu can dch. Viec con lai la tao canh dng tai pin SCK e a trang thai logic
cua ng d lieu SDI vao trong IC 74HC595. Nh vay sau 8 lan dch, 8 bit d lieu cha
trong thanh ghi sendreg a c a vao thanh ghi dch ben trong IC, va e a d lieu o ra
cac pin output QH:QA, ta ch viec tao mot canh dng tai pin RCK, d lieu trong thanh ghi
sendreg se c the hien bang cac trang thai sang/tat cua cac LED gan vao IC 74HC595, tat
nhien vi ieu kien pin
phai c noi mass hoac c a ve mc logic 0.
Mot ieu can lu y na la canh tac ong cua pin
. Do canh tac ong cua pin nay
la canh am nen can co s ieu chnh thch hp e co the ieu khien IC 74HC595 mot cach
ung an.
Trong trng hp noi nhieu IC 74HC595 lai vi nhau th thuat toan hoan toan tng
t, tuy nhien d lieu se lan lt a vao thanh ghi sendreg va goi chng trnh con serout.
Qua trnh nay c lap lai cho en khi toan bo d lieu a c a vao cac IC, sau o mi
a d lieu ra ngoai bang cach tao mot canh dng tai pin RCK.
4.3 PIC16F877A VA LED 7 OAN
LED 7 oan la mot cong cu thong dung c dung e hien th cac thong so di dang
cac so t 0 en 9. Mac du cong cu LCD giup ta the hien cac thong so mot cach linh ong hn
nhng LED 7 oan van c s dung nhieu trong cong nghiep do cac u the cua no nh
chu s anh hng cua nhiet o, de nhan ra va goc nhn rong.
LED 7 oan bao gom 7 oan LED c anh dau la cac k t a,b,c,d,e,f,g va mot dau
cham thap phan k hieu la dp. Nh vay ta co the xem LED 7 oan la mot to hp gom 8 LED
c bo tr theo mot qui tac nhat nh dung e hien th cac ch so thap phan.
Co hai loai LED 7 oan, o la loai Anode chung (cc Anode cua cac LED c noi
chung vi nhau) va loai Cathode chung (Cc Cathode cua cac LED c noi chung vi
nhau). Tuy theo tng loai ma ta co the ieu khien cac LED trong to hp o sang tat mot cach
thch hp. oi vi loai Anode chung, mot LED se sang neu mc logic a vao pin ieu khien
LED o la mc 0. . oi vi loai Cathode chung, mot LED se sang neu mc logic a vao pin
ieu khien LED o la mc 1.
Hnh 4.9 LED 7 oan.

Hnh ve tren la mot LED 7 oan loai Cathode chung. Thc ra cau truc cac pin cua
LED 7 oan co the thay oi tuy theo loai ch khong co nh, va cach duy nhat e xac nh
chnh xac cac pin ieu khien cua LED 7 oan la phai kiem tra tng pin cua LED o. Da vao
hnh ve ta co the hieu c mot phan nao cach hien th cua LED 7 oan. V du, muon hien
th so 6 ta se cho cac oan LED a, c, d, e, g, f sang va oan LED b tat. Viec ieu khien sang
tat c thc hien bang cach a d lieu thch hp vao cac pin a, b, c, d, e, f, g va dp cua
LED 7 oan. o la cach hien th theo tng LED, tuy nhien trong thc te e tiet kiem so pin
can thiet e ieu khien mot luc nhieu LED 7 oan, cac pin a, b, c, d, e, f, g va dp se c noi
song song vi nhau, cac pin Anode chung hoac Cathode chung c dung e cho phep LED 7
oan o sang hay tat. S d ta noi chung cac pin a, b, c, d, e, f, g va dp lai vi nhau c la
da vao hien tng lu anh cua mat. Mat ngi ch co kha nang nhan c 24 hnh anh trong
mot giay, do o khi cac LED 7 oan chp tat vi mot toc o qua nhanh nh toc ot x l cua
mot vi ieu khien th mat ngi khong co kha nang phat hien ra. Bang cach o neu ta lan
lt cho tng LED 7 oan sang trong mot khoang thi gian rat ngan nao o th mat ngi se
b anh la rang tat ca cac LED ang sang cung mot luc.
e hieu them ve cach hien th va thuat toan dung e hien th LED 7 an, ta se thc
hien mot ng dung n gian la hien th 2 LED 7 oan.
ng dung 4.6: Hien th LED 7 oan.
Trong ng dung nay ta se hien th mot so co 2 ch so tren 2 LED.
Loai LED 7 oan ta se s dung la loai Anode chung. Trc het ta can xac nh trc
s o noi chan gia vi ieu khien va cac LED 7 oan e t o xac nh c d lieu can a
vao e ieu khien LED 7 oan hien th mot ch so thap phan nao o. Gia s ta noi cac pin
d lieu cua LED 7 oan vao PORTD cua PIC16F877A theo th t nh sau:
Pin dp noi vao pin RD7
Pin g noi vao pin RD6
Pin f noi vao pin RD5
Pin e noi vao pin RD4
Pin d noi vao pin RD3
Pin c noi vao pin RD2
Pin b noi vao pin RD1
Pin a noi vao pin RD0
Cac pin Anode chung cua LED 7 oan se c noi vao cac pin RB0 va RB1 cua
PORTB. Nh vay muon ieu khien mot oan LED nao o sang a pin ieu khien oan LED
tng ng ve mc logic 0. Vi cach noi chan nh vay ta co bang d lieu tng ng vi cac
ch so can hien th tren LED 7 oan nh sau:
Ch so
0
1
2
3
4
5
6
7
8
9
RB7
(dp)
1
1
1
1
1
1
1
1
1
1
RB6
(g)
1
1
0
0
0
0
0
1
0
0
RB5
(f)
0
1
1
1
0
0
0
1
0
0
RB4
(e)
0
1
0
1
1
1
0
1
0
1
RB3
(d)
0
1
0
0
1
0
0
1
0
0
RB2
(c)
0
0
1
0
0
0
0
0
0
0
RB1
(b)
0
0
0
0
0
1
1
0
0
0
RB0
(a)
0
1
0
0
1
0
0
0
0
0
Ma
Hex
C0h
F9h
A4h
B0h
99h
92h
82h
F8h
80h
90h
Da vao bang d lieu tren, muon hien th mot ch so thap phan nao o ra LED 7
oan, ta ch viec a ma hex cua ch so o ra PORTD cua vi ieu khien. Mot iem can lu y
la bang ma tren khong co nh ma no phu thuoc nhieu vao cau truc phan cng cua mang
ieu khien, do o tuy theo cach ket noi phan cng ma ta co c bang ma tng ng.
en ay xem nh ta a hoan tat qua trnh chuyen oi d lieu t dang thap phan sang
dang ma cua LED 7 oan. Viec con lai la lam sao e cho phep mot LED nao o trong day
LED 7 oan mac song song tat hoac sang len. Mot giai phap n gian la s dung cac BJT
hoat ong vi chc nang nh la cac cong tac ong m e cho phep hoac khong cho phep
nguon cung cap a vao LED 7 oan, cac cong tac nay se c ieu khien bi cac pin
trong PORTB. S o nguyen l cua cac cong tac nay khi dung e ieu khien LED 7 oan
loai Anode chung nh sau:
5V
HI
10 K
RBx
LO
Hnh 4.9 S o nguyen l cong tac ieu khien cap nguon cho LED 7 oan Anode chung
Ta noi pin cua Port ieu khien vao cc B cua BJT loai pnp thong qua mot ien tr, gia
tr ien tr nay phu thuoc vao kha nang chu dong toi a cua LED 7 oan. Cc E cua BJT
c noi len nguon 5V va cc C c a vao pin VCC cua LED 7 oan. Khi pin ieu khien
mc logic 1, do VEB cua BJT bang 0 nen BJT khong dan, do o khong co dong ien o qua
LED. Khi Port ieu khien mc logic 0, dong o t cC E sang cc B cua BJT lam cho BJT
dan bao hoa, tr khang cua BJT xem nh bang 0 va LED 7 oan xem nh c noi trc tiep
vi nguon cung cap.
Vi ng dung tren, chang han ta s dung 2 pin RB0 (ieu khien LED hang n v) va
RB1 (ieu khien LED hang chuc) e ieu khien cap nguon cho cac LED. Khi o chng trnh
c viet nh sau:
;Chng trnh 4.3.1
; Chng trnh hien th mot so co hai ch so cho trc ra LED 7 oan
processor
16f877a
include
<p16f877a.inc>
start
loop
count1
counta
countb
EQU
EQU
EQU
ORG
GOTO
0x000
start
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CLRF
CLRF
STATUS, RP1
STATUS,RP0
0x00
TRISD
0x00
TRISB
STATUS,RP0
PORTB
PORTD
MOVLW
MOVWF
MOVLW
MOVWF
CALL
0x99
PORTD
b'11111101'
PORTB
delay_1ms
MOVLW
MOVWF
MOVLW
MOVWF
CALL
0x92
PORTD
b'11111110'
PORTB
delay_1ms
; cap nguon cho LED hang n v
GOTO
loop
; lap lai cac thao tac tren
delay_1ms
MOVLW
MOVWF
d1
MOVLW
MOVWF
MOVLW
MOVWF
delay_0
DECFSZ
GOTO $+2
0x20
0x21
0x22
;cac tham so s dung cho chng trnh con

; delay_1ms
; chon BANK1
; PORTD <- output
; PORTB <- output
; chon BANK0
; hien th so 4
; cap nguon cho LED hang chuc
; goi chng trnh con delay_1ms
; hien th so 5
; goi chng trnh con delay_1ms
; chng trnh con delay_1ms

d'1'
count1
0xC7
counta
0x01
countb
counta,1
END
DECFSZ
GOTO
DECFSZ
GOTO
RETURN
countb,1
delay_0
count1,1
d1
Nh vay trong chng trnh tren, moi LED 7 oan se lan lt c bat sang trong
khoang thi gian 1 ms, sau o LED khac c bat len trong khoang thi gian 1 ms. Thao tac
nay c lap i lap lai trong vong lap loop. Thc chat la cac LED se chp tat lien tuc moi
khoang thi gian 1ms, nhng do thi gian chp tat qua nhanh nen mat ngi b anh la la
ca hai LED ang sang cung mot luc. Hien tng nay co the nhan biet ro rang hn bang cach
tang thi gian delay en mot mc nao o ma mat ngi co the nhan biet c, khi o ta se
thay ro rang la tng LED mot c bat tat mot cach tuan t.
Tng t ta co the m rong so lng LED bang cach noi song song tat ca chung lai
vi nhau va ap dung thuat toan tren e hien th.
Bay gi ta th giai quyet mot trng hp phc tap hn. Trong v du tren ta t an nh
ch so hien th, tuy nhien neu ch so can hien th (ch so hang chuc va hang n v) c
vha trong mot thanh ghi nao o th se co mot so van e phat sinh nh sau:
Th nhat, do d lieu trong thanh ghi c lu di dang d lieu 8 bit nen ch
so hang chuc se c cha trong 4 bit cao va ch so hang n v se c cha trong 4 bit
thap. Vay lam the nao e tach c ch so hang chuc va hang n v cha trong thanh ghi??
Mot thuat toan n gian la s dung phep toan AND. D lieu dang nh phan se gi nguyen gia
tr khi ta thc hien phep toan AND vi 1 va se c xoa ve 0 neu thc hien phep toan AND
vi gia tr 0. Bang cach o muon tach 4 bit thap, ta AND 4 bit cao vi 0, 4 bit thap vi 1 va
ngc lai oi vi trng hp can tach 4 bit cao.
Th hai, do d lieu c lu di dang ma HEX, bao gom cac ch so t 0 en
9 va cac k t t 0 en A. Vay lam the nao e chuyen oi d lieu t dang ma HEX ve dang
thap phan?? ( can lu y la tap lenh danh cho PIC khong co phep toan chia lay phan d hay
phan nguyen DIV va MOD cung nh cac phep toan so sanh). Phng phap n gian nhat la
so sanh vi tng ch so HEX va ap dung phep chuyen oi oi vi tng trng hp.
Va cuoi cung, lam sao hien th ch so thap phan tren ra LED 7 oan?? Nh
vay ta can tien hanh mot bc na la chuyen oi t ma thap phan sang ma LED 7 oan, va
mot phng phap ta van thng s dung trong cac ng dung trc la phng phap bang d
lieu se tiep tuc c s dung trong chng trnh nay. Gia tr cua ch so can chuyen oi se
c cong vao thanh ghi PCL e mang ma chuyen oi tng ng t bang d lieu tr ve.
Bay gi ta th viet chng trnh thc hien thao tac tren theo cac giai thuat a e ra.
Chng trnh se c viet nh sau:
; Chng trnh 4.3.2

; Chng trnh hien th so co hai ch so c lu trong mot thanh ghi
processor
16f877a
include
<p16f877a.inc>
start
count1
counta
countb
display_reg
hang_chuc
hang_don_vi
EQU
EQU
EQU
EQU
EQU
EQU
0x20
0x21
0x22
0X23
0X24
0X25
xx
xx1
EQU
EQU
0x26
0X27
ORG
GOTO
0x000
start
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
CLRF
STATUS, RP1
STATUS,RP0
0x00
TRISD
0x00
TRISB
STATUS,RP0
b'11111111'
PORTB
PORTD
MOVLW
MOVWF
ANDLW
MOVWF
0X5F
display_reg
0x0F
hang_don_vi
MOVLW
ANDWF
MOVWF
SWAPF
0xF0
display_reg,0
hang_chuc
hang_chuc,1
; dung cho chng trnh delay_1ms

; cha gia tr can hien th
; cha hang chuc cua thanh ghi display_reg
; cha hang n v cua thanh ghi
; display_reg
; dung cho chng trnh con chuyen_ma
; bat au chng trinh(

; chon BANK1
; PORTD <- output
; PORTB <- output
; chon BANK0
; tat tat ca cac LED
; gia tr can hien th

; tach ch so hang n v
; tach ch so hang chuc
Loop
MOVF
CALL
hang_don_vi,0
chuyenma
MOVWF
BTFSC
hang_don_vi
xx1,0
INCF
MOVF
hang_chuc,1
hang_chuc,0
CALL
MOVWF
chuyen_ma
hang_chuc
MOVF
CALL
MOVWF
MOVLW
MOVWF
CALL
hang_don_vi,0
table
PORTD
b'11111110'
PORTB
delay_1ms
MOVF
CALL
MOVWF
MOVLW
MOVWF
CALL
GOTO
chuyen_ma
hang_chuc,0
table
PORTD
b'11111101'
PORTB
delay_1ms
loop
MOVWF
MOVLW
XORWF
BTFSC
GOTO
xx
0x00
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x01
xx,0
STATUS,Z
nho_hon_10
MOVLW
0x02
; goi chng trnh con dung e chuyen t

; ma HEX sang ma thap phan
; lu gia tr sau khi chuyen oi
; kiem tra xem gia tr can chuyen oi co
; ln hn 10 hay khong
; neu ung, tang hang chuc 1 n v
; neu khong tiep tuc chuyen ma ch so
; hang chuc
; lu lai gia tr sau khi chuyen oi
; oan chng trnh hien th ket qua
; chuyen oi ra LED 7 oan
; chng trnh con chuyen t ma HEX sang

; dang ma thap phan
; lu so can chuyen oi vao thanh ghi xx
; so sanh vi so 0
; neu bang 0, nhay ti label nho_hon_10

; neu khong bang 0, tiep tuc so sanh vi 1
; tiep tuc tien hanh so sanh vi cac ch
; so tiep theo
XORWF
BTFSC
GOTO
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x03
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x04
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x05
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x06
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x07
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x08
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x09
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
0x0A
xx,0
BTFSC
GOTO
STATUS,Z
bang_10
MOVLW
XORWF
BTFSC
GOTO
0x0B
xx,0
STATUS,Z
bang_11
MOVLW
XORWF
BTFSC
GOTO
0x0C
xx,0
STATUS,Z
bang_12
MOVLW
XORWF
BTFSC
GOTO
0x0D
xx,0
STATUS,Z
bang_13
MOVLW
XORWF
BTFSC
GOTO
0x0E
xx,0
STATUS,Z
bang_14
MOVLW
XORWF
BTFSC
GOTO
nho_hon_10
MOVLW
MOVWF
MOVF
0x0F
xx,0
STATUS,Z
bang_15
0x00
xx1
xx,0
RETURN
bang_10
MOVLW
MOVWF
RETLW
0x01
xx1
0x00
bang_11
MOVLW
MOVWF
0x01
xx1
; x l trng hp nho hn 10
; bit 0 cua thanh ghi xx1 mang gia tr 0
; lu gia tr sau chuyen oi cha trong
; thanh ghi xx vao thanh ghi W
; bit 0 cua thanh ghi xx1 mang gia tr 1
; e bao hieu can tang gia tr hang tiep theo
; mang gia tr chuyen oi tng ng tr ve
; chng trnh chnh thong qua thanh ghi W
; thao tac tng t vi cac trng hp con lai
RETLW
bang_12
MOVLW
MOVWF
RETLW
bang_13
MOVLW
MOVWF
RETLW
bang_14
MOVLW
MOVWF
RETLW
bang_15
MOVLW
MOVWF
RETLW
Table
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
delay_1ms
MOVLW
MOVWF
d1
MOVLW
MOVWF
MOVLW
MOVWF
delay_0
DECFSZ
GOTO $+2
DECFSZ
0x01
0x01
xx1
0x02
0x01
xx1
0x03
0x01
xx1
0x04
0x01
xx1
0x05
PCL,1
0xC0
0xF9
0xA4
0xB0
0x99
0x92
0x82
0xF8
0x80
0x90
d'1'
count1
0xC7
counta
0x01
countb
counta,1
countb,1
; tra bang d lieu e chuyen oi t ma thap phan

; sang ma LED 7 oan
; chng trnh con tao thi gian delay 1ms
GOTO delay_0
DECFSZ
count1,1
GOTO d1
RETURN
END
Trong chng trnh con chuyen_ma, ta lan lt so sanh gia tr sau khi tach t thanh
ghi dplay_reg thanh hang chuc (cha trong thanh ghi hang_chuc) va hang n v (cha
trong thanh ghi hang_don_vi) so sanh vi tng gia tr t 0 en 15. Neu so can chuyen ma
nho hn 10, ta ch viec gi nguyen gia tr va tr ve chng trnh chnh. Neu so can chuyen
ma co gia tr ln hn hoac bang 10, ta a gia tr can chuyen vao thanh ghi W thong qua lenh
RETLW va thiet lap mot c hieu nao o do ta t tao e bao hieu rang ch so can chuyen
oi co gia tr ln hn 10 ( ay la bit 0 cha trong thanh ghi xx1 e bao hieu rang can tang
gia tr hang tiep theo len 1 n v). Chng trnh chnh se co oan chng trnh x l c
hieu nay e cho ra cac ch so thap phan thch hp ng vi cac ch so HEX. Cong viec con
lai la chuyen oi t so thap phan sang ma LED 7 oan thong qua bang d lieu va hien th ket
qua ra cac LED.
Nh vay trong muc nay ta a thc hien c mot so thao tac, chng trnh va giai
thuat c ban oi vi LED 7 oan va cach hien th tren LED. Cac thao tac bao gom cach hnh
thanh bang d lieu, cach ket noi LED 7 oan va phng phap hien th. Cac giai thuat bao
gom cac cach chuyen oi t ma HEX sang ma thap phan, t ma thap phan sang ma LED 7
oan va cach tach ch so hang chuc va hang n v cha trong mot thanh ghi bat k. T cac
thao tac c ban nay ta co the phat trien thanh nhieu ng dung phc tap hn cho vi ieu khien
khi lam viec vi LED 7 oan, ac biet la cac ng dung can hien th ket qua di dang so. Ta
se tiep ban k en cac ng dung nay trong phan tiep theo khi e cap en cac TIMER.
4.4 NGAT VA CAU TRUC CUA MOT CHNG TRNH NGAT
Ngat va cac loai ngat a c trnh bay cu the trong chng 2. ay ta ch tom tat lai
mot so ac iem quan trong cua ngat va thong tin mang tnh ng dung.
Co the noi ay la mot khai niem mang tnh tru tng cao nhng cung c thiet lap
da tren cac hien tng va tnh huong co thc trong thc te. Chang han nh trong cuoc song
hang ngay, oi khi ta phai tam ngng mot cong viec nao o e lam mot cong viec khac can
thiet hn, chang han nh tam ngng mot cong viec nao o ang lam e nghe ien thoai. S
tam ngng nay can c bao hieu bi mot tn hieu (trong trng hp tren la chuong ien
thoai chang han) va phai c ta cho phep trc o (neu ta khong cho phep ien thoai reo th
ien thoai se khong reo). T v du thc te tren ta co the lien tng en ngat va cach x l
ngat cua mot vi ieu khien. Mot ngat la mot tn hieu ieu khien bat buoc vi ieu khien tam
ngng cong viec ang lam e tien hanh cac thao tac ma ngat o qui nh thong qua chng
trnh ngat. Tn hieu ieu khien nay c bao hieu bi c ngat (tng ng vi chuong ien
thoai v du tren) va phai c ta cho phep trc o thong qua cac bit ieu khien cho phep
hoac khong cho phep ngat. Mot chng trnh ngat thong thng se c tach rieng vi
chng trnh chnh e bao am tnh oc lap cua chng trnh ngat.
oi vi vi ieu khien PIC16F877A, khi mot ngat (a c cho phep trc o) xay ra
th phan ng cua no la quay ve a ch 0004h va thc hien cac lenh bat au tai a ch nay.
Thong thng oi vi chng trnh viet cho vi ieu khien PIC, chng trnh ngat se c at
tai ay va chng trnh chnh se c bat au mot a ch cach o mot oan an toan sao
cho chng trnh chnh va chng trnh ngat khong bi chong len nhau. Neu ta s dung trnh
bien dch MPLAB, trnh bien dch se bao loi khi hien tng tren xay ra va ta co the khac
phuc bang cach di chng trnh chnh i mot oan xa hn.
Mot iem can lu y na la trong qua trnh thc hien chng trnh ngat, noi dung cua
mot so thanh ghi quan trong co kha nang b thay oi (thanh ghi W chang han). Do o trc
khi thc hien chng trnh ngat ta can thc hien mot thao tac la cat mot so thanh ghi quan
trong vao mot vai o nh nao o va phai tra lai gia tr ban au cho cac thanh ghi o trc khi
thoat khoi chng trnh ngat bang lenh RETFIE.
Neu s dung trnh bien dch MPLAB, cau truc chng trnh nay a c viet san, ta
ch viec a chng trnh ngat va chng trnh chnh vao cac v tr thch hp c chu thch
trong chng trnh, tuy nhien da vao cac nhan nh nh tren ta hoan toan co the t nh ra
mot cau truc chng trnh cho rieng mnh nh sau:
;------------------------------------------------------------------------------------------------------------; Mot so thong tin can ghi chu ve chng trnh
;------------------------------------------------------------------------------------------------------------TITLE "ten chng trnh"
processor
16f877a
include
<p16f877a.inc>
; V du ve cach khai bao mot vi ieu khien
;---------------------------------------------------------------------------------------------------------------; nh ngha phan cng
;---------------------------------------------------------------------------------------------------------------; nh ngha cac chan xuat nhap e de dang s dung
; v du
#DEFINE
DEN1
PORTB,0
#DEFINE
DEN2
PORTB,1
#DEFINE
DEN3
PORTB,2
;---------------------------------------------------------------------------------------------------------------; nh ngha cac bien, cac thanh ghi cac tham so

;--------------------------------------------------------------------------------------------------------------;Nen at tat ca cac bien trong BANK0
; v du
ORG 0x020
REGAD1
RES
; bien nay co o ln 1 byte, a ch

; bat au la 0x20
Variables
RES
32
; bien nay co o ln 32 byte, a ch
; bat au la 0x21
;------------------------------------------------------------------------------------------------------------; Chng trnh ngat
;------------------------------------------------------------------------------------------------------------; Chu y la tuyet oi khong thay oi cau truc oan chng trnh bat au va thoat ra
; khoi chng trnh ngat
; Neu thay oi chng trnh se chay khong ung
ORG 0X0004
;--------------------------------------------------------------------------------------------------------------; Bat au chng trnh ngat
; oan chng trnh bat buoc va khong c thay oi
; co tac dung lu lai mot so thanh ghi quan trong
;--------------------------------------------------------------------------------------------------------------MOVWF
W_SAVE
; W_SAVE(bank unknown!) = W
SWAPF
STATUS,W
CLRF
STATUS
; force bank 0 for remainder of handler
MOVWF
STAT_SV
; STAT_SV = swap_nibbles( STATUS )
; STATUS = 0
MOVF
PCLATH,W
MOVWF
PCH_SV
; PCH_SV = PCLATH
CLRF
PCLATH
; PCLATH = 0
MOVF
FSR,W
MOVWF
FSR_SV
; FSR_SV = FSR
; 12 cycles from interrupt to here!
;-------------------------------------------------------------------------------------------------------------; oan chng trnh ngat bat au tai ay
;-------------------------------------------------------------------------------------------------------------; Kiem tra xem ngat nao a xay ra
; Xoa c ngat trc khi thc hien cac lenh trong ngat
; Bat au cac lenh cho chng trnh ngat
;--------------------------------------------------------------------------------------------------------------; Ket thuc chng trnh ngat
; oan chng trnh bat buoc va khong c thay oi
; co tac dung phuc hoi gia tr ban au cho mot so thanh ghi quan trong
;--------------------------------------------------------------------------------------------------------------ENDINT
MOVF
MOVWF
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
RETFIE
FSR_SV,W
FSR
PCH_SV,W
PCLATH
STAT_SV,W
STATUS
W_SAVE,F
W_SAVE,W
; FSR = FSR_SV
; PCLATH = PCH_SV
; STATUS = swap_nibbles( STAT_SV )
; W = swap(swap( W_SAVE )) (no change Z bit)
; RETURN!
; 1 cycle to resumption of code (branch penalty)
;------------------------------------------------------------------------------------------------------------; Cham dt chng trnh ngat
; Bat au cac bc khi tao cho toan bo chng trnh
;------------------------------------------------------------------------------------------------------------ORG
0X0000
GOTO
START
ORG
0X0050
; Phai cach ra mot oan e tranh e len chng trnh ngat
START
;----------------------------------------------------------------------------------------------------------; Khi tao cac PORT
; Khi tao cac bien
; Khi tao cac khoi chc nang (Timer, CCP, PWM,)
;----------------------------------------------------------------------------------------------------------; Bat au vong lap chnh
MAIN
; Cac thao tac trong vong lap chnh
; Cac chng trnh con
END
So vi cac chng trnh trc ay th bat au t giai oan nay, cac chng trnh se tr
nen phc tap hn ve cau truc cung nh chc nang do co them chng trnh ngat. Tuy nhien ta
se de dang lam quen vi cau truc mi nay sau mot vai chng trnh n gian co lien quan
en ngat. Ta se bat au vi Timer va cac ngat cua Timer.
4.5 TIMER VA NG DUNG
Nh ta a biet PIC16F877A co 3 bo nh thi la Timer0, Timer1 va Timer2. Moi
Timer co mot cau truc va chc nang rieng tuy thuoc vao muc ch s dung. Co the phan chia
mot cach tng oi muc ch s dung cua mot Timer nh sau:
Tac dung nh thi (Timing): cac Timer se s dung xung clock ong bo c
cung cap bi oscillator cua vi ieu khien hoac t mot oscillator co nh RC0/T1OSO/T1CKI
va RC1/T1OSICCP2 oi vi Timer1. Gia tr em cha trong thanh ghi cua cac Timer se tang
tuan t sau mot khoang thi gian tuan t c nh trc da vao cac thong so cua prescaler,
postscaler, chu k lenh va cac gia tr nh trc c a vao cac thanh ghi cha gia tr em
cua cac Timer. Day cung la l do tai sao ta noi Timer co tac dung nh thi v da vao gia tr
em cua cac Timer, ta co the xac nh mot cach tng oi chnh xac thi gian thc.
Tac dung em (Counting): cac Timer se lay xung em t ben ngoai. Cac xung
em nay co tac dung phan anh mot hien tng nao o t the gii ben ngoai va thong qua
viec em cac xung clock o, ta co the xac nh c so lan mot hien tng nao o xay ra, t
o an nh cac thao tac tng ng oi vi hien tng o.
Thong thng cac thao tac oi vi Timer da vao cac ngat va chng trnh ngat. Ta
can xem lai cau truc mot chng trnh ngat c trnh bay phan trc e qua trnh viet
chng trnh cho Timer tr nen thuan li hn. Ben canh o cach thiet lap cac che o hoat
ong oi vi moi Timer cung khac nhau. Van e nay se c trnh bay cu the trong tng
chng trnh ng dung, ngoai ra co the tham khao them mot so tai lieu cua nha san xuat
Microchip e biet them chi tiet.
4.5.1 TIMER VA HOAT ONG NH THI
Trong phan nay ta se lam bc au lam quen vi cac Timer cua vi ieu khien
PIC16F877A va cac thao tac c ban oi vi cac Timer, bao gom thao tac khi tao va x l
ngat. e cu the hn ta se i sau vao ng dung sau:
ng dung 4.7: Hien th cac gia tr nh thi cua Timer ra LED 7 oan.
ng dung nay c phat trien da tren ng dung 4.6 ve hien th tren LED 7 oan.
ng dung 4.6 ta a lam quen vi cac thao tac c ban oi vi LED 7 oan. Trong ng dung
nay ta se dung cac Timer e hien th cac gia tr tang dan t 0 en 99 sau mot khoang thi
gian nh trc tren 2 LED hang chuc va hang n v. Cau truc phan cng van khong co g
thay oi, tuy nhien ve chng trnh se co nhng thay oi ang ke.
Trc het la giai thuat cho ng dung tren. Ta se khi tao Timer e hnh thanh thi
gian delay co nh. Thi gian delay se ket thuc bang mot tn hieu t ngat Timer, chng trnh
ngat co nhiem vu cap nhat gia tr em moi khi ngat xay ra, chng trnh chnh co tac dung
hien th cac gia tr a c cap nhat ra LED 7 oan. Trc tien ta se s dung Timer0 cho ng
dung tren va chng trnh cu the nh sau:
;----------------------------------------------------------------------------------------------------------; Ghi chu ve chng trnh
;----------------------------------------------------------------------------------------------------------; Chng trnh 4.5.1
; Chng trnh hien th so em tren hai LED 7 oan theo th t tang dan
; Timer s dung: Timer2
;-----------------------------------------------------------------------------------------------------------; Khai bao vi ieu khien
;-----------------------------------------------------------------------------------------------------------processor
16f877a
include
<p16f877a.inc>
; ----------------------------------------------------------------------------------------------------------; Khai bao bien
;-----------------------------------------------------------------------------------------------------------count1
EQU
0x20
; Cac thanh ghi s dung cho chng
counta
EQU
0x21
; trnh delay
countb
EQU
0x22
hang_don_vi
hang_chuc
EQU
EQU
0x23
0x24
; Cac thanh ghi cha gia tr can

; hien th ra LED 7 oan
W_save
EQU
0x25
; Cac thanh ghi dung e cat cac
PCLATH_save
EQU
0x26
; thanh ghi quan trong khi thc thi
STATUS_save
EQU
0x27
; chng trnh ngat
FSR_save
EQU
0x28
;------------------------------------------------------------------------------------------------------------; Chng trnh ngat
;------------------------------------------------------------------------------------------------------------ORG
0x0004
GOTO
ISR
ISR
;-----------------------------------------------------------------------------------------------------------; oan chng trnh bat buoc au chng trnh ngat

;-----------------------------------------------------------------------------------------------------------MOVWF
W_save
SWAPF
STATUS,W
CLRF
STATUS
MOVWF
STATUS_save
MOVF
PCLATH,W
MOVWF
PCLATH_save
CLRF
PCLATH
MOVF
FSR,W
MOVWF
FSR_save
BTFSS
GOTO
INTCON,TMR0IF
exit_int
BCF
INTCON,TMR0IF
; Kiem tra c ngat Timer0

; Neu c ngat cha c set, thoat khoi
; chng trnh ngat
; neu c ngat a c set, xoa c ngat e

; cho phep nhan biet thi iem tiep theo
; xay ra ngat
;------------------------------------------------------------------------------------------------------------; Cac thao tac chnh cua chng trnh ngat
;------------------------------------------------------------------------------------------------------------INCF
hang_don_vi,1
; tang hang n v
MOVLW
0x0A
XORWF
hang_don_vi,0
; so sanh hang n v vi 10
BTFSS
STATUS,Z
GOTO
exit_int
; thoat chng trnh ngat neu cha bang 10
CLRF
hang_don_vi
; neu bang 10, xoa hang n v
INCF
hang_chuc,1
; tang hang chuc
MOVLW
0x0A
XORWF
hang_chuc,0
; so sanh hang chuc vi 10
BTFSS
STATUS,Z
GOTO
exit_int
; thoat chng trnh ngat neu cha bang 10
CLRF
hang_chuc
; neu bang 10, xoa hang chuc, bat au em
; lai t gia tr 00
GOTO
exit_int
; thoat chng trnh ngat
;--------------------------------------------------------------------------------------------------------------; oan chng trnh bat buoc trc khi thoat khoi chng trnh ngat
;--------------------------------------------------------------------------------------------------------------exit_int
MOVF
FSR_save,W
MOVWF
FSR
MOVF
PCLATH_save,W
MOVWF
PCLATH
SWAPF
STATUS_save,W
MOVWF
STATUS
SWAPF
W_save,1
SWAPF
W_save,0
RETFIE
;---------------------------------------------------------------------------------------------------------------; Ket thuc chng trnh ngat
;---------------------------------------------------------------------------------------------------------------ORG
0x0000
GOTO
start
ORG
0x050
;---------------------------------------------------------------------------------------------------------------; Bat au chng trnh chnh
;---------------------------------------------------------------------------------------------------------------start
;--------------------------------------------; Khi tao cac PORT
;--------------------------------------------BCF
STATUS,RP1
BSF
STATUS,RP0
; Chon BANK1
MOVLW
MOVWF
MOVLW
MOVWF
0x00
TRISD
b'11111100'
TRISB
; PORTB<1:0> <- output
BCF
STATUS,RP0
; chon BANK0
CLRF
PORTD
MOVLW
b'00000011'
MOVWF
PORTB
;---------------------------------------; Khi tao Timer0
;---------------------------------------CLRF
TMR0
CLRF
INTCON
BSF
STATUS,RP0
; PORTD <- output
; tat cac LED hang chuc va hang n v
; xoa thanh ghi TMR0

; xoa thanh ghi INTCON
; chon BANK0
MOVLW
MOVWF
b'10000001'
OPTION_REG
; tat chc nang ien tr keo len PORTB,

; chon xung em la xung lenh, gan
; prescaler cho Timer0 va chon t so chia
; tan so prescaler la 1:4
; chon BANK0
; cho phep ngat Timer0
; cho phep ngat ngoai vi
; cho phep toan bo cac ngat
BCF
STATUS,RP0
BSF
INTCON,TMR0IE
BSF
INTCON,PEIE
BSF
INTCON,GIE
;---------------------------------------------; Khi tao cac bien
;---------------------------------------------CLRF
hang_chuc
CLRF
hang_don_vi
;---------------------------------------------; Vong lap chnh
;---------------------------------------------main
CALL
hien_thi
; goi chng trnh con
GOTO
main
;---------------------------------------------------------------------------------------------------------------; Chng trnh con hien th cac gia tr cha trong cac thanh ghi hang_chuc va hang_don_vi ra
; cac LED hang chuc va LED hang n v
;---------------------------------------------------------------------------------------------------------------hien_thi
MOVF
hang_chuc,0
; hien th LED hang chuc
CALL
table
MOVWF
PORTD
MOVLW
b'11111101'
MOVWF
PORTB
CALL
delay_1ms
MOVF
hang_don_vi,0
; hien th LED hang n v
CALL
table
MOVWF
PORTD
MOVLW
b'11111110'
MOVWF
PORTB
CALL
delay_1ms
RETURN
; ket thuc chng trnh con hien_thi
;-------------------------------------------------------------------------------------------------------; Cac chng trnh con dung cho chng trnh con hien_thi
;--------------------------------------------------------------------------------------------------------
table
; bang d lieu chuyen t ma thap phan sang ma

; LED 7 oan
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
delay_1ms
MOVLW
MOVWF
d2
MOVLW
MOVWF
MOVLW
MOVWF
delay_1
DECFSZ
GOTO
DECFSZ
GOTO
DECFSZ
GOTO
RETURN
END
PCL,1
0xC0
0xF9
0xA4
0xB0
0x99
0x92
0x82
0xF8
0x80
0x90
d'1'
count1
0xC7
counta
0x01
countb
; chng trnh con tao thi gian delay 1 ms
counta,1
$+2
countb,1
delay_1
count1,1
d2
; chng trnh ket thuc tai ay
Ta nhan thay rang cau truc chng trnh tren hoan toan tng t nh cau truc cua
chng trnh mau, cac giai thuat ve hien th LED a c e cap cu the ng dung 4.6, do
o van e con lai ch la cac van e lien quan en Timer0. Cac bc khi tao Timer0 a c
e cap cu the trong cac tai lieu cua nha san xuat, ta ch viec da theo sn bai co san o
va them vao cac thong so thch hp at vao cac thanh ghi ieu khien (oi vi Timer0 la cac
thanh ghi OPTION_REG, thanh ghi INTCON va thanh ghi TMR0) e khi tao cac ieu kien
ban au cho Timer0 sao cho phu hp vi muc ch s dung.
Vi chng trnh tren, moi lan ngat Timer0 xay ra, vi ieu khien se t vong lap cua
chng trnh chnh quay tr ve chng trnh ngat. Chng trnh ngat se thc hien cong viec
tang gia tr em mot cach thch hp cac thanh ghi hang_chuc va thanh ghi hang_don_vi.
Thuat toan danh cho chng trnh ngat cung tng oi n gian, gia tr em se c lu trc
tiep di dang ma thap phan nen ta khong can phai chuyen oi t ma HEX sang ma thap
phan. Khi qua trnh cap nhat gia tr em ket thuc, vi ieu khien quay tr ve vong lap chnh
va tiep tuc qua trnh hien th cac gia tr a c cap nhat t chng trnh ngat.
Bay gi ta th tnh thi gian nh thi do Timer0 tao ra. Do ta khi tao Timer0 s
dung xung em la xung lenh nen moi xung co thi gian la 1 uS (oi vi oscillator 4 MHz),
xung lenh c chia 4 bi prescaler nen gia tr cua thanh ghi TMR0 se tang len 1 n v sau
khoang thi gian (4*1 uS) = 4 uS. Nh vay ngat se xay ra sau moi quang thi gian (256*4 uS)
= 1024 uS (Timer0 la bo em 8 bit va ngat xay ra khi TMR0 b tran).
Da vao chng trnh tren ta co the kiem tra c tac ong cua prescaler bang cach
thay oi gia tr a vao thanh ghi OPTION_REG. S thay oi thi gian nh thi khi ta thay
oi t so chia cua prescaler la tng oi ro rang.
Cung da vao chng trnh tren ta co the thay Timer0 bang Timer1 hoac Timer2 e
lam quen vi cac Timer cua vi ieu khien. S thay oi duy nhat so vi chng trnh tren la
cac bc khi tao, do moi Timer eu co mot cau truc va hoat ong oc lap vi nhau. Cac
bc khi tao co the c tham khao trong cac tai lieu cua nha san xuat. Chng trnh sau co
tac dung nh chng trnh 4.5.1 nhng lan nay ta se s dung Timer2 lam bo nh thi.
;----------------------------------------------------------------------------------------------------------; Ghi chu ve chng trnh
;----------------------------------------------------------------------------------------------------------; Chng trnh 4.5.2
; Chng trnh hien th so em tren hai LED 7 oan theo th t tang dan
;-----------------------------------------------------------------------------------------------------------processor
16f877a
include
<p16f877a.inc>
; ----------------------------------------------------------------------------------------------------------; Khai bao bien
;-----------------------------------------------------------------------------------------------------------count1
EQU
0x20
counta
EQU
0x21
countb
EQU
0x22
hang_don_vi
EQU
0x23
hang_chuc
EQU
0x24
W_save
PCLATH_save
STATUS_save
FSR_save
EQU
EQU
EQU
EQU
0x25
0x26
0x27
0x28
ORG
0x0004
GOTO
ISR
;------------------------------------------------------------------------------------------------------------; Chng trnh ngat
;------------------------------------------------------------------------------------------------------------ISR
;-----------------------------------------------------------------------------------------------------------; oan chng trnh bat buoc au chng trnh ngat
;-----------------------------------------------------------------------------------------------------------MOVWF
W_save
SWAPF
STATUS,W
CLRF
STATUS
MOVWF
STATUS_save
MOVF
PCLATH,W
MOVWF
PCLATH_save
CLRF
PCLATH
MOVF
FSR,W
MOVWF
FSR_save
;------------------------------------------------------------------------------------------------------------; Cac thao tac chnh cua chng trnh ngat
;------------------------------------------------------------------------------------------------------------BTFSS
PIR1,TMR2IF
GOTO
exit_int
BCF
INCF
MOVLW
XORWF
BTFSS
GOTO
CLRF
INCF
MOVLW
XORWF
BTFSS
GOTO
PIR1,TMR2IF
hang_don_vi,1
0x0A
hang_don_vi,0
STATUS,Z
exit_int
hang_don_vi
hang_chuc,1
0x0A
hang_chuc,0
STATUS,Z
exit_int
CLRF
hang_chuc
GOTO
exit_int
;--------------------------------------------------------------------------------------------------------------; oan chng trnh bat buoc trc khi thoat khoi chng trnh ngat
;--------------------------------------------------------------------------------------------------------------exit_int
MOVF
FSR_save,W
MOVWF
FSR
MOVF
PCLATH_save,W
MOVWF
PCLATH
SWAPF
STATUS_save,W
MOVWF
STATUS
SWAPF
W_save,1
SWAPF
W_save,0
RETFIE
;---------------------------------------------------------------------------------------------------------------; Ket thuc chng trnh ngat
;---------------------------------------------------------------------------------------------------------------ORG
0x0000
GOTO
start
ORG
0x050
;---------------------------------------------------------------------------------------------------------------; Bat au chng trnh chnh
;---------------------------------------------------------------------------------------------------------------start
;--------------------------------------------; Khi tao cac PORT
;--------------------------------------------BCF
STATUS,RP1
BSF
STATUS,RP0
MOVLW
MOVWF
MOVLW
MOVWF
0x00
TRISD
b'11111100'
TRISB
BCF
STATUS,RP0
CLRF
MOVLW
MOVWF
PORTD
b'00000011'
PORTB
;---------------------------------------; Khi tao Timer2

;---------------------------------------MOVLW
b'11111111'
MOVWF
T2CON
BSF
MOVLW
MOVWF
BSF
STATUS,RP0
.249
PR2
PIE1,TMR2IE
BCF
STATUS,RP0
; postscaler 1:16, prescaler 1:16, Timer2 ON
; at trc gia tr can so sanh vi thanh ghi TMR2

; vao thanh ghi PR2
; cho phep ngat Timer2
BSF
INTCON,PEIE
; cho phep cac ngat ngoai vi
BSF
INTCON,GIE
; cho phep toan bo cac ngat
;---------------------------------------------; Khi tao cac bien
;---------------------------------------------CLRF
hang_chuc
CLRF
hang_don_vi
;---------------------------------------------; Vong lap chnh
;---------------------------------------------main
CALL
hien_thi
GOTO
main
;---------------------------------------------------------------------------------------------------------------; Chng trnh con hien th cac gia tr cha trong cac thanh ghi hang_chuc va hang_don_vi ra
; cac LED hang chuc va LED hang n v
;---------------------------------------------------------------------------------------------------------------hien_thi
MOVF
hang_chuc,0
CALL
table
MOVWF
PORTD
MOVLW
b'11111101'
MOVWF
PORTB
CALL
delay_1ms
MOVF
CALL
MOVWF
hang_don_vi,0
table
PORTD
MOVLW
b'11111110'
MOVWF
PORTB
CALL
delay_1ms
RETURN
;-------------------------------------------------------------------------------------------------------; Cac chng trnh con dung cho chng trnh con hien_thi
;-------------------------------------------------------------------------------------------------------table
ADDWF
PCL,1
RETLW
0xC0
RETLW
0xF9
RETLW
0xA4
RETLW
0xB0
RETLW
0x99
RETLW
0x92
RETLW
0x82
RETLW
0xF8
RETLW
0x80
RETLW
0x90
delay_1ms
MOVLW
MOVWF
d2
MOVLW
MOVWF
MOVLW
MOVWF
delay_1
DECFSZ
GOTO
DECFSZ
GOTO
DECFSZ
GOTO
RETURN
END
d'1'
count1
0xC7
counta
0x01
countb
counta,1
$+2
countb,1
delay_1
count1,1
d2
Timer2 cung la bo em 8 bit c ho tr them thanh ghi so sanh PR2 va hai bo chia
tan so postscaler prescaler giup ta linh ong hn trong viec tao ra khoang thi gian delay
thch hp cho ng dung. Thanh ghi ieu khien Timer2 la thanh ghi T2CON. Chng trnh tren
khong co g mi, no ch giup ta on lai mot so ac iem cua Timer2 va cach khi tao no.
ng dung 4.8: ng dung PIC16F877A va cac LED 7 oan e lam ong ho.
Vi hai v du tren ta co the nam bat c cac khai niem c ban ve tac dung nh thi
dung Timer, va mot trong nhng ng dung pho bien nhat cua che o nh thi la lam ong ho
ien t. Ta co the s dung bat c Timer nao cua vi ieu khien e phuc vu cho ng dung nay,
tuy nhien e co mot cach nhn tong quat hn ve cac Timer, lan nay ta se s dung Timer1.
Bay gi ta se tien hanh tng bc e thc hien thanh cong ng dung nay.
Trc tien la van e ve cau truc phan cng, e hien th c gi, phut, giay ta can
en 6 LED 7 oan, cach ket noi hoan toan tng t nh cac ng dung s dung 2 LED v du
4.7, ch viec noi them 4 LED 7 oan mac song song vi hai LED trc o va ket noi them 4
cong tac dung BJT vao PORTB e ieu khien quet LED.
Tiep theo la van e ve chng trnh viet cho vi ieu khien. Cach phan cong oi vi
chng trnh se khong co g thay oi, tc la chng trnh chnh se lam nhiem vu hien th LED
va chng trnh ngat se thc hien cong viec cap nhat cac gia tr can hien th. Tuy nhien co
mot so van e phat sinh nh sau:
Th nhat, lam sao tao ra thi gian nh thi 1 giay?? Timer ta s dung la
Timer1 16 bit vi bo chia tan so prescaler co cac t so chia la 1:1, 1:2, 1:4, 1:8 va c ieu
khien bi thanh ghi T1CON (xem lai Timer1 e biet them chi tiet). Gia tr em toi a cua
Timer1 se la 65534, trong khi neu ta s dung oscillator 4 MHz (moi xung lenh co thi gian 1
uS) th Timer1 can phai em en gia tr 1 000 000, va neu ta co huy ong toi a kha nang
chia tan so cua prescaler (1:8 ) th gia tr em cung phai at en 1 000 000/8 = 125 000 (van
con ln hn rat nhieu so vi gia tr em toi a cua Timer1. Mot giai phap cho van e nay la
dung them mot thanh ghi em phu( thanh ghi count). Cu the nh sau: ta cho Timer1 em t 0
en 25000, do o ta can 5 lan em nh vay (5 lan ngat Timer1 xay ra) e at c gia tr
em 125 000. Nh vay trc khi cap nhat gia tr giay, ta can kiem tra xem bien phu count a
bang 5 hay cha, neu bang roi th mi tang gia tr giay va reset lai bien count.
Th hai, lam sao cap nhat gia tr gi??? Cac gia tr phut va giay tang t 0 en
60 nen thuat toan dung e cap nhat la tng oi n gian (tng t nh thuat toan ng dung
4.7, ch co ieu ta khong so sanh hang chuc vi 10 ma so sanh vi 6), con gia tr gi ch tang
t 0 en 24. Giai thuat e ra la ta khong cap nhat tng hang n v va hang chuc cua gia tr
gi nh oi voi phut va giay, thay vao o gia tr gi se c cap nhat vao mot thanh ghi, sau
o dung thuat toan tach hang chuc va hang n v cua gi nh ng dung 4.6 (chng trnh
4.3.2) e hien th cac gia tr thanh ghi cha gia tr gi ra LED 7 oan.
en ay ta a co the viet chng trnh cho ng dung theo cac giai thuat e ra tren.
Chng trnh cu the se c viet nh sau:
-----------------------------------------------------------------------------------------------------------; Ghi chu ve chng trnh

;----------------------------------------------------------------------------------------------------------; Chng trnh 4.5.3
; Chng trnh ng dung PIC16F877A va LED 7 oan e lam ong ho ien t
;-----------------------------------------------------------------------------------------------------------processor
16f877a
include
<p16f877a.inc>
;----------------------------------------------------------------------; Khai bao bien
;----------------------------------------------------------------------count1
EQU
0x20
; Cac thanh ghi dung cho
counta
EQU
0x21
; chng trnh con delay_1ms
countb
EQU
0x22
hang_don_vi_giay
hang_chuc_giay
hang_don_vi_phut
hang_chuc_phut
gio
hang_don_vi_gio
hang_chuc_gio
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0x23
0x24
0x25
0x26
0x27
0x28
0x29
; Cac thanh ghi cha cac gia tr

; gi, phut, giay can hien th
count
display_reg
xx
xx1
EQU
EQU
EQU
EQU
0x30
0x31
0x32
0x33
; Cac thanh ghi phu
W_save
PCLATH_save
STATUS_save
FSR_save
EQU
EQU
EQU
EQU
0x34
0x35
0x36
0x37
; Cac thanh ghi dung e lu lai gia

; tr cac thanh ghi quan trong khi
; thc thi chng trnh ngat
ORG
GOTO
0x0004
ISR
;----------------------------------------------------------------------------; Chng trnh ngat

;----------------------------------------------------------------------------ISR
;--------------------------------------------------------------------------; oan chng trnh bat buoc khi bat au chng trnh ngat
;-------------------------------------------------------------------------MOVWF
W_save
SWAPF
STATUS,W
CLRF
STATUS
MOVWF
STATUS_save
MOVF
PCLATH,W
MOVWF
PCLATH_save
CLRF
PCLATH
MOVF
FSR,W
MOVWF
FSR_save
;-------------------------------------------------------------------------------; Kiem tra cac c ngat
;-------------------------------------------------------------------------------BTFSS
PIR1,TMR1IF
; kiem tra c ngat cua Timer1
GOTO
exit_int
BCF
T1CON,TMR1ON ; tam thi tat Timer1 e khi tao lai
;-------------------------------------------------------------------------------; Cac thao tac chnh cua chng trnh ngat
;-------------------------------------------------------------------------------CLRF
TMR1L
; Khi tao lai cac gia tr cha trong thanh
CLRF
TMR1H
; ghi TMRH va TMRL
MOVLW
0x61
; a vao cac thanh ghi em cua Timer1
MOVWF
TMR1H
; gia tr 25000 (25000 -> 61A8h)
MOVLW
0xA8
MOVWF
TMR1L
BSF
BCF
T1CON,TMR1ON
PIR1,TMR1IF
INCF
MOVLW
XORWF
BTFSS
GOTO
CLRF
count
d'5'
count,0
STATUS,Z
exit_int
count
; Bat Timer1
; xoa c ngat e tiep tuc nhan biet thi iem tiep
; theo ngat xay ra
; bien em phu
; so sanh count vi gia tr 5
; neu cha bang 5, thoat khoi ngat

; neu a bang 5, reset lai bien count
INCF
MOVLW
XORWF
BTFSS
GOTO
CLRF
INCF
MOVLW
XORWF
BTFSS
GOTO
hang_don_vi_giay,1
0x0A
hang_don_vi_giay,0
STATUS,Z
exit_int
hang_don_vi_giay
hang_chuc_giay,1
0x06
hang_chuc_giay,0
STATUS,Z
exit_int
; tang hang n v cua bien giay

; so sanh vi 10
; cap nhat hang chuc cua gia tr giay
CLRF
INCF
MOVLW
XORWF
BTFSS
GOTO
CLRF
INCF
MOVLW
XORWF
BTFSS
GOTO
hang_chuc_giay
; cap nhat gia tr phut
hang_don_vi_phut,1
0x0A
; so sanh hang n v cua gia tr phut vi 10
hang_don_vi_phut,0
STATUS,Z
exit_int
hang_don_vi_phut
hang_chuc_phut,1
0x06
; so sanh hang chuc cua gia tr phut vi 6
hang_chuc_phut,0
STATUS,Z
exit_int
; so sanh gia tr hang chuc giay vi 6
CLRF
hang_chuc_phut
INCF
gio,1
; cap nhat gia tr gi
MOVLW
0x18
XORWF
gio,0
BTFSS
STATUS,Z
GOTO
exit_int
CLRF
gio
GOTO
exit_int
;---------------------------------------------------------------------------------------------------------------; oan chng trnh bat buoc dung e ket thuc chng trnh ngat
;---------------------------------------------------------------------------------------------------------------exit_int
MOVF
FSR_save,W
MOVWF
FSR
MOVF
PCLATH_save,W
MOVWF
PCLATH
SWAPF
MOVWF
SWAPF
SWAPF
RETFIE
STATUS_save,W
STATUS
W_save,1
W_save,0
ORG
0x0000
GOTO
start
ORG
0x050
;--------------------------------------------------------------------------------------------------; Chng trnh chnh
;--------------------------------------------------------------------------------------------------start
;--------------------------------------------------------------; Khi tao cac PORT ieu khien
;--------------------------------------------------------------BCF
STATUS,RP1
BSF
STATUS,RP0
MOVLW
0x00
; PORTD <-output
MOVWF
TRISD
MOVLW
b'11000000'
; PORTB <5:0> <- output
MOVWF
TRISB
; Ta can 6 pin PORTB e ieu khien quet LED
BCF
STATUS,RP0
CLRF
PORTD
MOVLW
b'00111111'
; Tat tat ca cac LED
MOVWF
PORTB
;----------------------------------------------------------------; Khi tao Timer1
;----------------------------------------------------------------CLRF
T1CON
CLRF
INTCON
CLRF
TMR1H
CLRF
TMR1L
BSF
STATUS,RP0
; Chon BANK1
CLRF
PIE1
BSF
PIE1,TMR1IE
; Cho phep ngat Timer1
BCF
STATUS,RP0
; Chon BANK0
CLRF
PIR1
; xoa tat ca cac c ngat
MOVLW
0X30
; prescaler 1:8, xung em la xung lenh, tam thi
MOVWF
T1CON
; tat Timer1
MOVLW
MOVWF
MOVLW
MOVWF
0x61
TMR1H
0xA8
TMR1L
; Khi tao cac gia tr trong thanh ghi TMR1H

; va TMR1L (TMR1H:TMR1L = 25000)
BSF
T1CON,TMR1ON ; Bat Timer1
BSF
INTCON,TMR1IE ; Cho phep ngat Timer1
BSF
INTCON,PEIE
; Cho phep ngat ngoai vi
BSF
INTCON,GIE
; Cho phep toan bo cac ngat
;-------------------------------------------------------------------------------; Khi tao cac bien
;-------------------------------------------------------------------------------CLRF
gio
CLRF
hang_chuc_gio
CLRF
hang_don_vi_gio
CLRF
hang_don_vi_phut
CLRF
hang_chuc_phut
CLRF
hang_chuc_giay
CLRF
hang_don_vi_giay
CLRF
count
;-------------------------------------------------------------------------------; Vong lap chnh
;-------------------------------------------------------------------------------main
CALL
hien_thi
GOTO
main
hien_thi
CALL
MOVF
CALL
MOVWF
MOVLW
MOVWF
CALL
MOVF
CALL
MOVWF
MOVLW
MOVWF
CALL
chuyen_ma_gio
hang_chuc_gio,0
table
PORTD
b'11011111'
PORTB
delay_1ms
hang_don_vi_gio,0
table
PORTD
b'11101111'
PORTB
delay_1ms
; goi chng trnh con chuyen_ma_gio

; Hien th gia tr gi ra LED
table
MOVF
CALL
MOVWF
MOVLW
MOVWF
CALL
MOVF
CALL
MOVWF
MOVLW
MOVWF
CALL
hang_chuc_phut,0 ; Hien th gia tr phut ra LED

table
PORTD
b'11110111'
PORTB
delay_1ms
hang_don_vi_phut,0
table
PORTD
b'11111011'
PORTB
delay_1ms
MOVF
CALL
MOVWF
MOVLW
MOVWF
CALL
MOVF
CALL
MOVWF
MOVLW
MOVWF
CALL
RETURN
hang_chuc_giay,0 ; Hien th gia tr giay ra LED

table
PORTD
b'11111101'
PORTB
delay_1ms
hang_don_vi_giay,0
table
PORTD
b'11111110'
PORTB
delay_1ms
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
delay_1ms
MOVLW
PCL,1
0xC0
0xF9
0xA4
0xB0
0x99
0x92
0x82
0xF8
0x80
0x90
d'1'
; Bang d lieu dung e chuyen oi

; t ma thap phan sang ma LED 7 oan
; Chng trnh con tao thi gian delay 1ms
MOVWF
d2
MOVLW
MOVWF
MOVLW
MOVWF
delay_1
DECFSZ
GOTO
DECFSZ
GOTO
DECFSZ
GOTO
RETURN
chuyen_ma_gio
MOVF
MOVWF
ANDLW
MOVWF
MOVLW
ANDWF
MOVWF
SWAPF
MOVF
CALL
MOVWF
BTFSC
INCF
MOVF
CALL
MOVWF
RETURN
chuyen_ma
MOVWF
MOVLW
XORWF
BTFSC
GOTO
MOVLW
count1
0xC7
counta
0x01
countb
counta,1
$+2
countb,1
delay_1
count1,1
d2
gio,0
display_reg
0x0F
hang_don_vi_gio
0xF0
display_reg,0
hang_chuc_gio
hang_chuc_gio,1
hang_don_vi_gio,0
chuyen_ma
hang_don_vi_gio
xx1,0
hang_chuc_gio,1
hang_chuc_gio,0
chuyen_ma
hang_chuc_gio
xx
0x00
xx,0
STATUS,Z
nho_hon_10
0x01
; chng trnh con dung e tach ri gia tr hang

; chuc va hang n v cua thanh ghi cha gia tr
; gi va chuyen sang ma thap phan
; Ket qua chuyen oi c lu trong thanh ghi
; hang_don_vi_gio va hang_phut_gio
; chng trnh con chuyen t ma HEX sang

; ma thap phan
XORWF
BTFSC
GOTO
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x02
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x03
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x04
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x05
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x06
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x07
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x08
xx,0
STATUS,Z
nho_hon_10
MOVLW
XORWF
0x09
xx,0
BTFSC
GOTO
STATUS,Z
nho_hon_10
MOVLW
XORWF
BTFSC
GOTO
0x0A
xx,0
STATUS,Z
bang_10
MOVLW
XORWF
BTFSC
GOTO
0x0B
xx,0
STATUS,Z
bang_11
MOVLW
XORWF
BTFSC
GOTO
0x0C
xx,0
STATUS,Z
bang_12
MOVLW
XORWF
BTFSC
GOTO
0x0D
xx,0
STATUS,Z
bang_13
MOVLW
XORWF
BTFSC
GOTO
0x0E
xx,0
STATUS,Z
bang_14
MOVLW
XORWF
BTFSC
GOTO
0x0F
xx,0
STATUS,Z
bang_15
nho_hon_10
MOVLW
MOVWF
MOVF
RETURN
bang_10
MOVLW
MOVWF
0x00
xx1
xx,0
0x01
xx1
RETLW
0x00
bang_11
MOVLW
MOVWF
RETLW
0x01
xx1
0x01
bang_12
MOVLW
MOVWF
RETLW
0x01
xx1
0x02
bang_13
MOVLW
MOVWF
RETLW
0x01
xx1
0x03
bang_14
MOVLW
MOVWF
RETLW
0x01
xx1
0x04
bang_15
MOVLW
MOVWF
RETLW
END
0x01
xx1
0x05
; Ket thuc chng trnh
Thc ra ta co nhieu phng phap khac e tao thi gian nh thi 1s bang cach s dung
cac ac tnh cua Timer1, chang han ta co the s dung oscillator ngoai vi khac cho Timer1 ma
khong can dung chung vi oscillator cua vi ieu khien. Ta cung co the s dung cac Timer
khac cho ng dung nay va tuy theo ac iem cau tao cua tng Timer ta co the xac nh c
cac gia tr thch hp e tao thi gian nh thi 1s.
Tuy nhien du s dung phng phap nao i na ta cung khong the tao ra ong ho ien
t co o chnh xac tuyet oi khi sd dung vi ieu khien do thi gian thc thi lenh cua vi ieu
khien sau moi thi gian nh thi khong the c xac nh mot cach chnh xac. Tuy nhien
ay cung la ng dung hoan chnh nhat va mang tnh thc tien nhieu nhat so vi cac ng dung
trc.
PHU LUC 1 S O KHOI CAC PORT CUA VI IEU KHIEN PIC16F877A

P1.1 PORTA
S o khoi RA3:RA0
S o khoi RA4.
S o khoi RA5
P1.2 PORTB
S o khoi RB3:RB0
S o khoi RB7:RB4
P1.3 PORTC
S o khoi RC7:RC5 va RC2:RC0
S o khoi RC4:RC3
P1.4 PORTD
S o khoi RD7:RD0
P1.5 PORTE
S o khoi RE2:RE0
PHU LUC 2 THANH GHI SFR (SPECIAL FUNCTION REGISTER)

P2.1 Thanh ghi TMR0: a ch 01h, 101h.
Thanh ghi 8 bit cha gia tr cua bo nh thi Timer0.
P2.2 Thanh ghi PCL: a ch 02h, 82h, 102h, 182h.
Thanh ghi cha 8 bit thap cua bo em chng trnh (PC).
P2.3 Thanh ghi STATUS: a ch 03h, 83h, 103h, 183h
Bit 7: IRP
bit chon bank bo nh d lieu can truy xuat (dung cho a ch gian tiep).
IRP = 0: bank 2,3 (t 100h en 1FFh)
IRP = 1: bank 0,1 (t 00h en FFh)
Bit 6,5:RP1:RP0 hai bit chon bank bo nh d lieu can truy xuat (dung cho a ch trc
tiep)
Bit 4:
bit ch th trang thai cua WDT(Watch Dog Timer)

=1 khi vi ieu khien va c cap nguon, hoac sau khi lenh
CLRWDT hay SLEEP c thc thi.
=0 khi WDT b tran
bit ch th trang thai nguon
Bit 3:
= 1 khi vi ieu khien c cap nguon hoac sau lenh CLRWDT
= 0 sau khi lenh SLEEP c thc thi
Bit 2: Z
bit Zero
Z =1 khi ket qua cua phep toan hay logic bang 0
Z = 0 khi ket qua cua phep toan hay logic khac 0
Bit 1: DC
Digit carry/Borrow
DC = 1 khi ket qua phep toan tac ong len 4 bit thap co nh.
DC = 0 khi ket qua phep toan tac ong len 4 bit thap khong co nh.
Bit 0 C
Carry/borrow
C =1 khi ket qua phep toan tac ong len bit MSB co nh.
C=0 khi ket qua phep toan tac ong len bit MSB khong co nh.
P2.4 Thanh ghi SFR: a ch 04h.
Thanh ghi cha con tro a ch gian tiep cua bo nh d lieu.
P2.5 Thanh ghi PORTA: a ch 05h.

Thanh ghi cha gia tr nhan vao hay xuat ra PORTA.
P2.6 Thanh ghi PORTB: a ch 06h, 106h.
Thanh ghi cha gia tr nhan vao hay xuat ra PORTB.
P2.7 Thanh ghi PORTC: a ch 07h.
Thanh ghi cha gia tr nhan vao hay xuat ra PORTC
P2.8 Thanh ghi PORTD: a ch 08h.
Thanh ghi cha gia tr nhan vao hay xuat ra PORTD.
P2.9 Thanh ghi PORTE: a ch 09h.
Thanh ghi cha gia tr nhan vao hay xuat ra PORTE.
P2.10 Thanh ghi PCLATCH: a ch 0Ah, 8Ah, 10Ah, 18Ah.
Thanh ghi ong vai tro la buffer em trong qua trnh ghi gia tr len 5 bit cao cua bo
em chng trnh PC.
P2.11 Thanh ghi INTCON: a ch 0Bh, 8Bh, 10Bh, 18Bh.
Thanh ghi cha cac bit ieu khien va cac bit c hieu khi timer0 b tran, ngat ngoai vi
RB0/INT va ngat interrput-on-change tai cac chan cua PORTB.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
GIE
Global Interrupt Enable bit

GIE = 1 cho phep tat ca cac ngat.
GIE = 0 khong cho phep tat ca cac ngat.
PEIE Pheripheral Interrupt Enable bit
PEIE = 1 cho phep tat ca cac ngat ngoai vi
PEIE = 0 khong cho phep tat ca cac ngat ngoai vi
TMR0IE
Timer0 Overflow Interrupt Enable bit
TMR0IE = 1 cho phep ngat Timer0
TMR0IE = 0 khong cho phep ngat Timer0
RBIE RB0/INT External Interrupt Enable bit
RBIE = 1 cho phep ngat ngoai vi RB0/INT
RBIE = 0 khong cho phep ngat ngoai vi RB0/INT
RBIE RB Port change Interrupt Enable bit
RBIE = 1 cho phep ngat RB Port change
RBIE = 0 khong cho phep ngat RB Port change
Bit 2
Bit 1
Bit 0
TMR0IF
Timer0 Interrupt Flag bit
TMR0IF = 1 thanh ghi TMR0 b tran (phai xoa bang chng
trnh) .
TMR0IF = 0 thanh ghi TMR0 cha b tran.
INTF BR0/INT External Interrupt Flag bit
INTF = 1 ngat RB0/INT xay ra (phai xoa c hieu bang chng
trnh).
INTF = 0 ngat RB0/INT cha xay ra.
RBIF RB Port Change Interrupt Flag bit
RBIF = 1 t nhat co mot chan RB7:RB4 co s thay oi trang
thai.Bit nay phai c xoa bang chng trnh sau khi a kiem tra lai
cac gia tr cua cac chan tai PORTB.
RBIF = 0 khong co s thay oi trang thai cac chan RB7:RB4.
P2.12 Thanh ghi PIR1: a ch 0Ch

Thanh ghi cha c ngat cua cac khoi ngoai vi.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PSPIF
Parallel Slave Port Read/Write Interrupt Flag bit

PSPIF = 1 va hoan tat thao tac oc hoac ghi PSP (phai xoa bang
chng trnh).
PSPIF = 0 khong co thao tac oc ghi PSP nao dien ra.
ADIF
ADC Interrupt Flag bit
ADIF = 1 hoan tat chuyen oi ADC.
ADIF = 0 cha hoan tat chuyen oi ADC.
RCIF
USART Receive Interrupt Flag bit
RCIF = 1 buffer nhan qua chuan giao tiep USART a ay.
RCIF = 0 buffer nhan qua chuan giao tiep USART rong.
TXIF
USART Transmit Interrupt Flag bit
TXIF = 1 buffer truyen qua chuan giao tiep USART rong.
TXIF = 0 buffer truyen qua chuan giao tiep USART ay.
SSPIF
Synchronous Serial Port (SSP) Interrupt Flag bit
SSPIF = 1 ngat truyen nhan SSP xay ra.
SSPIF = 0 ngat truyen nhan SSP cha xay ra.
CCP1IF
CCP1 Interrupt Flag bit
Khi CCP1 che o Capture
CCP1IF=1 a cap nhat gia tr trong thanh ghi TMR1.
CCP1IF=0 cha cap nhat gia tr trong thanh ghi TMR1.
Khi CCP1 che o Compare
CCP1IF=1 gia tr can so sanh bang vi gia tr cha trong TMR1

CCP1IF=0 gia tr can so sanh khong bang vi gia tr trong TMR1.
Bit 1 TMR2IF
TMR2 to PR2 Match Interrupt Flag bit
TRM2IF = 1 gia tr cha trong thanh ghi TMR2 bang vi gia tr cha
trong thanh ghi PR2.
TRM2IF = 0 gia tr cha trong thanh ghi TMR2 cha bang vi gia tr
cha trong thanh ghi PR2.
Bit 0 TMR1IF
TMR1 Overflow Interrupt Flag bit
TMR1IF = 1 thanh ghi TMR1 b tran (phai xoa bang chng trnh).
TMR1IF = 0 thanh ghi TMR1 cha b tran.
P2.13 Thanh ghi PIR2: a ch 0Dh
Bit 7, 5, 2, 1: khong quan tam va mac nh mang gia tr 0.

Bit 6 CMIF
Comparator Interrupt Flag bit
CMIF = 1 tn hieu ngo vao bo so sanh thay oi.
CMIF = 0 tn hieu ngo vao bo so sanh khong thay oi.
Bit 4 EEIF
EEPROM Write Operation Interrupt Flag bit
EEIF = 1 qua trnh ghi d lieu len EEPROM hoan tat.
EEIF = 0 qua trnh ghi d lieu len EEPROM cha hoan tat hoac cha
bat au.
Bit 3 BCLIF
Bus Collision Interrupt Flag bit
BCLIF = 1 Bus truyen nhan ang ban khi (ang co d lieu truyen i
trong bus) khi SSP hat ong che o I2C Master mode.
BCLIF = 0 Bus truyen nhan cha b tran (khong co d lieu truyen i
trong bus).
Bit 0 CCP2IF
CCP2 Interrupt Flag bit
che o Capture
CCP2IF = 1 a cap nhat gia tr trong thanh ghi TMR1.
CCP2IF = 0 cha cap nhat gia tr trong thanh ghi TMR1.
che o Compare
CCP2IF = 1 gia tr can so sanh bang vi gia tr cha trong TMR1.
CCP2IF = 0 gia tr can so sanh cha bang vi gia tr cha trong TMR1.
P2.14 Thanh ghi TMR1L: a ch 0Eh
Thanh ghi cha 8 bit thap cua bo nh thi TMR1.
P2.15 Thanh ghi TMR1H: a ch 0Fh
Thanh ghi cha 8 bit cao cua bo nh thi TMR2.
P2.16 Thanh ghi T1CON: a ch 10h

Thanh ghi ieu khien Timer1.
Bit 7,6
Bit 5,4
Khong quan tam va mang gia tr mac nh bang 0.

T1CKPS1:T1CKPS0 Timer1 Input Clock Prescaler Select bit
11 t so chia tan so cua prescaler la 1:8
Bit 3 T1OSCEN Timer1 Oscillator Enable Control bit
T1OSCEN = 1 cho phep Timer1 hoat ong vi xung do oscillator cung cap.
T1OSCEN = 0 khong cho phep Timer1 hoat ong vi xung do oscillator cung
cap (tat bo chuyen oi xung ben trong Timer1).
Timer1 ternal Clock Input Synchronization Control bit
Bit 2
Khi TMR1CS = 1:
= 1 khong ong bo xung clock ngoai vi a vao Timer1.
= 0 ong bo xung clock ngoai vi a vao Timer1.
Khi TMR1CS = 0
Bit
khong c quan tam do Timer1 s dung xung clock ben
trong.
Bit 1 TMR1CS Timer1 Clock Source Select bit
TMR1CS = 1 chon xung em la xung ngoai vi lay t pin RC0/T1OSC/T1CKI
(canh tac ong la canh len).
TMR1CS = 0 chon xung em la xung clock ben trong (FOSC/4).
Bit 0 TMR1ON Timer1 On bit
TMR1ON = 1 cho phep Timer1 hoat ong.
TMR1ON = 0 Timer1 ngng hoat ong.
P2.17 Thanh ghi TMR2: a ch 11h

Thanh ghi cha gia tr bo em Timer2.
P2.18 Thanh ghi T2CON: a ch 12h
Thanh ghi ieu khien Timer2.
Bit 7 Khong quan tam va mac nh mang gia tr 0

Bit 6-3
TOUTPS3:TOUTPS0 Timer2 Output Postscaler Select bit
Cac bit nay ieu khien viec la chon t so chia tan so cho postscaler.
0000 t so 1:1
0001 t so 1:2
0010 t so 1:3
1111 t so 1:16
Bit 2 TMR2ON Timer2 On bit
TMR2ON = 1 bat Timer2.
TMR2ON = 0 tat Timer2.
Bit 1,0 T2CKPS1:T2CKPS0 Timer2 Clock Prescaler Select bit
Cac bit nay ieu khien t so chi tan so cua prescaler
00
t so 1:1
01
t so 1:4
1x
t so 1:16
P2.19 Thanh ghi SSPBUF: a ch 13h
Thanh ghi em d lieu 8 bit cho chuan giao tiep MSSP.
P2.20 Thanh ghi SSPCON: a ch 14h
Thanh ghi ieu khien chuan giao tiep MSSP.
Khi MSSP che o SPI:

Bit 7 WCOL Write Collition Detect bit
WCOL = 1 d lieu mi c a vao thanh ghi SSPBUF trong khi cha truyen
xong d lieu trc o.
WCOL = 0 khong co hien tng tren xay ra.
Bit 6 SSPOV Receive Overflow Indicalor bit (bit nay ch co tac dung che o SPI
Slave mode).
SSPOV = 1 d lieu trong bufer em (thanh ghi SSPBUF) b tran (d lieu cu
cha c oc th co d lieu mi gi e len).
SSPOV = 0 khong co hien tng tren xay ra.
Bit 5 SSPEN Synchronous Serial Port Enable bit
SSPEN = 1 cho phep cong giao tiep MSSP (cac pin SCK, SDO, SDI va ).
SSPEN = 0 khong cho phep cong giao tiep MSSP.
Bit 4 CKP Clock Polarity Select bit
CKP = 1 trang thai ch cua xung clock la mc logic cao.
CKP = 0 trang thai ch cua xung clock la mc logic thap.
Bit 3-0 SSPM3:SSPM0 Synchronous Serial Mode Select bit
Cac bit nay ong vai tro la chon cac che o hoat ong cua MSSP.
0101 Slave mode, xung clock lay t pin SCK, khong cho phep pin ieu khien
(
la pin I/O bnh thng).
0100 SPI Slave mode, xung clock lay t pin SCK, cho phep pin ieu khien .
0011 SPI Master mode, xung clock bang (ngo ra TMR2)/2.
0010 SPI Master mode, xung clock bang (FOSC/64).
Cac trang thai khong c liet ke hoac khong co tac dung ieu khien hoac ch
co tac dung oi vi che o I2C mode.
Khi MSSP che o I2C
Bit 7 WCOL Write Collition Detect bit
Khi truyen d lieu che o I2C Master mode:
WCOL = 1 a d lieu truyen i vao thanh ghi SSPBUF trong khi che o
truyen d lieu cua I2C cha san sang.
WCOL = 0 khong xay ra hien tng tren.
khi truyen d lieu che o I2C Slave mode:
WCOL = 1 d lieu mi c a vao thanh ghi SSPBUF trong khi d lieu cu
cha c truyen i.
WCOL = 0 khong co hien tng tren xay ra.
che o nhan d lieu (Master hoac Slave):
Bit nay khong co tac dung ch thi cac trang thai.
Bit 6 SSPOV Receive Overflow Indicator Flag bit.
Khi nhan d lieu:
SSPOV = 1 d lieu mi c nhan vao thanh ghi SSPBUF trong khi d lieu cu
cha c oc.
SSPOV = 0 khong co hien tng tren xay ra.
Khi truyen d lieu:
Bit nay khong co tac dung ch th cac trang thai.
Bit 5 SSPEN Synchronous Serial Port Enable bit
SSPEN = 1 cho phep cong giao tiep MSSP (cac pin SDA va SCL).
SSPEN = 0 khong cho phep cong giao tiep MSSP.
Can chu y la cac pin SDA va SCL phai c ieu khien trang thai bang cac bit
tng ng trong thanh ghi TRISC trc o).
Bit 4 CKP SCK Release Control bit
che o Slave mode:
CKP = 1 cho xung clock tac ong.
CKP = 0 gi xung clock mc logic thap (e bao am thi gian thiet lap d
lieu).
Bit 3,0 SSPM3:SSPM0
Cac bit nay ong vai tro la chon cac che o hoat ong cua MSSP.
1111 I2C Slave mode 10 bit a ch va cho phep ngat khi phat hien bit Start va
bit Stop.
1110 I2C Slave mode 7 bit a ch va cho phep ngat khi phat hien bit Start va
bit Stop.
1011 I2C Firmwave Controlled Master mode (khong cho phep che o Slave).
1000 I2C Master mode, xung clock = FOSC/(4*(SSPADD+1)).
0111 I2C Slave mode 10 bit a ch.
Cac trang thai khong c liet ke hoac khong co tac dung ieu khien hoac ch co tac
dung oi vi che o SPI mode.
P2.21 Thanh ghi CCPR1L: a ch 15h
Thanh ghi cha 8 bit thap cua khoi CCP1.
P2.22 Thanh ghi CCPR1H: a ch 16h
Thanh ghi cha 8 bit cao cua khoi CCP1.
P2.23 Thanh ghi CCP1CON va thanh ghi CCP2CON: a ch 17h (CCP1CON) va 1Dh
(SSP2CON)
Thanh ghi ieu khien khoi CCP1.
Bit 7,6 Khong co tac dung va mac nh mang gia tr 0.

Bit 5,4 CCPxX:CCPxY: PWM least Significant bits (cac bit nay khong co tac dung
che o Capture va Compare)
che o PWM, ay la 2 bit MSB cha gia tr tnh o rong xung (duty cycle)
cua khoi PWM (8 bit con lai c cha trong thanh ghi CCPRxL).
Bit 3-0 CCPxM3:CCPxM0 CCPx Mode Select bit
Cac bit dung e xac lap cac che o hoat ong cua khoi CCPx
0000 khong cho phep CCPx (hoac dung e reset CCPx)
0100 CCPx hoat ong che o Capture, hien tng c thiet lap la moi
canh xuong tai pin dung cho khoi CCPx.
canh len tai pin dung cho khoi CCPx.
canh len th 4 tai pin dung cho khoi CCPx.
canh len th 16 tai pin dung cho khoi CCPx.
1000 CCPx hoat ong che o Compare, ngo ra c a len mc cao va bit
CCPxIF c set khi cac gia tr can so sanh bang nhau.
1001 CCPx hoat ong che o Compare, ngo ra c xuong mc thap va bit
CCPxIF c set khi cac gia tr can so sanh bang nhau.
1010 CCPx hoat ong che o Compare, khi cac gia tr can so sanh bang
nhau, ngat xay ra, bit CCPxIF c set va trang thai pin output khong b anh
hng.
1011 CCPx hoat ong che o Compare, khi cac gia tr can so sanh bang
nhau, xung trigger ac biet (Trigger Special Event) se c tao ra, khi o c
ngat CCPxIF c set, cac pin output khong thay oi trang thai, CCp1 reset
Timer1, CCP2 reset Timer1 va khi ong khoi ADC.
11xx CCPx hoat ong che o PWM.
P2.24 Thanh ghi RCSTA: a ch 18h
Thanh ghi cha cac bit trang thai va cac bit ieu khien qua trnh nhan d lieu qua
chuan giao tiep USART.
Bit 7
SPEN Serial Port Enable bit

SPEN = 1 Cho phep cong giao tiep USART (pin RC7/RX/DT va RC6/TX/CK).
SPEN = 0 khong cho phep cong giao tiep USART.
Bit 6 RX9 9-bit Receive Enable bit
RX9 = 1 nhan 9 bit d lieu.
RX9 = 0 nhan 8 bit d lieu.
Bit 5 SREN Single Receive Enable bit
che o USART bat ong bo: bit nay khong can quan tam.
che o USART Master ong bo:
SREN = 1 cho phep chc nang nhan 1 byte d lieu (8 bit hoac 9 bit).
SREN = 0 khong cho phep chc nang nhan 1 byte d lieu.
Bit 4 CREN Continous Receive Enable bit
che o bat ong bo:
CREN = 1 cho phep nhan 1 chuoi d lieu lien tuc.
CREN = 0 khong cho phep nhan 1 chuoi d lieu lien tuc.
che o bat ong bo:
CREN = 1 cho phep nhan d lieu cho ti khi xoa bit CREN.
CREN = 0 khong cho phep nhan chuoi d lieu.
Bit 3 ADDEN Address Detect Enable bit
che o USART bat ong bo 9 bit
ADDEN = 1 cho phep xac nhan a ch, khi bit RSR<8> c set th ngat c
cho phep thc thi va gia tr trong buffer c nhan vao.
ADDEN = 0 khong cho phep xac nhan iz5 ch, cac byte d lieu c nhan
vao va bit th 9 co the c s dung nh la bit parity.
Bit 2
FERR Framing Eror bit

FERR = 1 xuat hien loi Framing trong qua trnh truyen nhan d lieu.
FERR = 0 khong xuat hien loi Framing trong qua trnh truyen nhan d lieu.
Bit 1 OERR Overrun Error bit,
OERR = 1 xuat hien loi Overrun
OERR = 0 khong xuat hien loi Overrun
Bit 0 RX9D
Bit nay cha bit d lieu th 9 cua d lieu truyen nhan.
P2.25 Thanh ghi XTREG: a ch 19h
Thanh ghi ong vai tro la buffer em 8 bit trong qua trnh truyen d lieu thong qua
chuan giao tiep USART.
P2.26 Thanh ghi RCREG: a ch 1Ah
Thanh ghi ong vai tro la buffer em trong qua trnh nhan d lieu qua chuan giao tiep
USART.
P2.27 Thanh ghi CCPR2L: a ch 1Bh
Thanh ghi cha 8 bit thap cua khoi CCP2.
P2.28 Thanh ghi CCPR2H: a ch 1Ch
Thanh ghi cha 8 bit cao cua khoi CCP2.
P2.29 Thanh ghi ADRESH: a ch 1Eh
Thanh ghi cha byte cao cua ket qua qua trnh chuyen oi ADC.
P2.30 Thanh ghi ADCON0: a ch 1Fh
ay la mot trong hai thanh ghi ieu khien khoi chuyen oi ADC. Thanh ghi con lai la
thanh ghi ADCON1 (a ch 9Fh)
Bit 7,6 ADCS1:ADCS0 A/D Conversion Clock Select bit
Bit 5-3 CHS2:CHS0 Analog Channel Select bit

Cac bit nay dung e chon kenh chuyen oi ADC
000 kenh 0 (AN0)
001 kenh 1 (AN1)
010 kenh 2 (AN2)
011 kenh 3 (AN3)
100 kenh 4 (AN4)
101 kenh 5 (AN5)
110 kenh 6 (AN6)
111 kenh 7 (AN7)
Bit 2
A/D Conversion Status bit
Khi ADON = 1
= 1 A/D ang hoat ong (set bit nay se lam khi ong ADC va t xoa
khi qua trnh chuyen oi ket thuc).
= 0 A/D khong hoat ong.
Bit 1 Khong can quan tam va mac nh mang gia tr 0.
Bit 0 ADON A/D On bit
ADON = 1 bat A/D
ADON = 0 tat A/D
P2.31 Thanh ghi OPTION_REG: a ch 81h, 181h
Thanh ghi nay cho phep ieu khien chc nang pull-up cua cac pin trong PORTB, xac
lap cac tham so vexung tac ong, canh tac ong cua ngat ngoai vi va bo em Timer0.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PORTB pull-up enable bit

= 1 khong cho phep chc nang pull-up cua PORTB
= 0 cho phep chc nang pull-up cua PORTB
INTEDG Interrupt Edge Select bit
INTEDG = 1 ngat xay ra khi canh dng chan RB0/INT xuat hien.
INTEDG = 0 ngat xay ra khi canh am chan BR0/INT xuat hien.
TOCS Timer0 Clock Source select bit
TOSC = 1 clock lay t chan RA4/TOCK1.
TOSC = 0 dung xung clock ben trong (xung clock nay bang vi xung clock
dung e thc thi lenh).
TOSE Timer0 Source Edge Select bit
TOSE = 1 tac ong canh len.
TOSE = 0 tac ong canh xuong.
PSA Prescaler Assignment Select bit
PSA = 1 bo chia tan so (prescaler) c dung cho WDT
PSA = 0 bo chia tan so c dung cho Timer0

Bit 2:0 PS2:PS0 Prescaler Rate Select bit
Cac bit nay cho phep thiet lap t so chia tan so cua Prescaler.
P2.32 Thanh ghi TRISA: a ch 85h

Thanh ghi ieu khien xuat nhap cua cac pin trong PORTA.
P2.33 Thanh ghi TRISB: a ch 86h, 186h
Thanh ghi ieu khien xuat nhap cua cac pin trong PORTB.
P2.34 Thanh ghi TRISC: a ch 87h
Thanh ghi ieu khien xuat nhap cua cac pin trong PORTC.
P2.35 Thanh ghi TRISD: a ch 88h
Thanh ghi ieu khien xuat nhap cua cac pin trong PORTD.
P2.36 Thanh ghi TRISE: a ch 89h
Thanh ghi ieu khien xuat nhap cua cac pin trong PORTE, ieu khien cong giao tiep
song song PSP (Parallel Slave Port).
Bit 7 BIF Input Buffer Full Status bit

BIF = 1 mot Word d lieu va c nhan va ang ch CPU oc vao.
BIF = 0 cha co Word d lieu nao c nhan.
Bit 6 OBF Output Buffer Full Status bit
OBF = 1 Buffer truyen d lieu van con cha d lieu cu va van cha c oc.
OBF = 0 Buffer truyen d lieu a c oc.
Bit 5 IBOV Input Buffer Overflow Detect bit
IBOV = 1 d lieu c ghi len buffer trong khi d lieu cu van cha c oc.
IBOV = 0 buffer cha b tran.
Bit 4 PSPMODE Parallel Slave Port Mode Select bit
PSPMODE = 1 Cho phep PSP, PORTD ong vai tro la cong giao tiep song
song PSP.
PSPMODE = 0 Khong cho phep PSP.

.
Bit 2 Bit2 Direction Control for pin
Bit2 = 1 Input
Bit2 = 0 Output
Bit 1 Bit1 Direction Control for pin
Bit1 = 1 Input
Bit1 = 0 Output
Bit 0
Bit0 Direction Control for pin

Bit0 = 1 Input
Bit0 = 0 Output
P2.37 Thanh ghi PIE1: a ch 8Ch

Thanh ghi cha cac bit cho phep cac ngat ngoai vi.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bt 1
Bit 0
PSPIE Parallel Slave Port Read/Write Interrupt Enable bit

PSPIE = 1 cho phep ngat PSP read/write.
PSPIE = 0 khong cho phep nga PSP read/write.
ADIE ADC (A/D converter) Interrupt Enable bit
ADIE = 1 cho phep ngat ADC.
ADIE = 0 khong cho phep ngat ADC.
RCIE USART Receive Interrupt Enable bit
RCIE = 1 cho phep ngat nhan USART
RCIE = 0 khong cho phepn gat nhan USART
TXIE USART Transmit Interrupt Enable bit
TXIE = 1 cho phep ngat truyen USART
TXIE = 0 khong cho phep ngat truyen USART
SSPIE Synchronous Serial Port Interrupt Enable bit
SSPIE = 1 cho phep ngat SSP
SSPIE = 0 khong cho phep ngat SSP
CCP1IE CCP1 Interrupt Enable bit
CCP1IE = 1 cho phep ngat CCP1
CCP1IE = 0 khong cho phep ngat CCP1
TMR2IE TMR2 to PR2 Match Interrupt Enable bit
TMR2IE = 1 cho phep ngat.
TMR2IE = 0 khong cho phep ngat.
TMR1IE TMR1 Overflow Interrupt Enable bit
TMR1IE = 1 cho phep ngat.
TMR1IE = 0 khong cho phep ngat.
P2.38 Thanh ghi PIE2: a ch 8Dh

Thanh ghi cha cac bit cho phep cac ngat ngoai vi.
Bit 7, 5, 2, 1 Khong can quan tam va mac nh mang gia tr 0.

Bit 6 CMIE Comparator Interrupt Enable bit
CMIE = 1 Cho phep ngat cua bo so sanh.
CMIE = 0 Khong cho phep ngat.
Bit 4 EEIE EEPROM Write Operation Interrupt Enable bit
EEIE = 1 Cho phep ngat khi ghi d lieu len bo nh EEPROM.
EEIE = 0 Khong cho phep ngat khi ghi d lieu len bo nh EEPROM.
Bit 3 BCLIE Bus Collision Interrupt Enable bit
BCLIE = 1 Cho phep ngat.
BCLIE = 0 Khong cho phep ngat.
Bit 0 CCP2IE CCP2 Interrupt Enable bit
CCP2IE = 1 Cho phep ngat.
CCP2IE = 0 Khong cho phep ngat.
P2.39 Thanh ghi PCON: a ch 8Eh
Thanh ghi ieu khien
cha cac c hieu cho biet trang thai cac che o reset cua vi ieu khien.
Bit 7, 6, 5, 4, 3, 2 Khong can quan tam va mac nh mang gia tr 0.

Power-on Reset Status bit
Bit 1
= 1 khong co s tac ong cua Power-on Reset.
= 0 co s tac ong cua Power-on reset.
Bit 0
Brown-out Reset Status bit
= 1 khong co s tac ong cua Brown-out reset.
= 0 co s tac ong cua Brown-out reset.
P2.40 Thanh ghi SSPCON2: a ch 91h
Thanh ghi ieu khien cac che o hoat ong cua chuan giao tiep I2C.
Bit 7
GCEN General Call Enable bit

GCEN = 1 Cho phep ngat khi a ch 0000h c nhan vao thanh ghi SSPSR
(a ch cua che o General Call Address).
GCEN = 0 Khong cho phep che o a ch tren.

Bit 6 ACKSTAT Acknowledge Status bit (bit nay ch co tac dung khi truyen d lieu
che o I2C Master mode).
ACKSTAT = 1 nhan c xung
t I2C Slave.
ACKSTAT = 0 chaq nhan c xung
.
Bit 5 ACKDT Acknowledge Data bit (bit nay ch co tac dung khi nhan d lieu che
o I2C Master mode).
ACKDT = 1 cha nhan c xung
.
.
ACKDT = 0 a nhan c xung
Bit 4 ACKEN Acknowledge Sequence Enable bit (bit nay ch co tac dung khi nhan
d lieu che o I2C Master mode)
ACKEN = 1 cho phep xung
xuat hien 2 pin SDA va SCL khi ket thuc
qua trnh nhan d lieu.
ACKEN = 0 khong cho phep tac ong tren.
Bit 3 RCEN Receive Enable bit (bit nay ch co tac dung che o I2C Master mode).
RCEN = 1 Cho phep nhan d lieu che o I2C Master mode.
RCEN = 0 Khong cho phep nhan d lieu.
Bit 2 PEN Stop Condition Enable bit
PEN = 1 cho phep thiet lap ieu kien Stop 2 pin SDA va SCL.
PEN = 0 khong cho phep tac ong tren.
Bit 1 RSEN Repeated Start Condition Enable bit
RSEN = 1 cho phep thiet lap ieu kien Start lap lai lien tuc 2 pin SDA va
SCL.
RSEN = 0 khong cho phep tac ong tren.
Bit 0 SEN Start Condition Enable/Stretch Enable bit
che o Master mode:
SEN = 1 cho phep thiet lap ieu kien Start 2 pin SDA va SCL.
SEN = 0 khong cho phep tac ong tren.
che o Slave mode:
SEN = 1 cho phep khoa xung clock t pin SCL cua I2C Master.
Khong cho phep tac ong tren.
P2.41 Thanh ghi PR2: a ch 92h
Thanh ghi dung e an nh trc gia tr em cho Timer2. Khi vi ieu khien c
reset, PR2 mang gia tr FFh. Khi ta a mot gia tr vao thanh ghi PR2, Timer2 se em t 00h
cho en khi gia tr bo em cua Timer2 bang vi gia tr cua bo em trong thanh ghi PR2. Nh
vay mac nh Timer2 se em t 00h en FFh.
P2.42 Thanh ghi SSPADD: a ch 93h
Thanh ghi cha a ch cua vi ieu khien khi hoat ong chuan giao tiep I2C Slave
mode. Khi khong dung e cha a ch (I2C Master mode) SSPADD c dung e cha gia
tr tao ra xung clock ong bo tai pin SCL.
P2.43 Thanh ghi SSPSTAT: a ch 94h

Thanh ghi cha cac bit trang thai cua chuan giao tiep MSSP.
Khi MSSP hoat ong che o SPI:

Bit 7 SMP Sample bit
SPI Master mode:
SMP = 1 d lieu c lay mau (xac nh trang thai logic) tai thi iem cuoi
xung clock.
SMP = 0 d lieu c lay mau tai thi iem gia xung clock.
SPI Slave mode: bit nay phai c xoa ve 0.
Bit 6 CKE SPI Clock Select bit
CKE = 1 SPI Master truyen d lieu khi xung clock chuyen t trang thai tch
cc en trang thai ch.
CKE = 0 SPI Master truyen d lieu khi xung clock chuyen t trang thai ch
en trang thai tch cc.
(trang thai ch c xac nh bi bit CKP (SSPCON<4>).
Bit 5
bit.
Bit nay ch co tac dung che o I2C mode.
Bit 4 P Stop bit
Bit nay ch s dung khi MSSP che o I2C.
Bit 3 S Start bit
Bit nay ch co tac dung khi MSSP che o I2C.
Bit 2
bit information
Bit 1 UA Update Address bit
Bit 0 BF Buffer Status bit
BF = 1 thanh ghi em SSPBUF a co d lieu.
BF = 0 thanh ghi em SSPBUF cha co d lieu.
Khi hoat ong che o I2C
Bit 7 SPM Slew Rate Control bit
SPM = 1 dung toc o chuan (100 KHz va 1 MHz).
SPM = 0 dung toc o cao ( 400 KHz).
Bit 6 CKE MSBus Select bit
CKE = 1 cho phep MSBus.
CKE = 0 khong cho phep MSBus.
Bit 5
bit
I2C Master mode: khong quan tam.
= 1 byte va truyen i hoac nhan c la d lieu.

= 0 byte va truyen i hoac nhan c la a ch.
Bit 4 P Stop bit
P = 1 va nhan c bit Stop.
P = 0 cha nhan c bit Stop.
Bit 3 S Start bit
S = 1 va nhan c bit Start.
S = 0 cha nhan c bit Start.
Bit 2
bit information
I2C Slave mode:
= 1 oc d lieu.
= 0 ghi d lieu.
I2C Master mode:
= 1 ang truyen d lieu.
= 0 khong truyen d lieu.
Bit 1 UA Update Address
Bit nay ch co tac dung oi vi che o I2C Slave mode10 bit a ch.
UA = 1 vi ieu khien can cap nhat them a ch t thanh ghi SSPADD.
UA = 0 khong can cap nhat them a ch.
Bit 0 BF Buffer Full Status bit
BF = 1 Thanh ghi SSPBUF ang cha d lieu truyen i hoac nhan c.
BF = 0 thanh ghi SSPBUF khong co d lieu.
P2.44 Thanh ghi TXSTA: a ch 98h
Thanh ghi cha cac bit trang thai va ieu khien viec truyen d lieu thong qua chuan
giao tiep USART.
Bit 7 CSRC Clock Source Select bit

che o bat ong bo: khong can quan tam.
che o ong bo:
CSRC = 1 Master mode (xung clock c lay t bo tao xung BRG).
CSRC = 0 Slave mode (xung clock c nhan t ben ngoai).
Bit 6 TX-9 9-bit Transmit Enable bit
TX-9 = 1 truyen d lieu 9 bit.
TX-9 = 0 truyen d lieu 8 bit.
Bit 5 TXEN Transmit Enable bit
TXEN = 1 cho phep truyen.
TXEN = 0 khong cho phep truyen.
Bit 4 SYNC USART Mode Select bit
Bit 3
Bit 2
Bit 1
Bit 0
SYNC = 1 dang ong bo

SYNC = 0 dang bat ong bo.
Khong can quan tam va mac nh mang gia tr 0.
BRGH High Baud Rate Select bit
Bit nay ch co tac dung che o bat ong bo.
BRGH = 1 toc o cao.
BRGL = 0 toc o thap.
TRMT Transmit Shift Register Status bit
TRMT = 1 thanh ghi TSR khong co d lieu.
TRMT = 0 thanh ghi TSR co cha d lieu.
TX9D
Bit nay cha bit d lieu th 9 khi d lieu truyen nhan la 9 bit.
P2.45 Thanh ghi SPBRG: a ch 99h

Thanh ghi cha gia tr tao xung clock cho bo tao xung BRG (Baud Rate Generator).
Tan so xung clock do BRG tao ra c tnh theo cac cong thc trong bang sau:
Trong o X la gia tr cha trong thanh ghi SRBRG.

Thanh ghi CMCON: a ch 9Ch
Thanh ghi ieu khien va ch th cac trang thai cung nh ket qua cua bo so sanh.
Bit 7 C2OUT Comparator 2 (C2) Output bit

Khi C2INV = 0
C2OUT = 1 khi (pin VIN+ cua C2)> (pin VIN- cua C2).
C2OUT = 0 khi (pin VIN+ cua C2) < (pin VIN- cua C2).
Khi C2INV = 1
C2OUT = 1 khi (pin VIN+ cua C2)< (pin VIN- cua C2).
C2OUT = 0 khi (pin VIN+ cua C2) > (pin VIN- cua C2).
Bit 6 C1OUT Comparator 1 (C1) Output bit
Khi C1INV = 0
C1OUT = 1 khi (pin VIN+ cua C1)> (pin VIN- cua C1).
C1OUT = 0 khi (pin VIN+ cua C1) < (pin VIN- cua C1).
Khi C1INV = 1
C1OUT = 1 khi (pin VIN+ cua C1)< (pin VIN- cua C1).
C1OUT = 0 khi (pin VIN+ cua C1) > (pin VIN- cua C1).
Bit 5 C2INV Comparator 2 Output Conversion bit
C2INV = 1 ngo ra C2 c ao trang thai.

C2INV = 0 ngo ra C2 khong ao trang thai.
Bit 4 C1INV Comparator 1 Output Conversion bit
C1INV = 1 ngo ra C1 c ao trang thai.
C1INV = 0 ngo ra C1 khong ao trang thai.
Bit 3 CIS Comparator Input Switch bit
Bit nay ch co tac dung khi CM2:CM0 = 110
CIS = 1 khi pin VIN- cua C1 noi vi RA3/AN3 va
pin VIN- cua C2 noi vi RA2/AN2
CIS = 0 khi pin VIN- cua C1 noi vi RA0/AN0 va
pin VIN- cua C2 noi vi RA1/AN1
Bit 2-0 CM2:CM0 Comparator Mode bit
Cac bit nay ong vai tro trong viec thiet lap cac cau hnh hoat ong cua bo
Comparator. Cac dang cau hnh cua bo Comparator c trnh bay trong bang sau:
Trong o: A la ngo vao Analog, khi o gia tr cua cac pin nay oc t cac PORT luon bang 0.
B la ngo vao Digital.
P2.46 Thanh ghi CVRCON: a ch 9Dh
Thanh ghi ieu khien bo tao ien ap so sanh khi bo Comparator hoat ong vi cau
hnh 110.
Bit 7
CVREN Comparator Voltage Reference Enable bit.

CVREN = 1 bo tao ien ap so sanh c cap ien ap hoat ong.
CVREN = 0 bo tao ien ap so sanh khong c cap ien ap hoat ong.
Bit 6 CVROE Comparator VREF Output Enable bit
CVROE = 1 ien ap do bo tao ien ap so sanh tao ra c a ra pin RA2.
CVROA = 0 ien ap do bo tao ien ap so sanh tao ra khong c a ra ngoai.
Bit 5 CVRR Comparator VREF Range Selection bit
CVRR = 1 mot mc ien ap co gia tr VDD/24 (ien ap do bo tao ien ap so
sanh tao ra co gia tr t 0 en 0.75VDD).
CVRR = 0 mot mc ien ap co gia tr VDD/32 (ien ap do bo tao ien ap so
sanh tao ra co gia tr t 0.25 en 0.75VDD).
Bit 3-0 CVR3:CVR0 Cac bit chon ien ap ngo ra cua bo tao ien ap so sanh.
Khi CVRR = 1:
ien ap tai pin RA2 co gia tr CVREF = (CVR<3:0>/24)*VDD.
Khi CVRR = 0
ien ap tai pin RA2 co gia tr CVREF = (CVR<3:0>/32)*VDD + VDD.
P2.47 Thanh ghi ADRESL: a ch 9Eh
Thanh ghi cha cac bit thap cua ket qua bo chuyen oi A/D (8 bit cao cha trong
thanh ghi ADRESH a ch 1Eh).
P2.48 Thanh ghi ADCON1: a ch 9Fh

Thanh ghi cha cac bit ieu khien bo chuyen oi ADC (ADC co hai thanh ghi ieu
khien la ADCON1 va ADCON0).
Bit 7
ADFM A/D Result Format Select bit

ADFM = 1 Ket qua c lu ve pha ben phai 2 thanh ghi ADRESH:ADRESL
(6 bit cao mang gia tr 0).
ADFM = 0 Ket qua c lu ve pha ben trai 2 thanh ghi ADRESH:ADRESL
(6 bit thap mang gia tr 0).
Bit 6 ADCS2 A/D Conversion Clock Select bit
ADCS2 ket hp vi 2 bit ADCS1:ADCS0 trong thanh ghi ADCON0 e ieu
khien viec chon xung clock cho khoi chuyen oi ADC.
Bit 5,4 Khong can quan tam va mac nh mang gia tr 0.

Bit 3-0 PCFG3:PCFG0 A/D Port Configuration Control bit
Cac bit nay ieu khien viec chon cau hnh hoat ong cac cong cua bo chuyen
oi ADC.
Trong o A la ngo vao Analog.

D la ngo vao Digital.
C/R la so ngo vao Analog/so ien ap mau.
P2.49 Thanh ghi EEDATA: a ch 10Ch
Thanh ghi cha byte thap cua d lieu trong qua trnh ghi oc tren bo nh d lieu
EEPROM.
P2.50 Thanh ghi EEADR: a ch 10Dh
Thanh ghi cha byte thap cua a ch trong qua trnh ghi oc tren bo nh d lieu
EEPROM.
P2.51 Thanh ghi EEDATH: a ch 10Eh
Thanh ghi cha byte cao cua d lieu trong qua trnh ghi oc tren bo nh d lieu
EEPROM (thanh ghi nay ch s dung 6 bit thap).
P2.52 Thanh ghi EEADRH: a ch 10Fh
Thanh ghi cha byte cao cua a ch trong qua trnh ghi oc tren bo nh d lieu
EEPROM (thanh ghi nay ch s dung 4 bit thap).
P2.53 Thanh ghi EECON1: a ch 18Ch
Thanh ghi ieu khien bo nh EEPROM.
Bit 7
EEPGD Program/Data EEPROM Select bit

EEPGD = 1 truy xuat bo nh chng trnh.
EEPGD = 0 truy xuat bo nh d lieu.
Bit 6-4 Khong can quan tam va mac nh mang gia tr 0.
Bit 3 WRERR EEPROM Error Flag bit
WRERR = 1 qua trnh ghi len bo nh b gian oan va khong the tiep tuc (do
cac che o Reset WDT hoac
).
WRERR = 0 qua trnh ghi len bo nh hoan tat.
Bit 2 WREN EEPROM Write Enable bit
WREN = 1 cho phep ghi.
WREN = 0 khong cho phep ghi.
Bit 1 WR Write Control bit
WR = 1 ghi d lieu. Bit nay ch c set bang chng trnh va t ong xoa ve 0
khi qua trnh ghi d lieu hoan tat.
WR = 0 hoan tat qua trnh ghi d lieu.
Bit 0 RD Read Control bit
RD = 1 oc d lieu. Bit nay ch c set bang chng trnh va t ong xoa ve 0
khi qua trnh oc d lieu hoan tat.
RD = 0 qua trnh oc d lieu khong xay ra.
P2.54 Thanh ghi EECON2: a ch 18Dh.
ay la mot trong 2 thanh ghi ieu khien bo nh EEPROM. Tuy nhien ay khong phai
la thanh ghi vat l thong thng va khong cho phep ngi1 s dung truy xuat d lieu tren
thanh ghi.
TAI LIEU THAM KHAO

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CHNG 1 TONG QUAN VE VI IEU KHIEN PIC

CHNG 4 MOT SO NG DUNG CU THE CUA PIC16F877A

CHNG 1 TONG QUAN VE VI IEU KHIEN PIC

Hnh 1.1: Kien truc Havard va kien truc Von-Neuman

Hnh 1.2: C che pipelining

CHNG 2 VI IEU KHIEN PIC16F877A

Hnh 2.1 Vi ieu khien PIC16F877A/PIC16F874A va cac dang s o chan

2.2 MOT VAI THONG SO VE VI IEU KHIEN PIC16F877A

2.3 S O KHOI VI IEU KHIEN PIC16F877A

Hnh 2.2 S o khoi vi ieu khien PIC16F877A.

Hnh 2.3 Bo nh chng trnh PIC16F877A

Bo nh d lieu cua PIC la bo nh EEPROM c chia ra lam nhieu bank. oi vi

Hnh 2.4 S o bo nh d lieu PIC16F877A

2.4.2.1 THANH GHI CHC NANG AC BIET SFR

2.4.2.2 THANH GHI MUC CH CHUNG GPR

2.5 CAC CONG XUAT NHAP CUA PIC16F877A

: cha gia tr cac pin trong PORTA.

Hnh 2.5 S o khoi cua Timer0.

Hnh 2.6 S o khoi cua Timer1.

Hnh 2.7 S o khoi Timer2.

PR2 (a ch 92h): thanh ghi ho tr cho Timer2.

3. i cho ti khi qua trnh lay mau hoan tat.

Hnh 2.8 S o khoi bo chuyen oi ADC.

Hnh 2.9 Cac cach lu ket qua chuyen oi AD.

Tn hieu analog chan VIN + se c so sanh vi ien ap chuan chan VIN- va tn

Hnh 2.10 Nguyen l hoat ong cua mot bo so sanh n gian.

Hnh 2.11 Cac che o hoat ong cua bo comparator.

Cac thanh ghi lien quan en bo so sanh bao gom:

Hnh 2.12 S o khoi bo tao ien ap so sanh.

Khi hoat ong che o Capture th khi co

Hnh 2.13 S o khoi CCP (Capture mode).

Hnh 2.14 S o khoi CCP (Compare mode).

Khi hoat ong che o PWM (Pulse

Hnh 2.15 S o khoi CCP (PWM mode).

Hnh 2.16 Cac tham so cua PWM

Trong o X la gia tr cua thanh ghi RSBRG ( X la so nguyen va 0<X<255).

Cac thanh ghi lien quan en BRG bao gom:

Hnh 2.17 S o khoi cua khoi truyen d lieu USART.

Hnh 2.18 S o khoi cua khoi nhan d lieu USART.

2.12.1.1.2 USART ONG BO

Set bit SYNC, SPEN va clear bit CSRC.

Thanh ghi PIR1 (a ch 0Ch): cha c hieu RCIE.

Hnh 2.20 S o ket noi cua chuan giao tiep SPI.

Hnh 2.21 Gian o xung SPI che o Master mode.

2.12.2.1.2 SPI SLAVE MODE

Thanh ghi TRISC (a ch 87h): ieu khien xuat nhap PORTC.

e xac nh thao tac (oc

Gia tr trong thanh ghi SSPSR c a vao thanh ghi SSPBUF.

Hnh 2.31 S o khoi MSSP (I2C Master mode).

Hnh 2.38 S o khoi cua PORTD va

2.14 TONG QUAN VE MOT SO AC TNH CUA CPU.

Bit 13 CP: (Code Protection)

Bit 1-0 FOSC1:FOSC0 la chon loai oscillator

Hnh 2.41 S o cac che o reset cua PIC16F877A.

2.14.4.1 NGAT INT

2.14.6 CHE O SLEEP

CHNG 3 TAP LENH CUA VI IEU KHIEN PIC

Hnh 3.1 C che ma hoa lenh cua

3.2 TAP LENH CUA VI IEU KHIEN PIC

3.2.5 Lenh BCF

Cu phap: ADDLW k (0 k255)

Cu phap: BCF f,b (0f127, 0b7)