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The document discusses the characteristics of a digital computer's memory unit and instruction set. It notes that the memory unit has 32 bits per word, the instruction set contains 150 different operations with each instruction stored in one word of memory using an opcode and address part. It then poses a series of questions about determining the number of bits needed for the opcode, the maximum memory size, and cache mapping.
Originalbeschreibung:
From the Essentials of Computer Organization and Architecture used for USF CDA3103 Lecture
The document discusses the characteristics of a digital computer's memory unit and instruction set. It notes that the memory unit has 32 bits per word, the instruction set contains 150 different operations with each instruction stored in one word of memory using an opcode and address part. It then poses a series of questions about determining the number of bits needed for the opcode, the maximum memory size, and cache mapping.
The document discusses the characteristics of a digital computer's memory unit and instruction set. It notes that the memory unit has 32 bits per word, the instruction set contains 150 different operations with each instruction stored in one word of memory using an opcode and address part. It then poses a series of questions about determining the number of bits needed for the opcode, the maximum memory size, and cache mapping.
bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. 1. How many bits are needed for the opcode? 2. How many bits are left for the address part of the instruction? 3. What is the maximum allowable size for memory? 4. What is the largest unsigned binary number that can be accommodated in
A digital computer has a memory unit with 32
bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. 5. Assume the memory is byteaddressable. How many bits are in the memory address? 6. If only 1M 8 bits RAM chips are available, how many such chips are needed to build the memory? 7. In a memory address, how many bits are used to select a chip? How many bits are needed to find offset on a chip?
5. Suppose a computer using fully associative
cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. 1. How many blocks of main memory are there?
2. What is the format of a memory address as seen by the
cache, i.e., what are the sizes of the tag and offset fields?
3. To which cache block will the memory address 0x01D87