A

Biwa POWER TOPLOGY AND POWER SEQUENCING

CLK GEN
CK_PWRGD/PD#
DDR_VREF_S3
1D8V_S3
4

PM_SLP_S4#

TPS51100
S5

3b

4b

VTTREF

CLK_PWRGD
PM_SLP_S3# S3
DCBATOUT

5V_AUX_S5

3D3V_AUX_S5

M State

DDR_VREF_S0

1D8V_S3

37

G913

-3

34

DCBATOUT

ICH8M

RTC_RST# RTCRST#

R7
10KR2J-3-GP

SW1

R18
1
2
470R2J-2-GP

2
-1

VCC_POR#

GPIO23

GPIO03

GPIO40 RSMRST#_KBC

C14

WPC8768L PM_PWRBTN#

ECRST#
KBC_PWRBTN#

ISL6236

GPIO36

PWRBTN#

SLP_S4#

RSMRST#

SLP_S3#

PLT_RST1#
PCIRST1#

CLPWROK CPUPG
PWROK
VRMPWRGD

62.40009.631

PLTRST#
PCIRST#

SCD1U16V2ZY-2GP

4
3
SW-TACT-59-GP-U1

RTC

3
5
4

RTC_BAT

-2
S5_ENABLE

5
2
4
SW-TACT-103-GP-U

PURE_HW_SHUTDOWN#

62.40009.631

PM_SLP_M#

ON1
ON2

1
R3852

LX1
PGOOD1
LX2
PGOOD2

1D05V_S0

D31

Power
Wells

AC or
Battery

All wells
powered

Powered

Clock chip powered and PLL

/DLL in use.
Clock chip powered with only
the GMCH clock running and
PLL/DLL in use.
None, ME powered off.

ME Clocking

M1

S3-S5

AC only

Main well down,

M rails down.

In self reflash;ME
DRAM controller is
on,using Channel A

M-off

S3-S5

AC or
Battery

Main well down,

M rails down.

Powered off(or
self reflash

1D8V_LDO_1D25V
GAP-OPEN-PWR
G64
2
1

4a

GAP-OPEN-PWR

CPUCORE_ON
3D3V_S0

S5_ENABLE

PM_SLP_S4#

PM_SLP_S3#

5V_Aux_S5

3D3V_S5

1D8V_S3

1D05V_S0

3D3V_Aux_S5

5V_S5

DDR_VREF_S3

VCC_CORE_S0
DCBATOUT

14

5V_S0

3D3V_S0
5V_S0

13

MAX8770

DDR_VREF_S0

PWRGD VGATE_PWRGD

SHDN#

1D5V_S0

5V_S5

1D25V_S0

5V_S0

DCBATOUT
3

ISL6236

2
0R2J-2-GP

EN1

PHASE1
POK1

EN2

PHASE2
POK2

3V/5V_EN

3D3V_S5

3D3V_S0
U46
1
1

2
U50

BAS16-1-GP

DRAM

System
Power
Source

1D8V_LDO_1D5V
G28

3a

MAX8717
TP49 TPAD30

PM_SLP_S3#

10 8
10

KBC_PWRBTN#_R
1 PWRSW1 3

H_PWRGD

PM_SLP_S4#

S0

M0

VTT

RTC_AUX_S5

Host
System
State

3V/5V_POK

R372 2
1
0R2J-2-GP

1D5V_S0
1D8V_LDO_1D5V

PM_SLP_S3#

4b

APL5912

DY

VGATE_PWRGD

1 R252
2
0R2J-2-GP 2 R255
1
PWROK 0R2J-2-GP
RESET#

PWROK

VOUT
PM_SLP_S3#

EN

5912_POK
POK

R328 1
2
0R2J-2-GP

CPUCORE_ON

10

CPUCORE_ON

G792

PWROK

PWROK_GD

1
R246

CLPWROK_MCH
2
0R2J-2-GP

11
14

1D25V_S0
1D8V_LDO_1D25V

APL5915

4b

12

Crestline

15

PWROK
CPU_CPURST#
CL_PWROK

H_CPURST#

CPU
RESET#
PWRGOOD

RSTIN#

H_PWRGD

PLT_RST1#

PLT_RST1#

13

VOUT
PM_SLP_S3#

EN
POK

5915_POK R229
2
0R2J-2-GP

PCIRST1#

TI 7412

level shift HDDDRV#_5 HDD

2

RESET#

Sequence of Events:
LPC debug BD
(-4)VccRTC active to RTCRST# inactive >18ms.
(-3)Insert ADT, ISL6236 output "5V_AUX_S5", G913(LP2951) output "3D3V_AUX_S5" when 5V_AUX_S5 ready.
(-2)WPC8768L asserts "S5_ENABLE", OR gate enables PWM IC for "5V_S5" ad "3D3V_S5".
Mini Card
PESET#
(-1)WPC8768L drived "RSMRST#_KBC" to ICH8M(rise time 10%-90% <15ns)
(1)User push power botton : "KBC_PWRBTN#" to WPC8768L.
P2231
NEW Card
(2)"PM_PWRBTN#" from KBC to ICH8M.
SYSRST#
(3)ICH8M asserts "PM_SLP_S4#" to enable PWM IC MAX8717 out "1D8V_S3".
1D8V_S3 regulator comes followed by "DDR_VREF_S3" regulators
KBC WPC8768L
LRESET#
(3.1)SLP_S4# inactive to SLP_S3# inactive 1~4 RTCCLK.
(4)ICH8M asserts "PM_SLP_S3#" to enable PWM IC out "1D05V_S0".
LAN BCM5787M
After aprox 10ms soft start delay S0 power switches are turned on connecting S0 planes with S5/S3 planes.
PERST#
5V_S5->"5V_S0",3D3V_S5->"3D3V_S0","1D8V_LDO_1D5V"->"1D5V_S0","1D8V_LDO_1D25V"->"1D25V_S0", "DDR_VREF_S3".
(4.1)V5REF(5V_S0) must be powered up before 3D3V_S0, or after winthin 0.7V. Also V5REF must power down after 3D3V_S0, or before within 0.7V.
(4.2)1D5V_S0 must power up before V_CPU_IO(1D05V_S0) or after winthin 0.7V. Also V_CPU_IO must power down before 1D5V_S0 or after within 0.7V.
(5)PM_SLP_M# : TP.
(6)When 3V, 5V, 1.8V, 1.05V ready, they are asserts "CPUCORE_ON" to PWM IC for CPU power.
(7)5ms after VCC_CORE_S0 regulation, VGATE_PWRGD is driven to ICH8M VRMPWRGD.
(8)"G792_PWROK" Output remains low while VCC is below the reset threshold,
and for 220ms after VCC rises above the reset threshold.
(9)10ms after "VGATE_PWRGD" plane comes up "CLK_PWRGD" is driven.
(10)Power OK for ICH8M(PWROK assertion indicates that PCICLK has been stable for at least 1ms, Vcc supplies active to PWROK >99ms) .
(10.1)VGATE_PWRGD active to PWROK active >3 ms.
(11)CL_PWROK
(12)POWER OK for GMCH
(13)"H_PWRGD" from ICH8M to CPU
(14)"PLT_RST1#"(PCIRST1#) from ICH8M to GMCH.
(14.1)PWROK active to PLTRST1# active 34~41 RTCCLK
(15)"H_CPURST#" from GMCH to CPU
A

bom1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size

POWER SEQUENCING
Document Number

Date: Monday, October 16, 2006

Rev

Biwa
E

SA
Sheet

of