EDA TOOLS

Why EDA?
Imagine a Intel based micro processor
having 1.5 million transistors. Would it be
feasible to design such a complex system
with help of truth table and K-maps?
Obviously Impossible.

Continued
Todays semiconductors and electronic systems
are complex that designing them would be
impossible without electronic design automation
(EDA). This primer provides a comprehensive
over view of the electronic design process, then
describes how design teams use Cadence tools to
create the best possible design in the least amount
of the time.

Digital Design Flow

Design Analysis
Design Specification
Verilog/
VHDL
Library

Std., Cell.
Library

Design Implementation using HDL

Synthesis
Simulation

Look up
Table for
timing

Tech file
For layout
values

Timing Analysis
Place & Route
Extraction

Tech file
For RC
Parasite
extraction

Verification

Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Design Analysis
This is a very crucial step in digital
design where the design functionality
is stated.
Like if we are making a processor,
what type of functionality is expected??

Design Specification
Design Analysis

This step involved stating in definite

terms the performance of the chip.

Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Like if we are making a processor,

data size, processor speed, special
functions, power etc. is clearly stated
at this point. Also somewhat it is decided,
the way to implement the design.
So, it deals with architectural part of the
design at highest level possible.
Based on these foundation , the whole
design is built

HDL
Design Analysis
Design Specification

Hardware Description Language is used

to run the simulations.

Design Implementation using HDL

Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

It is very expensive to build the entire

chip and then verify the performance of
the architecture. Imagine if after designing
a chip for a whole year, the chip fabricated,
does not come even closer to the stated
specifications.

HDL (contd.)
Design Analysis
Design Specification
Design Implementation using HDL

Hardware description languages provides

a way to implement a design without going
into much architecture, simulate and verify
the design output and functionality.

Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

For eg. rather than building a mux design

in hardware, we can write verilog code
and verify the output at higher level
of abstraction.
Examples of HDL: VHDL, Verilog HDL

HDL (Contd.)
Design Analysis
Design Specification

At this time we can see the design

in the form of Source Codes.

Design Implementation using HDL

Synthesis

It seems more of the software

visualization of the circuit.

Simulation
Timing Analysis
Place & Route
Extraction
Verification

The simulated code is taken to

Synthesis to generate the Logic
Circuit.

Synthesis
Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route

Imagine the use of K-Maps and Truth

Tables to make and implement a digital
design.
If you notice, most of the digital designs
are build up of some basic elements or
components like gates, registers, counters,
adders, subtractors, comparators, RAM,
ROM etc.

Extraction
Verification

It forms the fundamentals of Logic

Synthesis using EDA tools.

Synthesis (Contd.)
Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Standard Cell Library is the collection

of such building blocks which comprises
most of the digital designs.
These cell libraries are fabrication
technology specific.

Synthesis ( Contd.)
Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

After the RTL simulation, the HDL,

code is taken as input by Synthesis
Tool and converted to Gate level.
At this stage that the digital design
becomes dependent on the
fabrication process.
At the end of this stage, we have
the logic circuit I.e. in terms of
gates and memories.

Synthesis ( Contd.)
Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation

What synthesis does is , when it

encounters a specific construct
in HDL it replaces it with the
corresponding Standard Cell
Component from the library to
build the entire design.

Timing Analysis
Place & Route
Extraction
Verification

Like if we use a for loop , it gets

converted to counter and a
combinational circuit.

Synthesis ( Contd.)
Design Analysis
Design Specification

The output of synthesis is a gate

level netlist.

Design Implementation using HDL

Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Netlist is an ASCII file which

enlists and indicates the devices
and the interconnections between
them.

Simulation
Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

After the netlist is generated as part

of synthesis, this netlist is simulated
to verify the functionality of this
gate level implementation of design.
Till this level we just dealt with
functionality part. Now each step
onward deals with performance
part too.

Timing Analysis
Design Analysis
Design Specification
Design Implementation using HDL
Synthesis

RTL and Gate Level simulation

doesnt take into account the physical
time delay in signal propagation from
one device to another and through
the device.

Simulation
Timing Analysis
Place & Route
Extraction
Verification

This time delay is dependent on the

fabrication process adopted.

Timing Analysis (Contd.)

Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Each component in standard cell

library is associated with some
specific delay.
Delay Lookup Tables list the
delays associated with the
components.
Delays are in the form of
rise time, fall time and turn off
time delays.

Timing Analysis (Contd.)

Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Most of the digital designs employ

concept of timing by using clocks.
This makes the circuits synchronous.
Consider an AND gate with two inputs,
x and y. If at time t = 1 ns, x is available,
and y comes 1 ns later, what would be
the output. This mismatch in timing
leads to erroneous performance of design.

Timing Analysis (Contd.)

Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

In timing analysis, using Delay

Lookup Tables, all the inputs
and outputs of components are
verified with timing introduced.

Place & Route

Design Analysis
Design Specification
Design Implementation using HDL

This is the actual stage where

the design implemented at
semiconductor layout level.

Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

This the stage which really

requires more knowledge of
semiconductor physics than
digital design.

Place & Route (Contd.)

Design Analysis
Design Specification

Semiconductor layout has to follow

certain design rules to lay devices
at semiconductor level.

Design Implementation using HDL

Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

These design rules are fabrication

process dependent.
The layout uses layers as p/n diffusion,
nwell, pwell, metals, via, iso etc.
Rules involving min. spacing, and
electrical relation between two layers
are known as DESIGN RULES.

Place & Route (Contd.)

Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Placement and Routing involves

laying of the devices, placing them
and making interconnection between
them, following the Design Rules.
The result is the design implemented
in the form of semiconductor layers.

Extraction
Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Once the layout is made, there always

is parasitic capacitances and resistances
associated with the design.
This is because of the compact layouts
to make the chips smaller. More you make
compact layout more will it introduce
these parasitic components. These
interferes in the functioning and
performance of the circuit in terms of
timing, speed and power consumption.

Extraction (Contd.)
Design Analysis
Design Specification
Design Implementation using HDL

Due to these factors it becomes very

much important to extract these devices
from layout and check the design for
performance and functionality.

Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Extraction would extract from the layout,

the devices formed because of junctions
of different semiconductor and metal
layers and the interconnections.

Verification
Design Analysis
Design Specification
Design Implementation using HDL
Synthesis
Simulation
Timing Analysis
Place & Route
Extraction
Verification

Verification would either be the

tape out stage of the chip or the stage
where design is again taken back
through the same flow for
optimization or modification.
It verifies the extracted view of the
chip for performance and functionality.

Major Companies in EDA Tools

Cadence Design Systems
Synopsys
Avanti
Tanner

Cadence
Fact sheet
Cadence is the world's largest provider
of electronic design automation (EDA)
products and services. Our end-to-end
solutions help computer,
communication, and consumer
electronics companies create highperformance systems and integrated
circuits (ICs) in the shortest possible
time. Cadence is a global company
with 5,700 employees in over 30 major
locations, and revenues of nearly $1.3
billion in 2000.

History of Cadence

Cadence Design Systems, Inc. was established in 1988

through the merger of two EDA pioneersECAD, Inc.
and SDA Systems. Through innovative product
development, strategic partnerships, and highly
successful business mergers, Cadence has become the
industry's leading supplier of EDA software technology
and services.

Cadence Design Technologies

System-level Design
Functional Verification
Emulation and Acceleration
Synthesis/Place-and-Route
Analog, RF, and Mixed-signal Design
Custom IC Layout
Physical Verification and Analysis
IC Packaging
PCB Design

Cadence Design Flow

Digital Design:
Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification

NC - Verilog
NC-Family of Simulators

Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification

The Cadence NC family of

simulators (NC-Sim, NCVerilog, NC-VHDL and the
Verilog and VHDL Desktop
simulators) provides a singlekernel simulator that can verify
both mixed-language and mixedsignal designs.

NC Verilog (Contd.)
Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Advantage
Works on the principle of Native
Compilation.
Unlike other compilers it compiles
HDL code directly to machine
executable codes, rather than going
through the intermediate
conversion to C.

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification

It decreases:
Compilation time, Memory
requirement and use of system
resources

NC Verilog (Contd.)
Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification

Key Features
Fastest mixed-language
simulation available due to unique
NC architecture
Powerful integrated debug and
analysis environment
Mixed-language, mixed-signal,
and system-level support

Ambit Buildgates Synthesis

Key Features
Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification

BuildGates Synthesis can

synthesize multimillion-gate
designs very rapidly.
BuildGates features high-capacity
and high-performance timing
analysis.
.

Ambit Buildgates Synthesis

Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification

BuildGates Synthesis can

synthesize multimillion-gate
designs very rapidly.
BuildGates features high-capacity
and high-performance timing
analysis.
.

Ambit Buildgates Synthesis

Contd.
Key Features

Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification

Provides productive multimilliongate synthesis through higher

capacity and faster runtimes
Delivers accuracy and reduced
iterations through integrated signoff static timing analysis
Reduces IC power consumption
with the Low-power Synthesis
Option
.

Ambit Buildgates Synthesis

Contd.
Optimized Design

Standard
Cell
Library
NC-Verilog

Ambit Synthesis

Pearl Static Timing Analysis

Silicon Ensemble
Placement & Route

Hyper Extract Tech. Rules

verification

It can optimize the design for:

Speed
Size
Power Consumption
.

Static Timing Analysis (Pearl)

In this era of high performance
electronics, timing continues to be a top
priority and designers are spending
increased effort addressing IC
performance.
Two Methods are employed for Timing
Analysis:
Dynamic Timing Analysis
Static Timing Analysis

Static Timing Analysis (Pearl)

(Contd.)

Dynamic Timing Analysis

Traditionally, a dynamic simulator has
been used to verify the functionality and
timing of an entire design or blocks
within the design.
Dynamic timing simulation requires
vectors, a logic simulator and timing
information. With this methodology, input
vectors are used to exercise functional
paths based on dynamic timing
behaviors for the chip or block.

Static Timing Analysis (Pearl)

(Contd.)

Dynamic Timing Analysis: Limitations

The advent of larger designs and mammoth vector
sets make dynamic simulation a serious bottleneck
in design flows.
Dynamic simulation is becoming more problematic
because of the difficulty in creating comprehensive
vectors with high levels of coverage.
Time-to-market pressure, chip complexity, limitations
in the speed and capacity of traditional simulators -all are motivating factors for migration towards static
timing techniques.

Static Timing Analysis (Pearl)

(Contd.)
STA is an exhaustive method of analyzing,
debugging and validating the timing performance of
a design.
First, a design is analyzed, then all possible paths
are timed and checked against the requirements.
Since STA is not based on functional vectors, it is
typically very fast and can accommodate very large
designs (multimillion gate designs).
STA is exhaustive in that every path in the design is
checked for timing violations.

Static Timing Analysis (Pearl)

(Contd.)
Limitations:

STA does not verify the functionality of a design.

Also, certain design styles are not well suited for
static approach. For instance, dynamic simulation
may be required for asynchronous parts of a design
and certainly for any mixed-signal portions.

Silicon Ensemble
Place & Route

Future Trends

Verilog AMS
CCAR (Cadence Chip Assemble Router)
VCC
Testbuilder for Verification
PKS (Physically Knowledgeable Synthesis)
ATS