FPGA

Prototyping and Software Construction for ASIC and USB Interface

for Stereo Vision Hardware Accelerator

Sungil Kim1, Ziyun Li2, Hun-Seok Kim2, and David T. Blaauw2
1Department of Electrical and Computer Engineering, Auburn University 200 Broun Hall,

Auburn, AL 36830
2Department of Electrical Engineering and Computer Science, University of Michigan 1301

Beal Avenue, Ann Arbor, MI 48109

ASICs (Application-Specific Integrated Circuits) development cost is increasing due to
emerging design and computational complexity, while time to market is decreasing due to
fast-growing technology. To reduce potential failures and cost, ASIC design that uses FPGA
(Field-Programmable Gate Array) prototyping to verify functionality of the circuit is both
effective and reliable, especially for real-time systems like stereo cameras. We develop a
faster stereo vision hardware accelerator that consumes less power than a GPU-based
stereo camera by addressing the data communication between the ASIC chip, FX3, and host
PC. Yet, streaming from the chip and into the chip needs verification. This study determines
the extent to which functionality of ASICs and Interface between the chip and USB
peripheral controller (FX3) can be verified. Coupled with software verification, FPGA
performs the logic behavior of the chip to run at near real time with data transfer rate of 2
Gigabits per second. As the interface between ASIC and FX3 involves 12 signals (i.e., clock,
flags, read/write strobe, address, 32-bit data), debugging of the behavior requires designers
to observe real-time signals and transitions. Using Xilinx ChipScope Pro, we verify the
handshaking and timing. From the host side, we prototype with compatible software
libraries for USB interfaces. After processing left and right images, the developed software
verifies the bidirectional data transfer. These results suggest FPGA prototyping is
particularly effective for handling real-time signals. The verifying step via FPGA prototyping
can significantly reduce chip failure and manufacturing cost and increase design pace.