VHDL code for 2 to 4 decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity twoto4decvhdl is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end twoto4decvhdl;
architecture Behavioral of twoto4decvhdl is
begin
process (a)
begin
case a is
when "00"=> y<="0001";
when "01"=> y<="0010";
when "10"=> y<="0100";
when "11"=> y<="1000";
when others => null;
end case;
end process;
end Behavioral;

Test bench code for 2 to 4 decoder

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_2to4 IS
END tb_2to4;

ARCHITECTURE behavior OF tb_2to4 IS

COMPONENT twoto4decvhdl
PORT(
a : IN std_logic_vector(1 downto 0);
y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(1 downto 0) := (others => '0');

--Outputs
signal y : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

uut: twoto4decvhdl PORT MAP (

a => a,
y => y
);

- Stimulus process
stim_proc: process
begin
a<="00";
wait for 100 ns;
a<="01";
wait for 100 ns;
a<="10";
wait for 100 ns;
a<="11";
wait for 100 ns;
end process;
END;

VHDL code for 8 to 3 encoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity eight23encodervhdl is
Port ( en : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end eight23encodervhdl;
architecture Behavioral of eight23encodervhdl is

begin
process ( En,I)

begin
if En='0' then Y<="XXX";
else
case I is
when"00000001"=>Y<="000";
when"00000010"=>Y<="001";
when"00000100"=>Y<="010";
when"00001000"=>Y<="011";
when"00010000"=>Y<="100";
when"00100000"=>Y<="101";
when"01000000"=>Y<="110";
when"10000000"=>Y<="111";
when others=> null;
end case;
end if;
end process;
end Behavioral;

Testbench code for 8 to 3 encoder

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_eight23 IS

END tb_eight23;
ARCHITECTURE behavior OF tb_eight23 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT eight23encodervhdl
PORT(
en : IN std_logic;
I : IN std_logic_vector(7 downto 0);
Y : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal en : std_logic := '0';
signal I : std_logic_vector(7 downto 0) := (others => '0');

--Outputs
signal Y : std_logic_vector(2 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: eight23encodervhdl PORT MAP (
en => en,
I => I,
Y => Y
);
-- Stimulus process

stim_proc: process
begin
en<='1';
I<="00000001" ;
wait for 100 ns;
I<="00000010" ;
wait for 100 ns;
I<="00000100";
wait for 100 ns;
I<="00001000";
wait for 100 ns;
I<="00010000";
wait for 100 ns;
I<="00100000"
;

wait for 100 ns;

end process;

END;

VHDL Code for 8 to 3 encoder with priority

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity eight23wpvhdl is
Port ( En : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (7 downto 0);

Y : out STD_LOGIC_VECTOR (2 downto 0));

end eight23wpvhdl;
architecture Behavioral of eight23wpvhdl is
begin
process ( En,I)
begin
if En='0' then Y<="XXX";
elsif I(7)='1' then Y<="111";
elsif I(6)='1' then Y<="110";
elsif I(5)='1' then Y<="101";
elsif I(4)='1' then Y<="100";
elsif I(3)='1' then Y<="011";
elsif I(2)='1' then Y<="010";
elsif I(1)='1' then Y<="001";
elsif I(0)='1' then Y<="000";
else Y<="ZZZ";
end if;
end process;
end Behavioral;
Test bench code for 8 to 3 encoder with priority
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_eight23wpvhdl IS
END tb_eight23wpvhdl;
ARCHITECTURE behavior OF tb_eight23wpvhdl IS
-- Component Declaration for the Unit Under Test (UUT)

COMPONENT eight23wpvhdl
PORT(
En : IN std_logic;
I : IN std_logic_vector(7 downto 0);
Y : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal En : std_logic := '0';
signal I : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Y : std_logic_vector(2 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: eight23wpvhdl PORT MAP (
En => En,
I => I,
Y => Y
);
-- Stimulus process
stim_proc: process
begin
en<='1';
I(7)<='1';

I(6)<='0';
I(5)<='0';
I(4)<='0';
I(3)<='0';
I(2)<='0';
I(1)<='0';
I(0)<='0';
wait for 100 ns;
en<='1';
I(7)<='0';
I(6)<='1';
I(5)<='0';
I(4)<='0';
I(3)<='0';
I(2)<='0';
I(1)<='0';
I(0)<='0';
wait for 100 ns;
en<='1';
I(7)<='0';
I(6)<='1';
I(5)<='1';
I(4)<='0';
I(3)<='0';
I(2)<='0';
I(1)<='0';

I(0)<='0';
end process;
END;
VHDL Code for 8 to 1 multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity eightto1muxvhd is
Port ( En : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (2 downto 0);
D : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC);
end eightto1muxvhd;
architecture Behavioral of eightto1muxvhd is
begin
process ( S,D,En)
begin
if En='1' then Y<='0';
else
case S is
when "000"=>Y<=D(0);
when "001"=>Y<=D(1);
when "010"=>Y<=D(2);
when "011"=>Y<=D(3);
when "100"=>Y<=D(4);
when "101"=>Y<=D(5);
when "110"=>Y<=D(6);

when "111"=>Y<=D(7);
when others=> Y<='Z';
end case;
end if;
end process;
end Behavioral;
Test bench code for 8 to 1 multiplexer
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_eightto1muxvhd IS
END tb_eightto1muxvhd;
ARCHITECTURE behavior OF tb_eightto1muxvhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT eightto1muxvhd
PORT(
En : IN std_logic;
S : IN std_logic_vector(2 downto 0);
D : IN std_logic_vector(7 downto 0);
Y : OUT std_logic
);
END COMPONENT;
--Inputs
signal En : std_logic := '0';
signal S : std_logic_vector(2 downto 0) := (others => '0');
signal D : std_logic_vector(7 downto 0) := (others => '0');
--Outputs

signal Y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: eightto1muxvhd PORT MAP (
En => En,
S => S,
D => D,
Y => Y
);
-- Stimulus process
stim_proc: process
begin
En<='0';
S<="000";
D<="00000001";
wait for 100 ns;
S<="001";
D<="00000010";
wait for 100 ns;
S<="010";
D<="00000100";
wait for 100 ns;

S<="011";
D<="00001000";
wait for 100 ns;
S<="100";
D<="00010000";
wait for 100 ns;
S<="101";
D<="00100000";
wait for 100 ns;
S<="110";
D<="01000000";
wait for 100 ns;
S<="111";
D<="10000000";
wait for 100 ns;
end process;
END;

VHDL Code for 4 bit comparator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cmparatorvhdl is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
AEQB : out STD_LOGIC;
AGTB : out STD_LOGIC;

ALTB : out STD_LOGIC);

end cmparatorvhdl;
architecture Behavioral of cmparatorvhdl is
begin
process(A,B)
begin
if A=B then AEQB<='1'; AGTB<='0';ALTB<='0';
elsif A>B then AEQB<='0';AGTB<='1';ALTB<='0';else AEQB<='0';AGTB<='0';
ALTB<='1';
end if;
end process;
end Behavioral;
Test bench code for comparator
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_cmparator IS
END tb_cmparator;
ARCHITECTURE behavior OF tb_cmparator IS
COMPONENT cmparatorvhdl
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
AEQB : OUT std_logic;
AGTB : OUT std_logic;
ALTB : OUT std_logic
);

END COMPONENT;

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal AEQB : std_logic;
signal AGTB : std_logic;
signal ALTB : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cmparatorvhdl PORT MAP (
A => A,
B => B,
AEQB => AEQB,
AGTB => AGTB,
ALTB => ALTB
);
-- Stimulus process
stim_proc: process
begin
A<="0000";
B<="1001";
wait for 100 ns;
A<="0010";
B<="1001";

wait for 100 ns;

A<="1010";
B<="1001";
wait for 100 ns;
A<="1010";
B<="1001";
wait for 100 ns;
A<="1110";
B<="1001";
wait for 100 ns;
A<="1010";
B<="1011";
wait for 100 ns;
A<="1010";
B<="1101";
wait for 100 ns;
A<="0010";
B<="1011";
wait for 100 ns;
A<="1111";
B<="1001";
wait for 100 ns;
A<="1111";
B<="1111";
wait for 100 ns;
A<="0100";

B<="1010";
wait for 100 ns;
A<="1010";
B<="1010";
end process;
END;

VHDL Code for Binary to gray converter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity btog is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
g : out STD_LOGIC_VECTOR (3 downto 0));
end btog;
architecture Behavioral of btog is
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor b(0);
end Behavioral;

Test bench code for binary to gray converter

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
ENTITY adsdsdsd IS
END adsdsdsd;
ARCHITECTURE behavior OF adsdsdsd IS
COMPONENT btog
PORT(
b : IN std_logic_vector(3 downto 0);
g : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal g : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: btog PORT MAP (
b => b,
g => g
);
-- Stimulus process
stim_proc: process
begin

b(3)<='0';
b(2)<='0';
b(1)<='0';
b(0)<='0';
wait for 100 ns;
b(3)<='0';
b(2)<='0';
b(1)<='0';
b(0)<='1';
wait for 100 ns;
b(3)<='0';
b(2)<='0';
b(1)<='1';
b(0)<='0';
wait for 100 ns;
b(3)<='0';
b(2)<='0';
b(1)<='1';
b(0)<='1';
wait for 100 ns;
b(3)<='0';
b(2)<='1';
b(1)<='0';
b(0)<='0';
wait for 100 ns;
b(3)<='0';

b(2)<='1';
b(1)<='0';
b(0)<='1';
wait for 100 ns;
b(3)<='0';
b(2)<='1';
b(1)<='1';
b(0)<='0';
wait for 100 ns;
b(3)<='0';
b(2)<='1';
b(1)<='1';
b(0)<='1';
wait for 100 ns;
b(3)<='1';
b(2)<='0';
b(1)<='0';
b(0)<='0';
wait for 100 ns;
b(3)<='1';
b(2)<='0';
b(1)<='0';
b(0)<='1';
wait for 100 ns;
b(3)<='1';
b(2)<='0';

b(1)<='1';
b(0)<='0';
wait for 100 ns;
b(3)<='1';
b(2)<='0';
b(1)<='1';
b(0)<='1';
wait for 100 ns;
b(3)<='1';
b(2)<='1';
b(1)<='0';
b(0)<='0';
wait for 100 ns;
b(3)<='1';
b(2)<='1';
b(1)<='0';
b(0)<='1';
wait for 100 ns;
b(3)<='1';
b(2)<='1';
b(1)<='1';
b(0)<='0';
wait for 100 ns;
b(3)<='1';
b(2)<='1';
b(1)<='1';

b(0)<='1';
wait for 100 ns;
end process;
END;
VHDL code for full adder (dataflow)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Fulladdervhdl is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC
);
end Fulladdervhdl;
architecture Behavioral of Fulladdervhdl is

signal X: STD_LOGIC;
begin
X <=(a xor b) and Cin;
Sum<= a xor b xor Cin;
Carry<= X or ( a and b);
end Behavioral;
Test bench code for Full adder (data flow)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fdad IS
END fdad;
ARCHITECTURE behavior OF fdad IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Fulladdervhdl
PORT(
a : IN std_logic;
b : IN std_logic;
Cin : IN std_logic;
Sum : OUT std_logic;
Carry : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal Cin : std_logic := '0';
--Outputs
signal Sum : std_logic;
signal Carry : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: Fulladdervhdl PORT MAP (

a => a,
b => b,
Cin => Cin,
Sum => Sum,
Carry => Carry
);
-- Stimulus process
stim_proc: process
begin
a<='0';
b<='0';
cin<='0';

wait for 100 ns;

a<='0';
b<='0';
cin<='1';
wait for 100 ns;
a<='0';
b<='1';
cin<='0';
wait for 100 ns;
a<='0';
b<='1';
cin<='1';

wait for 100 ns;

a<='1';
b<='0';
cin<='0';
wait for 100 ns;
a<='1';
b<='0';
cin<='1';
wait for 100 ns;
a<='1';
b<='1';
cin<='0';
wait for 100 ns;
a<='1';
b<='1';
cin<='1';
wait for 100 ns;
end process;
END;
VHDL code for Full adder in Behavioral model
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Fadderbehavoural is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
Sum : out STD_LOGIC;

Carry : out STD_LOGIC);

end Fadderbehavoural;
architecture Behavioral of Fadderbehavoural is
begin
process ( a)
begin
case a is
when "000"=> Sum<='0';Carry<='0';
when "001"=> Sum<='1';Carry<='0';
when "010"=> Sum<='1';Carry<='0';
when "011"=> Sum<='0';Carry<='1';
when "100"=> Sum<='1';Carry<='0';
when "101"=> Sum<='0';Carry<='1';
when "110"=> Sum<='0';Carry<='1';

when "111"=> Sum<='1';Carry<='1';

when others=> null;
end case;
end process;
end Behavioral;

Test bench code for Full adder (Behavioral model ) is same as the above

VHDL code for Full adder (Structural model)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_g is
port ( a: in std_logic;
b: in std_logic;
c:out std_logic);
end or_g;
architecture behavioural of or_g is
begin
c<= a or b;
end behavioural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_g is
port ( a: in std_logic;
b: in std_logic;
c:out std_logic);
end and_g;
architecture behavioural of and_g is
begin
c<= a and b;
end behavioural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_g is
port ( a: in std_logic;

b: in std_logic;
c:out std_logic);
end xor_g;
architecture behavioural of xor_g is
begin
c<= a xor b;
end behavioural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Faddstruct is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end Faddstruct;
architecture Behavioral of Faddstruct is
component or_g is
port( a,b: in std_logic;
c:out std_logic);
end component;
component and_g is
port (a,b: in std_logic;
c:out std_logic);
end component;
component xor_g is

port ( a,b: in std_logic;

c: out std_logic);
end component;
signal y1,y2,y3:STD_LOGIC;
begin
X1: xor_g port map (A,B,y1);
a1: and_g port map ( A,B,y2);
X2: xor_g port map( y1,Cin, Sum);
a2: and_g port map ( y1,Cin,y3);
r1: or_g port map ( y2,y3,Cout);
end Behavioral;
Testbench code for Full adder ( Struct) is same as the above

VHDL code for DFF with Asynchronous reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dffvhd is
Port ( clk : in STD_LOGIC;
Rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end dffvhd;
architecture Behavioral of dffvhd is
begin
process(clk,D,Rst)
begin

if Rst='1' then Q<='0';

elsif (rising_edge(clk)) then
Q<=D;
end if;
end process;
end Behavioral;
Test bench code for DFF with Asynchronous reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_dffvhd IS
END tb_dffvhd;

ARCHITECTURE behavior OF tb_dffvhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT dffvhd
PORT(
clk : IN std_logic;
Rst : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';

signal Rst : std_logic := '0';

signal D : std_logic := '0';
--Outputs
signal Q : std_logic;
-- Clock period definitions
constant clk_period : time := 100 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: dffvhd PORT MAP (
clk => clk,
Rst => Rst,
D => D,
Q => Q
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process

stim_proc: process
begin
Rst<='0';
D<='0';
wait for 100 ns;

Rst<='0';
D<='1';
wait for 100 ns;

Rst<='1';
D<='0';
wait for 100 ns;
Rst<='1';
D<='1';
wait for 100 ns;
Rst<='0';
D<='0';
wait for 100 ns;
Rst<='1';
D<='0';
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here

end process;

END;

VHDL code for DFF with synchronous reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dffsrstvhd is
Port ( clk : in STD_LOGIC;
Rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end dffsrstvhd;
architecture Behavioral of dffsrstvhd is
begin
process
begin
wait until clk'event and clk='1';
If Rst='1' then Q<='0';
elsif (rising_edge(clk)) then
Q<=D;
end if;
end process;
end Behavioral;
Testbench code for DFF with Synchronous reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_dffsrstvhd IS

END tb_dffsrstvhd;
ARCHITECTURE behavior OF tb_dffsrstvhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dffsrstvhd
PORT(
clk : IN std_logic;
Rst : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal Q : std_logic;
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dffsrstvhd PORT MAP (
clk => clk,
Rst => Rst,
D => D,
Q => Q
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
Rst<='0';
D <='0';
wait for 100 ns;
Rst<='0';
D <='1';
wait for 100 ns;
Rst <='1';
D <='0';
wait for 100 ns;
Rst <='1';
D <='1';
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

end process;
END;
VHDL code for TFF with Asynchronous reset
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tffasrst is
Port ( clk : in STD_LOGIC;
data :in std_logic;
reset : in STD_LOGIC;
q : out STD_LOGIC
);
end tffasrst;
architecture Behavioral of tffasrst is
signal t: std_logic;
begin
process (clk,reset)
begin
if ( reset='0') then
t<='0';
elsif (rising_edge(clk)) then
t<=not t;
end if;
end process;
q<=t;
end Behavioral;

Test bench code for TFF with Asynchronous reset

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY gdfd IS
END gdfd;
ARCHITECTURE behavior OF gdfd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT tffasrst
PORT(
clk : IN std_logic;
data : IN std_logic;
reset : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal data : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal q : std_logic;

-- Clock period definitions

constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: tffasrst PORT MAP (
clk => clk,
data => data,
reset => reset,
q => q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
data<='0';
reset<='0';

wait for 100 ns;

data<='0';
reset<='1';
wait for 100 ns;
data<='1';
reset<='0';
wait for 100 ns;
data<='1';
reset<='1';
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
end process;
END;
VHDL code for TFF with Synchronous reset
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tffsrstvhd is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Q : out STD_LOGIC);
end tffsrstvhd;

architecture Behavioral of tffsrstvhd is

signal t: std_logic;

begin
process (clk)
begin
if (rising_edge(clk)) then
if (Rst ='0') then
t<='0';
else
t<= not t;
end if;
end if;
end process;
q<=t;
end Behavioral;
Test bench code for TFF with Synchronous reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fgfg IS
END fgfg;
ARCHITECTURE behavior OF fgfg IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT tffsrstvhd
PORT(
D : IN std_logic;
clk : IN std_logic;
Rst : IN std_logic;
Q : OUT std_logic

);
END COMPONENT;
--Inputs
signal D : std_logic := '0';
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
--Outputs
signal Q : std_logic;
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: tffsrstvhd PORT MAP (
D => D,
clk => clk,
Rst => Rst,
Q => Q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process

stim_proc: process
begin
D<='0';
Rst<='0';
wait for 100 ns;
D<='0';
Rst<='1';
wait for 100 ns;
D<='1';
Rst<='0';
wait for 100 ns;
D<='1';
Rst<='1';
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here
end process;
END;

VHDL code for JK FF with Asynchronous reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jkffasrstvhd is
Port ( clk : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
Rst : in STD_LOGIC;
Q : out STD_LOGIC;
Qbar: out STD_LOGIC
);
end jkffasrstvhd;
architecture Behavioral of jkffasrstvhd is
signal state:std_logic;
signal input: std_logic_vector(1 downto 0);
begin
input<= J & K;
process (clk,Rst) is
begin
if Rst='1' then
state<='0';
elsif( rising_edge(clk)) then
case ( input ) is
when"11"=> state <= not state;
when"10"=> state<='1';
when"01"=> state<='0';
when others=> null;
end case;
end if;

end process;
Q<= state;
Qbar<= not state;
end Behavioral;
Test bench code for JK FF with Asynchronous reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY asadd IS
END asadd;
ARCHITECTURE behavior OF asadd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT jkffasrstvhd
PORT(
clk : IN std_logic;
J : IN std_logic;
K : IN std_logic;
Rst : IN std_logic;
Q : OUT std_logic;
Qbar : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';

signal J : std_logic := '0';

signal K : std_logic := '0';
signal Rst : std_logic := '0';
--Outputs
signal Q : std_logic;
signal Qbar : std_logic;
-- Clock period definitions
constant clk_period : time := 100 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: jkffasrstvhd PORT MAP (
clk => clk,
J => J,
K => K,
Rst => Rst,
Q => Q,
Qbar => Qbar
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;

clk <= '1';

wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
J<='0';
K<='0';
Rst<='1';

wait for 100 ns;

J<='0';
K<='0';
Rst<='0';
wait for 100 ns;
J<='0';
K<='1';
Rst<='0';
wait for 100 ns;
J<='1';
K<='0';
Rst<='0';
wait for 100 ns;
J<='1';

K<='1';
Rst<='0';
wait for 100 ns;
J<='1';
K<='0';
Rst<='1';
wait for 100 ns;
J<='1';
K<='1';
Rst<='1';
wait for 100 ns;
J<='0';
K<='0';
Rst<='1';
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here
wait;
end process;
END;
VHDL code for JK FF with synchronous reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity jkffsrstvhd is
Port ( clk : in STD_LOGIC;
Rst : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
Q : out STD_LOGIC;
clken : in STD_LOGIC);
end jkffsrstvhd;

architecture Behavioral of jkffsrstvhd is

signal State:std_logic;
begin
process(clk)
begin
if (rising_edge(clk)) then
if Rst='1' then
State <= '0';
elsif clken ='1' then
if (J='0' and K='0') then
State <= State;

elsif (J='0' and K='1') then

State <= '0';
elsif (J='1' and K='0') then
State <= '1';
elsif (J='1' and K='1') then
State <= not State;
end if;
end if;
end if;
end process;
Q <= State;
end Behavioral;

Test bench code for JKFF with Synchronous reset

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fdfdf IS
END fdfdf;
ARCHITECTURE behavior OF fdfdf IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT jkffsrstvhd
PORT(
clk : IN std_logic;
Rst : IN std_logic;
J : IN std_logic;

K : IN std_logic;
Q : OUT std_logic;
clken : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal J : std_logic := '0';
signal K : std_logic := '0';
signal clken : std_logic := '0';
--Outputs
signal Q : std_logic;
-- Clock period definitions
constant clk_period : time := 100 ns;
constant clken_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: jkffsrstvhd PORT MAP (
clk => clk,
Rst => Rst,
J => J,
K => K,
Q => Q,
clken => clken
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
clken_process :process
begin
clken <= '0';
wait for clken_period/2;
clken <= '1';
wait for clken_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
J<='0';
K<='0';
Rst<='0';
wait for 100 ns;
J<='0';
K<='0';
Rst<='1';
wait for 100 ns;

J<='0';
K<='1';
Rst<='0';
wait for 100 ns;
J<='0';
K<='1';
Rst<='1';
wait for 100 ns;
J<='1';
K<='0';
Rst<='0';
wait for 100 ns;
J<='1';
K<='0';
Rst<='1';
wait for 100 ns;
J<='1';
K<='1';
Rst<='0';
wait for 100 ns;
J<='1';
K<='1';
Rst<='1';
wait for 100 ns;
wait for clk_period*10;

--insert stimulus here

end process;

END;

VHDL code for BCD counter with Asynchronous reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcdcountervhdasrst is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : buffer STD_LOGIC_VECTOR( 3 downto 0));
end bcdcountervhdasrst;
architecture Behavioral of bcdcountervhdasrst is
begin
process(rst,clk,q)
begin
if rst='1' then q<="0000";
elsif (rising_edge(clk)) then
q<=q + 1;
if q ="1111" then q<="0000";
end if;
end if;

end process;
end Behavioral;
Test bench code for BCD counter with Asynchronous reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ggdgdfd IS
END ggdgdfd;
ARCHITECTURE behavior OF ggdgdfd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcdcountervhdasrst
PORT(
rst : IN std_logic;
clk : IN std_logic;
q : Buffer std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal q : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcdcountervhdasrst PORT MAP (

rst => rst,

clk => clk,
q => q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 100 ns;
rst<='0';
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
end process;
END;

VHDL Code for BCD counter with Synchronous reset

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcdcountersrstvhd is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : buffer STD_LOGIC_VECTOR (3 downto 0));
end bcdcountersrstvhd;
architecture Behavioral of bcdcountersrstvhd is
begin
process
begin
wait until (rising_edge(clk));
if rst='1' then Q<="0000";
elsif (rising_edge(clk)) then
Q<=Q+1;
if Q="1111" then Q<="0000";
end if;
end if;
end process;
end Behavioral;

Test bench code for BCD counter with synchronous reset

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY asascvcv IS

END asascvcv;
ARCHITECTURE behavior OF asascvcv IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bcdcountersrstvhd
PORT(
rst : IN std_logic;
clk : IN std_logic;
q : buffer std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal q : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bcdcountersrstvhd PORT MAP (
rst => rst,
clk => clk,
q => q
);
-- Clock process definitions
clk_process :process

begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 100 ns;
rst<='0';
wait for 100 ns;
wait for clk_period*10;

end process;

END;

VHDL code for SRFF with Asynchronous reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;
--use UNISIM.VComponents.all;
entity srffvhdasrst is
Port ( s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end srffvhdasrst;
architecture Behavioral of srffvhdasrst is
begin
process(s,r,clk,rst) is
begin
if(rst ='1') then
q<='0';
qbar<='1';
elsif( rising_edge(clk)) then
if(s/=r) then
q<=s;
qbar<=r;
elsif(s='1' and r='1') then
q<='Z';
qbar<='Z';
end if;

end if;
end process;
end Behavioral;
Test bench code for SRFF with Asynchronous reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY jhkhjk IS
END jhkhjk;
ARCHITECTURE behavior OF jhkhjk IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT srffvhdasrst
PORT(
s : IN std_logic;
r : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic
);
END COMPONENT;
--Inputs
signal s : std_logic := '0';
signal r : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs

signal q : std_logic;
signal qbar : std_logic;
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: srffvhdasrst PORT MAP (
s => s,
r => r,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
s<='0';

r<='0';
rst<='1';
wait for 100 ns;
s<='0';
r<='0';
rst<='0';
wait for 100 ns;
s<='0';
r<='1';
rst<='0';
wait for 100 ns;
s<='0';
r<='1';
rst<='1';
wait for 100 ns;
s<='1';
r<='0';
rst<='0';
wait for 100 ns;
s<='1';
r<='0';
rst<='1';
wait for 100 ns;
s<='1';
r<='1';
rst<='0';

wait for 100 ns;

s<='1';
r<='1';
rst<='1';
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
end process;
END;

Write a VHDL code for SR FF with synchronous reset and its testbench
code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity srffvhdsrst is
Port ( s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC);
end srffvhdsrst;
architecture Behavioral of srffvhdsrst is

begin
process (clk)
variable tmp: std_logic;
begin
if(rising_edge(clk)) then
if(s='0' and r='0')then
tmp:=tmp;
elsif(s='1' and r='1')then
tmp:='Z';
elsif(s='0' and r='1')then
tmp:='0';
else
tmp:='1';
end if;
end if;
q <= tmp;
qb <= not tmp;
end process;
end behavioral;

Test bench code for SRFF with synchronous reset

ENTITY aasavcv IS
END aasavcv;
ARCHITECTURE behavior OF aasavcv IS
COMPONENT srffvhdsrst
PORT(

s : IN std_logic;
r : IN std_logic;
clk : IN std_logic;
q : OUT std_logic;
qb : OUT std_logic
);
END COMPONENT;

--Inputs
signal s : std_logic := '0';
signal r : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal q : std_logic;
signal qb : std_logic;
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: srffvhdsrst PORT MAP (
s => s,
r => r,
clk => clk,
q => q,
qb => qb
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
s<='1';
r<='0';
wait for clk_period;
s<='1';
r<='1';
wait for clk_period;
s<='0';
r<='1';
wait for clk_period;
s<='1';
r<='1';
wait for clk_period;
wait for clk_period*10;
end process;

END;