library ieee;

use ieee.std_logic_1164.all;
entity cylook is
port(s,t:in std_logic_vector(3 downto 0);
result:out std_logic_vector(4 downto 0));
end cylook;
architecture st of cylook is
signal c:std_logic_vector(4 downto 0);
signal su:std_logic_vector(3 downto 0);
signal p,g:std_logic_vector(3 downto 0);
signal pg,gg,a1,a2,a3:std_logic;
component FA is
port(a,b,c:in std_logic;
sum,carry:out std_logic);
end component;
begin
c(0)<='0';
p<=s and t;
g<=s xor t;
c(1)<=g(0) or(p(0) and c(0));
c(2)<=g(1) or(p(1) and c(1));
c(3)<=g(2) or(p(2) and c(2));
c(4)<=g(3) or(p(3) and c(3));
fa0:FA port map(s(0),t(0),c(0),su(0),c(1));
fa1:FA port map(s(1),t(1),c(1),su(1),c(2));
fa2:FA port map(s(2),t(2),c(2),su(2),c(3));

fa3:FA port map(s(3),t(3),c(3),su(3),c(4));

pg<=p(0) and p(1) and p(2) and p(3);

a1<=g(3) and g(2) and p(3);
a2<=g(1) and p(3) and g(2);
a3<=g(0) and p(3) and p(2) and p(1);
gg<=a1 or a2 or a3;
result<=c(4)&su;
end;