Sie sind auf Seite 1von 5

8/9/2015 DesignofSerialInSerialOutShiftRegisterusingDFlipFlop(StructuralModelingStyle)(VerilogCODE).

~VerilogProgrammingByNareshSinghDo

HOME

VERILOGPROGRAMS

VHDL

Projects

FaceBookLikes
Like

VERILOGDESIGNS

PROJECTS

TUTORIALS

ASSIGNMENTS

ABOUTUS

NareshSingh

TESTIMONIAL

SearchHere
Search

Followers

2comments

Search

CONTACTUS

DesignofSerialInSerialOutShiftRegisterusing
DFlipFlop(StructuralModelingStyle)(Verilog
CODE).

06:14
Share 28,166peoplelikethis.

+1 Recommend this on Google

EmailSubscribe
Emailaddress...

Jointhissite
withGoogleFriendConnect

Members(28) More
Submit

PoweredbyBlogger.

DesignofSerialINSerialOUTShiftRegisterusingDFlip
Flop(StructuralModelingStyle)..

AboutMe

Alreadyamember?Signin

Digitalclock

NARE S H S I NGH
Follow

22:38:06

78

V I E W M Y COM P LE T E
P ROF I LE

TotalPageviews

OutputWaveform:SerialINSerialOUTShiftRegister

280,551

PopularPosts
Designof
ParallelIN
SerialOUT
ShiftRegister
using
Behavior
ModelingStyle(Verilog
CODE).
DesignofParallelInSerial
OUTShiftRegisterusing
BehaviorModelingStyle
OutputWaveform:Parallel
INSerialOUTShi...
4to1
Multiplexer
Designusing
Logical
Expression
(Verilog
CODE)
4to1MultiplexerDesign
usingLogicalExpression
(DataFlowModelingStyle)
OutputWaveform:4to1
MultiplexerProgram...
1:4

DemultiplexerDesign
usingGates(Verilog
CODE).

VerilogCODE

Archives
2013(108)
November(8)

//
//
//Title:siso
//Design:upload_design1
//Author:NareshSinghDobal
//Company:nsd
//
//
//
//File:DesignofSerialInSerialOutShiftRegisterusingd_flipflop.v

modulesiso(din,clk,reset,dout)
outputdout
inputdin
inputclk
inputreset
wire[2:0]s
d_flip_flopu0(.din(din),

http://verilogbynaresh.blogspot.in/2013/07/designofserialinserialoutshift.html

July(100)
TheThreeBasic
Elementinsidea
ComputerChip
Let'sstartwithmaking
aSemiconductor
Chip
Let'sKnowaboutour
Semiconductor
Industry
ComputerChipsare
EveryWhere
(ApplicationofEle...
VeryImportant
ACRONYMS&
TERMSof
SemiconductorI...
ElectronicsTrends
SettingPoints
WorldofIntegrated
ChipsAND
ElectronicDesign
Designof8to3Parity
Encoderusingif
elsesta...

1/5

8/9/2015 DesignofSerialInSerialOutShiftRegisterusingDFlipFlop(StructuralModelingStyle)(VerilogCODE).~VerilogProgrammingByNareshSinghDo
1:4DemultiplexerDesign
usingLogicalGates(Data
FlowModelingStyle)Output
WaveForm:1:4
DemultiplexerProgram//...
Designof4
Bit
Comparator
using
Behavior
Modeling
Style(VerilogCODE)
Designof4BitComparator
usingBehaviorModeling
StyleOutputWaveform:4
BitComparatorDesign
VerilogCODE//...
DesignofJK
FlipFlop
using
Behavior
Modeling
Style(Verilog
CODE)
DesignofJKFlipFlopusing
BehaviorModelingStyle
OutputWaveform:JKFlip
FlopVerilogCODE//
...
Designof
Frequency
Divider
(Divideby10)
using
Behavior
ModelingStyle(Verilog
CODE)
DesignofFrequencyDivider
(Divideby10)using
BehaviorModelingStyle
OutputWaveform:
FrequencyDivider(Divideby
10)....
Designof4
BitAdder
using4Full
Adder
Structural
Modeling
Style(VerilogCode)
Designof4BitAdderusing
4FullAdder(Structural
ModelingStyle)Output
Waveform:4BitAdder
using4FullAdderVerilog...
Designof
SerialIn
SerialOut
ShiftRegister
usingDFlip
Flop
(StructuralModelingStyle)
(VerilogCODE).
DesignofSerialINSerial
OUTShiftRegisterusingD
FlipFlop(Structural
ModelingStyle)..Output
Waveform:SerialIN...
BinaryTo
GrayCode
Converter
usingLogical
Gates
(Verilog
CODE).
BinaryToGrayCode
ConverterusingLogical
Gates(DataFlowModeling
Style)OutputWaveform:
BinaryToGrayCode

.clk(clk),
.reset(reset),
.dout(s[0]))

Designof8:3Parity
Encoderusing
conditionalo...

d_flip_flopu1(.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]))

Designof8nibble
StackusingBehavior
ModelingS...

d_flip_flopu2(.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]))

d_flip_flopu3(.din(s[2]),
.clk(clk),
.reset(reset),
.dout(dout))

endmodule

//Dflipflopdesign

Designof8nibble
queueusingBehavior
ModelingS...

DesignofParallelIN
SerialOUTShift
Register...
FPGA/CPLDBased
Project
SystemDesignusing
LoopStatements
(BehaviorMode...
SampleProgramsfor
BasicSystemsusing
VerilogHD...
Designof4BitAdder
cumSubtractorusing
Loops(...
Designof4Bit
Subtractorusing
Loops(BehaviorM...
Designof4BitAdder
usingLoops
(BehaviorModeli...
DesignofStepper
MotorDriver(Half
Step)usingB...
DesignofStepper
MotorDriver(Full
Step)usingB...

//
//
//Title:d_flip_flop
//Design:upload_design1
//Author:NareshSinghDobal
//Company:nsd
//
//
//
//File:d_flip_flop.v

DesignofFirstInFirst
Out(FIFO)Register
usi...
Designof8NibbleRAM
(memory)using
BehaviorMod...
Designof8NibbleROM
(Memory)using
BehaviorMod...
SensorBasedTraffic
LightControllerusing
FSMTe...
TimerBasedSingle
WayTrafficLight
Controllerus...

moduled_flip_flop(din,clk,reset,dout)
outputdout
regdout
inputdin
inputclk
inputreset
always@(posedgeclk)
begin
if(reset)
dout<=1
else
dout<=din
end
endmodule

http://verilogbynaresh.blogspot.in/2013/07/designofserialinserialoutshift.html

DesignofODDCounter
usingFSM
Technique(Verilog...
DesignofFrequency
DividersinVerilog
HDL
CountersDesignin
VerilogHDL.
DesignofMOD6
Counterusing
BehaviorModeling
St...
DesignofBCDCounter
usingBehavior
ModelingStyl...
DesignofInteger
Counterusing
BehaviorModeling...
Designof4BitBinary
Counterusing
BehaviorMode...

2/5

8/9/2015 DesignofSerialInSerialOutShiftRegisterusingDFlipFlop(StructuralModelingStyle)(VerilogCODE).~VerilogProgrammingByNareshSinghDo
ConverterVer...
Designof
SerialIN
ParallelOUT
ShiftRegister
using
Behavior
ModelingStyle(Verilog
CODE)
DesignofSerialINParallel
OutShiftRegisterusing
BehaviorModelingStyle
OutputWaveform:Serial
INParallelOUT...

NewerPost

Home

2comments:

cgthanessaid...
howtowritethetestbenchfortheshiftregister......pleasehelpme....

OlderPost

Designof2BitBinary
Counterusing
BehaviorMode...
DesignofFrequency
Divider(Divideby10)
usingB...
DesignofFrequency
Divider(Divideby8)
usingBe...

13October2013at22:26

DesignofFrequency
Divider(Divideby4)
usingBe...

HariharaSravansaid...

DesignofFrequency
Divider(Divideby2)
usingBe...

moduletestregister()
wireQ

ModelingStylesin
VerilogHDL

regd,clk
shiftregisters1(Q,d,clk)
initial
begin
clk=0
forever#5clk=~clk
end
initial

HowtouseCASE
Statementsin
BehaviorModeling
St...
HowtouseIFELSE
Statementsin
BehaviorModeling...
Designof4Bit
Comparatorusing
BehaviorModeling...

begin
d=0
#10d=1

DesignofBinaryTo
GRAYCode
Converterusing
CASE...

#2d=0
#5d=1
#10d=0
#3d=1

DesignofGRAYto
BinaryCode
Converterusingife...

#4d=0
end
endmodule
9January2015at08:20

SmallDescriptionabout
BehaviorModeling
Stylein...
DesignofParallelIN
ParallelOUTShift
Registe...

PostaComment

Enteryourcomment...

DesignofSerialIN
ParallelOUTShift
Register...
DesignofSerialIN
SerialOUTShift
Registerus...

Commentas:

Publish

GoogleAccount

Preview

DesignofSRLatch
usingBehavior
ModelingStyle(...
DesignofDLatchusing
BehaviorModeling
Style(V...
DesignofToggleFlip
FlopusingBehavior
Modeling...
DesignofJKFlipFlop
usingBehavior
ModelingSty...
DesignofSR(Set
Reset)FlipFlop
usingBehavio...
DesignofDFlipFlop
usingBehavior
ModelingStyl...
DesignofBCDto7
SegmentDriverfor
CommonCatho...
DesignofBCDto7
SegmentDriverusing
IFELSESt...
DesignofGRAYto
BinaryCode

http://verilogbynaresh.blogspot.in/2013/07/designofserialinserialoutshift.html

3/5

8/9/2015 DesignofSerialInSerialOutShiftRegisterusingDFlipFlop(StructuralModelingStyle)(VerilogCODE).~VerilogProgrammingByNareshSinghDo
Converterusing
CASE...
DesignofBinaryto
GRAYCode
Converterusingife...
Designof2to4
DecoderusingCASE
Statements(Be...
Designof4to2
EncoderusingCASE
Statements(Be...
Designof1to4
Demultiplexeruisng
CASEStatemen...
Designof4to1
Multiplexerusing
casestatements...
Designof2to4
Decoderusingifelse
statements...
Designof4to2
Encoderusingif
elsestatements...
Designof1to4
Demultiplexerusing
IFELSEstate...
Designof4to1
Multiplexerusingif
elsestatem...
DesignofMasterSlave
FlipFlopusingDFlip
Flo...
DesignoftoggleFlip
FlopusingDFlip
Flop(Stru...
DesignofParallelIN
ParallelOUTShift
Regis...
Designof4BitSerialIN
ParallelOUTShift...
DesignofSerialIn
SerialOutShift
Registeru...
Designof4BitAdder
cumSubtractorusing
xorGat...
Designof4BitAdder
cumSubtractorusing
Structu...
Designof4Bit
Subtractorusing
StructuralModeli...
Designof4BitAdder
using4FullAdder
Structura...
Designof2to1
Multiplexerusing
GateLevelMode...
SmallDescriptionabout
GateLevelModeling
Style...
ConditionalOperator
(DataFlowModeling
Style)Ve...
Designof2Bit
Comparatorusing
ConditionalOpera...
DesignofBCDto7
SegmentDriverfor
CommonAnode...
DesignofBCDto7

http://verilogbynaresh.blogspot.in/2013/07/designofserialinserialoutshift.html

4/5

8/9/2015 DesignofSerialInSerialOutShiftRegisterusingDFlipFlop(StructuralModelingStyle)(VerilogCODE).~VerilogProgrammingByNareshSinghDo
SegmentDriverfor
CommonCatho...
DesignofBinaryTo
Excess3Code
ConverterusingC...
Designof2:4Decoder
usingConditional
Operator...
Designof4:2Encoder
usingConditional
Operator...
Designof1:4
Demultiplexerusing
ConditionalOpe...
Designof4:1
Multiplexerusing
ConditionalOper...
DigitalSystemDesign
usingLogical
Expression(Ve...
DesignofGrayto
BinaryCode
Converterusing
Logi...
BinaryToGrayCode
Converterusing
LogicalGates...
Designof1Bit
Comparatorusing
LogicalGates(V...
4:2Encoderusing
LogicalGates
(VerilogCODE).
2:4Decoderusing
LogicalGates
(VerilogCODE).
HalfSubtractorDesign
usingLogical
Expression(V...
1:4Demultiplexer
DesignusingGates
(VerilogCO...
4to1Multiplexer
DesignusingLogical
Expression...
FullSubtractorDesign
usingLogicalGates
(Verilo...
FullAdderDesignusing
LogicalExpression
(Verilo...
HalfAdderDesignusing
LogicalExpressions
(Veril...
LogicalOperatorstest
inVerilogHDL
Design
SimpleANDGate
DesignusingVerilog
HDL
SmallDescriptionabout
DataFlowModeling
Stylei...

Copyright2011VerilogProgrammingByNareshSinghDobal|PoweredbyBlogger
DesignbyWordpressTheme|BloggerizedbyFreeBloggerTemplates|couponcodes

http://verilogbynaresh.blogspot.in/2013/07/designofserialinserialoutshift.html

5/5

Das könnte Ihnen auch gefallen