A Tutorial on Built-In Self-Test Part 1: Principles Dunno rs ures, a distal VISHWANID, AGRAWAL In the several yeas since this system is tested and diagnosed on are nagazine's publication of a pair of numerous occasions. For the sy ATT Bll Laboratories |} | tutorial articles on BIST? both temto perform ssintended mission CHARLES R. KIME BIST researcin and its application with high availabilty, esting and a } | have grown rapidly. Although our agnosis must be quick and elec KEWALK. SALWA ‘origina goal was townie adetaled tive. Asensible way ensure thisis University of Wisconsin, tutorial, we found that adequate tospecy stax one ofthe ten | cevengetie ad fens functions—in other words seltes, Madison salable wes not feasible wit our Digital yer involve a hierarchy ————————li, | spce liniaons Hence on some of pats: chip, boards, cabinets, aspects of BIST we presen limited and so on. At the highest level, | Thishoral provides on overview) | deta supportedbypointerstothe ‘which may include the entre 9° | ef ban alfest IST pring} literate Alot it the number ‘tem, the operation is controlled by ‘i ee of sources the interested reader ‘mented in software, While a purely dors present the issues or | books rather than original papers. Soitware approach to selfest may economics underlying BIST ond; | In noway dowe intend todiminish suffice at the system level, ithas sev- ‘introduce the related | at the contributions of the original re- ‘eral disadvantages. Such testing ‘est sructures. They explain the | ‘searchers or developers, tmyhoeordapenc rate | aueelasrerena: | Set viteat pce tomy | PMB emis | Me OS us me considerations. nado, agcod |= RAIA desir ian i a ibe software testean be very ong sow, h Port 1-Potys, | ing not only fast and efficient but and expensive to develop. ‘nour June issue, will cover BIST. also hierarchical, In other words, in ‘An increasingly attractive alter “-hardwore implementations! awelldesigned testing strategy, the native is builtin selftest—that is, us and tools, 8:2 same hardware can test chips, ‘Senora hart | NON | a ware set: fis which may notseem sigiicant ‘The simplicity ofthis definition belies | at the chip level, are enormous atthe BISTisadesigrfortestabity (DFT) tech | the complextesinvolved inimplement| system level, Altematve strategies are aque whch testing (tt generation | ing BIST. Thi aticle addresses the | chipwse andsjtermfoolsh Moreover, and test application) és accomplished | pertinent issues and describes the ad-| BIST offers solutions to several major (trough bakin harvare features. | Vantages and limitations Of BIS. testing problems,Table 1. BiSTeoss Design test Maintenance Diognesis, Service hips + * ‘ Boords —4/- + . - Systems f= + - - e - + cst nese = cost redo ing) +/-cot nro = sing The complexity issue. As the com: | plexity of VLSI systems increases, we ask If the testing problem can be parti tioned. Theanswer,unforunatey,isn0, | Forexample, considertwo devieescon- | nected in a cascade. There is often no | simple way to derive tests forthe cas | cade from the given tests for its individ- ual parts Another pessibiliystheuse of a hierarchical approach. The complex. {sign automation problems of synthe. sis and physical design are often solved through hierarchical procedures. The testing problem, however, isnot easy to solve with traditional hierarchical tech niques. For example, no simple method exissfor deriving a board est fom tess for chips onthe board BIST, however, does offlera hierarchi cal solution tothe testing problem, Con- sider the testing ofa chip embedded in a board that isa pant of a system. The ‘top-down hierarchy consist of system, boards, and chips. Suppose all levels of the hierarchy use BIST. To test the chip, the system sends a contol signal to the board, which in turn activates sellzest ‘onthe chip and passestheresultbackto thesystem, Thus, BIST providesficent testing of the embedded components and interconnections reducing the bur den on sjstenrlevel test, which need only verify the components functional synergy The quality issue. A product's qual ity depends on the tenacity ofits ests. Test tenacity or ability is most frequent ly measured as coverage ofsinglestuck- at faults Thus, we calibratetessaccord- | tomized forthe board undertest enables ing to their ability to detect single lines | the tester to acces the pins ofthe chips that appear as if shorted to ground | mounted on the board. ICT effectively (Guckat0) or to the power supply | apples chip tests for diagnosis and also (atuckat, Since thekind and number | effectively ets board wiring. The meth faults that occur depends on the ype | od. however, presents several problems. of device (chip, bard, and so on) and | Fini, CT selective only alter board is the technology (CMOS, bipolar, GaAs), | removed from the system; therefore itis evaluating est quality can be a compl: | no help in systermlevel diagnosis. Sec- cated task: In general, quality require- | ond, in surfacemount technology ments such as 96% fault coverage for complex VLSI chipsor 100% coverage of all interconnect faults on a printed ci- cuitboard (PCB) ae based on practical considerations. The test engineer tiesto achievea low reject rato (percentage of faulty pans in the number passing the test)—for example, 1 in 10,000—while controling the cost of test generation and application, For very large systems, ‘such requirements are achievable only through DET. Our discussion wil show that BIST isthe prefered form of DFT. ‘Test generation problem. As point- ed outearler, the problem of generating tess is dificult to solve by using hierar: chy. The dificult les in camyingthe test stimulus through many layers of circul= ry tothe element under test and then conveying the result again through ‘many layesof cicuitr to an observable point. BIST simplifies this problem by localizing testing ‘Test application problem. Fora: most a decade, incircut testing (ICT) has dominated the PCB testing scene Inthismethod,abedofnaiisfisture cus ‘densely on bot sides ofthe board, Bed | ofnails fixtures for such boards are e- | ther too expensive or impossible to | build. BIST offers a superior solution tothe | test application problem. First, builtin test clreuty can test chips, boards, and. | the entie system without expensive, ex- femal automatic test equipment, Sec- ‘ond, for oftlne testing of boards and chipsand forpeoduction esting, wean use the same tests and tes circuitry that ‘we use atthe system level | Gat, components are oten mounte i Economies of BIST. In deciding whether to use BIST, system planners and designers must weigh costs against benefits. At the chip level, BIST offers, small savings in testing costs, But in product lifecycle costs, te savings are ‘overwhelmingly in favor of BST, Table I shows the impact of BIST on testing costs for chips, boards, and sy tems, We find thatthe adcltional ex- pense of designing BIST hardware is somewhat balanced bythe savings from ‘est generation. Fabrication costincreas ‘satall levels due tothe extra hardwareBIST requires. Testing cost decreases | several circuit board. Each board may due to moreefiicient tests, lessexpensive _ contain several VLSI chips. Figure 1 | SH eee test equipment and improved rouble | showssuch asytem, The tet manager || | Tt Segura Meaty nd inege | ae acm tt cr smatanensiy || |= thon Maintenance tet 6a ystemlvel | actvteselftest on allboards Thetest || srettehagaycceand | manage onc bn act [ Tm) diagnosis Ths BISTsimpact on main | vates selftest on each chip on that || | |marge fenance costs greatest atthe system | board A chip tet managers respons ; ae Settee dag | Be cxecrgscres on mec || | |] nosis and repair costs atthe board and | and then transmitting the result aul Arata) [a ‘Men leek In atematve stategies | fe or faulty tothetestmanage ofthe || | responsibleforgreatlossofrevenuedve , test manager accumulates test results | to service interuption; BIST decreases | from alts chips and transmits them to lengthy oF improper dlagnosis is often | board containing the chip. The board pret ecco uence 7 Reis ieesege| xmod pi), we aban oll possible non 2210 polynomials of degree less thon thotof phat, 2°—1 distinc non: z2r0 polynomial. Such © pabmomial ‘Axis called primitive. Let usdlrifyhis.| through on example by computing 22, 23, ... mod af). The sequence we Gicinion re eater est el sex We can now concude that the succeeding powers of x will generate the some remainders ‘ond ovr. Thus, in his cose, succoed ing powers of x gonerce only five dis fine polomias. On the ther hand, | if we repeat the some process for he polynomial Hx, we cbain al 15 non- {ero pobmomiois of dogreelesthon 4 5 bn. Computers and Mather | ‘mates with Applications, Vol. 13, No. 5/6, Feb, 1987, pp. 537-545, RECHT auibee e 4 | Figure E. Three lip input IFSRs, or mulipl-iput signature registers ISR). References 1, Bd. MeChske, “Built Set Test Tech niques” IBEE Design & Test of Comput 8, Vol 2, No.2, Ar. 985, pp. 2128 2. EJ McCluskey, Buln Seles Src ‘ures IEEE Design & Testo Computers, Vol. 2 No.2, Ap: 1985, pp. 2998. 3. SC.Sethand VD. Agrawal, ‘Character ‘ngthe LSI Vielé Equation rom Waler “Test Dat” IEEE Trans Computersied | mane 1999 Ea | j | | Desig, VoL.CAD-8, No.8, pr. 1984p. 132 Bateson, InCrcuit Testing, Van Nos tvand Reinhold, New York, 185. 5. AP.Ambleretal, Economical Viable ‘Awomatic Insertion of Self Test Features for Custom VLS\" Proc Test Con, IEE Computer Society Press, Las Alan ios Call, Sept, 1986, pp, 230248, 4 B. 18 1D. Dear, "Economic Etec in Design and Test EEE Design & Test of Cm 8, Vol 8 No.4 Dec. 191, pp. 647 ‘Kuban and. Bruce, "SllTesingthe Motorola MCGSO4P2" IEEE Design & Test of Computers, Vo. 1, No.2, May 1954, pp 3941 Wa, "PEST: A Too! for Implementing PreudoEshaustve Seles” AT&T Technical J, Vol 70, No.1, Jan/Feb 1901, pp. 87.10, Abramov, M.Brever, and A Fried ‘man, Digital Systems Testing and Test table Design, Computer Science Press, New York, 191 SW. Golomb, Shi Register Sequences, ‘Aegean Park Press, Laguna Hil, Cali, 1982 PH. Bardel, WH. MeAnney, andJ.Sa- vir Buln Testor VISE seudorandom Techniques, John Wiley & Sons, New Yotk, i987, ‘SC. Seth, VD. Agawal, and H, Fart “A Satistical Theory of Digital Circuit ‘estab BBE Tens. Computes, Vol (C38, No.4, Ape 1980 pp. 582585, EB Elchebergeretal, Sructred Logic Tesing, Prentice al, Englewood Ci, NJ, 1981, PD Homers, RD. McLeod and BW. Podaima, "Cellular Automata Circus for Buln SelFTes,” IBM J. Research «and Development, Vol. 34, No.2P,Mard May 1860, pp. 380405. Dulaza and G.Cambon, LESR Based Deterministic and Pseadorandom Test Pate Generator Structures” Poe. Bu- ropean Tet Cort, IEE CS Press, 198, pp.2rst M Khare and A. Albick, "Cellular A tomata Used fr Tet Pattem Genera tion, Pre. nt Cone Compute Design IEEECS Press, 187, pp. 5559 JLyan Sas F.Catthor and H. De Man, “Cellular Automata Based SelTest for Programmable Data Paths” Po. J’! Tes Cont, IEEE CS Press, 190, pp. 768. 7. NR Saxena and JP. Robinson, "Syn: «rome and Transtion Count Are Uncor ‘elated, IEEE Trans inormation Teo,Selected sources of BIST information | Abramov MM Breer, ond A. | Friedman, Digital Systems Testing ond Tesbl Desr, Computer Sconce Press (W. H. Freeman ond Co., New York, 1990. The lalestcomprehensive | reversing Agrawal, VD. ond SC. Sah, Test (Genero for VSI Chips EEE Comput er Socily Pres, los Alamitos, Cif, 1988. Easytovead terial on sing | wit comprehensive bblography, Borde P, W. MeAnney, and J Sov, Buln Tes for VIS Peudo- random Techniques, John Wiley 8 Sons, New York, 1987. Provides ‘mathematical reamen’ of BIST heo- ‘yond proce. Eichalberger, £8, E,Lindbloom, 1A. Woicukousk, ond T.W. Wil liams, Sructured loge Testing, Pen ficeHall, Englewood Clif, NJ. | 1991, Provides dele testing ond selFest techniques used in lve sen- sive scan design environmen IEEE Trans. Industrial Elacronics, Specie lve co Tesog, Vl 36, No. | 2. Moy 1989. Contains fe torial | rls on testing, DFT, ond ST. | J. Blecronic Teting: Theory and Special sve on Bound! ary Sean, Vol 2, No. 1, 1991. lies @ rial on boundory scan cand orcles on recnt research resus. Yarmolik, VN. and SIN. Demiden- | he, Generation end Applicaton of | Paeuderonom Sequenees ky Rondon Teng hn Wey 8 Sons, Chichester, Uk 1968. Provides mathematical he. 27 of edbock shit registers os op- | pled in esting ervironment. 2. a4 Vol. 3, fn, 1988, p. 648, SSM. Reddy, KK. Saja and MG. Kar povsly, “A Data Compression Tech nique for Buin Sees” BEE Tans Computer, Vol.C:7, No, 9, Sept. 1988, p.1151-1135;conecton, Vol C38,No, 2, Feb 1988, p 300, K Iwasaki and F Arakawa “An Analy sisolthe Asin Probably of Mukiple- Inpu Signature Registers inthe Case of 8 Paty Symmetric Channel” IE Trans. Conputeraided Design, Vol (CAD, No.4, Ap. 1960, pp. 27-98 DX. Pradhan, K Gupta and MG. Kar powsk, “Alsing Probability for Mult DleInput Signature Analyzer” IEEE Trans. Computers, Vol. C38, No.4, Ap. 1990, pp. 586591, 82 Hassan and EJ, MeCioskey, “in ‘reasd Fault Coverage Through Mul ple Signatures Proc dn Symp. Foul Tolernt Compuing, IEEE C3 Pres, 1984, pp. 35485, Y.Zorianand¥-K. Agar “Optimizing nor Masking in BST by Output Dats Modiiation J Elenenc Testing: The- ‘ay and Applications, Vol. 1, Fb. 188, pp. 5872 Akiva and KK Sal, “A Method of Reducing Alasing in a Buln Slt Test Environment, IEE Tons Comput Aided Design, Vol.CADL0, No.4, ABE 1901, pp 548553 Vishwani D. Agrawals biographical sketch and photo appear on page 28 (Garles Kimessaprofesoria te Depa mentolBlecticaland ComputerEngineeins at the University of Waconsin Madison, where he has developed and taught bro range of computer engineering counes. HS rescrch interest inlude testing, design for ‘etait, BIST, and aoe computing. He has saved as general chairman ofthe 19tDlnemtonl Sympesiv on Fal Ter ant Computing as associate editor of EEE Transaction on Cotes an EEE Tans tions on Campari Design, anon the progam commites of IEE conferences. Kime sa felow ote IEE anda member of the FEE Computer Society KewalK Salis profesor the Depart ment of Eletical and Computer Engine: ing atthe University of Wisconsin taco, where he teaches logic design, computer architecture, mierprocessorbased $s ‘eins and VLSI design and sing Presious- ly. heworkedatth Univers af Neweaste, Australia. He hasaso held sting and con. suing potions atthe University of South er California, the University of low, and Hiroshima Univesity, Hisrescarch ners Ince design fr tesabiliy,fulolerant computing, VSI design, and computer a hierar, He is an assciate editor of the Joumato Bleconie Testing: Theory a p> pcanors. Saluja received the BE tom the Univesiy of Roorke, India end the NS and the PhD in electrical and computer eng neering fom the Univers of lowa. He Sa member ofthe IEEE Compute Society Send comespondence abourthisaricieta VishwanD. Aga. ATA Bel Laborto- ries, HH Mountain Ave., Room 2C47, “Murray Hl, NI 07574; ell: va@reserch.