Experiment No.

Date __ - __ - 2014

Aim of The Experiment:

To design and implement half adder circuit using VHDL

Platform Required:
Windows 7 Operating System

Software Required:
Xilinx ISE Design Suite 14.7

Theory:
The half adder circuit is a digital circuit consisting of logic gates that adds two single bit
inputs and produces a single bit sum and carry. A half adder circuit having inputs A and B
produces a sum S and a carry C given by,
S=AB
C = A.B
Truth Table for Half Adder
Input
A
0
0
1
1

Output
B
0
1
0
1

S
0
1
1
0

Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
Port ( A,B : in STD_LOGIC;
S,C : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
S <= A xor B;
C <= A and B;
end Behavioral;

Department of Electronics & Telecommunication Engineering

Veer Surendra Sai University of Technology, Burla

C
0
0
0
1

Experiment No. 1

Date __ - __ - 2014

Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY halfadder_tb IS
END halfadder_tb;
ARCHITECTURE behavior OF halfadder_tb IS
COMPONENT halfadder
PORT(
A : IN std_logic;
B : IN std_logic;
S : OUT std_logic;
C : OUT std_logic
);
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal S : std_logic;
signal C : std_logic;
BEGIN
uut: halfadder PORT MAP (
A => A,
B => B,
S => S,
C => C
);
stim_proc: process
begin
a <= '0';b <= '0';
wait for 100 ns;
a <= '0';b <= '1';
wait for 100 ns;
a <= '1';b <= '0';
wait for 100 ns;
a <= '1';b <= '1';
wait for 100 ns;
wait;
end process;
END;

Department of Electronics & Telecommunication Engineering

Veer Surendra Sai University of Technology, Burla

Experiment No. 1

Date __ - __ - 2014

RTL Schematic Diagram:

Test bench Waveform:

Conclusion:
Thus we have implemented half adder circuit in VHDL and studied its operation by giving
several inputs.

Department of Electronics & Telecommunication Engineering

Veerr Surendra
Su
Sai University of Technology, Burla