JEDEC

STANDARD

High Temperature Storage Life

JESD22-A103D
(Revision o f JESD22-A103C, November 2004)

DECEMBER 2010

JE D EC SOLID STATE TECHNOLOGY ASSOCIATION

JEDEC

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JEDEC Standard 22-A103D

Page I

TEST METHOD A103D

HIGH TEMPERATURE STORAGE LIFE
(From JEDEC Board Ballot JC'B-10-58 and JCB -10-65, formulated under the cognizance of
JC -14.1 Subcommittee on Reliability Test Methods for Packaged Devices.)

Scope

The test is applicable for evaluation, screening, monitoring, and/or qualification o f all solid state
devices.
The high temperature storage test is typically used to determine the effects o f time and
temperature, under storage conditions, for thermally activated failure mechanisms and time-tofailure distributions o f solid state electronic devices, including nonvolatile memory devices (data
retention failure mechanisms). Thermally activated failure mechanisms are modeled using the
Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used
w ithout electrical conditions applied. This test may be destructive, depending on time,
temperature and packaging (if any).

Reference documents (informative)

JE SD 22-B 101, External Visual.

JESD47, Stress-Test-Driven Qualification o f Integrated Circuits.
J-STD-020, Joint IPC/JEDEC Standard, M oisture/Reflow Sensitivity Classification fo r
Nonhermetic Solid State Surface-M ount Devices.

Apparatus

3.1

High temperature storage chambers

The apparatus required for this test shall consist o f a controlled temperature chamber capable of
maintaining the specified temperature over the entire sample population under test.

3.2

Electrical test equipment

Electrical equipment capable o f performing the appropriate measurements for the devices being
tested, including write and verify the required data retention pattem(s) for nonvolatile memories.

Test Method AI03D

(Revision o f AI03C)

JE D EC Standard 22-A 103D

Page 2

Procedure

4.1

High temperature storage conditions

The devices under test shall be subjected to continuous storage at one o f the tem perature
conditions o f Table I.

Table 1 High temperature storage conditions

_____________ Condition
_____________ Condition
Condition
C ondition
_____________ Condition
_____________ C ondition

A: +125
B: +150
C :+ 1 7 5
D: +200
E: +250
F: +300

(-0/+10)
(-0/+10)
(-0/+10)
(-()/+10)
(-0/+10)
(-0/+10)

C_____________
C_____________
C
C
C_____________
C_____________

N O T E C A U T IO N should be ex ercised w hen selecting an accelerated test condition since the

accelerated tem p eratu re used m ay exceed the cap ab ilities o f the dev ice and m aterials, thereby inducing
(ov erstress) failu res that w ould not o ccu r u nder norm al use conditions.

As a m inim um the follow ing items should be taken into consideration:

1) M elting point o f m etals present, especially solder. D egradation o f m etals including
m etallurgical interfaces.
2) Package degradation. For exam ple: glass transition tem perature and therm al stability (in air)
o f any polym eric materials.
3) M oisture rating o f package (per J-STD -020).
4) T em perature lim itations o f silicon devices. For exam ple: charge loss in nonvolatile mem ories.
5) T est conditions (tem perature, time) should be selected to cover the acceleration o f the
corresponding failure mechanism and the anticipated lifetim e (operational tim e) o f the device.
Q ualification (JESD 47) and reliability m onitoring test conditions typically require a duration o f
1000 hours per condition B o f T able 1. O ther conditions and durations may be used as
appropriate. JE S D 471 also recom m ends that some package styles be subjected to SM T reflow
sim ulation prior to stress.
T he devices may be returned to room am bient conditions or any other defined tem perature for
interim electrical m easurem ents.

1 From T able 2 o f JF.SD47 - Preco n d itio n in g to JF.SD 22AI 13 is recom m ended, specifically for w irebonded products
q ualified to Pb-free reflow profiles. M oisture soak as pari o f the preconditioning is optional.

Test Method A I03D

(Revision o f A I03C )

JED EC Standard 22-A 103D

Page 3

Procedure (contd)

4.2

Measurements

U nless otherw ise specified, interim and final electrical test m easurem ents shall be com pleted
w ithin 168 hours after rem oval o f the devices from the specified test conditions. Interim
m easurem ents are optional unless otherw ise specified. The time window need not be met if
verification data fo r a given technology is provided. I f the final readpoint time window is
exceeded then the units m ay be restressed for the sam e am ount o f time that the w indow is
exceeded.
T he electrical test m easurem ents shall consist o f param etric and functional tests specified in the
applicable procurem ent docum ent. For nonvolatile m em ories, the data specified data retention
pattern must be written initially, and then subsequently verified without re-writing.

4.3

Failure criteria

A device will be considered a high tem perature storage failure if param etric lim its are exceeded,
or if functionality cannot be dem onstrated under nominal and w orst-case conditions, as specified
in the applicable procurem ent docum ent. For nonvolatile m em ories, the specified data retention
pattern shall be verified before and after storage. A margin test may be used to detect data
retention degradation.
M echanical dam age, such as cracking, chipping, or breaking o f the package, (as defined in test
method B 101 External V isual) will be considered a failure, provided that such dam age w as not
induced by fixtures or handling and it is critical to the package perform ance in the specific
application.
C osm etic package defects and degradation o f lead finish; or solderability are not considered valid
failure criteria for this stress.

Summary

The follow ing details shall be specified in the applicable procurem ent docum ent.
a) Electrical test m easurem ents, failure criteria and specifications
b) Sam ple size and num ber o f failures (specify zero if none observed).
c) Tim e and conditions, if other than 1000 hours per condition B.
d) Interim electrical test m easurem ents, if required.
e) N onvolatile mem ory data retention pattern (for appropriate devices)

Test Method A I03D

(Revision o f A I03C )

JE D EC Standard 22-A 103D

Page 4

Annex A (informative) Differences between JESD22-A103D and JESD22-A103C

T his table briefly describes most o f the changes made to entries that appear in this standard,
JE SD 22-A 103D , com pared to its predecessor, JE SD 22-A 103C (N ovem ber 2004). If the change
to a concept involves any w ords added or deleted (excluding deletion o f accidentally repeated
w ords), it is included. Som e punctuation changes are not included.

Clause

Description of change

In Scope, added reference that therm ally activated failure m echanism s are
A rrhenius based.
New section (2) added to denote docum ents referenced by this test method
Renum bered clauses accordingly based on new clause added.
A dded reference from JESD 47 that recom m ends preconditioning for some
package types prior to stress
First paragraph, modified time w indow requirem ent from 96 hours to 168
hours
First paragraph, add last 2 sentences

2
4 . 1 (5)
4.2
4.2

Test Method A103D

(Revision o f A I03C )

Standard Improvement Form

JEDEC

JESD22-A103D

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