Beruflich Dokumente
Kultur Dokumente
vin 20 0 dc 5v
iin 20 1 dc 100ua
m11 1 1 3 3 nm(l=2u w=5u)
m12 3 3 0 0 nm (l=2u w=5u)
m13 4 3 0 0 nm (l=2u w=5u)
mo1 5 1 4 4 nm (l=2u w=5u)
* clock 1
.subckt swod 1 3
m1 1 2 3 4 nmod
.model nmod
m2 3 7 1 6 pmod
.model pmod
vb1 4 0 dc -5v
vb2 6 0 dc 5v
vg1 2 0 pulse(-1 1 3u 0.25u 0.25u 2u 5u)
vg2 7 0 pulse(1 -1 3u 0.25u 0.25u 2u 5u)
.ends swod
* clock 2
.subckt swev 1 3
m1 1 2 3 4 nmod
.model nmod
m2 3 7 1 6 pmod
.model pmod
vb1 4 0 dc -5v
vb2 6 0 dc 5v
vg1 2 0 pulse(-1 1 0.5u 0.25u 0.25u 2u 5u)
vg2 7 0 pulse(1 -1 0.5u 0.25u 0.25u 2u 5u)
.ends swev
vin 1 0 dc 5v
iin 1 2 sin(0 45ua 2000hz)
* integrator start
i11 20 3 200ua
i12 20 8 12.5ua
i13 20 10 100ua
vs11 5 0 dc -5v
vs12 7 0 dc -5v
vs13 9 0 dc -5v
vs14 11 0 dc -5v
x11 2 3 swev
x13 3 4 swev
x14 3 6 swod
x16 3 8 swod
.ic v(4)=1v
.ic v(6)=1v
*outputs
vdummy 10 12 dc 1v
vo1 12 0 5v
vbias 20 0 5v
.op
.tran 0.5us 2ms
.probe
.end
* clock 1
.subckt swod 1 3
m1 1 2 3 4 nmod
.model nmod
m2 3 7 1 6 pmod
.model pmod
vb1 4 0 dc -5v
vb2 6 0 dc 5v
vg1 2 0 pulse(-1 1 3u 0.25u 0.25u 2u 5u)
vg2 7 0 pulse(1 -1 3u 0.25u 0.25u 2u 5u)
.ends swod
* clock 2
.subckt swev 1 3
m1 1 2 3 4 nmod
.model nmod
m2 3 7 1 6 pmod
.model pmod
vb1 4 0 dc -5v
vb2 6 0 dc 5v
vg1 2 0 pulse(-1 1 0.5u 0.25u 0.25u 2u 5u)
vg2 7 0 pulse(1 -1 0.5u 0.25u 0.25u 2u 5u)
.ends swev
vin 1 0 dc 5v
iin 1 2 sin(0 45ua 2000hz)
* integrator start
i11 20 3 200ua
i12 20 8 12.5ua
i13 20 10 100ua
vs11 5 0 dc -5v
vs12 7 0 dc -5v
vs13 9 0 dc -5v
vs14 11 0 dc -5v
x11 2 3 swev
x13 3 4 swev
x14 3 6 swod
x16 3 8 swod
.ic v(4)=1v
.ic v(6)=1v
*outputs
vdummy 10 12 dc 0v
vo1 12 0 5v
vbias 20 0 5v
.tran 0.5us 2ms
.probe
.end
* clock 1
.subckt swod 31 33
m1 31 32 33 34 nmod
.model nmod
NMOS (level=1 )
m2 33 37 31 36 pmod
.model pmod
PMOS (level=1 )
vb1 34 0 dc -2.5v
vb2 36 0 dc 2.5v
vg1 32 0 pulse(-2 2 2.5u 0.25u 0.25u 2u 5u)
vg2 37 0 pulse(2 -2 2.5u 0.25u 0.25u 2u 5u)
.ends swod
* clock 2
.subckt swev 31 33
m1 31 32 33 34 nmod
.model nmod
NMOS (level=1 )
m2 33 37 31 36 pmod
.model pmod
PMOS (level=1 )
vb1 34 0 dc -2.5v
vb2 36 0 dc 2.5v
vg1 32 0 pulse(-2 2 0.5u 0.25u 0.25u 1u 5u)
vg2 37 0 pulse(2 -2 0.5u 0.25u 0.25u 1u 5u)
.ends swev
vin 1 0 dc 3v
iin 1 2 sin(0 30ua 500hz)
* integrator start
i11 20 3 200ua
i12 20 7 12.5ua
i13 20 9 100ua
vs11 5 0 dc -2.5v
vs12 17 0 dc -2.5v
vs13 8 0 dc -2.5v
vs14 10 0 dc -2.5v
x11 2 3 swev
x13 3 4 swev
x14 3 6 swod
x16 3 7 swod
*outputs
vdummy1 9 11 0v
vo1 11 0 3v
vbias 20 0 2.5v
.tran 0.5us 2ms
.ac dec 100 10hz 100MEGhz
.probe
.print ac i(iin)
.end
vin 1 0 dc 5v
iin 1 2 dc 100ua
*outputs
rout 3 4 1k
vout 4 0 3v
.DC LIN Iin 0 500U 10U
.op
.tran 0.5us 2ms
.probe
.end