9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

//
//
//AXIMaster
//
//Verilogstandard:Verilog2001
//
//
//Structure:
//axi3_master
//
//LastUpdate:
//2/07/2013
//
//
/*
AXIMasterExample

ThepurposeofthisdesignistoprovideahighthroughputAXI3example
andAXIthroughputdemonstration.

Theexampleuserapplicationperformsasimplememory
testthroughcontinuousburstwritestomemory,followedbyburst
reads.Thesimpledatapatternischeckedandanydatacomparisonor
interfaceerrorsarelatchedwiththeexampleERRORoutput.

Tomodifythisexampleforotherapplications,edit/removethelogic
associatedwiththe'Example'sectioncomments.Forclarity,most
transferqualifiersareleftasconstants,butcanbeeasilyadded
totheirassociatedchannels.

ThelatestversionofthisfilecanbefoundinXilinxAnswer37425
http://www.xilinx.com/support/answers/37425.htm
*/
`timescale1ns/1ps
//SimpleLog2calculationfunction
`defineC_LOG_2(n)(\
(n)<=(1<<0)?0:(n)<=(1<<1)?1:\
(n)<=(1<<2)?2:(n)<=(1<<3)?3:\
(n)<=(1<<4)?4:(n)<=(1<<5)?5:\
(n)<=(1<<6)?6:(n)<=(1<<7)?7:\
(n)<=(1<<8)?8:(n)<=(1<<9)?9:\
(n)<=(1<<10)?10:(n)<=(1<<11)?11:\
(n)<=(1<<12)?12:(n)<=(1<<13)?13:\
(n)<=(1<<14)?14:(n)<=(1<<15)?15:\
(n)<=(1<<16)?16:(n)<=(1<<17)?17:\
(n)<=(1<<18)?18:(n)<=(1<<19)?19:\
(n)<=(1<<20)?20:(n)<=(1<<21)?21:\
(n)<=(1<<22)?22:(n)<=(1<<23)?23:\
(n)<=(1<<24)?24:(n)<=(1<<25)?25:\
(n)<=(1<<26)?26:(n)<=(1<<27)?27:\
(n)<=(1<<28)?28:(n)<=(1<<29)?29:\
(n)<=(1<<30)?30:(n)<=(1<<31)?31:32)
moduleaxi3_master#
(
parameterC_M_AXI_PROTOCOL="AXI3",
parameterintegerC_M_AXI_THREAD_ID_WIDTH=1,
parameterintegerC_M_AXI_ADDR_WIDTH=32,
parameterintegerC_M_AXI_DATA_WIDTH=32,
parameterintegerC_M_AXI_AWUSER_WIDTH=1,
parameterintegerC_M_AXI_ARUSER_WIDTH=1,
parameterintegerC_M_AXI_WUSER_WIDTH=1,
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

1/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

parameterintegerC_M_AXI_RUSER_WIDTH=1,
parameterintegerC_M_AXI_BUSER_WIDTH=1,

/*Disablingtheseparameterswillremoveanythrottling.
TheresultingERRORflagwillnotbeuseful*/
parameterintegerC_M_AXI_SUPPORTS_WRITE=1,
parameterintegerC_M_AXI_SUPPORTS_READ=1,

/*Maxcountofwrittenbutnotyetreadbursts.
Iftheinterconnect/slaveisabletoacceptenough
addressesandthereadchannelsarestalled,the
masterwillissuethismanycommandsaheadof
writeresponses*/
parameterintegerC_INTERCONNECT_M_AXI_WRITE_ISSUING=8,

////////////////////////////
//Exampledesignparameters
////////////////////////////

//Baseaddressoftargetedslave
parameterC_M_AXI_TARGET='h00000000,

//Numberofaddressbitstotestbeforewrapping
parameterintegerC_OFFSET_WIDTH=20,

/*Burstlengthfortransactions,inC_M_AXI_DATA_WIDTHs.
Non2^nlengthswilleventuallycauseburstsacross4K
addressboundaries.*/
parameterintegerC_M_AXI_BURST_LEN=16
)
(
//SystemSignals
inputwire

ACLK,
inputwire

ARESETN,

//MasterInterfaceWriteAddress
outputwire[C_M_AXI_THREAD_ID_WIDTH1:0]M_AXI_AWID,
outputwire[C_M_AXI_ADDR_WIDTH1:0]M_AXI_AWADDR,
outputwire[41:0]

M_AXI_AWLEN,
outputwire[31:0]

M_AXI_AWSIZE,
outputwire[21:0]

M_AXI_AWBURST,
outputwire

M_AXI_AWLOCK,
outputwire[41:0]

M_AXI_AWCACHE,
outputwire[31:0]

M_AXI_AWPROT,
//outputwire[41:0]

M_AXI_AWREGION,
//AXI4outputwire[41:0]

M_AXI_AWQOS,
outputwire[C_M_AXI_AWUSER_WIDTH1:0]M_AXI_AWUSER,
outputwire

M_AXI_AWVALID,
inputwire

M_AXI_AWREADY,

//MasterInterfaceWriteData
outputwire[C_M_AXI_THREAD_ID_WIDTH1:0]M_AXI_WID,
outputwire[C_M_AXI_DATA_WIDTH1:0]M_AXI_WDATA,
outputwire[C_M_AXI_DATA_WIDTH/81:0]M_AXI_WSTRB,
outputwire

M_AXI_WLAST,
outputwire[C_M_AXI_WUSER_WIDTH1:0]M_AXI_WUSER,
outputwire

M_AXI_WVALID,
inputwire

M_AXI_WREADY,

//MasterInterfaceWriteResponse
inputwire[C_M_AXI_THREAD_ID_WIDTH1:0]M_AXI_BID,
inputwire[21:0]

M_AXI_BRESP,
inputwire[C_M_AXI_BUSER_WIDTH1:0]M_AXI_BUSER,
inputwire

M_AXI_BVALID,
outputwire

M_AXI_BREADY,
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

2/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

//MasterInterfaceReadAddress
outputwire[C_M_AXI_THREAD_ID_WIDTH1:0]M_AXI_ARID,
outputwire[C_M_AXI_ADDR_WIDTH1:0]M_AXI_ARADDR,
outputwire[41:0]

M_AXI_ARLEN,
outputwire[31:0]

M_AXI_ARSIZE,
outputwire[21:0]

M_AXI_ARBURST,
outputwire[21:0]

M_AXI_ARLOCK,
outputwire[41:0]

M_AXI_ARCACHE,
outputwire[31:0]

M_AXI_ARPROT,
//AXI3outputwire[41:0]

M_AXI_ARREGION,
//outputwire[41:0]

M_AXI_ARQOS,
outputwire[C_M_AXI_ARUSER_WIDTH1:0]M_AXI_ARUSER,
outputwire

M_AXI_ARVALID,
inputwire

M_AXI_ARREADY,

//MasterInterfaceReadData
inputwire[C_M_AXI_THREAD_ID_WIDTH1:0]M_AXI_RID,
inputwire[C_M_AXI_DATA_WIDTH1:0]M_AXI_RDATA,
inputwire[21:0]

M_AXI_RRESP,
inputwire

M_AXI_RLAST,
inputwire[C_M_AXI_RUSER_WIDTH1:0]M_AXI_RUSER,
inputwire

M_AXI_RVALID,
outputwire

M_AXI_RREADY,
//ExampleDesign
outputwire
);

ERROR

//Afancyterminalcounter,usingextrabitstoreducedecodelogic
localparaminteger

C_WLEN_COUNT_WIDTH=
`C_LOG_2(C_M_AXI_BURST_LEN2)+2;
reg[C_WLEN_COUNT_WIDTH1:0]

wlen_count;
//Localaddresscounters
reg[C_OFFSET_WIDTH1:0]
reg[C_OFFSET_WIDTH1:0]

araddr_offset='b0;
awaddr_offset='b0;

//Examplethrottlingcounters
reg[`C_LOG_2(C_INTERCONNECT_M_AXI_WRITE_ISSUING)1:0]
reg[`C_LOG_2(C_INTERCONNECT_M_AXI_WRITE_ISSUING)1:0]
reg[`C_LOG_2(C_INTERCONNECT_M_AXI_WRITE_ISSUING)1:0]
//Throttlingflags
reg

reg

reg

//Exampleuserapplicationsignals
reg

reg

reg[C_OFFSET_WIDTH1:0]

reg[C_OFFSET_WIDTH1:0]

//Interfaceresponseerrorflags
wire

wire

//AXI4tempsignals
reg

wire

reg

reg

reg

unread_writes;
aw_issue_count;
w_issue_count;

aw_throttle;
w_throttle;
ar_throttle;

read_mismatch;
error_reg;
data_gen;//optimizedforexampledesign
wdata;//optimizedforexampledesign

write_resp_error;
read_resp_error;

awvalid;
wlast;
wvalid;
bready;
arvalid;

http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

3/11

9/17/2015

reg

wire

/////////////////
//I/OConnections
/////////////////
////////////////////
//WriteAddress(AW)
////////////////////

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

rready;

wnext;

//Singlethreaded
assignM_AXI_AWID='b0;
//TheAXIaddressisaconcatenationofthetargetbaseaddress+activeoffsetrange
assignM_AXI_AWADDR={C_M_AXI_TARGET[C_M_AXI_ADDR_WIDTH1:C_OFFSET_WIDTH],awaddr_offset};
//BurstLENgthisnumberoftransactionbeats,minus1
assignM_AXI_AWLEN=C_M_AXI_BURST_LEN1;
//SizeshouldbeC_M_AXI_DATA_WIDTH,in2^SIZEbytes,otherwisenarrowburstsareused
assignM_AXI_AWSIZE=`C_LOG_2(C_M_AXI_DATA_WIDTH/8);
//INCRbursttypeisusuallyused,exceptforkeyholebursts
assignM_AXI_AWBURST=2'b01;
assignM_AXI_AWLOCK=1'b0;
//NotAllocated,ModifiableandBufferable
assignM_AXI_AWCACHE=4'b0011;
assignM_AXI_AWPROT=3'h0;
assignM_AXI_AWQOS=4'h0;
//SetUser[0]to1toallowZynqcoherentACPtransactions
assignM_AXI_AWUSER='b1;
assignM_AXI_AWVALID=awvalid;
///////////////
//WriteData(W)
///////////////
assignM_AXI_WDATA={C_M_AXI_TARGET[C_M_AXI_ADDR_WIDTH1:C_OFFSET_WIDTH],wdata};
//Allburstsarecompleteandalignedinthisexample
assignM_AXI_WID='b0;
assignM_AXI_WSTRB={(C_M_AXI_DATA_WIDTH/8){1'b1}};
assignM_AXI_WLAST=wlast;
assignM_AXI_WUSER='b0;
assignM_AXI_WVALID=wvalid;
////////////////////
//WriteResponse(B)
////////////////////
assignM_AXI_BREADY=bready;
///////////////////
//ReadAddress(AR)
///////////////////
assignM_AXI_ARID='b0;
assignM_AXI_ARADDR={C_M_AXI_TARGET[C_M_AXI_ADDR_WIDTH1:C_OFFSET_WIDTH],araddr_offset};
//BurstLENgthisnumberoftransactionbeats,minus1
assignM_AXI_ARLEN=C_M_AXI_BURST_LEN1;
//SizeshouldbeC_M_AXI_DATA_WIDTH,in2^nbytes,otherwisenarrowburstsareused
assignM_AXI_ARSIZE=`C_LOG_2(C_M_AXI_DATA_WIDTH/8);
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

4/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

//INCRbursttypeisusuallyused,exceptforkeyholebursts
assignM_AXI_ARBURST=2'b01;
assignM_AXI_ARLOCK=1'b0;

//NotAllocated,ModifiableandBufferable
assignM_AXI_ARCACHE=4'b0011;
assignM_AXI_ARPROT=3'h0;
assignM_AXI_ARQOS=4'h0;
//SetUser[0]to1toallowZynqcoherentACPtransactions
assignM_AXI_ARUSER='b1;
assignM_AXI_ARVALID=arvalid;
////////////////////////////
//ReadandReadResponse(R)
////////////////////////////
assignM_AXI_RREADY=rready;
////////////////////
//ExampledesignI/O
////////////////////
assignERROR=error_reg;
////////////////////////////////////////////////
//Resetlogic,workaroundforAXI_BRAMCR#582705
////////////////////////////////////////////////
regaresetn_r=1'b0;
regaresetn_r1=1'b0;
regaresetn_r2=1'b0;
regaresetn_r3=1'b0;
regaresetn_r4=1'b0;
always@(posedgeACLK)
begin
aresetn_r<=ARESETN;
aresetn_r1<=aresetn_r;
aresetn_r2<=aresetn_r1;
aresetn_r3<=aresetn_r2;
aresetn_r4<=aresetn_r3;
end

///////////////////////
//WriteAddressChannel
///////////////////////
/*
Thepurposeofthewriteaddresschannelistorequesttheaddressand
commandinformationfortheentiretransaction.Itisasinglebeat
ofdataforeachburst.

TheAXI4Writeaddresschannelinthisexamplewillcontinuetoinitiate
writecommandsasfastasitisallowedbytheslave/interconnect.

Theaddresswillbeincrementedoneachacceptedaddresstransaction,
untilwrappingontheC_OFFSET_WIDTHboundarywithawaddr_offset.
*/
always@(posedgeACLK)
begin

/*DelaywriteaddresschannelbyafewcyclesforCR#582705
Onlynecessarywhenpoint2pointtoAXI_BRAMslave*/
if(aresetn_r4==0)
//if(ARESETN==0)
awvalid<=1'b0;

//Ifpreviouslynotvalidandnothrottling,startnexttransaction
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

5/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

elseif(C_M_AXI_SUPPORTS_WRITE&&awvalid==0&&aw_throttle==0)
awvalid<=1'b1;

/*Onceasserted,VALIDscannotbedeasserted,soAWVALID
mustwaituntiltransactionisacceptedbeforethrottling*/
elseif(M_AXI_AWREADY&&awvalid&&aw_throttle)
awvalid<=1'b0;
else
awvalid<=awvalid;
end

//NextaddressafterAWREADYindicatespreviousaddressacceptance
always@(posedgeACLK)
begin
if(ARESETN==0)
awaddr_offset<='b0;
elseif(M_AXI_AWREADY&&awvalid)
awaddr_offset<=awaddr_offset+C_M_AXI_BURST_LEN*C_M_AXI_DATA_WIDTH/8;
else
awaddr_offset<=awaddr_offset;
end

////////////////////
//WriteDataChannel
////////////////////
/*
Thewritedatawillcontinuallytrytopushwritedataacrosstheinterface.
TheamountofdataacceptedwilldependontheAXIslaveandtheAXI
Interconnectsettings,suchasifthereareFIFOsenabledininterconnect.

Notethatthereisnoexplicittimingrelationshiptothewriteaddresschannel.
Thewritechannelhasitsownthrottlingflag,separatefromtheAWchannel.

Synchronizationbetweenthechannelsmustbedeterminedbytheuser.

Thesimpliestbutlowestperformancewouldbetoonlyissueoneaddresswrite
andwritedataburstatatime.

Inthisexampletheyarekeptinsyncbyusingthesameaddressincrement
andburstsizes.ThentheAWandWchannelshavetheirtransactionsmeasured
withthresholdcountersaspartoftheuserlogic,tomakesureneither
channelgetstoofaraheadofeachother.
*/
//Forwardmovementoccurswhenthechannelisvalidandready
assignwnext=M_AXI_WREADY&wvalid;
//WVALIDlogic,similartotheAWVALIDalwaysblockabove
always@(posedgeACLK)
begin
if(aresetn_r4==0)
//if(ARESETN==0)
wvalid<=1'b0;

//Ifpreviouslynotvalidandnotthrottling,startnexttransaction
elseif(C_M_AXI_SUPPORTS_WRITE&&wvalid==0&&w_throttle==0)
wvalid<=1'b1;
/*IfWREADYandtoomanywrites,throttleWVALID
Onceasserted,VALIDscannotbedeasserted,soWVALID
mustwaituntilburstiscompletewithWLAST*/
elseif(wnext&&wlast&&w_throttle)
wvalid<=1'b0;
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

6/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

else
wvalid<=wvalid;
end
//WLASTgenerationontheMSBofacounterunderflow
assignwlast=wlen_count[C_WLEN_COUNT_WIDTH1];
/*Burstlengthcounter.Usesextracounterregisterbittoindicateterminal
counttoreducedecodelogic*/
always@(posedgeACLK)
begin
if(ARESETN==0||(wnext&&wlen_count[C_WLEN_COUNT_WIDTH1]))

wlen_count<=C_M_AXI_BURST_LEN2;
elseif(wnext)

wlen_count<=wlen_count1;
else

wlen_count<=wlen_count;
end
/*WriteDataGenerator
Datapatternisonlyasimpleincrementingcountfrom0foreachburst*/
always@(posedgeACLK)
begin
if(ARESETN==0)
wdata<='b0;
elseif(wnext&&wlast)
wdata<='b0;
elseif(wnext)
wdata<=wdata+1;
else
wdata<=wdata;
end
////////////////////////////
//WriteResponse(B)Channel
////////////////////////////
/*
Thewriteresponsechannelprovidesfeedbackthatthewritehascommitted
tomemory.BREADYwilloccurwhenallofthedataandthewriteaddress
hasarrivedandbeenacceptedbytheslave.

Thewriteissuance(numberofoutstandingwriteaddresses)isstartedby
theAddressWritetransfer,andiscompletedbyaBREADY/BRESP.

WhilenegatingBREADYwilleventuallythrottletheAWREADYsignal,
itisbestnottothrottlethewholedatachannelthisway.

TheBRESPbit[1]isusedindicateanyerrorsfromtheinterconnector
slavefortheentirewriteburst.Thisexamplewillcapturetheerror
intotheERRORoutput.
*/
//Alwaysacceptwriteresponses
always@(posedgeACLK)
begin
if(ARESETN==0)

bready<=1'b0;
else

bready<=C_M_AXI_SUPPORTS_WRITE;
end
//Flaganywriteresponseerrors
assignwrite_resp_error=bready&M_AXI_BVALID&M_AXI_BRESP[1];
//////////////////////
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

7/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

//ReadAddressChannel
//////////////////////
/*
TheReadAddressChannel(AW)providesasimilarfunctiontothe
WriteAddresschanneltoprovidethetranferqualifiersforthe
burst.

Inthisexample,thereadaddressincrementsinthesame
mannerasthewriteaddresschannel.
*/
always@(posedgeACLK)
begin
if(ARESETN==0)
begin

arvalid<=1'b0;

araddr_offset<='b0;
end
elseif(arvalid&&M_AXI_ARREADY)
begin

arvalid<=1'b0;

araddr_offset<=araddr_offset+C_M_AXI_BURST_LEN*C_M_AXI_DATA_WIDTH/8;
end
elseif(C_M_AXI_SUPPORTS_READ&&ar_throttle==0)
begin

arvalid<=1'b1;

araddr_offset<=araddr_offset;
end
else
begin

arvalid<=arvalid;

araddr_offset<=araddr_offset;
end
end
//////////////////////////////////
//ReadData(andResponse)Channel
//////////////////////////////////
/*
TheReadDatachannelreturnstheresultsofthereadrequest

Inthisexamplethedatacheckerisalwaysabletoaccept
moredata,sononeedtothrottletheRREADYsignal
*/
always@(posedgeACLK)
begin
if(ARESETN==0)

rready<=1'b0;
else

rready<=C_M_AXI_SUPPORTS_READ;
end
//Checkreceivedreaddataagainstdatagenerator
always@(posedgeACLK)
begin
if(ARESETN==0)

read_mismatch<=1'b0;
//OnlycheckdatawhenRVALIDisactive
elseif((M_AXI_RVALID&&rready)&&(M_AXI_RDATA!=data_gen))

read_mismatch<=1'b1;
else

read_mismatch<=1'b0;
end
assignread_resp_error=rready&M_AXI_RVALID&M_AXI_RRESP[1];
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

8/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

//////////////////////////////////////////
//Exampledesignreadcheckdatagenerator
//////////////////////////////////////////
//Generateexpectedreaddatatocheckagainstactualreaddata
always@(posedgeACLK)
begin
if(ARESETN==0)
data_gen<='b0;
//Onahandshakedcycle,resetiflasttransfer,otherwiseincrement
elseif(M_AXI_RVALID&&rready)
begin

if(M_AXI_RLAST)

data_gen<='b0;

else

data_gen<=data_gen+1;
end
else
data_gen<=data_gen;
end
///////////////////////////////
//Exampledesignerrorregister
///////////////////////////////
//Registerandholdanydatamismatches,orread/writeinterfaceerrors
always@(posedgeACLK)
begin
if(ARESETN==0)
error_reg<=1'b0;
elseif(read_mismatch||write_resp_error||read_resp_error)
error_reg<=1'b1;
else
error_reg<=error_reg;
end
///////////////////////////
//Exampledesignthrottling
///////////////////////////
/*
Formaximumportthroughput,thisuserexamplecodewilltrytoallow
eachchanneltorunasindependentlyandasquicklyaspossible.

However,therearetimeswhentheflowofdataneedstobethrottedby
theuserapplication.Thisexampleapplicationrequiresthatdatais
notreadbeforeitiswrittenandthatthewritechannelsdonot
advancebeyondanarbitrarythreshold(saytopreventan
overrunofthecurrentreadaddressbythewriteaddress).

FromAXI4Specification,13.13.1:"Ifamasterrequiresorderingbetween
readandwritetransactions,itmustensurethataresponseisreceived
fortheprevioustransactionbeforeissuingthenexttransaction."

Thisexampleaccomplishesthisuserapplicationthrottlingthrough:
Readswaitforwritestofullycomplete
Addresswriteswaitwhennotread+issuedtransactioncountspass
aparameterizedthreshold
Writeswaitwhenanotread+activedataburstcountpass
aparameterizedthreshold
*/
//Up/downcounterofaccepted,butnotcompleted,writeaddresscommands
always@(posedgeACLK)
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

9/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

begin
if(ARESETN==0)
aw_issue_count<='b0;
elseif(bready&&M_AXI_BVALID&&M_AXI_AWVALID&&M_AXI_AWREADY)
aw_issue_count<=aw_issue_count;
elseif(bready&&M_AXI_BVALID)
aw_issue_count<=aw_issue_count1;
elseif(M_AXI_AWVALID&&M_AXI_AWREADY)
aw_issue_count<=aw_issue_count+1;
else
aw_issue_count<=aw_issue_count;
end
//Up/downcounterofburstsofdatawritten,butnotcompletedwithBREADY
always@(posedgeACLK)
begin
if(ARESETN==0)
w_issue_count<='b0;
elseif(bready&&M_AXI_BVALID&&(M_AXI_WLAST&M_AXI_WVALID&&M_AXI_WREADY))
w_issue_count<=w_issue_count;
elseif(bready&&M_AXI_BVALID)
w_issue_count<=w_issue_count1;
elseif(M_AXI_WLAST&M_AXI_WVALID&&M_AXI_WREADY)
w_issue_count<=w_issue_count+1;
else
w_issue_count<=w_issue_count;
end
//Up/downcounterofwritesthathavebeencompleted,butnotyetread
always@(posedgeACLK)
begin
if(ARESETN==0)

unread_writes<='b0;
elseif(bready&&M_AXI_BVALID&&M_AXI_ARVALID&&M_AXI_ARREADY)

unread_writes<=unread_writes;
elseif(bready&&M_AXI_BVALID)

unread_writes<=unread_writes+1;
elseif(M_AXI_ARVALID&&M_AXI_ARREADY)

unread_writes<=unread_writes1;
else

unread_writes<=unread_writes;
end
/*Iftherearefullycompletedwrites,allowreadstostart
Ifthewritelogicisremoved,neverthrottlereads*/
always@(unread_writes)
begin
if(unread_writes>0||C_M_AXI_SUPPORTS_WRITE==0)
ar_throttle=1'b0;
else
ar_throttle=1'b1;
end
/*Ifreadssupportedandthenumberofcompletedbutnotreadbursts+
issuedbutnotyetcompletedwriteaddressesisequalorgreaterthanathreshold,
throttletheaddresswritechannel.*/
always@(aw_issue_count,unread_writes)
begin
if(C_M_AXI_SUPPORTS_READ&&(aw_issue_count+unread_writes>=
C_INTERCONNECT_M_AXI_WRITE_ISSUING))
aw_throttle=1'b1;
else
aw_throttle=1'b0;
end
http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

10/11

9/17/2015

vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

/*Ifthenumberofcompletedbutnotreadbursts+issuedbutnot
yetcompletedwriteaddressesisequalorgreaterthanathreshold,
throttletheaddresswritechannel.*/
always@(w_issue_count,unread_writes)
begin
if(C_M_AXI_SUPPORTS_READ&&(w_issue_count+unread_writes>=
C_INTERCONNECT_M_AXI_WRITE_ISSUING))
w_throttle=1'b1;
else
w_throttle=1'b0;
end
endmodule

http://vserver.13thfloor.at/Stuff/XILINX/axi3_master/repository/axi3_master.v

11/11