Princess Sumaya Univ.

Computer Engineering Dept.

Chapter 6:

Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Registers

I0

Group of D Flip-Flops

Synchronized (Single Clock)

Store Data

A0

A1

A2

A3

R
I1

D
R

I2

D
R

I3
CLK
Reset

D
R

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Registers

CLK

I0

A0

A1

A2

A3

I3
I2

I1

I1

I0
I2

A3

A2

A1

I3

A0
Note:
Note New data has to go in
with every clock

CLK
Reset

D
R

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Registers with Parallel Load

Control Loading the Register with New Data

D7
D6
D5
D4
D3
D2
D1
D0

R
E
G
I
S
T
E
R
LD

Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0

LD
0
1

Q(t+1)
Q(t)
D

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Registers with Parallel Load

Should we block the Clock to keep the Data?

D7
D6
D5
D4
D3
D2
D1
D0

R
E
G
I
S
T
E
R
LD

Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0

Delays
the
Clock

Load
CLK

I0

A0

I1

A1

I2

A2

I3

A3

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Registers with Parallel Load

Circulate the old data

I0

I0 MUX
Y
I1
S

A0

I1

I0 MUX
Y
I1
S

A1

I2

I0 MUX
Y
I1
S

A2

I3

I0 MUX
Y
I1
S

A3

Load

CLK

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Shift Registers

4-Bit Shift Register

Serial SI
Input

SO
Serial
Output

CLK

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Shift Registers

SI

Q3

Q2

Q1

Q0

SO

CLK
CLK
SI
Q3
Q2
Q1
Q0

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Serial Transfer

SI
Clock
Shift
Control

Shift Register A
CLK

SO

SI

Shift Register B
CLK

Clock
Shift
Control
CLK

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Serial Addition

Shift
Control

CLK

SI
Shift Register A

x
S
y FA
C
z

Shift Register B

CLR
Clear

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Universal Shift Register

Parallel-in Parallel-out
Serial-in Serial-out
Serial-in Parallel-out
Parallel-in Serial-out

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Universal Shift Register

CLR
CLK
S1

Q3

Q2

Q1

Q0

S1

Y
S0 MUX
I3 I2 I1 I0

S0
SI
for
SR

D3

D2

D1

D0

SI
for
SL
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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Universal Shift Register

S1
S0
SRin

Q3 Q2 Q1 Q0

CLR

USR
D3 D2 D1 D0

Mode Control

SLin

S1

S0

Register
Operation

0
0
1
1

0
1
0
1

No change
Shift right
Shift left
Parallel load

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Ripple Counters

Ripple Asynchronous
Q3

Q2
Q

T 1

Q1
Q

T 1

Q0
Q

T 1

T 1
CLK

CLR

CLR

CLR

CLR

CLR
CLK
Q0
Q1
Q2
Q3

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Ripple Counters

Q3

Q2

Q1

Q0

D
CLK

CLK
Q0
Q1
Q2
Q3

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

BCD Ripple Counter

0000

0001

0010

0011

0100

1001

1000

0111

0110

0101

Q3

Q2

Q1
1

K 1

K 1

Q0
1

K 1

K 1

CLK

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Decades Counter

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

BCD
Counter

BCD
Counter

BCD
Counter

100s Digit

10s Digit

1s Digit

Count
(CLK)

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Synchronous Binary Counter

Q3

Q2

Q1

Q0
Enable

To
Next
Stage

K
CLK

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Up-Down Binary Counter

Q3

Q2
Q
Q

Q1
Q
Q

Q0
Q
Q

Q
CLK

Up

Down
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Dept.

4241 Digital Logic Design

Computer Engineering

BCD Counter
0
0000

0
1

0001

0
1

0010

0
1

0011

0
1

0100
1

1
1001
0

1000
0

0111

0110

0101
0

Q3 Q2 Q1 Q0
E

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

BCD Counter
0
0000 / 0

0
1

0001 / 0

0010 / 0

0
1

0011 / 0

0
1

0100 / 0
1

1
1001 / 1
0

1000 / 0
0

0111 / 0

0110 / 0

0101 / 0
0

Q3 Q2 Q1 Q0
y

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Binary Counter with Parallel Load

CLR

LD

Count

Q(t+1)

Q(t)

Q(t)+1

I3

Q3

I2

Q2

I1

Q1

I0

Q0

LD
Count
CLR

Usually Asynchronous Clear

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

BCD Counter Example

LD

Count

I3

Q3

A3

I2

Q2

A2

I1

Q1

A1

I0

Q0

A0

Count
CLR
1

CLK
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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Ring Counter
0001

T3 T2 T1 T0

0010

0100

1000

CLK
T0

2-to-4 Decoder

T1
T2

2-bit counter

T3

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Johnson Counter
0000

0001

0011

0111

1000

1100

1110

1111

Q3

Q1

Q2
Q
Q

Q
Q

Q0
Q
Q

Q
CLK
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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Homework

Mano
Chapter 6
6-2
6-3
6-4
6-13
6-14
6-16
6-18

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Homework

6-2

Include a synchronous clear input to the Register with

Parallel Load. The modified register will have a parallel
load capability and a synchronous clear capability. The
register is cleared synchronously when the clock goes
through a positive transition and the clear input is equal
to 1.

6-3

What is the difference between serial and parallel

transfer? Explain how to convert serial data to parallel
and parallel data to serial. What type of register is
needed?

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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Homework

6-4

The content of a 4-bit register is initially 1101. The

register is shifted six times to the right with the serial
input being 101101. What is the content of the register
after each shift?

6-13 Show that a BCD ripple counter can be constructed using

a 4-bit binary ripple counter with asynchronous clear and
a NAND gate that detects the occurrence of count 1010.
6-14 How many flip-flop will be complemented in a 10-bit
binary ripple counter to reach the next count after the
following count:
(a) 1001100111
(b) 0011111111
(c) 1111111111
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Princess Sumaya University

Dept.

4241 Digital Logic Design

Computer Engineering

Homework

6-16 The BCD ripple counter has four flip-flops and 16 states,
of which only 10 are used. Analyze the circuit and
determine the next state for each of the other six unused
states. What will happen if a noise signal sends the circuit
to one of the unused states?
6-18 What operation is performed in the up-down counter
when both the up and down inputs are enabled? Modify
the circuit so that when both inputs are equal to 1, the
counter does not change state, but remains in the same
count.

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