library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is port(
A, B: in STD_LOGIC_VECTOR (3 downto 0)
S: in STD_LOGIC_VECTOR (3 downto 0)
R: out STD_LOGIC_VECTOR (3 downto 0);
Bdrs: out STD_LOGIC_VECTOR (2 downto 0));
en ALU;
architecture OPARLO of ALU is
signal dato,dato1: std_logic_vector(3 downto 0);
signal slow_clk1,reloj : std_logic; --reloj se utiliza para control del display
signal clk_divider : std_logic_vector(23 downto 0):= x"000000";
begin
clk_division : process (clk, clk_divider)
begin
if clk'event and clk = '1' then
clk_divider <= clk_divider + 1;
end if;
slow_clk1<= clk_divider(15);
end process clk_division;
display: process(slow_clk1)
begin
if slow_clk1'event and slow_clk1= '1' then
reloj <= not reloj;
if reloj = '1' then
c1 <= '0';
c2 <= '1';
c3 <= '1';
c4 <= '1';
dato <= dato1;
end if;
end if;
end process display;
operaciones: porcess (A, B, S, R) begin
with S (3 downto 0) select
R <= A AND B when "0000", "0001";
A OR B when "0010", "0011";
NOT A when "0100", "0101";
A XOR B when "0110", "0111";
A + B when "1000";
A + B + 1 when "1001";
A + 1 when "1010";
A - 1 when "1011";
A - B when "1100";

A when "1101";
A - B - 1 when "1110";
B - A when "1111";
dato1<=R;
end process operaciones;

O <=

c1<=dato
end OPARLO;

"0000001" when
"1001111" when
"0010010" when
"0000110" when
"1001100" when
"0100100" when
"0100000" when
"0001111" when
"0000000" when
"0000100" when
"0001000" when
"1100000" when
"0110001" when
"1000010" when
"0110000" when
"0011000" when
"1001000";

(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato
(dato

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

"0000")
"0001")
"0010")
"0011")
"0100")
"0101")
"0110")
"0111")
"1000")
"1001")
"1010")
"1011")
"1100")
"1101")
"1110")
"1111")

else
else
else
else
else
else
else
else
else
else
else
else
else
else
else
else