MAHA BARATHI ENGINEERING COLLEGE

CHINNASALEM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
EC6612-VLSI DESIGN
LAB MANUAL

EC6612 VLSI DESIGN LAB

1.

HDL based design entry and simulation of simple counters, state machines, adders
(min 8 bit) and multipliers (4 bit min).

2.

Synthesis, P&R and post P&R simulation of the components simulated in (I) above.
Critical paths and static timing analysis results to be identified. Identify and verify
possible conditions under which the blocks will fail to work correctly.

3.

Hardware fusing and testing of each of the blocks simulated in (I). Use of either

chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL
and demonstrate the use of the PLL module for clock generation in FPGAs.
4. Design and simulation of a simple 5 transistor differential amplifier. Measure gain,
ICMR, and CMRR.
5. Layout generation, parasitic extraction and resimulation of the circuit designed in (I)
6. Synthesis and Standard cell based design of an circuits simulated in 1(I) above.
Identification of critical paths, power consumption.
7. For expt (c) above, P&R, power and clock routing, and post P&R simulation.
8.

Analysis of results of static timing analysis.

COMBINATIONAL CIRCUIT DESIGN

STUDY EXPERIMENTS
BASIC LOGIC GATES
AIM:
To study and synthesis of basic logic gates in Verilog HDL using Xilinx tools
APPARATUS REQUIRED:

PC with Windows XP.

XILINX software.

Theory:
A logic gate is a physical model of a boolean function that is, it performs a logical operation on
one or more logic inputs and produces a single logic output. Logic gates are primarily
implemented electronically using diodes or transistors, but can also be constructed using
electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even
mechanical elements.With amplification, logic gates can be cascaded in the same way that
Boolean functions can be composed, allowing the construction of a physical model of all of
Boolean logic, and therefore, all of the algorithms and mathematics that can be described with
Boolean logic Synthesis is the process of constructing a gate level netlist from a register-transfer
Level models of the circuit described in Verilog HDL ,VHDL or mixed language designs.

PROCEDURE:
1. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project navigator
2. File New Project
3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports click
next and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax process window synthesize double click check syntax and
remove errors, if present , with proper syntax & coding.
9. synthesis your design, from the source window select, Synthesis/Implementation from the
window Now double click the synthesis XSt
10. After the HDL synthesiss phase of the synthesis process,you can display a schematic
representation of your synthesized source file.This schematic shows a representation of the
pre-optimized design in terms of generic symbols,such as adders,multipliers,counters,Ann
gates and OR gates double click View RTL schematic
11. Double click the schematic to internal view
12. Double click outside the schematic to move one-level back

13. This Schematic Shows a representation of the design in terms of logic elements optimized to
the target device. For example,in terms of LUTs(Look Up Table),carry logic,I/O buffers and
other technology-specific components
Double click View technology Schematic
14.Double click the Schematic to inner view
15.Double click the LUT to inner View.This is gate lenel view of LUT ,if you want see Truth
Table and K-Map for your design just click the respective tabs
16.After finishing the synthesis,you can view number of Slices,LUT(Look Up Table),I/Os are
taken by your design in Device using Design Summary
AND Gate:

PROGRAM:
AND Gate:
module Andgate(i1, i2, out);
input i1;
input i2;
output out;
and (out,i1,i2);
endmodule

Truth table:
AND Gate
-----------------------------------------------Input1

Input2

Output

-----------------------------------------------0

-------------------------------------------------

OUTPUT WAVE

OR Gate:

Program:
module Orgate(i1, i2, out);
input i1;

input i2;
output out;
or(out,i1,i2);
endmodule

Truth table:
OR Gate
-----------------------------------------------Input1

Input2

Output

-----------------------------------------------0

------------------------------------------------

Output Wave

NAND Gate:

Program
module Nandgate(i1, i2, out);
input i1;
input i2;
output out;
nand(out,i1,i2);
endmodule

Truth table:
NAND Gate
-----------------------------------------------Input1

Input2

Output

-----------------------------------------------0

------------------------------------------------

Output Wave:

NOR Gate:

Program
module Norgate(i1, i2, out);
input i1;
input i2;
output out;
nor(out,i1,i2);
endmodule

Truth table:
NOR Gate
-----------------------------------------------Input1

Input2

Output

-----------------------------------------------0

------------------------------------------------

Output wave

XOR Gate:

Program
module Xorgate(i1, i2, out);
input i1;
input i2;
output out;
xor(out,i1,i2);
endmodule

Truth table:

XOR Gate
-----------------------------------------------Input1

Input2

Output

-----------------------------------------------0

------------------------------------------------Output Wave

XNOR Gate:

Program
module Xnorgate(i1, i2, out);
input i1;
input i2;
output out;

xnor(out,i1,i2);
endmodule

Truth table:
XNOR Gate
-----------------------------------------------Input1

Input2

Output

-----------------------------------------------0

------------------------------------------------

Output Wave:

Not Gate:

Program
module Notgate(in, out);
input in;
output out;
not(out,in);
endmodule

Truth table:
NOT Gate
--------------------------Input

Output

--------------------------0

---------------------------

Output Wave

Buffer:

Program
module Buffer(in, out);
input in;
output out;
buf(out,in);
endmodule

Truth table :

BUFFER
--------------------------Input

Output

--------------------------0

--------------------------Output Wave:

RESULT:

HALF ADDER AND FULL ADDER

AIM:
To study and synthesis of half adder and full adder circuits in Verilog HDL using Xilinx
tools.
APPARATUS REQUIRED:

PC with Windows XP
XILINX.

Theory:
A half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value
theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design,
pictured on the right, incorporates an XOR gate for S and an AND gate for C. Half adders cannot be
used compositely, given their incapacity for a carry-in bit.
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder
adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit
carried in (in theory from a past addition). The circuit produces a two-bit output sum typically
represented
by
the
signals
Cout
and
S.
Synthesis is the process of constructing a gate level netlist from a register-transfer Level models of the
circuit described in Verilog HDL ,VHDL or mixed language designs.The netlist files contain both
logical design data and constraints .
XILINX SYNTHESIS TOOL enable us to study
1.
2.
3.
4.

Utilization of LUTs & Slices

I/O Buffers assignment
RTL schematic in gate level
Time delay between i/Os and path.

PROCEDURE:

1. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project
navigator
2. File New Project
3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports click
next and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax process window synthesize double click check syntax
and remove errors, if present , with proper syntax & coding.
9. synthesis your design, from the source window select,Synthesis/Implementation from the
window Now double click the synthesis XSt
10. After the HDL synthesiss phase of the synthesis process,you can display a schematic
representation of your synthesized source file.This schematic shows a representation of
the pre-optimized design in terms of generic symbols,such as
adders,multipliers,counters,Ann gates and OR gates double click View RTL
schematic
11. Double click the schematic to internal view
12. Double click outside the schematic to move one-level back
13. This Schematic Shows a representation of the design in terms of logic elements
optimized to the target device. For example,in terms of LUTs(Look Up Table),carry
logic,I/O buffers and other technology-specific components
14. Double click View technology Schematic
15. 14.Double click the Schematic to inner view
16. 15.Double click the LUT to inner View.This is gate lenel view of LUT ,if you want see
Truth Table and K-Map for your design just click the respective tabs
17. 16.After finishing the synthesis,you can view number of Slices,LUT(Look Up
Table),I/Os are taken by your design in Device using Design Summary

Half Adder:

Program :
module HalfAddr(sum, c_out, i1, i2);
output sum;
output c_out;
input i1;
input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule

truth table:

Half Adder
-----------------------------------------------------------------Input1

Input2

Carry

Sum

-----------------------------------------------------------------0

------------------------------------------------------------------

Output Wave:

Full Adder:

Program:
module FullAddr(i1, i2, c_in, c_out, sum);
input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule

Truth Table:

Full Adder
-----------------------------------------------------------------------------------------------i1

i2

C_in

C_out

Sum

-----------------------------------------------------------------------------------------------0

------------------------------------------------------------------------------------------------Output Wave:

Result:

HALF SUBTRACTOR & FULL SUBTRACTOR

AIM:
To study and synthesis of half subtractor and full subtractor circuits in Verilog HDL using
Xilinx tools.
APPARATUS REQUIRED:

PC with Windows XP.

XILINX software.

Theory:
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two
inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).The
Full_subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three
inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D (difference) and B
(borrow).Easy
way
to
write
truth
table
D=X-Y-Z (don't bother about sign)
Synthesis is the process of constructing a gate level netlist from a register-transfer Level models of the
circuit described in Verilog HDL ,VHDL or mixed language designs.
The netlist files contain both logical design data and constraints .
XILINX SYNTHESIS TOOL enable us to study
1.
2.
3.
4.
.

Utilization of LUTs & Slices

I/O Buffers assignment
RTL schematic in gate level
Time delay between i/Os and path

PROCEDURE:
1. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project
navigator
2. File New Project
3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports click
next and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax process window synthesize double click check syntax
and remove errors, if present , with proper syntax & coding.
9. synthesis your design, from the source window select,Synthesis/Implementation from the
window Now double click the synthesis XSt
10. After the HDL synthesiss phase of the synthesis process,you can display a schematic
representation of your synthesized source file.This schematic shows a representation of
the pre-optimized design in terms of generic symbols,such as
adders,multipliers,counters,Ann gates and OR gates double click View RTL
schematic
11. Double click the schematic to internal view
12. Double click outside the schematic to move one-level back
13. This Schematic Shows a representation of the design in terms of logic elements
optimized to the target device. For example,in terms of LUTs(Look Up Table),carry
logic,I/O buffers and other technology-specific components
14. Double click View technology Schematic
15. Double click the Schematic to inner view
16. Double click the LUT to inner View.This is gate lenel view of LUT ,if you want see
Truth Table and K-Map for your design just click the respective tabs
17. After finishing the synthesis,you can view number of Slices,LUT(Look Up Table),I/Os
are taken by your design in Device using Design Summary

Halfsubtractor:

Program:
module HalfSub(i0, i1, bor, dif);
input i0;
input i1;
output bor;
output dif;
wire i0n;
not(i0n,i0);
xor(dif,i0,i1);
and(bor,i0n,i1);
endmodule

Truth Table:
Half Subtractor

-----------------------------------------------------------------------Input1

Input2

Borrow

Difference

------------------------------------------------------------------------0

------------------------------------------------------------------------

Output Wave:

FULL SUBTRACTOR:

Program:
module FullSub(b_in, i1, i0, b_out, dif);
input b_in;
input i1;
input i0;
output b_out;
output dif;
assign {b_out,dif}=i0-i1-b_in;
endmodule

Truth Table:
Full Subtractor

-----------------------------------------------------------------------------------------------A

Difference

bout

-----------------------------------------------------------------------------------------------0

------------------------------------------------------------------------------------------------Output Wave:

Result:

DESIGN AND SIMULATION OF 8-BIT ADDER

Expt. No: 1(A)

Date

AIM:

To design an unsigned 8-bit adder in behavioral modeling of Verilog HDL using Xilinx
tools.

APPARATUS REQUIRED:

PC with Windows XP
XILINX.

Theory:
In electronics, an adder or summer is a digital circuit that performs addition of numbers. In
modern computers adders reside in the arithmetic logic unit (ALU) where other operations are
performed. Although adders can be constructed for many numerical representations, such as
Binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases
where two's complement or one's complement is being used to represent negative numbers, it is
trivial to modify an adder into an adder-subtractor. Other signed number representations require
a more complex adder.
Synthesis is the process of constructing a gate level netlist from a register-transfer Level models
of the circuit described in Verilog HDL ,VHDL or mixed language designs. The netlist files
contain both logical design data and constraints .
XILINX SYNTHESIS TOOL enable us to study
1.
2.
3.
4.

Utilization of LUTs & Slices

I/O Buffers assignment
RTL schematic in gate level
Time delay between i/Os and path

PROCEDURE:
1. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project
navigator

2. File New Project

3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports
click next and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax process window synthesize double click check
syntax and remove errors, if present , with proper syntax & coding.
9. synthesis your design, from the source window select,Synthesis/Implementation from
the window Now double click the synthesis XSt
10. After the HDL synthesiss phase of the synthesis process,you can display a schematic
representation of your synthesized source file.This schematic shows a representation
of the pre-optimized design in terms of generic symbols,such as
adders,multipliers,counters,Ann gates and OR gates double click View RTL
schematic
11. Double click the schematic to internal view
12. Double click outside the schematic to move one-level back
13. This Schematic Shows a representation of the design in terms of logic elements
optimized to the target device. For example, in terms of LUTs(Look Up Table),carry
logic, I/O buffers and other technology-specific components
14. Double click View technology Schematic
15. Double click the Schematic to inner view
16. Double click the LUT to inner View. This is gate lenel view of LUT ,if you want see
Truth Table and K-Map for your design just click the respective tabs
17. After finishing the synthesis,you can view number of Slices,LUT(Look Up
Table),I/Os are taken by your design in Device using Design Summary
RTL-SCHEMATIC

program
module adder(a, b, ci, sum, co);
input
ci;
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output
co;
wire [8:0] tmp;
assign tmp = a + b + ci;
assign sum = tmp [7:0];
assign co = tmp [8];
endmodule

Output Wave:

Result:

DESIGN OF UNSIGNED 4-BIT MULTIPLIER..

Expt. No:1(B)
Date

AIM:
To design of unsigned 4-bit multiplier in Verilog HDL usins Xilinx tools

APPARATUS REQUIRED:

PC with Windows XP
XILINX.

Theory:
A combinational multiplier is a good example of how simple logic functions (gates, half adders
and full adders) can be combined to construct a much more complex function. In particular, it is
possible to construct a 4x4 combinational multiplier from an array of AND gates, half-adders and
full-adders, taking what you have learned recently and extending it to a more complex circuit.
The purpose of this document is to introduce how a relatively complex arithmetic function, such
as binary multiplication, can be realized using simple logic building blocks.
Synthesis is the process of constructing a gate level netlist from a register-transfer Level models
of the circuit described in Verilog HDL ,VHDL or mixed language designs.
The netlist files contain both logical design data and constraints .
XILINX SYNTHESIS TOOL enable us to study
1.
2.
3.
4.

Utilization of LUTs & Slices

I/O Buffers assignment
RTL schematic in gate level
Time delay between i/Os and path

PROCEDURE:
1. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project
navigator
2. File New Project
3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source

6. Select the Verilog Module and give the file name click next and define ports click
next and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax process window synthesize double click check syntax and
remove errors, if present, with proper syntax & coding.
9. synthesis your design, from the source window select, Synthesis/Implementation from the
window Now double click the synthesis XSt
10. After the HDL synthesis phase of the synthesis process, you can display a schematic
representation of your synthesized source file. This schematic shows a representation of
the pre-optimized design in terms of generic symbols, such as
adders,multipliers,counters,Ann gates and OR gates double click View RTL
schematic
11. Double click the schematic to internal view
12. Double click outside the schematic to move one-level back
13. This Schematic Shows a representation of the design in terms of logic elements
optimized to the target device. For example,in terms of LUTs(Look Up Table),carry
logic,I/O buffers and other technology-specific components
14. Double click View technology Schematic
15. Double click the Schematic to inner view
16. Double click the LUT to inner View. This is gate lenel view of LUT ,if you want see
Truth Table and K-Map for your design just click the respective tabs
17. After finishing the synthesis, you can view number of Slices,LUT(Look Up Table),I/Os
are taken by your design in Device using Design Summary

RTL SCHEMATIC

PROGRAM:
module fg(a, b, res);
input [3:0] a;
input [3:0] b;
output [7:0] res;
reg [7:0] res;
always @(a or b )
begin
res=a * b;
end
endmodule

OUTPUT WAVEFORM

Result:
DESIGN OF 4-BIT COUNTER

Expt No:1(C)
Date:
AIM:

To design of 4-Bit Counter in Verilog HDL using Xilinx tools.

Theory:
A counter that can change state in either direction, under the control of an up/down
selector input, is known as an up/down counter. When the selector is in the up state, the
counter increments its value. When the selector is in the down state, the counter
decrements the count. Synthesis is the process of constructing a gate level netlist from a
register-transfer Level models of the circuit described in Verilog HDL ,VHDL or mixed
language designs. The netlist files contain both logical design data and constraints .
XILINX SYNTHESIS TOOL enable us to study
1.
2.
3.
4.

Utilization of LUTs & Slices

I/O Buffers assignment
RTL schematic in gate level
Time delay between i/Os and path

PROCEDURE:
1. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project
navigator
2. File New Project
3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports
click next and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax process window synthesize double click check
syntax and remove errors, if present , with proper syntax & coding.
9. synthesis your design, from the source window select,Synthesis/Implementation from
the window Now double click the synthesis XSt
10. After the HDL synthesiss phase of the synthesis process,you can display a schematic
representation of your synthesized source file.This schematic shows a representation
of the pre-optimized design in terms of generic symbols,such as
adders,multipliers,counters,Ann gates and OR gates double click View RTL
schematic

11. Double click the schematic to internal view

12. Double click outside the schematic to move one-level back
13. This Schematic Shows a representation of the design in terms of logic elements
optimized to the target device. For example,in terms of LUTs(Look Up Table),carry
logic,I/O buffers and other technology-specific components
14. Double click View technology Schematic
15. Double click the Schematic to inner view
16. Double click the LUT to inner View.This is gate lenel view of LUT ,if you want see
Truth Table and K-Map for your design just click the respective tabs
17. After finishing the synthesis,you can view number of Slices,LUT(Look Up
Table),I/Os are taken by your design in Device using Design Summary
RTL-SCHEMATIC

PROGRAM
module counter (clk, s, q);
input
clk, s;
output [3:0] q;

reg [3:0] tmp;

always @(posedge clk)
begin
if (s)
tmp <= 4b1111;
else
tmp <= tmp - 1b1;

end
assign q = tmp;
endmodule
Output Wave

Result:

DESIGN OF STATE MACHINE

Expt No:1(D)
Date:
AIM:
To design of State Machine in Verilog HDL using Xilinx tools.

Theory:
A counter that can change state in either direction, under the control of an up/down
selector input, is known as an up/down counter. When the selector is in the up state, the
counter increments its value. When the selector is in the down state, the counter
decrements the count. Synthesis is the process of constructing a gate level netlist from a
register-transfer Level models of the circuit described in Verilog HDL ,VHDL or mixed
language designs. The netlist files contain both logical design data and constraints .
XILINX SYNTHESIS TOOL enable us to study
5. Utilization of LUTs & Slices

6. I/O Buffers assignment

7. RTL schematic in gate level
8. Time delay between i/Os and path
PROCEDURE:
18. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project
navigator
19. File New Project
20. Enter the project name and location then click next
21. select the Device and other category and click next twice and finish
22. Click on the symbol of FPGA device and then right click click on new source
23. Select the Verilog Module and give the file name click next and define ports
click next and finish
24. Writing the behavioral verilog code in verilog Editor
25. Run the Check syntax process window synthesize double click check
syntax and remove errors, if present , with proper syntax & coding.
26. synthesis your design, from the source window select,Synthesis/Implementation from
the window Now double click the synthesis XSt
27. After the HDL synthesiss phase of the synthesis process,you can display a schematic
representation of your synthesized source file.This schematic shows a representation
of the pre-optimized design in terms of generic symbols,such as
adders,multipliers,counters,Ann gates and OR gates double click View RTL
schematic
28. Double click the schematic to internal view
29. Double click outside the schematic to move one-level back
30. This Schematic Shows a representation of the design in terms of logic elements
optimized to the target device. For example,in terms of LUTs(Look Up Table),carry
logic,I/O buffers and other technology-specific components
31. Double click View technology Schematic
32. Double click the Schematic to inner view

33. Double click the LUT to inner View.This is gate lenel view of LUT ,if you want see
Truth Table and K-Map for your design just click the respective tabs
34. After finishing the synthesis,you can view number of Slices,LUT(Look Up
Table),I/Os are taken by your design in Device using Design Summary

Program:
module stmach(x,clk,reset,y);
input x,clk,reset;
output y;
reg y;
reg [1:0]prestate;
parameter a=2b00, b=2b01, c=2b10, d=2b11;
always @ (posdege clk or negedge reset)
if(~reset) prestate=a;
else
case (prestate)
a: if(x) prestate=a; else prestate=b;
b: if(x) prestate=c; else prestate=d;
c: if(x) prestate=c; else prestate=d;
d: if(x) prestate=d; else prestate=a;
endcase
always @ (prestate)
case (prestate)
a:y=0;
b:y=1;
c:y=1;

d:y=0;
endcase
endmodule

OUTPUT FOR STATE MACHINE

RESELT:

SYNTHESIS OF PLACE AND ROUTE

Expt No:2
Date:
AIM:
To Synthesis of Place and Route the Exno1.
APPARATUS REQUIRED:

PC with Windows XP.

XILINX,.

Theory:
1. Back annotation is the translation of a routed or fitted design to a timing simulation netlist.
2. To define the behavior of the FPGA,a hardware description language(HDL)or Schematic design
methods are used.Common HDLs are VHDL and verilog.Then,using an electronics design
automation (EDA) tool,a technology-mapped netlist is generated .
3. The netlist can then be fitted to the actual FPGA architecture using a process called place-and
route,usually performed by the FPGA vendors proprietary place-and-route software
4. the user will validate the map, place and route results via timing analysis,
simulation, and other verification methodologies. Once the design and validation process is
complete, the binary file generated is used to (re)configure the FPGA.

5. In an attempt to reduce the complexity of designing in HDLs, which have been

compared to
the equivalent of assembly.
6. In a typical design flow, an FPGA application developer will simulate the design at multiple
stages throughout the design process.
7. Initially the RTL description in VHDL or verilog is simulated by creating test benches to simulate
the system and observe results.
8. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a
gate level description where simulation is repeated to confirm the synthesis proceeded without
errors.
9. Finally the design is laid out in the FPGA at which point propagation delays can be added and the
simulation run again with these values back-annotated onto the netlist.
10. Place & Route, the process of optimization of logic cells for effective utilization of FPGA area
and the speed of operation, is used to modify and infer the following:
1. Re-assignment of Pins
2. Re-location of slices
3. Run time minimization
PROCEDURE:

1. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project
navigator
2. File New Project
3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports
click next and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax process window synthesize double click check
syntax and remove errors, if present , with proper syntax & coding.
9. synthesis your design, from the source window select,Synthesis/Implementation from
the window Now double click the synthesis XST
10. Afterr Synthesis you assign the Pin Value for your design so, double click the
Assign Package Pins
11. Enter the Pin value for your input and output signals. If you want see your Pin
assignment in FPGA zoom in Architecture View or Package View
12. You see the Pins in FPGA. Save file as XST Default click ok and close the window

13. Design Implementation begins with the mapping or fitting of a logical design file to a
specific device and is complete when the physical design is successfully routed and a
bit stream is generated. Double Click Implementation Design.
14. After implementation you see Design Summary, you get the all details about your
design. If you want edit the place and route double click View/Edit placed design
15. You see where your IOs are placed in FPGA. And zoom to view how Pins are plaved
in FPGA. You can see where your pins are placed.
16. Just double click View/Edit Routed Design to view interconnection wires and blocks
17. Click the pin to see where its placed in FPGA. And Zoom particular area to see Place
and Routing.
18. If you want to change the place of the design, click and trace to another slice. See!!!
You changed place and route of the design.

PROGRAM:
Adder
module addsub(a, b, oper, res);

input
oper;
input [7:0] a;
input [7:0] b;
output [7:0] res;
reg [7:0] res;
always @(a or b or oper)
begin
if (oper == 1b0)
res = a + b;
else
res = a - b;
end
endmodule
Multiplier
module fg(a, b, res);
input [3:0] a;
input [3:0] b;

output [7:0] res;

reg [7:0] res;
always @(a or b )
begin
res=a * b;
end
endmodule

Placed Design

Routed Design

Result

IMPLEMENTATION OF COUNTER AND ADDER

Expt No:3

Date:
AIM:
To Implement the Adder, Counter and Multiplier in verilog HDL using FPGA board.
APPARATUS REQUIRED:

PC with Windows XP.

XILINX,
Spartan 3 kit
RS 232

PROCEDURE:

1. Start the Xilinx ISE by using start program file Xilinx ISE (8.1i) Project navigator
2. File New Project
3. Enter the project name and location then click next
4. select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports click next
and finish
7. Writing the behavioral verilog code in verilog Editor
8. Run the Check syntax process window synthesize double click check syntax and
remove errors, if present , with proper syntax & coding.
9. synthesis your design, from the source window select,Synthesis/Implementation from the
window Now double click the synthesis XSt
10. Afterr Synthesis you assign the Pin Value for your design so, double click the Assign
Package Pins
11. Enter the Pin value for your input and output signals. If you want see your Pin assignment in
FPGA zoom in Architecture View or Package View
12. You see the Pins in FPGA. Save file as XST Default click ok and close the window
13. Double Click Implementation Design

14. Right click the Generate Programming fileselect properties and then select the start-up
optionschange the clock into JTAG clock, then click apply and ok.
15. Double click the Generate Programming file.
16. Double click Configure Deviceclick finish select the bit file and then click ok
17. Right click Xilinx Deviceclick Programok.
PROGRAM:COUNTER
module counter (clk, s, q);
input

clk, s;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk)
begin
if (s)
tmp <= 4b1111;
else
tmp <= tmp - 1b1;
end
assign q = tmp;
endmodule
PROGRAM: ADDER
module adder(a, b, sum, co);
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output
co;
wire [8:0] tmp;
assign tmp = a + b;
assign sum = tmp [7:0];
assign co = tmp [8];
endmodule

Multiplier

module fg(a, b, res);

input [3:0] a;
input [3:0] b;
output [7:0] res;
reg [7:0] res;
always @(a or b )
begin
res=a * b;
end
endmodule

RESULT:

STUDY EXPERIMENTS
CMOS INVERTER

OBJECTIVE
To design and simulate the Cmos inverter circuits using tanner EDA tool.
SOFTWARE USED
Tanner EDA Tools
(i)

S-Edit

(ii)

T-Edit

(iii)

W-Edit

DESCRIPTION
CMOS INVERTER
The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS)
device. When a low voltage (0 V) is applied at the input, the top transistor (P-type) is conducting
(switch closed) while the bottom transistor behaves like an open circuit. Therefore, the supply
voltage (5 V) appears at the output. Conversely, when a high voltage (5 V) is applied at the input,
the bottom transistor (N-type) is conducting (switch closed) while the top transistor behaves like
an open circuit. Hence, the output voltage is low (0 V).

PROCEDURE:

1. Open a schematic editor(S-Edit) from the Tanner EDA Tools.

2. Select the required components from the symbol browser and design given circuit using S-Edit.
3. Write the program in T-Edit and run the simulation to simulate the given program to view the
result.
4. Output waveform is viewed in the waveform viewer.

CIRCUIT DIAGRAM:
CMOS INVERTER

PROGRAM
MNMOS_1 Out In Vss 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_2 Vdd Vss DC 5
VVoltageSource_1 In Vss PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(In)
.PRINT TRAN V(Out)
OUTPUTWAVE

RESULT:
The design and simulation of CMOS inverter has been performed using Tanner EDA Tools.

DESIGN AND SIMULATION OF DIFFERENTIAL AMPLIFIER

Expt No:4
Date:
OBJECTIVE

To design and simulate the differential amplifier circuits using tanner EDA tool.
SOFTWARE USED
Tanner EDA Tools
(iv)

S-Edit

(v)

T-Edit

(vi)

W-Edit

THEORY:
Differential amplifier:

Differential Amplifier amplifies the current with very little voltage gain. It consists of two FETs
connected so that the FET sources are connected together. The common source is connected to a
large voltage source through a large resistor Re, forming the "long tail" of the name, the long tail
providing an approximate constant current source. The higher the resistance of the current source
Re, the lower Ac is, and the better the CMRR. In more sophisticated designs, a true (active)
constant current source may be substituted for the long tail. The output from a differential
amplifier is itself often differential.

CIRCUIT DIAGRAM:

DIFFERENTIAL AMPLIFIER:

PROCEDURE:

1.

Open a schematic editor(S-Edit) from the Tanner EDA Tools.

2.

Select the required components from the symbol browser and design given circuit
using

S-Edit.

3. Write the program in T-Edit and run the simulation to simulate the given program to view
the result.
4. Output waveform is viewed in the waveform viewer.

PROGRAM:
DIFFERENTIAL AMPLIFIER

.model pmos pmos

.model nmos nmos
.tran 1m 2m
.print in1 in2 out1 out2

WAVEFORM:

DIFFERENTIAL AMPLIFIER:

RESULT:
The design and simulation of Differential Amplifier has been performed using Tanner EDA Tools.

LAYOUT DESIGN FOR N-WELL CMOS INVERTER

Expt No:5
Date:
OBJECTIVE
To draw the layout of an n well CMOS inverter using L-Edit of Tanner EDA tools.

SOFTWARE USED
Tanner EDA Tools

L-Edit

DESCRIPTION
CMOS INVERTER
The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS)
device. When a low voltage (0 V) is applied at the input, the top transistor (P-type) is conducting
(switch closed) while the bottom transistor behaves like an open circuit. Therefore, the supply
voltage (5 V) appears at the output. Conversely, when a high voltage (5 V) is applied at the input,
the bottom transistor (N-type) is conducting (switch closed) while the top transistor behaves like
an open circuit. Hence, the output voltage is low (0 V).

PROCEDURE

1. Open layout Editor (L-Edit) from Tanner EDA tools.

2. Select a New file and enter the File type and enter the cell name in the new cell section.
3. Making use of the pallets in L-edit draw the required layers for the Layout.
4. Each Layer should be based on the Lambda rules.
5. Check for DRC for any error at each level of Layer.

LAYOUT DIAGRAM

STICK DIAGRAM

RESULT:
DESIGN AND IMPLEMENT REDUCING POWER CONSUMPTION

Expt No: 6
Date:
AIM:
To design and implement reducing power consumption in 6T SRAM cell memories using
Tanner EDA Tool.
APPARATUS REQUIRED:
Tanner T-spice v13.0
PROCEDURE FOR TANNER TOOLS:
STEP1: open s-edit window
STEP2: go to file- > new- > new design
STEP3: go to cell- > new view
STEP4: add libraries file to the new cell
STEP5: instance the devices by using appropriate library files
STEP6: save the design & setup the simulation
STEP7: run design &observe waveforms
STEP8: observe the input & output waveform by given appropriate inputs.
THEORY:
MEMORIES:
A memory, a data byte, or a word, or a double word, or a quad word may be accessed
from or at all addressable locations with a similar process would be used to access from all
locations and there is would be equal access time for a read or for a write that is independent of a
memory address location.
SRAM:
Static random-access memory (SRAM) is a type of semiconductor memory that uses bi-stable
latching circuitry to store each bit. SRAM exhibits data permanence, but it is still volatile in the
conventional sense that data is eventually lost when the memory is not powered.
The power consumption of SRAM varies widely depending on how frequently it is
accessed. Static RAM used at a somewhat slower pace, such as in applications with moderately
clocked microprocessors, draws very little power and can have nearly negligible power

consumption when sitting idle -in the region of a few micro-watts. While DRAM supports access
times of about 60 nanoseconds, SRAM can give access times as low as 10 nanoseconds.
A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored on four
transistors (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has two
stable states which are used to denote 0 and 1. Two additional access transistors serve to control
the access to a storage cell during read and write operations. In addition to such six-transistor
(6T) SRAM, other kinds of SRAM chips use 4T, 8T, 10T, or more transistors per bit Fourtransistor SRAM is quite common in stand-alone SRAM devices, implemented in special
processes with an extra layer of polysilicon, allowing for very high-resistance pull-up resistors.
The principal drawback of using 4T SRAM is increased static power due to the constant current
flow through one of the pull-down transistors.
Access to the cell is enabled by the word line (WL in figure) which controls the two access
transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit
lines: BL and BL. They are used to transfer data for both read and write operations. Although it is
not strictly necessary to have two bit lines, both the signal and its inverse are typically provided
in order to improve noise margins.
During read accesses, the bit lines are actively driven high and low by the inverters in the
SRAM cell. The size of an SRAM with m address lines and n data lines is 2m words, or 2m n
bits.
DESIGN SPECIFICATION:
L=1.8um, W=2L
WRITE OPERATION:
Pull-up ratio=W4/W6=W5/W3=13
W4=W5=3.6, W6=W3=10.8
READ OPERATION:
Cell Ratio=W1/W5=W2/W6=2.5
W1=0.9, W2=2.7, W3=1.08,W4=0.36,W5=0.36, W6=1.08

CIRCUIT DESCRIPTION:

SRAM ARCHITECTURE:

CIRCUIT DIAGRAM:

WAVEFORM:
For Write:

ANALYSIS:
Power Results:
For Write:
Power Estimated = 2.375677e-003 at time 5.26611e-009
For Read:
Power Estimated=3.036401e-003 at time 5.47523e-009

RESULT: