Beruflich Dokumente
Kultur Dokumente
(EEE3544)
Fall semester, 2013
Objectives of lecture
For junior or senior students,
A. Introduce digital system concept and design flow
B. Learn hardware description language(HDL) Verilog
C. Learn high-level & structurallevel design methods
of digital system using Verilog language
(including logic synthesis method)
D. Learn system implementation techniques
E. Understand design verification and testing methods
F. Perform a team project to implement an example of digital
system on FPGA kit
Reference Books
Lecture notes:
(website://it_soc.yonsei.ac.kr)
2013 2
Digital System Design
Reference Book
Verilog HDL (2nd Edition), Samir palnitkar, PRENTICE HALL
Yonsei University
Contents (Syllabus)
* Review of digital logic (Self-study)
1. Overview of digital system design
2. System-level design
3. Basics of Verilog HDL
4. Verilog behavioral-level design
5. Verilog data flow-level design
6. Verilog gate-level modeling
7. Functions, tasks, & UDPs
8. Useful modeling techniques
9. Advanced Verilog topics
10. Logic synthesis
11. Implementation techniques
12. Verification techniques
* Lab hours
Yonsei University
Yonsei University
Contact information
Prof. Jaeseok Kim ()
- jaekim@yonsei.ac.kr
- Office: 2 621 (Tel: 2123-4018)
- Office hours : Mon. 1pm ~ 2pm
Wed. 3pm ~ 5pm
Teaching Assistants:
- (2123-3880, B703)
- (2123-3880, B703)
Yonsei University