• Block diagram
• Role of Power Electronics
• Reasons for growth
• Transistor as a switch
• High Efficiency
• HighFrequency Transformer
• Semicontrolled device
• Latches ON by a gatecurrent pulse if forward biased
• Turnsoff if current tries to reverse
Copyright © 2003 Chapter 2 Power Semiconductor 24
by John Wiley & Sons, Inc. Switches: An Overview
Thyristor in a Simple Circuit
• Symbols
• Polarity of Voltages; Direction of Currents
• MKS SI units
• Ampseconds
over T equal zero.
• Definition of permeability
φ1 + φ2 + φ3 = 0
Copyright © 2003 Chapter 3 Basic Electrical and 315
by John Wiley & Sons, Inc. Magnetic Circuit Concepts
Concept of Magnetic
Reluctance
• Schematic approach
is far superior
• Simulation results
• Simulation results
• Resistive load
• Current begins to flow when the input voltage exceeds the dc backemf
• Current continues to flows for a while even after the input voltage has
gone below the dc backemf
Copyright © 2003 Chapter 5 LineFrequency Diode 55
by John Wiley & Sons, Inc. Rectifiers
SinglePhase Diode Rectifier Bridge
• Commonly used
• Output current is
assumed to be dc
• output
current is
assumed to be
purely dc
• PSpicebased analysis
• Twoquadrant conversion
• ICs available
• PSpicebased simulation
• PSpicebased simulation
• Waveforms at startup
• Realistic load
Copyright © 2003 Chapter 6 Thyristor Converters 630
by John Wiley & Sons, Inc.
Thyristor Converter Waveforms
• Constant dc current
• Guidelines
• Role of PWM
Copyright © 2003 Chapter 7 DCDC SwitchMode 74
by John Wiley & Sons, Inc. Converters
StepDown DCDC Converter
• Pulsating input to
the lowpass filter
• The capacitor
voltage is assumed
constant
• Harmonic
components around
the switching
frequency are absent
• Results in
nonlinearity
Optimum mode
NonOptimum
mode
Classifications
• A practical circuit
• Serious limitations
• Waveforms
• Commonly used
• Example
considered earlier
• An example
• Commonly used
• SeparatelyExcited field
Copyright © 2003 Chapter 13 DC Motor Drives 136
by John Wiley & Sons, Inc.
Controlling Torque, Speed and Position
• Nonlinearity is introduced
Copyright © 2003 Chapter 13 DC Motor Drives 1314
by John Wiley & Sons, Inc.
Converters for Limited Operational
Capabilities
• Highly inefficient in
most cases
• Optimum operation
• Lowfrequency ac output is
synthesized
• Three options
• Idealized waveforms
Copyright © 2003 Chapter 17 Electric 174
by John Wiley & Sons, Inc. Utility Applications
HVDC Transmission: Converters
• Bock diagram
• Various Standards
• Filter arrangement
= q n A d x = q n A vdt
• Current density J = (dQ/dt)A1 Electrons moving
Current with velocity v
=qnv Density
= J

• Si atoms have
thermal vibrations ionized
about equilibrium silicon
atom
+
point.
• Small percentage of
Si atoms have large +
enough vibrational
energy to break 
covalent bond and free
electron
liberate an electron.
covalent bond
neutral silicon atom
• T3 > T2 > T1 
A
t = T1
• Density of free electrons
= n : Density of free
holes = p
• p = n = ni(T) = intrinsic generation of B
B
carrier density.
 +
• ni2(T) = C exp(qEg/(kT )) A
= 1020 cm6 at 300 °K t = T
2
• T = temp in °K
• k = 1.4x1023 joules/ °K recombination of B apparent
movement
• Eg = energy gap = 1.1 eV

of "Hole"
in silicon
A
•q= 1.6x1019 coulombs t = T
3
• Ptype silicon with Na >> ni: • Ntype silicon with Nd >> ni:
po ≈ Na , no ≈ ni2/ Na no ≈ Nd , po ≈ ni2/ Nd
extra valance
empty
 electron

bond
A D
+

 +
x x
+ V 
• Jdiff = Jn + Jp = q Dndn/dx  q Dp dp/dx
• Jdrift = q µn n E + q p µp E
• Dn/mn = Dp/mp = kT/q ; Einstein relation
• µn = 1500 cm2/Vsec
for silicon at
room temp. and Nd < 1015 cm3 • D = diffusion constant, m = carrier mobility
• µp = 500 cm2/Vsec for silicon at
room temp. and Na < 1015 cm3 • Total current density J = Jdrift + Jdiff
metallurgical junction
P N
N N ND
ND A
A
N N
A A
x x
 N
D  N
D
metallurgical
junction x
• Diffusing electrons and holes ionized ionized
leave the region near acceptors donors
metallurgical junction depleted
of free carriers (depletion P + N
region). + +
Electric
field
 opposing
Diffusing
form space charge layer.
electrons + +
Diffusing
holes
+

• Electric field due to space + +
charge opposes diffusion.
space charge
layer width = W
d 2F r x
=  e x p xn
dx 2
r =  qNa ; x < 0 qN a
w
r = qNd ; x > 0
E
dF
=  E(x ) x
dx
qNa(x +x p )
E(x ) = e ;  xp <x <0
qNd (x  x n) E max
E(x ) = e ; 0< x < x n
xn
F
Fc =  ÛE(x )dx
ı
x
 xp
Fc
qNax p 2!+!qNd x n2
Fc =  depletion layer
2e
dF dn
• In thermal equilibrium Jn = q µn n dx + q Dn dx = 0
n(xn)
F(xn)
Dn Ûdn
• Separate variables and integrate ; Û
ıdF =  Ù
µn ı n
F(xp) n(xp)
kT ÈNaNd˘
• F(xn)  F(xp) = Fc = q lnÍ 2 ˙ ; Fc = contact potential
Î ni ˚
• Example
• W(V) = Wo 1+V/Fc x
F
c
2eFc(Na+Nd) Fc + V
• Wo =
qNaNd
x (V)
n
2Fc
 x p(V)
• Emax = 1!+!V/Fc
Wo
np o
p • Minority carrier
no
x diffusion lengths.
!!∞ È ni 2 ˘˙
• Ln = [Dntn]0.5
!!∞ È
Í ni 2 ˘
˙ Í
Qn = Ú!np (x)dx = q Í np (0)!! !˙ Qp = !pn(x)dx = q Í p n(0)!!
Ú !
ÈÎ Na ˚ Î Nd ˙ ˚ • Lp = [Dptp]0.5
0
È 0
Qn Qp È Ln Lp ˘ È qV ˘
2
J = t + t = q ni Í + Í ˙
n p N t N t
˙ Í exp( kT )!!1˙
Î an d p˚ Î ˚
È qV ˘ È Ln Lp ˘
J = Js Í ˙ 2
Í exp( kT )!!1˙ ; Js = q ni Í + ˙
Î ˚ ÎNatn Ndtp˚
J i
J
v
 Js
v
reverse combined
forward bias bias characteristic v
Wo • Js independent of reverse
W(V) voltage V because carrier
density gradient unaffected by
applied voltage.
np o
p
no
+ • Js extremely temperature
n p (x) p (x) sensitivity because of
n
dependence on ni2(T.)
x
Electric field, J
s
Copyright © by John Wiley & Sons 2003 Semiconductor Physics  16
Impact Ionization

• E ≥ EBD ; free electron can
acquire sufficient from the field Si
between lattice collisions (tc ≈  
1012 sec) to break covalent bond.
 Si
• Energy = 0.5mv2 = q Eg ; v = q EBDtc


• Solving for EBD gives Si
2! Eg! m
EBD = Electric field E 
q! tc2
• Numerical evaluation
OUTLINE
19 3
N+ substrate N = 10 cm 250
D
microns
Cathode
anode i
1
i
R on
B VBD
v v
ª 1 V v
cathode
Fc
• W(V) = Wo 1+V/Fc
Fc + V
2eFc(Na+Nd )
• Wo =
qNaNd 4!Fc
• (Emax )2 = (EBD)2 = BV BD
Wo 2
2Fc
• Emax = 1!+!V/Fc
Wo
• Sol ve for W(BV BD) and BV BD
• Power di ode at r ev er se br eak down:
Na >> Nd ; E = EBD ; V = BV BD >> Fc to obtai n (put i n Si val ues)
e!EBD2 1.3x 1017
Wo 2!BV BD 2eFc
BV BD = = ; [V]
• W2(BV BD) = ; Wo
2= 2!q!Nd Nd
Fc q!Nd
2!BV BD
W(BV BD) = = 10 5 BV BD ; [µ m]
EBD
• Concl usi ons
1. Lar ge BV BD (103 V) r equi r es Nd < 1015 cm  3
 V + • V1 + V2 = BVBD
P+ N N
+ • E1 + E2 = EBD
W qNdWd2
d
Electric
• BVBD = EBD Wd 
2e
E1 + E 2 field
V
1 e(EBD)2
E2 • If Nd << (required
V2 2q(BVBD)
x value of Nd for nonpunchthru
diode), then
qNdWd qNdWd2
• E1 = ; V1 = • BVBD ≈ EBD Wd and
e 2e
• Wd(Punchthru)
• V2 = E2 Wd ≈ 0.5 Wd(nonpunchthru)
N+ N+
SiO
2
N
N
P+ P+
bonding pad bonding pad
high field
region
QF q!A!Wd!na
• IF = = ; Current needed
t t
to maintain stored charge QF.
W
d
q![µn!+!µp]!na!A!Vd x
• IF = ;
Wd
Ohm’s Law (J = sE)
+ + 
P N  N+
IF
Wd2
• Vd = ; Equate above + V  + V 
![µn!+!µp]!t j d
Crosssectional
two equations and solve for Vd
area = A
µo
• µn + µp = ; nb ≈ 1017 cm3 . i
na
1!+!
nb
• Mobility reduction due to increased 1
carriercarrier scattering at large na. R on
v
q!na!A!Vd µo ª 1 V
• IF = ; Ohms Law
Wd na
1!+! If!Wd
nb
• Vd =
with densitydependent mobility. q!µo!nb!A
• Vd = IF Ron
• Invert Ohm’s Law equation to find Vd as
function IF assuming na >> nb.
• V = Vj + Vd
Copyright © by John Wiley & Sons 2003 Diodes  10
Diode Switching Waveforms in Power Circuits
Q rr = I t /2
rr rr
di /d t d i /d t
F I F R 0. 25 I rr
I
rr
t t t
3 4 5 diF diR
• dt and dt determined
V on t
V
FP
rr by external circuit.
t • Inductances or power
t V
V
R semiconductor devices.
2 rr
t
t 5
1 S =
t
4
t interval
2
 +
P+  + N N+
i (t)  +
F
Vj ≈ 1.0 V
time
• Injection of excess
time carriers into drift
time
region greatly
reduces Rd.
x
Rd
car r i er s ar e r emoved vi a
C sc L r ecombi nati on and car r i er
sweep out (negati ve cur r ent).
time
time time di R
• Vr = I r r R d + L
dt
t s i nt e r v a l
• I nsuffi ci ent ex cess car r i er s r emai n to suppor t I r r , so
aluminum
cathode
contact 
ohmic
Copyright © by John Wiley & Sons 2003 Diodes  16
Physics of Schottky Diode Operation
E
• Contact potential and rectifying Si
junction completely masked by Accumulation layer
i(t)
enhanced conductivity. Socalled PSi or

Al
ohmic contact.  N+Si
+ i
diode
• Cd  diffusion capacitance. Caused by excess
+
carriers. Based on quasistatic description of
v i (v ) stored charge in drift region of diode.
Cj j C
v d dc j
diode 
• Current source idc(vj) models the exponential
Rs IV characteristic.

• Rs accounts for parasitic ohmic losses at high
v = vj + R i
diode s diode currents.
+ 
• One dimensional diagram of a
P N N+
power diode.
n(x,t) n(x,t)
time
• Quasistatic view of decay of
time
excess carrier distribution
time
during diode turnoff.
n(x,t) = n(x=0,t) f(x)
x
0 Wd • Redistribution of excess
carriers via diffusion ignored.
time Equ;ivalent to carriers moving
with inifinte velocity.
time time
I o
+
D
f • Test circuit example  stepdown converter.
V 50 A
d
Diode
Voltage
0V
100V
200V
500V
0s 100ns 200ns 300ns 400ns 500ns
time
Diode
Current
100A
50A
0A
50A
100A
• Diode current transient.
0s 100ns 200ns 300ns 400ns 500ns
time
N  region
• More accurately model distributed nature p(x) = n(x)
of excess carrier distribution by dividing
it into several regions, each described by + N+
P Q3 Q
a quasistatic function. Termed the Q1 Q 4 region
region 2
lumpedcharge approach.
x
d d
1
i
diode • Circuit diagram of improved diode model. Circuit written in
+
D
terms of physical equations of the lumpedcharge model.
v Gd
CJ j
 Vsense1
5 6 7 8
+ 
2
Rs + + +
Ee Re Em Rm Edm Cdm
3    Rdm
+
Emo
 0
4
+
Vsense2  • Detailed equations of model given in subcircuit listing.
9
• Many other even better (but more complicated models available in
technical literature..
Copyright © by John Wiley & Sons 2003 Diodes  25
Details of LumpedCharge Model
Subcircuit Listing
.Subckt DMODIFY 1 9 Params: Is1=1e6, Ise=1e40, Tau=100ns, • Symbolize subcircuit listing into
+Tm=100ns,Rmo=Rs=.001, Vta=.0259, CAP=100p, Gde=.5,
+ Fbcoeff=.5, Phi=1, Irbk=1e20,Vrbk=1e20
SCHEMATICS using SYMBOL
*Node 1= anodeand Node 9 = cathode WIZARD
Dcj 1 2 Dcap ; Included for space charge capacitance and reverse
*breakdown. • Pass numerical values of
.model Dcap D (Is=1e25 Rs=0 TT=0 Cjo={CAP} M={Gde} parameters Tau, Tm, Rmo,Rs, etc.
+FC={Fbcoeff} Vj={Phi} +IBV={Irbk} BV=Vrbk}) by entering values in PART
Gd 1 2 Value={(v(5)v(6))/Tm +Ise*(exp(v(1,2)/Vta)1)}
*Following components model forward and reverse recovery. ATTRIBUTE window (called up
Ee 5 0 VALUE = {Is1*Tau*(exp(V(1,2)/(2*Vta))1)}; Ee=Qe within SCHEMATICS).
Re 5 0 1e6
Em 6 0 VALUE = {(V(5)/Tmi(Vsense1))*Tm*Tau/(Tm+Tau)} • See reference shown below for
*Em=Qm more details and parameter
Rm 6 0 1e6
extraction procedures.
Edm 7 0 VALUE = {v(6)};Edm=Qm
Vsense1 7 8 dc 0 ; i(vsense1)=dQm/dt • Peter O. Lauritzen and Cliff L. Ma,
Cdm 8 0 1
Rdm 8 0 1e9 "A Simple Diode Model with
Rs 2 3 4e3 Forward and Reverse Recovery",
Emo 3 4 VALUE={2*Vta*Rmo*Tm*i(Vsense2) IEEE Trans. on Power Electronics,
+/(v(6)*Rmo+Vta*Tm)}; Vm
Vsense2 4 9 dc 0
Vol. 8, No. 4, pp. 342346, (Oct.,
.ends 1993)
Copyright © by John Wiley & Sons 2003 Diodes  26
Simulation Results Using LumpedCharge Diode Model
100V
 100 V
Sw
200V
Outline
• BJT structure and IV characteristics
• Physical operation of power BJTs
• Switching characteristics
• Breakdown voltage
• Second breakdown
• Onstate voltage
• Safe operating areas
S i O2
N+ N+ N+ N+
P

N
N+
collector
Features to Note
• Multiple narrow emitters  minimize emitter current crowding.
• Multiple parallel base conductors  minimize parasitic resistance in series with the base.
+ 19 3
10 m N 10 cm base NPN
BJT
16 3 emitter
5 20 P 10 cm
m
50200 m
N
 10
14
cm
3 collector
(collector drift
region)
19 PNP
N+
3 base
250 m 10 cm BJT
collector emitter
Features to Note
• Wide base width  low (<10) beta.
• Lightly doped collector drift region  large breakdown voltage.
Copyright © by John Wiley & Sons 2003 BJTs  3
Darlingtonconnected BJTs
C B E
i E,D
I
C
N+ N+
i
B,D i
I B, M
P
B
B D
N S i O2
M
D1
I + i i
C N
b = = b Db M+ b D+ b M C,D C, M
IB
quasisaturation
hard
saturation 1 / R
d second breakdown
Features to Note
I B5 > I etc
i B4
C
I
B5 • 2nd breakdown  must be
avoided.
I
B4
I
B2
• BVCBO > BVCEO  extended
blocking voltage range.
I
B1
I < 0
B
I = 0
B
BV
CEO v
BV BV
CEO(sus)
CBO
Copyright © by John Wiley & Sons 2003 BJTs  5
BJT Internal Current Components
EB depletion
B CB depletion
layer
I layer
B • Ine and Ipe flow via diffusion. Inc
and Ipc flow via drift.
I pE + I + I
I pC C C
E N
E
N+ P
• Ine >> Ipe because of heavy emitter
 I  I nC
nE doping.
• Short base width conflicts with need for larger base width needed in HV
BJTs to accomodate CB depletion region.
• Long base lifetime conflicts with need for short lifetime for faster
switching speeds
log ( I )
C
I I
C,max C,max
10
• Beta decrease at large collector current due to high level injection effects
(conductivity modulation where dn = dp) in base.
• When dn = dp, base current must increase faster than collector current to provide
extra holes. This constitutes a reduction in beta.
+
N
current crowding
current crowding
C
• IB proportional to exp{qVBE/(kT)}
• Later voltage drops make VBE larger at edge of emitters.
• Base/emitter current and thus carrier densities larger at edge of emitters. Socalled emitter
current crowding.
• This emitter current crowding leads to high level injection at relatively modest values of
current.
• Reduce effect of current crowding by breaking emitters into many narrow regions connected
electrically in parallel.
+ V
BC 
VBC < 0
Hard saturation
VBC > 0 and drift region
filled with excess carriers.
virtual base
• Beta decreases in quasisaturation because effective base width (virtual base) width has increased.
D Model of an
F I o inductivelyloaded
switching circuit
R
B
+ Q
v
i

• Current source Io models an inductive load with an L/R time constant >> than switching period.
• Positive base current turns BJT on (hard saturation). Socalled forward bias operation.
• Negative base current/baseemitter voltage turns BJT off. Socalled reverse bais operation.
• Free wheeling diode DF prevents large inductive overvoltage from developing across BJT
collectoremitter terminals.
I
B,on
i (t) t
B
t d,on
V
BE,on
v (t) t
BE
V
BE,off
t ri
Io
i (t)
C
t fv1
t
fv2
V V
dc CE,sat
v (t)
CE
carrier
density time
versus
position
time
x
+
N P N N+
emitter base collector collector
drift region contact
• Growth of excess carrier distributions begins after td(on) when BE junction becomes forward biased.
• Entrance into quasisaturation discernable from voltage or current waveform at start of time tvf2.
• Collector current “tailing” due to reduced beta in quasisaturation as BJT turns off.
• Hard saturation entered as excess carrier distribution has swept across dirft region.
V
BE,on
V
BE,off
ts
tfi
I
o
i (t)
C
trv
1
V
CE,sat
V
dc
v (t)
CE tr v
2
• Base current must make a controlled transition (controlled value of diB/dt) from
positive to negative values in order to minimize turnoff times and switching losses.
Q1 Q3
time
+ +
N P N N
emitter base collector collector
drift region contact
i (t) t
B
VBE,on
t s
v (t)
BE VBE,off
t collector current
fi1 "tailing"
t fi2
Io
i (t)
C
t rv1
VCE,sat
V
dc
v (t)
CE
t
rv2
time
time
x
+
N P N N+
emitter base collector collector
drift region contact
• Uncontrolled base current removes stored charge in base faster than in collector drift region.
• Baseemitter junction reverse biased before collectorbase junction.
• Stored charge remaining in drift region now can be only removed by the negative base current
rather than the much larger collector current which was flowing before the BE junction was
reverse biased.
• Takes longer time to finish removal of drift region stored charge thus leading to collector current
“tailing” and excessive switching losses.
D
F
R
B
+ Q
D
v
i Q
 M
D
1
i (t)
B,D
t
be
i B , M (t)
I B,off
i (t) t
C,D
I o
i C , M (t) t
V
BE,on
vB E (t) t
V BE,off
Q & Q on Q off
D M D
V
CE,sat
Vd c
v (t) t
CE
• BE junction forward biased even when base current = 0 by reverse current from CB junction.
• Excess carriers injected into base from emitter and increase saturation current of CB junction.
• Extra carriers at CB junction increase likelyhood of impact ionization at lower voltages , thus
decreasing breakdown voltage.
• Typical base widths in high voltage (1000V) BJTs = 5 to 10 and BVCEO = 0.5 BVCBO .
B  V CB +
+ + C
+ 
E N+ P N N+
+ +
+
• Large electric field of depletion region will accelerate electrons from emitter across base and
into collector. Resulting large current flow will create excessive power dissipation.
• Avoidance of reachthru
• Wide base width so depletion layer width less than base width at CB junction breakdown.
• Heavier doping in base than in collector so that most of CB depletion layer is in drift region
and not in the base.
• 2nd breakdown during BJT turnoff in • Permanent damage to BJT or even device
stepdown converter circuit. failure if 2nd breakdown not terminated within
a few µsec.
+
N
P
• Emitter current crowding
during either turnon or turnoff
accenuates propensity of BJTs
N
to 2nd breakdown.
current crowding current crowding
C
current
C crowding
Electric field
E sat = 15 kV/cm
E
E max
B
E + N +
C
N P Jc N x
x
• Negative space density gives rise to nonuniform
electric field.
• Moderate current in drift region 
BJT active • Emax may exceed impact ionization threshold
while total voltage < BVCEO.
• Electric field E1 = Jc/(qµnNd) < Esat
+
N R
c
 V
BE,sat  V BC,sat
V
BE,sat
P
+ +
I   V BC,sat
C V
d
N
 + I
C
N+
Re
Forward bias safe operating area Reverse bias safe operating area
RBSOA
T j,max
4
10 sec
V
BE,off < 0
2nd 3 V =0
2nd 10 sec BE,off
breakdown
breakdown
dc BV v
BV CBO CE
BV log ( v )
CEO CE
Copyright © by John Wiley & Sons 2003 BJTs  27
Lecture Notes
Power MOSFETs
Outline
• Construction of power MOSFETs
• Physical operations of MOSFETs
• Power MOSFET switching Characteristics
• Factors limiting operating specfications of MOSFETs
• COOLMOS
• PSPICE and other simulation models for MOSFETs
contact to source
source
diffusion
conductor
field
oxide
gate
oxide
gate
width
N+ N+ N+ N+
P P
N
gate N+
conductor
N+ N+ N+ N+
P (body) P (body)
N parasitic i channel
(drift region) BJT
D length
integral
N+ diode
drain
boddysource short
Oxide
N+ N+
Gate
P Channel
P conductor
length • Trenchgate MOSFET
Parasitic BJT Integral
N ID
ID diode • Newest geometry. Lowest
N+ onstate resistance.
Drain
gate oxide
gate source
N+ N+ P
• Vgroove MOSFET.
P
• First practical power
N MOSFET.
i
N+
D • Higher onstate
resistance.
drain
VG S 3
linearized
V
GS2
VG S 1
v
V GS
v
V
GS
<V
GS(th) BV
DS GS(th)
DSS
D D
G
G
Nchannel Pchannel
MOSFET MOSFET
S S
+ +
N N
ionized P
depletion layer
acceptors
P boundary inversion layer
ionized with free electrons
N acceptors
electron
drift velocity
• Mobility also decreases because large
8 x 1 06
values of VGS increase free electron
cm/sec density.
• In MOSFET channel, J = q µn n E
• Mobilty decreases, especially via carrier
= q n v n ; velocity v n = µn E
carrier scattering leead to linear transfer
curve in power devices instead of square
• Velocity saturation means that the law transfer curve of logic level MOSFETs.
mobility µn inversely proportional to
electric field E.
Copyright © by John Wiley & Sons 2003
MOSFETs  7
ChanneltoSource Voltage Drop
P
• Smaller Vox corresponds to a smaller
N channel thickness. Hence reduction in
N+ channel thickness as drain is
approached from the source.
Io
r
D DS(on)
F
R
G
Cgd
+ G
V
GG
C
gs
S
• Buck converter using power MOSFET.
D
• MOSFET equivalent circuit valid for
onstate (triode) region operation.
C
gd
G I = f(V )
D GS
C
gs
• MOSFET equivalent circuit valid for off
S state (cutoff) and active region operation.
Copyright © by John Wiley & Sons 2003
MOSFETs  10
MOSFET Capacitances Determining Switching Speed
gate
source
C gs C
gd
C
N+ gd2
N+ P idealization
C
P gd
Cd s
N actual
C gd1
drainbody
N+ depletion layer
v
v = v 200 V DS
GS DS
drain
C gd C
bridge
G D
+V 
C gs Cd s b
S C gd
G D
C iss
S
C oss
S
C iss = C gs + C gd
C oss = C gd + C d s
Copyright © by John Wiley & Sons 2003
MOSFETs  12
Turnon Equivalent Circuits for MOSFET Buck Converter
Vi n Vi n
• Equi val ent ci r cui t • Equivalent cir cuit
dur i ng td(on). dur ing tr i .
D I o
F D I o
F
C
DC C
R C gd1 DC
G R C gd1
G
+
V i
G +
GG C V
gs i
GG G C
gs
Vi n
• Equi val ent ci r cui t • Equivalent cir cuit
V
dur i ng tfv1. in
dur ing tfv2.
I o I o r
DS(on)
R
G
R Cg d 1
G +
V i C
G gs
+ GG C gd2
V i
GG G
v (t)
GS
V
G S , Io
t = R (C + C )
G gd2 gs
V
GS(th)
i (t)
G
t
Charge on C
Charge on C + Cg d gd
gs
V in
t
fv2
• Freewheeling diode
assumed to be ideal.
v (t)
DS
i (t)
(no reverse recovery
D
current).
Io
t
t ri V t
d(on) t fv1 DS(on)
Q gate g (V  V )
Q Q m gs t
on p
Vgs V + I /gm
Q t D1
(Vt+ID1/gm) T1
V
Qon = ı![Cgs(Vgs)!+!Cgd(Vgs)]!Vgs!dVgs
Û t
t
Vgs,off Vgs,off V
gs,on
Vds,on I
d
Û ! I
Qp = ı!Cgd(Vds)!Vds dVds D1
t
Vd
V
Vgs,on ds
QT = Qon + Qp + ı![Cgs(Vgs)!+!Cgd(Vgs)]!Vgs!dVgs
Û V
V ds,on
(Vt+ID1/gm) d
t
Copyright © by John Wiley & Sons 2003
MOSFETs  15
Turnon Waveforms with Nonideal Freewheeling Diode
Vi n
Io i D (t)
F
Io + I rr
I rr t
C gd1
I rr R
G
i (t)
D +
t rr V i
Io
GG G Cgs
t t
ri
t
Copyright © by John Wiley & Sons 2003
MOSFETs  16
MOSFETbased Buck Converter Turnoff Waveforms
t 2= R (C
G gd2
+ C )
gs
v (t)
GS t1= R (C + C )
G gd1 gs • Assume ideal fr ee
V
GG V V
GS(th)
w heeling diode.
G S , Io
• Essentially the
t inver se of the tur n on
i (t)
G
pr ocess.
t
d(off)
v (t)
DS • Model quanitatively
i (t)
D using the same
I o
V
in equivalent cir cuits as
for tur n on. Simply
use cor r ect dr iving
t voltages and initial
t
rv2
t rv1 t fi conditions
Cg d
+ N+ G
N parasitic
BJT
P P
Cg d
N
+
N S
dVDS
drain
• Large positive Cgd
dt
could turn on parasitic BJT.
D
L+
• Turnon of T+ and reverse recovery of Df will
D
F+ dv DS
produce large positive Cgd in bridge circuit.
T+ I o dt
D
L • Parasitic BJT in T likely to have been in reverse
active mode when Df was carrying current. Thus
DF  stored charge already in base which will increase
T
dv DS
likeyhood of BJT turnon when positive Cgd is
dt
generated.
Copyright © by John Wiley & Sons 2003
MOSFETs  18
Maximum GateSource Voltage
• V GS(max) = maxi mum per mi ssi bl e gate
sour ce vol tage.
+ +
N N N
P P
+
N
drain region
resistance
+
N
drain
Rd
• MOSFETs can be easily
paralleled because of Q
1
positive temperature G
coefficient of rDS(on).
log ( i )
D
I
DM • No distinction betw een
5
FBSOA and RBSOA. SOA
10 sec
is squar e.
10  4 sec
Tj , m a x • FB = for w ar d bias.
10
3
sec
V GS ≥ 0.
• RB = r ever se bias.
DC
V GS ≤ 0.
BV
DSS
• No second br eakdow n.
log ( v )
DS
N+ N+ N+ N+
+ +
P P
• Conventional
vertically oriented
N
power MOSFET
N+
drain
source
gate
cond
uctor
• COOLMOS™ structure
N+ N+ N+ N+
P P (composite buffer structure,
b b
W superjunction MOSFET,
P N P super multiresurf
MOSFET)
b b b
• Vertical P and N regions of
width b doped at same
N+ density (Na = Nd)
drain
Copyright © by John Wiley & Sons 2003
MOSFETs  24
COOLMOS™ Operation in Blocking State
source
gate
cond • COOLMOS™ structure partially
uctor
depleted.
N+ N+ N+ N+
P P
b b • Arrows indicate direction of
depletion layer growth as device
N 
P
turns off.
V1
P
+ • Note ntype drift region and
N+
adjacent ptype stripes deplete
drain uniformly along entire vertical
length.
source
gate
cond
• COOLMOS™ structure at edge
uctor of full depletion with applied
N+ N+ N+ N+ voltage Vc. Depletion layer
P P
b b
N reaches to middle of vertical P
and N regions at b/2.
Ec Ec 
P P
Vc • Using step junction formalism,
+ Vc = (q b2 Nd)/(4 e) = b Ec,max/2
N+
• Keep Ec,max ≤ EBD/2. Thus
drain Nd ≤ ( e EBD)/(q b)
N+ N+ N+ N+
P P P
b N b
Ev Ev
Ev
P 
P
V
Ec Ec
+
N+
drain
V > Vc
• For applied voltages V > Vc, vertically oriented electric field Ev begins to grow in depletion region.
• Ev spatially uniform since space charge compensated for by Ec. Ev ≈ V/W for V >> Vc.
• Doping level Nd in ntype drift region can be much greater than in drift region of conventional
VDMOS drift region of similar BVBD capability.
source
gate
cond
uctor
• Onstate specific resistance ARon [Ωcm2]
N+ N+ Ro n N+ N+
P P much less than comparable VDMOS
b b because of higher drift region doping.
P P 
V1 • COOLMOS™ conduction losses much
N
less than comparable VDMOS.
+
N+
drain
ID R
L
• For more complete analysis see: Antonio G.M. Strollo and Ettore Napoli, “Optimal ONResistance
Versus Breakdown Voltage Tradeoff in Superjunction Power Device: A Novel Analytical Model”, IEEE
Trans. On Electron Devices,Vol. 48, No. 9, pp 21612167, (Sept., 2001)
t
• Effect on COOLMOS switching times
relative to VDMOS switching times.
v (t) V
DS V • Turnon delay time  shorter
DS(on)
d
• Current rise time  shorter
• Voltage fall time1  shorter
t
td ( o n ) t r i t fv1 t t rv1 tfi • Voltage fall time2  longer
fv2 t d(off)
• Turnoff delay time  longer
i (t) t rv2 • Voltage rise time1  longer
D Io
• Voltage rise time2  shorter
t • Current fall time  shorter
Copyright © by John Wiley & Sons 2003
MOSFETs  29
PSPICE Builtin MOSFET Model
Circuit components
Drain
RG RB
RDS Idrain • Cbs and Cbd = nonlinear voltage
Gate Bulk dependent capacitors (depletion layer
capacitances)
Cgs Cbs
N+ N+
C bg
• Bodysource short puts Cbd between drain and
source.
P
C bs C bd
• Variations in drainsource voltage relatively
Drainbody small, so changes in Cbd also relatively small.
Sourcebody B
depletion layer
depletion layer
Body
source source gate
short
Cg s
Cbg
N+
Cg d N+
Cbs P
P
Cb d N
N+
drain
drainbody depletion layer
• Draindrift region and large drainsource
voltage variations cause large variations in • MOSFET circuit simulation
drainbody depletion layer thickness models must take this variation
into account.
• Large changes in Cgd with changes in drainsource
voltage. 10 to 100:1 changes in Cgd measured in high
voltage MOSFETs.
0
0V
10V V 20V 30V
DS
60V
MTP3055E V
DS
• Comparison of transient response of drain
40V
source voltage using PSPICE model and
Motorola an improved subcircuit model. Both
SPICE
20V subcircuit model models used in same stepdown converter
model circuit.
0V
0s 100ns 200ns 300ns
Time
M2 M3
• JFET Q1 and Rd account for voltage drop
Dsub
V offset Q
1
in N drain drift region
+

Gate M1
• Dsub is builtin SPICE diode model used
LG R
G to account for parasitic antiparallel diode
in MOSFET structure.
RS
LS
• Reference  "An Accurate Model for
Power DMOSFETs Including Inter
Source electrode Capacitances", Robert Scott,
Gerhard A. Frantz, and Jennifer L.
• LG, RG, LS RS, LD, RD  parasitic Johnson, IEEE Trans. on Power
inductances and resistances Electronics, Vol. 6, No. 2, pp. 192198,
(April, 1991)
• M1= intrinsic SPICE level 2 MOSFET with no
parasitic resistances or capacitances.
Copyright © by John Wiley & Sons 2003
MOSFETs  35
Lecture Notes
Thyristors (SCRs)
OUTLINE
19
N+ 3 19
N+
3 1 0m • Crosssectional
10 cm 10 cm
J3 view showing
17
P 10 cm 3 30
100 m vertical
J 2
orientation of
13 14 50
N 10  5x10 cm 3 1000 SCR.
m
J1
17 • SCRs with
P 10 cm 3 30
50 µ kiloamp ratings
+ 19 3
P 10 cm
have diameters
Anode of 10 cm or
greater.
Gate and cathode metallization for
slow (phase control) thyristor. Gate and cathode metallization
for fast (inverter grade) SCR
cathode gate wafer
distributed
gate
cathode area
(metallization
wafer
not shown)
• At breakover a1 + a2 ≈ 1
K
Q2
• If VAK = VBO or if positive gate current pulse is applied
G
a1 + a2 becomes equal to unity and circuit connection becomes
K
unstable and SCR switches on.
Holes attracted
by negative
charge of injected
• Negative charge of electrons swept into n1
p electrons layer partially compensate positive charge
1 +
J1
n1 J 2 depletion of ionized donors exposed by growth of
+ +  width  no gate depletion of junction J2.
+  + + current
J
2   
  J 2 depletion • Growth of depletion reduces width of
+ p  bases of Qnpn and Qpnp and thus
2 width  with
J3 gate current
 increases a1 and a2.
n2 Electrons
injected in
response to • Holes attracted by first wave of injected
gate current elctrons attract additional electrons and so
flow on  regenerative action.
K
Negative gate • Conventional SCRs (phase control) have large
current G area cathodes  negative gate current cannot
remove stored charge from center of large
+
N N+ cathode area.
P
+   +
• SCR stays latched on in spite of negative gate
N current.
P
A
• External circuit must force anode current to
negative values in order that enough stored
charge be removed from SCR so that it can
turn off.
x
total
carrier
N NA
density D
2 1
1
NA
N
2 D1
x
T t t
C d(on)
v tr
C
Io tp s
control v (t)
AK
t
diR
t
dt 3
t2
iA (t)
I I t
R R
t1
4 Turnoff waveforms
dv
F
dt
v (t) V t
AK REV
N2 P2 N2
i (t)
G
N
1
P1
t
i
A A
• SCR first turns on at cathode periphery nearest gate. • Use shaped gate current pulse for
rapid turnon.
• Current constricted to small areas during initial phases of turn
on, td(on) and tr.
A
dv I
F < BO
dt C j2
max Rate effect
C j2 dv
100 V/ms < F < 2000 V/ms
G dt
max
K
Copyright © by John Wiley & Sons 2002 SCRs 11
Methods of Improving Thyristor di/dt Rating
distributed
gate
• Interdigitated gatecathode structure used to greatly
wafer
increase gatecathode periphery.
• If current thru Cj2 bypasses junction J3, then SCR will not be
turned on by the large displacement currents.
G
C j2 • Cathode shorts provide this desirable bypass. Most effective with
J
3 interdigitaated gatecathode geometry.
K dVFÔÔ
Cathode • dt ÔÔÔ significantly increased.
shorting max
structure cathode
short K G
N
+
N+ N+ N
+
N
P+
A
Copyright © by John Wiley & Sons 2002 SCRs 13
Thyristor Gate Trigger Requirements
V
G trigger maximum gate
K circuit load power
line dissipation Equivalent circuit of
minimum
V
G temperature
G SCR drive circuit
RG
maximum
V +
temperature G
G
I
I I V G
minimum G G G
trigger 1 2 R
GG
current
i (t)
G
OUTLINE
P
• GTO has no reverse blocking
N
capability because of anode
shorts P+ N+ P+ N+ P+
• Turn off GTO by pulling one or both of the BJTs out • Short lifetime causes higher onstate losses
of saturation and into active region.
• Anode shorts helps resolve lifetime delimma
• Force Q2 active by using negative base current IG ’ to 1. Reduce lifetime only moderately to keep
IC2 onstate losses reasonable
make IB2 <
b2 2. N+ anode regions provide a sink for
excess holes  reduces turnoff time
• IB2 = a1 IA  I'G ; IC2 = (1  a1 ) IA
• Make a2 ≈ unity by making p2 layer
(1!!a1)!IA ! (1!!a1)!(1!!a2)!IA ! relatively thin and doping in n2 region
• a1 IA  I'G < = heavily (same basic steps used in making
b2 a2
beta large in BJTs).
IA ! a2
• I'G < ; boff = = turnoff gain • Use highly interdigitated gatecathode
boff (1!!a1!!a2)
geometry to minimize cathode current
crowding and di/dt limitations.
Copyright © by John Wiley & Sons 2003 GTOs  3
Maximum Controllable Anode Current
K
G N+ G
Outline
• Construction and IV characteristics
• Physical operation
• Switching characteristics
• Limitations and safe operating area
• PSPICE simulation models
gate
oxide
gate
width
N+ N+ N+ N+
P
N
P
buffer layer
N+ (not essential)
P+ collector
metallization
gate
conductor
gate
emitter
SiO
2 + +
J N N
3 P
Ls
J
2
N
+
N
P+
boddysource short
Oxide
N+ N+
Gate
Channel
• Nonpunchthru IGBT
P conductor P
length
Parasitic
ID N ID
SCR
P+
Collector
Emitter
boddysource short
Oxide
N+ N+
Gate
Channel
P conductor P
length • Punchthru IGBT
Parasitic
I N ID
SCR D
N+
P+
Collector
drain collector
gate
gate
• Nchannel IGBT circuit symbols
source
emitter
• Blocking state operation  VGE < VGE(th) • With N+ buffer layer, junction J1 has
• Junction J2 is blocking junction  n+ drift small breakdownvoltage and thus IGBT
region holds depletion layer of blocking has little reverse blocking capability 
junction. antisymmetric IGBT
+ +
N N
+ + + + P+ + + + +
+ +
N N
collector
gate
I R gate
C channel
Principal
(desired) Body region
path of spreading
resistance
• Approximate equivalent circuit for collector
IGBT valid for normal operating current emitter
conditions.
• IGBT equivalent circuit showing
• VCE(on) = VJ1 + Vdrift + IC Rchannel transistors comprising the parasitic
thyristor.
Copyright © by John Wiley & Sons 2003 IGBTs  8
Static Latchup of IGBTs
lateral (spreading)
resistance gate
J emitter
3
+ +
N N
J2 N
+
N
J1
+ + + P+ + + + +
collector
Conduction paths causing lateral voltage drops and turnon
of parasitic thyristor if current in this path is too large
• Lateral voltage drops, if too large, will forward bias junction J3.
• Parasitic npn BJT will be turned on, thus completing turnon of parasitic thyristor.
• Large power dissipation in latchup will destroy IGBT unless terminated quickly.
External circuit must terminate latchup  no gate control in latchup.
+ +
N N
J2 P
lateral
(spreading) expansion of
resistance N depletion region
+
N
J1
+
P
collector
• MOSFET section turns off rapidly and depletion layer of junction J2 expands rapidly into
N layer, the base region of the pnp BJT.
• Expansion of depletion layer reduces base width of pnp BJT and its a increases.
• More injected holes survive traversal of drift region and become “collected” at junction J2.
• Increased pnp BJT collector current increases lateral voltage drop in pbase of npn BJT and
latchup soon occurs.
• Manufacturers usually specify maximum allowable drain current on basis of dynamic
latchup.
C gc C
bridge
G C
+V 
C ge C ce b
E C gc
Bridge balanced (Vb=0) Cbridge = C gc = C res
G C
G C
C ies
E
C oes
C ies = C g e + C gc E
C oes = C gc + C ce
v (t) V
GE GG+
• Turnon waveforms for
IGBT embedded in a t
stepdown converter.
• Maximum collectoremitter
i voltages set by breakdown
C
voltage of pnp transistor 
2500 v devices available.
5
10 sec
4
10 sec • Maximum collector current set
FBSOA
by latchup considerations  100
DC A devices can conduct 1000 A
v for 10 µsec and still turnoff
CE
dv via gate control.
i reapplied CE
C
dt
1000 V/ ms
• Maximum junction temp. = 150 C.
2000 V/ ms
Coxd
+ +
N N
Cgdj
P
Ccer Cdsj
Drainbody or N
+ Rb
basecollector N
Cebj + Cebd
depletion layer
P+
drain
• Nonlinear capacitors Cdsj and Ccer due to NP junction depletion layer. • Reference  "An
Experimentally Verified
• Nonlinear capacitor Cebj + Cebd due to P+N+ junction IGBT Model
Implemented in the
• MOSFET and PNP BJT are intrinsic (no parasitics) devices SABER Circuit
Simulator", Allen R.
• Nonlinear resistor Rb due to conductivity modulation of N drain drift region of Hefner, Jr. and Daniel
MOSFET portion. M. Diebolt, IEEE Trans.
on Power Electronics,
• Nonlinear capacitor Cgdj due to depletion region of drainbody junction (NP junction). Vol. 9, No. 5, pp. 532
542, (Sept., 1994)
• Circuit model assumes that latchup does not occur and parasitic thyristor does not turn.
Cebj +
Cgdj Cebd • Builtin model does not model
Ccer ultrafast IGBTs with buffer
Coxd Rb
layers (punchthrough IGBTs) or
Gate Cdsj reverse freewheeling diodes
Cm +
Coxs
Source
Copyright © by John Wiley & Sons 2003 IGBTs  16
PSpice IGBT  Simulation Vs Experiment
0V 5V 10 V 15 V 20 V 25 V
1
nF
Data from IXGH40N60 spec sheet
Simulated C versus V CE
GC
0.75
nF for IXGH40N60
V =0V
GE
0.5
nF
0.25
nF
0
100 V 200 V 300 V 400 V 500 V
Collector  emitter Voltage
Emerging Devices
Outline
+ + G
P P lc
Recessed gate
JFET  w channel
crosssection. N
l gd S
+
N
Pchannel JFET
drain
Output characteristics
VGS Transfer curve.
iD
VGS1 VGS2 VGS3 VGS4 v
D
S
blocking
gain µ
vD VGS
S
+
• Blocking capability limited by
P magnitude of electric field in drift
E
GS region. Longer drift regions have
larger blocking voltage capability.
V (x) N D
S CS
E • Normallyoff JFET created by
+ DS
V
GG
having narrow enough channel

N P+ width so that the channel is pinched
off at zero gatesource voltage.
G
+ +
VD D
VD D 
P+
N P+ P+
 P+
G G
S + 
S VGG
• Channel open between drain and source. • Channel pinchedoff (closed) between
drain and source.
G
S
 G
S +
V
GG
• Channel width and channel doping chosen
so that at zero gatesource voltage, • Forward bias gatechannel junction to
depletion layers of gatechannel junction reduce depletion region width and open up
pinchoff the channel. channel.
• Narrower channel than normallyon JFET. • Substantial current flow into gate.
• JFET VGS starts at negative values and steps to zero at turnon while MOSFET VGS starts
at zero and steps to positive value at turnon
• FET onstate losses somewhat higher than for MOSFET  technology related not fundamental
1. BSIT has no quasisaturation region and thus only one current fall time (no current tailing) at
turnoff.
3. Differences due to fact that BSIT has no inline pn junction that can block sweepout of
excess carriers as does BJT
cathode anode
gate
+ +
+ N + N
P P
gate
N
cathode
+
P
iA
V
GK
• FCT has a normallyon
V V V characteristic.
GK1 GK2 GK3
• Can be made to have a
FCT output characteristics
normallyoff
characteristic.
1. Reduce channel
width so that zerobias
V
RM
depletion layer width
V
AK of gatechannel
junction pinches off
V
AK
channel
2. Then termed a
blocking gain m Transfer curve bipolar static induction
thyristor (BSIThy).
V
GK
• FCT has much larger reapplied dv/dt rating than GTO because of lack of
latching action.
• Switching speeds of normallyon JFET somewhat slower than those of MOSFET  technology
limitation.
• BSIT switching times comparable to BJTs  in principle should be faster because of lack of in
line pn junction trapping stored charge at turnoff.
• JFETbased power devices much less widely used because of normallyon characteristic. This
has also slowed research and development efforts in these devices compared to other devices.
Copyright © by John Wiley & Sons 2003 Emerging Devices  12
PMCT (Ptype MOScontrolled Thyristor
SiO 2
A conductor
• Complete MCT composed of
tens of thousands of identical
cells connected in parallel.
G G
+ +
N N
P+ • Pdesignation refers to doping
P P of the lightlydoped P layer
ONFET which contains the depletion
ONFET channel layer of the blocking junction.
channel N
OFFFET
channels
P
• Note that ON and OFF FETs
are positioned at the anode end
+
N of the device.
anode
anode
i
A
+
gate
v
gate AK
OFFFET ONFET

cathode
cathode
anode
anode
ONFET
OFFFET gate
gate
cathode
cathode
• ONFET delivers base current to the lowgain BJT in the thyristor equivalent circuit
and activates that BJT.
• PNP transistor in the NMCT
• NPN transistor in the PMCT
• Lowgain transistor activates the higher gain transistor and thyristor latches on.
• Once higher gain transistor, which is in parallel with ONFET is activated, current
is shunted from ONFET to the BJT and the ONFET carries very little current in
the MCT onstate.
• Only 510% of the cells have an ONFET.
• Cells are closepacked. Within one excess carreier diffusion length of each other.
• Adjacent cells without an ONFET turned on via diffusion of excess carriers from
turnedon cell.
Copyright © by John Wiley & Sons 2003 Emerging Devices  17
Gatecontrolled Turnoff of MCTs
• Turn MCT off by turning on the OFFFET
• Negative gatecathode for the NMCT
• Positive gateanode voltage for the PMCT
• These gate voltage polarities automatically keep the ONFET in cutoff.
• OFFFET shunts base current away from the higher gain BJT in the thyristor
equivalent circuit and forces it to cutoff.
• NPN transistor in the NMCT.
• PNP transistor in the PMCT.
• Cutoff of higher gain BJT then forces lowgain BJT into cutoff.
• Thus maximum onstate current that can be turned off by means of gate control.
• OFFFET of the PMCT is an nchannel MOSFET which has three times larger
channel mobility than the pchannel OFFFET of the NMCT.
• Turning off the BJT with the larger PMCT crosssection showing
value of a most effective way to rationale for OFFFET placement
break the latching condition
a1 + a2 = 1 A
G
• BJT with the smaller base width has
the larger value of a.
N+ N+
• PMCT ; PNP BJT has smaller base
P+
width P P
• NMCT ; NPN BJT has smaller OFFFET OFFFET
base width
N
• OFFFET put in parallel with base
emitter of larger gain BJT so that P Wider of two base regions
OFFFET shorts out baseemitter
N+
when the FET is activated.
K
V
Tn
+ I
o
V
Tp t
V
d
t
t
fv1 d,off NMCT
Anodecathode
voltage t
fv2
t
rv1 
V
d
t
rv2
t  Io
Anode
current
I
o V
d
PMCT
+
t ri2 t
fi1 t
t
d,on
t ri1
Copyright © by John Wiley & Sons 2003 t
fi2
Emerging Devices  21
MCT Turnon Process
• Turnon delay time td,on  time required for gate voltage to reach ONFET threshold
starting from reversebias value of VGG,off
• Gatecathode voltage should reach final onstate value in times no longer than a
specified maximum value (typically 200 nsec). Insure that all paralleled cells turn on
at the same time to minimize current crowding problems.
• Keep gatecathode at onstate value for the duration of the onstate to minimize
likelyhood of inadvertant turnoff of some cells if current is substantially reduced
during onstate.
• Imax set by maximum controllable anode current. • MCT safe operating area. Very
Presently available devices have 50100 A ratings. conservatively estimated.
dvDS
• dt limited by mechanisms identical to those in
thyristors. Presently available devices rated at 500
1000 V/sec.
diD
• dt limited by potential current crowding problems.
Anodecathode voltage V
Presently available devices rated at 500 A/sec. BO
3. Discrete modules
• Multiple chips mounted on a common substrate. Separate chips for
drive, control, and power switch and possibly other functions.
• PIC rationale
• Lower costs
• Increased functionality
• Higher reliability
• Technical issues
• Economic issues
+
N N+ N
+
P
• Dielectrically isolated tubs 
P SiO2 isolation and silicon
N 
thin film overgrowth.
N+
Si wafer Si wafer
SiO
2
Si wafer with SiO 2
Si wafer with SiO 2
Wafers bonded together
A metallurgically C
• Wafer bonding and
subsequent wafer
Top Si wafer thinned
Si wafer thinning.
for circuit fabrication
Lateral Logic
Lateral HV MOSFET Level MOSFET
D G S D G S
+
• Selfisolation  only feasible
N N N
+
N
+
N
+
P P with MOSFET devices.
P  substrate
isolated regions
+ 
N + +
P N P N
• Junction isolation.
parasitic
P diode
SiO 2
+
N
N 
N
P+ • Fieldcrowding and
premature breakdown.
depletion
layer
P @ V
Polysilicon
field shield Metal at +V
SiO 2
+
N
N 
N  P
+ • Use of field shields to
minimize field crowding
depletion problems at HV/LV
layer
crossovers.
P  @ V
Lateral Logic
Vertical Power MOSFET Level MOSFET
G S Diode
S G S D
• Crosssectional
diagram of switch.
+ + + + + +
N N N N N N
P P P P

N
+
N
D
• Add additional components on vertical
• Circuit diagram MOSFET wafer as long as no major
process changes required.
Diode
• PN junction formed from N drift region
and Pbody region always reversebiased
if drain of power MOSFET positive
respect to source. Provides electrical
Power Lateral Logic
MOSFET Level MOSFET
isolation of the two MOSFETs.
E B E E B C E C B
+ + + + P P +
N N N N N
P + P +
P  P  Crosssectional view
 N epi N epi
N epi
+ +
N N
+
N Pepi
+
N
N+ N+ N+ P P N+ HVIC using
P+ P P+ P N
+
P
+
N  epi 
N epi N  epi junction isolation
N+ N+
Psubstrate
N+ N  P N
+ N+ N+ P
+
P
+
P+ P
N HVIC using self
isolation
P substrate
C1 Cn
Qn
10V  5A
GCT Gate
Control
Q1 Qn
20V  6 A
C1 C2 Cn
Turnoff
• Ratings
• Blocking voltage  4500V • Approximate gate drive circuit
• Controllable onstate current  4000A • Ion ≈ 500 A 10µsec
• Average fwd current  1200A
• Ioff  full forward current 10 usec
• Switching times  10µsec
• Very low series inductance  3 nH
Copyright © by John Wiley & Sons 2003 Emerging Devices  34
Emitter Turnoff Thyristor
Q1
C1 Cn
Qn
10V  5A
GTO or GCT
Control
Qn
Qn
Q1
Q1
Thyristors
5 kV
3 kV
MCT
s Io
IGBT
2 kV n
s
BJTs
1 kHz
1 kV 10 kHz
MOSFET
100 kHz
s
1 MHz
500 A 1000 A 1500 A 2000 A 3000 A
Frequency
• Largest bandgap
• Largest breakdown field strength
• Largest thermal conductivity
• Larger mobilities than silicon but less than GaAs
Copyright © by John Wiley & Sons 2003 Emerging Devices  38
Properties of Important Semiconductor Materials
Property Si GaAs 3CSiC 6HSiC Diamond
4"q"(BVBD)2
• Ron•A ≈
e"mn"(EBD)3
Ron(x)"A eSi"mSi ÈE ˘3
Í BD,Si˙
Ron(Si)"A = resistance ratio = ex"mx ÍE ˙
Î BD,x ˚
• Numerical comparison
Si 1
GaAs 6.4x102
SiC 9.6x103
Diamond 3.7x105
• Approximate design formulas for doping density and drift region length of HV pn
junctions
e"[EBD]2
• Nd = drift region doping level ≈ 2"q"BV
BD
2"BVBD
• Wd = drift region length ≈ E
BD
Material Nd Wd
Si 1.3x1014 cm3 67 µm
GaAs 5.7x1014 50
SiC 1.1x1016 10
Diamond 1.5x1017 2
q"Wd2 4"q"[BVBD]2
t ≈ k"T"m =
n k"T"mn"[EBD]2
• Numerical comparison
Material Lifetime
Si 1.2 µsec
GaAs 0.11 µsec
SiC 40 nsec
Diamond 7 nsec
• SiC
• Rapid advances in SiC device technology
• Spurred by the great potential improvement in SiC devices compared to
Si devices.
• Commercially available SiC power devices within 510 years.
• Diamond
• Research concentrated in improving materials technology.
• Growth of single crystal material
• Ancilliary materials issues  ohmic contacts, dopants, etc.
• No commercially available diamondbased power devices in the
forseeable future (next 1020 years).
Snubber Circuits
Outline
B. Diode Snubbers
C. Turnoff Snubbers
D. Overvoltage Snubbers
E. Turnon Snubbers
F. Thyristor Snubbers
di V
Df d
=
d t Ls
+ Ls Io
Rs
Io i Df (t) t
V Df Cs I rr
d
 Sw
v (t) t
Df Vd
• Ls = stray inductance
diLs
• Diode breakdown if Vd + Ls > BVBD
dt
Ls
• Simplified snubber 
the capacitive snubber
+ Rs
Ls
Vd Diode cathode
snapoff anode
 + +
Vd v Cs
Cs

i Df 
t
• Rs = 0
• Worst case assumption
diode snaps off instantaneously •v = v
Cs Df
at end of diode recovery
d2vCs vCs Vd
• Governing equation  + =
dt2 LsCs !LsCs
È I ˘2
1 Í rr ˙
• wo = ; Cbase = Ls Í ˙
LsCs ÎV d˚
Ï Cbase ¸
• Vcs,max =
Ì
Vd 1!+! 1!+! !
˝
Ó Cs ˛
V 3
Cs,max
Vd
2
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
C base
Cs
Ls i(t)
d2i di i
+  • Governing equation Ls + Rs + =0
Rs dt2 dt C s
V v (t)
d Df • Boundary conditions
Cs di(0+) Vd!!IrrRs
 + i(0+) = Irr and =
dt Ls
Vdf eat
Vd (t) =  1  h!cos(f)
sin(wat  f + z) ; Rs ≤ 2 Rb
Rs È ˘
1 Í (2x) h ˙
wa = wo 1!(a/!wo)2 ; a = 2!L ; wo = 1
; f = tan Í ˙
s LsCs Î 4!!hx2˚
Cs Rs Vd Ls![Irr]2
h = C ; x = R ; Rb = I ; Cb = 2 ; z = tan1(a/wa)
b b rr Vd
3
• At t = tm vDf(t) = Vmax
R s,opt
C s = Cbase = 1.3
tan1(wa/a)
R
f!!x base
• tm = wa + w ≥0
a 2
Vmax V max
• =1+ 1!+!h1!!x exp(atm)
Vd V
d
Cs Rs 1
• h = and x=
Cbase Rbase
R sI rr
Ls!Irr2 Vd V
d
• Cbase = and Rbase =
0
Vd2 Irr
0 1 Rs 2
R base
WR
2
L s I r r /2
2
0
0 V max
for R = R
0 Vd s s,opt
0
00
0 0
0 0
0 0 00
0 00 0 0 0 0 00
1 R s,op
R base
0
0 1 2 3
C s / Cbase
to t t t t t6
3 4 5
1
• L1 , L 2 , L 3 = stray inductances
to turnoff
• Overvoltage at turnoff
t1 due to stray inductance
turnon
• Overcurrent at turnon due to
diode reverse recovery
t
4 t3 vsw
Vd
Turnoff
D Io snubber
+ i f
DF
V
d Ds Stepdown converter with turnoff snubber
S Rs
 w i
Cs Cs
V 1. No stray inductance.
d
Io  i
sw
i sw 2. isw(t) = Io(1  t/tfi)
Cs
3. isw(t) uneffected by snubber circuit.
i i i
sw sw sw
Io
i i i
Df Df Df
tf i tf i t
fi
i
Cs
V
d
v
Cs
Cs < Cs 1 Cs = Cs 1 Cs > C
s
1
vs w
t rr
D Io Io
f
• Ds shorts out Rs
Rs i I rr
during Sw turnoff. D
f
V
d
• During Sw turnon, Vd
Sw Ds Io
Ds reversebiased and i sw Rs
Cs Cs discharges thru Rs.
I rr
discharge
• Turnon with Rs > 0
t rr
of C s
• Energy stored on Cs dissipated
• Turnon with Rs = 0
in Rs rather than in Sw.
vs w
• Energy stored on Cs dissipated
Io
• Voltage fall time kept quite
V in Sw.
d short.
W / Wbase WT = dissipation in
R
0.4
WT / W base
switch Sw
W
0.2
Iotfi
Cs1 =
0 2Vd
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Cs / Cs1
Wtotal = WR + WT
i
sw
Io
Wbase = 0.5 VdIotfi
Cs < Cs1 RBSOA
V vs w
d
Selection of Cs
• Minimize WR + WT
Vd
• Limit icap(0+) = R < Irr
s
Vd
• Usually designer specifies Irr < 0.2 Io so Rs = 0.2 Io
Ls
kV
+ d
D R i
f Io ov s
w
Vd
Io V
d
Sw Dov
 C ov v
s
w
o t
fi
• Stepdown converter with
overvoltage snubber comprised
of Dov, Cov, and Rov. • Switch Sw waveforms without overvoltage snubber
kVdtfi
• Ls =
Io
Copyright © by John Wiley & Sons 2003 Snubbers  15
Operation of Overvoltage Snubber
i π LsCov
Ls
• Dov on for 0 < t <
L 2
s
+
Dov R π LsCov
ov
• tfi <<
V 2
d
+ i
Ls • Equivalent circuit while
C v
 ov Cov inductor current decays to zero
 +
L
s + v Cov (0+) = Vd i Ls(0+) = I o
Vd v
C Cov
ov t
• Dov,Cov provide alternate path   i (t) = Io cos[ ]
for inductor current as Sw turns Ls ! Ls!Cov
off.
kVd!tfi
• Using Ls = in equation for Cov yields
!!Io
kVdtfiIo2 100k!tfi!Io
• Cov = =
!Io(0.1Vd)2 !!Vd
tfiIo
• Cov = 200 k Cs1 where Cs1 = which is used
!2Vd
in turnoff snubber
Stepdown converter
+ + with turnon snubber
D I D
f o f
R
Ls Ls
Io
Snubber • Snubber reduces Vsw at switch
D turnon due drop across
circuit Ls
R V inductor Ls.
V Ls Ls d
d D
D f • Will limit rateofrise of switch
Ls
current if Ls is sufficiently
Sw large.
 Sw 
i sw
Io
With Without
snubber snubber
v I rr
Small values of snubber inductance (Ls < Ls1) s
w
disw
• controlled by switch S w
dt V
and drive circuit. d Io
LsIo
• Dvsw =
tri i
s
t ri t rr
w
v I rr
Large values of snubber inductance (Ls > Ls1) s
disw Vd Io
reduced
w
• limited by circuit to <
dt Ls tri
V
d
Vdtri Io
• Ls1 =
Io
i
s
disw w
• Irr reduced when Ls > Ls1 because Irr proportional to Ls Io
dt t ≈ >
ri t rr+ t
on
V
d
Copyright © by John Wiley & Sons 2003 Snubbers  19
Turnon Snubber Recovery at Switch Turnoff
+
D Io R
f Io I o R Lsexp(R Lst/L s ) Ls
is
w V
Io d
R
V Ls Ls
d
vs
D t rv
Ls
w
 Sw
• Switch waveforms at turnoff with turnon snubber in circuit.
Selection of inductor
• Larger Ls decreases energy dissipation in switch at turnon
• Wsw = WB (1 + Irr/Io)2 [1  Ls/Ls1]
• WB = VdIotfi/2 and Ls1 = Vdtfi/Io
• Ls > Ls1 Wsw = 0
1 3 5
 va n + Ls
B i
d
• van(t) = Vssin(wt), vbn(t) = Vssin(wt  120°),  v cn + Ls
Cs
4 6 2
Rs
Phasetoneutral waveforms a v
v bn
an
• vLL(t) = 3 Vssin(wt  60°)
3
• Maximum rms linetoline voltage VLL = V
2 s
v LL = v v v w t
bn an= ba 1
Assumptions
È ˘2
Í Irr ˙
• Snubber capacitor Cs = Cbase = Ls Í ˙
ÎVd ˚
diLs
• From snubber equivalent circuit 2 Ls = 2 V LL
dt
• Vd = 2 VLL
0.05!VLL È25!wI ˘ 2
Í a1trr˙ 8.7!wIa1 trr
• Cs = C base = Í ˙ =
3!Ia1w Î ! 2VLL ˚ VLL
Vd
• Snubber resistance Rs = 1.3 Rbase = 1.3
Irr
2V LL 0.07!VLL
• Rs = 1.3 =
25wIa1 trr !wIa1 trr
LsIrr 2 CsV d2
• WR = + = 18 w I a1 V LL(trr )2
2 2
Outline
• Drive circuit design considerations
• DCcoupled drive circuits
• Isolated drive circuits
• Protection measures in drive circuits
• Component/circuit layout considerations
• Minimize turnon time through active region where power dissipation is large
• Signal processing circuits which generate the logic control signals not considered part of the drive circuit
• Drive circuit amplifies control signals to levels required to drive power switch
• Drive circuit has significant power capabilities compared to logic level signal processing circuits
• Provide electrical isolation when needed between power switch and logic level signal processing/control circuits
• Component layout to minimize stray inductance and shielding from switching noise
• Circuit operation
• Vcontrol > Vreference  BJT at comparator output on
which puts Qpnp and Qsw on
• Vcontrol < Vreference  BJT at comparator output off
V
which turns Qpnp off and thus Qsw off BB V
d
• Design procedure
VBE,off
Io
• R2 =
IB,off
; IB,off based on desired turnoff time. Comparator Q pnp
VBE,on
• Ipnp = IB,on + ; IB,on value based on BJT beta and R1
R2 Vcontrol
value of Io.
Q sw
• VBB = VCE,on(Qpnp) + R1 IC,pnp + VBE,on(Qsw) R
2
• VBB = 8 to 10 V ; compromise between larger values which
minimize effects of VBE variations and smaller values
which minimize power dissipation in drive circuit
Vreference
V
V d
GG
Io
Comparator R Io
B Df • Large reverse base current flows to
minimize turnoff time and baseemitter
Vcontrol C BB+ of Qsw reversed biased to insure off
T state.
+ B+
Q sw
 T
Vreference B • Vcontrol > Vreference  comparator output
high, TB+ on and Qsw on.
C
BB
• Large forward base current to minimize
V turnon time and to insure saturation of
BB
Qsw for low onstate losses
Comparator Io
D
f
T B+
Vcontrol C • Bipolar drive with substantial output
GG+
current capability
+
Q sw
R
 G
Vreference TB
C
GG
V
GG
V
V d
GG+
Io
C GG+
Isolated auxiliary
• Negative half cycle of vs(t)  positive dc power to base
drive circuits
rail near safety ground potential. T
emitter potential large and negative with
respect to safety and logic ground
base D
Signal T+ F+
• Postive half cycle of vs(t)  negative dc drive
isolation circuit
rail near safety ground potential. T+ V Logic and
+ d
emitter substantially positive with espect Control
v Electronics
to safety ground if T is off S
base D
 Signal T F
isolation drive
circuit
Control
• Variation in emitter potentials with Inputs
respect to safety and logic ground means
that electrical isolation of emitters from
logic ground is needed.
Safety
Ground
Signal
Input to remainder of
from
isolated drive circuit • Optocoupler isolation
control
logic
Power switch
Control logic reference node
ground Phototransistor
V
BB+
AC
power in
• Isolated dc power supplies
for drive circuits
V BB
Signal
from Optocoupler
control
electronics
R
B C
BB+
T
B+
Q sw
TB
C BB
V
BB
C
BB
V
control
V
BB+
AC
power
in
VBB
Oscillator output
t
V
control
t
Transformer
t primary voltage
Input to
t comparator
AC
power
in
V V
Signal GG+ d
Optocoupler
from control
electronics Io
C GG+
V
DD v
+ C
Buffer
+
v
sec
Buffer
output v = V (1  D)
voltage
C DD Most suitable for applications
where duty cycle D is 50% or
0
t duty
less. Positivegoing secondary
v
ratio voltage decreases as D increases.
sec D= 0.5
t
0
Buffer output
v
voltage C
0
t
duty
v ratio
sec
D= 0.3
t
0
Vc o n t r o l
Inverting A
Buffer
v
sec vc a p
C Noninverting
Buffer B
Schmitt
Zener diode voltage VZ
trigger must be less than negative
Vc o n t r o l t
pulse out of transformer
secondary or pulse will not
v
A t
reach MOSFET gate to turn
v C t it off.
v t
B
v v
A B t
V
Z
V
v Z
sec t
(dotted) vc a p
Q Buffer
4047 +
vc o n t r o l v
oscillator Q trans

(1 MHz) Buffer
C
R C 1
2 2
7555
+ R
G
+ v
v 2s
D 1s
B
 
vc o n t r o l
v
Q
C1 charges up to a
positive voltage at
v powerup and remains
Q
there. D B prevents
discharge
v
trans
v Decay of
1s
voltage on C 2
via R
v 2
2s
Power
BJT
T
E
control
v
CE
switching switching
locus with locus with
standard emitter open
base drive base drive
• Circuit operation
• Turn on power BJT by turning on MOSFET TE.
• Turn off power BJT by turning off MOSFET TE.
• Collector current flows out base as negative base current.
• Greater iB(off) compared to standard drive circuits iC = b iB(off) removes stored charge much faster
• Turn off times reduced (up to ten times).
1 4
Line
Voltage
3 2
gate pulse
Control isolation
Logic transformers
Ground
a a a Ramp
Control
voltage Thyristor gate drive waveforms
Control of
1 & 2
Control of
3 & 4
D1
15 V
D
f
R Gate pulse amplifier
G
T
Trigger signal G
R R
2 4
T T
G2 G1
R
1 10 A
pulse V
R GG+
R 6
5
2 A
L
G
Ls 2 • Turn off TG1 after some
V
GG
specified time to reduce total
R
7 gate current to backporch
T
G3 value.
turnoff
pulse
Auxilliary
power supply
for gate drive
circuit
Dp
overcurrent
protection BJT
control
V BB
• Point C one diode drop above VCE(sat) when BJT is on. Overcurrent will increase
VCE and thus potential at C.
• If C rises above a threshold value and control signal is biasing BJT on,
overcurrent protection block will turn off BJT. Conservate design would keep
BJT off until a manual reset had been done.
+ D Io
F
Vd • Stepdown converter with
Cd
short curcuit at t = t sc

i i
C C
I I
C,sc B,max
I
C(on)max
V v t sc t
in CE
• Same approach can be used with MOSFETs and IGBTs. VGS mustbe restricted to keep drain current to
safe values.
V control,
bridge
V
1+
V
1
dead
time
V control, T
+
blanking collector blanking
time current time
V control, T
 dead
time
V
BB+
R • Antisaturation diode Das keeps Qsw active.
B
• VAE = VBE(on) + VD1 = VCE(on) + Vdas
TB+ Da s • VCE(on) = VBE(on) > VCE(sat) because VD1 = Vdas
D1
Qsw
• Ds provides path for negative base current at Qsw turnoff.
A
D
• Storage delay time at turnoff reduced but onstate losses increase slightly.
T 2
B E
V Speedup capacitors
BB
V i
BB+ B
R
B C on
T B+
t
i
B • Transient overdrive
Qsw
provided via C on for
faster turnon of switch
T
B
• Same concept can be applied to
MOSFET and IGBT drive circuits
V
BB
TB
V
BB
Gate/base Back porch Front porch, back porch gate/base currents at
current V current
BB+ turnon
Front Front
porch R R porch
B1 B2 • Faster turnon without putting device
current Back current
porch deeply into onstate where turnoff delay
Control
current T time will be substantially increased.
B+ i
B
Q
sw
T • Applicable to BJTs, MOSFETs, IGBTs, and
B
V GTOs.
BB
t
b
• Generic geometry h
Pcond heat flow
of heat flow via direction
conduction
+ R qjc + R + R qs a +
qc s
P Tj Tc Ts Ta
Case Tc
   
Isolation pad
Heat sink Ts
• Ti = Pd (Rqjc + Rqcs + Rqsa) + Ta
• If there parallel heat flow paths,
then thermal resistances of the
parallel paths combine as do
electrical resistors in parallel.
Ambient Temperature T a
• Heat capacity per unit volume Cv = dQ/dT [Joules /°C] prevents short duration high
power dissipation surges from raising component temperature beyond operating limits.
Tj (t)
Z (t  t 1)
q
P(t) R
q
Half sine pulse
P
o
Equivalent • Symbolic solution for half sine power
rectangular dissipation pulse.
pulse
• P(t) = Po {u(t  T/8)  u(t  3T/8)} ; area
T/2 under two curves identical.
Tj
Silicon
TCu
• Multilayer geometry Tc
Copper mount
Heat sink
Ta
• Choice of heat sink depends on required thermal resistance, Rqsa, which is determined by
several factors.
• Maximum power, Pdiss, dissipated in the component mounted on the heat sink.
• Component's maximum internal temperature, Tj,max
• Component's junctiontocase thermal resistance, Rqjc.
• Maximum ambient temperature, Ta,max.
• Pconv = convective heat loss to surrounding air from a vertical surface at sea level having
a height dvert [in meters] less than one meter.
• Pconv = 1.34 A [Ts  Ta]1.25 dvert0.25
• A = total surface area in [m2]
• Ts = surface temperature [°K] of component. Ta = ambient temperature [°K].
Outline
D. Thermal Considerations
H. Eddy Currents
• Starting equations
• Hm lm + Hg g = N I (Ampere’s Law)
• Bm A = Bg A = f (Continuity of flux Core: Hm
mo Hg = Bg
DB
H
• Results DH
NI
• Bs > Bm = Bg = = f/A
lm/mm!+!g/mo
A!N2 linear region
• LI = Nf ; L =
lm/mm!+!g/mo DB B
m= =
DH H
Copyright © by John Wiley & Sons 2003 Magnetics  3
Review of Transformer Fundamentals
• Assumptions same as for inductor Crosssectional
l m= mean path length area of core = A
• Starting equations
• H1Lm = N1I1 ; H2Lm = N2I2
(Ampere's Law) i1 i2
• HmLm = (H1  H2)Lm = N1I1 N2I2
+ +
• µmHm = Bm (linearized BH curve) v1 N1 v
2
N2
df1 df2  
• v1= N1 ; v2 = N2
dt dt f1 f2
(Faraday's Law)
• Net flux f = f1  f2 = µmHmA
Magnetic flux f
µmA(N1I1!N2I2)
=
Lm B
Bs
• Results assuming µm fi •, i.e. ideal core
DB
or ideal transformer approximation.
H
f DH
• = 0 and thus N1I1= N2I2
µm
d(f1!f2) v1 v2 v1 v2
• = 0 =  ; = linear region
dt N1 N2 N1 N2
DB B
m= =
DH H
Copyright © by John Wiley & Sons 2003 Magnetics  4
Current/Flux Density Versus Core Size
• Larger electrical ratings require larger current I and
larger flux density B. B
Bs
• Core losses (hysteresis, eddy currents) increase
Minor
as B2 (or greater)
hystersis
• Winding (ohmic) losses increase as I2 and are loop
accentuated at high frequencies (skin effect,
proximity effect)
H
• To control component temperature, surface area of
component and thus size of component must be
increased to reject increased heat to ambient.
• At constant winding current density J and core  Bs
flux density B, heat generation increases with
volume V but surface area only increases as V2/3.
core
• Maximum J and B must be reduced as electrical
ratings increase.
• Flux density B must be < Bs
g
• Higher electrical ratings fi larger total flux
fi larger component size
• Flux leakage, nonuniform flux distribution fringing
complicate design flux
• Transformer electrical (converter circuit) 3. How to design low loss windings at high
specifications. operating frequencies.
• Rated rms primary voltage Vpri
• Rated rms primary current Ipri
• Turns ratio Npri/Nsec
• Operating frequency f • Detailed consideration of core losses, winding
• Allowable power dissipation in transformer or losses, high frequency effects (skin and proximity
equivalently maximum temperatures Ts and Ta effects), heat transfer mechanisms required for good
design procedures.
d
a
2
a a
2 1.9 a
1.4 a
hw
ha bw
2
ba Assembled core and winding
Bobbin
Core
Characteristic Relative Size Absolute Size for
a = 1 cm
Core area Acore 1.5 a2 1.5 cm2
Winding area Aw 1.4 a2 1.4 cm2
Area product AP = AwAc 2.1 a4 2.1 cm4
Core volume Vcore 13.5 a3 13.5 cm3
Winding volume Vw 12.3a3 12.3 cm3
Total surface area of 59.6 a2 59.6 cm2
assembled core and
winding
H Bac
Bdc B(t)
0
 Bs t
d
• Empirical equation  Pm,sp = k fa [Bac]
.
f = frequency of applied field. Bac =
basetopeak value of applied ac field. k,
a, and d are constants which vary from
material to material
2.5
• Pm,sp = 1.5x106 f1.3 [Bac]
mW/cm3 for 3F3 ferrite. (f in kHz and
B in mT)
• Pm,sp = 3.2x106 f1.8 [Bac]2
mW/cm3 METGLAS 2705M (f in kHz
and B in mT)
• Example: 3F3 ferrite with f = 100 kHz
and Bac = 100 mT, Pm,sp = 60
mW/cm3
• Core materials have different allowable values of Bac at a specific frequency. Bac limted by allowable Pm,sp.
• Choosing best material aided by defining an emperical performance factor PF = f Bac. Plots of PF versus
frequency for a specified value of Pm,sp permit rapid selection of best material for an application.
• Plot of PF versus frequency at Pm,sp = 100 mW/cm3 for several different ferrites shown below.
Eddy current
Bi(r)
• = exp({r  a}/d)
Bo
B (r) B (r)
i i
B
2
B (t)
o
o Bo
• d = skin depth = wms
• w = 2π f, f = frequency
r • m = magnetic permeability ;
a a
0
mo for magnetic materials.
• s = conductivity of material.
t
• Stacking factor kstack = !t!+!0.05t 0.5 t
t (typically
0.3 mm)
Insulator
Magnetic steel
lamination
B sin( wt)
x
x
x x
x
A A
x
x
x
x
x x
• Proximity effect  losses due to eddy
B B current generated by the magnetic
field experienced by a particular
MMF conductor section but generated
by the current flowing in the rest of
the winding.
x x
• Design methods for minimizing
proximity effect losses discussed
10
Eddy
100 later.
Current
30
Losses
3 10
1 1
x x
Resistance
• Pw = { Rdc + R ec} [Irms]2 = Rac [Irms]2
R
dc
R
• Rac = FR Rdc = [1 + Rec/Rdc] Rdc ec
• Pw = 1.5 Pdc
Psp 1
• Power per unit volume, Psp, dissipated in magnetic • Jrms = kcu!rcu = k2 k a ; k2 = constant
component is Psp = k1/a ; k1 = constant and cu
a = core scaling dimension.
Ts!!Ta
• Pw,sp Vw + Pm,sp Vm = R : • Pm,sp = Psp = k fb [Bac]d ; Hence
qsa
d P k3
Ta = ambient temperature and Rqsa = sp
Bac = = where k3 = constant
surfacetoambient thermal resistance of component. kfb d
fb!a
proportional to a3
7 350
Assumptions 6 300
4 200
2. Ts = 100 °C and Ta = 40 °C.
J rms
3 150
3. Winding made with Leitz wire  kcu =
0.3 2 100
P
sp
1 50
0 0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Ag
Copyright © by John Wiley & Sons 2003 Magnetics  23
Analysis of a Specific Inductor Design (cont.)
N!f
• L = = 310 mH
I
• f = Bac Ac = (0.18 T)(1.5x104 m2) = 2.6x105 Wb
g
• Overcurrent of 25% (I= 5 amp rms) makes Ts = 146 °C
A core
d
• Pw = (3.2 W)(1.25)2 = 5 W ; Pcore = (3.3 W)(1.25)2.5 = 5.8 W
Ag
• Input specifications for inductor design • Design procedure starting point  stored energy relation
• Inductance value L.
• [L I] Irms = [N f] Irms
• Rated peak current I
• Rated rms current Irms. kcu!Aw
• N= A
• Rated dc current (if any) Idc. cu
• Operating frequency f. • f = B Acore ; Irms = Jrms Acu
• Maximum inductor surface temperature Ts
and maximum ambient temperature Ta. • L I Irms = kcu Jrms B Aw Acore
• Information on all core types, sizes, and materials must be stored on spreadsheet. Info includes
dimensions, Aw, Acore, surface area of assembled inductor, and loss data for all materials of interest.
• Prestored information combined with user inputs to produce performance data for each core in
spreadsheet. Sample of partial output shown below.
4. Calculate airgap length Lg. Airgap length determined on basis that when inductor current
equals peak value I, flux density equals peak value B.
• Formulas for airgap length different for different core types. Example for doubleE core
given in next slide.
5. Calculate maximum inductance Lmax that core can support. Lmax = N Acore Bpeak / Ipeak .
If Lmax > required L value, reduce Lmax by removing winding turns.
• Save on copper costs, weight, and volume.
• Pw can be kept constant by increasing Pw,sp
• Keep flux density Bpeak constant by adjusting gap length Lg.
6. Alternative Lmax reduction procedure, increasing the value of Lg, keeping everything else
constant, is a poor approach. Would not reduce copper weight and volume and thus achieve
cost savings. Full capability of core would not be utilized.
Examine database
outputs & select core
Neglect skin,
proximity effects?
Yes No
Iterative selection of
Select wires
conductor type/size.
No Yes
Estimate Lmax.
Too large?
Finish
= 0.00068 Jm3
(63)(170!mT)(1.5x104!m2)
• Lmax = 5.6!A
• Core material and geometric shape
• High frequency operation dictates ferrite ≈ 290 microhenries
material. 3F3 material has highest
performance factor PF at 100 kHz. 102
• DoubleE core chosen for core shape. • Lg =
(0.17)!(1.5x104) 2.5x102
! !!
• DoubleE core with a = 1 cm meets requirements. (1.5x102)(4πx107)(63)(5.6) (4)(1.5x102)!
kcu Jrms B^ A A Lg ≈ 3 mm
w core ≥ 0.0125 kcu 0.0068
for kcu > 0.3
• Lmax ≈ L so no adjustment of inductance value
is needed.
• Database output: Rq = 9.8 °C/W and
Compute L I I r m s
• Assume Jrms= 24 A/mm2 and Bac = 50100 mT and use
LI Irms = kcu Jrms Bac Aw Acore to find the required area
Determine core size using product Aw Acore and thus the core size.
assumed values of J and B
• Assumed values of Jrmsand Bac based on experience.
Design winding (k cu
,J, A cu
, N)
• Complete design of inductor as indicated.
Set airgap length g to • Check power dissipation and surface temperature using
obtain desired inductance L Select
assumed values of Jrmsand Bac. If dissipation or
larger
core size temperature are excessive, select a larger core size and repeat
design steps until dissipation/temperature are acceptable.
No Check power dissipation Yes
and surface temperature.
Excessive?.
• Procedure is socalled area product method. Useful in
situations where only one ore two inductors are to be built
Done and size/weight considerations are secondary to rapid
construction and testing..
Copyright © by John Wiley & Sons 2003 Magnetics  33
Analysis of Specific Transformer Design
• Transformer specifications • Areas of primary and secondary conductors,
Acu,pri and Acu,sec.
• Wound on doubleE core with
a = 1 cm using 3F3 ferrite.
Npri!Acu,pri Nsec!Acu,sec
• Ipri = 4 A rms, sinusoidal waveform; • Aw,pri = !kcu,pri ; A w,sec = !kcu,sec
Vpri = 300 V rms.
Npri!Acu,pri Nsec!Acu,sec
• Frequency = 100 kHz • Aw,pri + Aw,sec = Aw = !kcu + !kcu
where kcu,pri = kcu,sec = kcu since we assume primary and
• Turns ratio Npri/Nsec = 4 and
secondary are wound with same type of conductor.
Npri = 32.
• Equal power dissipation density in primary and secondary gives
• Winding window split evenly between
primary and secondary and wound Ipri Acu,pri Nsec
with Litz wire. Isec = !Acu,sec = N
pri
• Transformer surface black (E = 0.9) kcu!Aw
and Ta ≤ 40 °C. • Using above equations yields Acu,pri = 2!N and
pri
kcu!Aw
• Find: core flux density, leakage inductance, Acu,sec = 2!N
and maximum surface temperature Ts, and sec
(0.3)(140!mm2)
effect of 25% overcurrent on Ts. • Numerical values: Acu,pri = (2)(32) = 0.64 mm2
(0.3)(140!mm2)
and Acu,sec = (2)(8) = 2.6 mm2
Copyright © by John Wiley & Sons 2003 Magnetics  34
Analysis of Specific Transformer Design (cont.)
Mean turn length l w
• Power dissipation in winding Pw = kcu rcu(Jrms)2 Vw Top view
r adi us = b /2
w
of bobbin
1.9 a
• Pw = (0.3)(2.2x108 ohmm) (6.2x106 A/m2)2(1.23x105 m3) 1.4 a
Pw = 3.1 watts
mo(Npri)2!bw!lw
• Effect of 25% overcurrent.
• Leakage inductance Lleak =
3!hw • No change in core flux density.
• lw = 8 a = 8 cm Constant voltage applied to
primary keeps flux density constant.
(4πx107)(32)2(0.7)(102)(8x102)
• Lleak = ≈ 12 microhenries • Pw = (3.1)(1.25)2 = 4.8 watts
(3)(2x102)
•` Ts = (9.8)(4.8 + 1.9) + 40 = 106 °C
x x x
x Primary
x x x • Reduce winding losses by reducing magnetic
x x x
Secondary field (or equivently the mmf) seen by
x x x
conductors in winding. Not possible in an
inductor.
MMF
• Simple twosection transformer winding
Npri I pri = Nsec I sec situation.
x
0 b
w
P P P S P S P
S
2 2 4 2 2 2 4 • Division into multiple
sections reduces MMF and
hence eddy current losses.
MMF MMF
0 x 0 x
Npri I pri
Npri I pri Npri I pri
2 Npri I pri
4 4
2
Fl!h
• Conductor height/diameter d
• Fl = copper layer factor
• Fl = b/bo for rectangular conductors
• Fl = d/do for round conductors
• h = effective conductor height
π
• h= d for round conductors
4
• m = number of layers
hw
b hw
N l turns per layer =
bo bo
do
hw
hw
N l turns per layer =
do
• Rated rms primary voltage Vpri • S = Vpri Ipri + Vsec Isec = 2 Vpri Ipri
df Npri!Acore!w!Bac
• Rated rms primary current Ipri • Vpri = Npri dt = ; Ipri = Jrms Acu,pri
2
• Turns ratio Npri/Nsec Npri!Acore!w!Bac
• S = 2 Vpri Ipri = 2 Jrms Acu,pri
2
• Operating frequency f
kcu!Aw
• Maximum temperatures Ts and Ta • Acu,pri = 2!N
pri
• Only solid conductors, round wires or rectangular wires (foils), used.Jrms = [{Psp Rdc}/{Rac kcu rcu}]1/2
• Conductor dimensions must simultaneously satisfy area requirements and requirements of normalized
power dissipation versus normalized conductor dimensions.
• May require change in choice of conductor shape. Most likely will require choice of foils (rectangular
shapes).
• Several iterations may be needed to find proper combinations of dimensions, number of turns per layer,
and number of layers and sections.
• Best illustrated by a specific design example.
6. IfSmax > S = 2 Vpri Ipri reduce Smax and save on copper cost, weight, and volume.
• If Npri w Ac Bac > Vpri, reduce Smax by reducing Npri and Nsec.
• If Jrms Acu, pri > Irms, reduce Acu,pri and Acu, sec.
• If S > Smax by only a moderate amount (1020%) and smaller than Smax of next core size, increase Smax of
present core size.
• Increase Irms (and thus winding power dissipation) as needed.Temperature Ts will increase a modest amount
above design limit, but may be preferable to going to larger core size.
Start
Examine database
outputs & select core
Neglect skin,
proximity effects?
Yes No
Iterative selection of
Select wires
conductor type/size.
No Yes
Estimate S max.
Too large?
Remove turns
Finish
P S P S P S P
6 3 3 3 3 3 6
• Three secondary sections requires four primary sections. • Leakage inductance Lleak
Select larger core size • Use initial values of Jrms = 24 A/mm2
Find allowable power and Bac = 50100 mT.
dissipation density P
sp
• Use initial core size estimate (value of a in
Find maximum V  I rating doubleE core example) to find corrected
Find corrected core flux
density B
values of Jrms and Bac and thus corrected
ac
^ A A
value of 4.4 f kcu Jrms B w core.
Set S max to desired S
Find corrected current
density J r m s • Compare 4.4 f kcu Jrms B ^ A A
w core with
2 Vpri Ipri and iterate as needed into proper
Estimate leakage inductance
size is found.
End
Set S max to desired S • Check power dissipation and surface temperature using
Select
larger assumed values of Jrmsand Bac. If dissipation or
core size temperature are excessive, select a larger core size and repeat
design steps until dissipation/temperature are acceptable.
No Check power dissipation Yes
and surface temperature.
Excessive?.
• Procedure is socalled area product method. Useful in
situations where only one ore two transformers are to be built
Done and size/weight considerations are secondary to rapid
construction and testing..
Copyright © by John Wiley & Sons 2003 Magnetics  48
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