B.

Tech Degree Examination November 2012

Model question paper
Branch : Electronics and communication
Semester : 5
Subject: EC010503 Digital System Design
Time : 3 Hrs
Max Marks: 100
Part A
(Answer all questions. Each question carries 3 marks)

1.
2.
3.
4.
5.

What are the different data types in Verilog HDL?

Draw the structure of 8:1 decoder.
Define metastability.
Explain ASM in brief.
What is a test bench? What is its relevance in Verilog?
Part B
(Answer all questions. Each question carries 5 marks)

6. Write the verilog code for a 2:4 decoder circuit.

7. Realise the functions f1(x,y,z) = m(1,2,4,5) and f2(x,y,z) = m(1,5,7) using MUX.
8. With a neat block diagram, explain Mealy and MOORE model.
9. Explain the relevance of implication table in state machine concepts.
10. Explain the different types of modelling in Verilog.
Part C
(Each question carries 12 marks)

11. Design and implement 16:1 Multiplexer using two 8:1 MUX in Verilog HDL.
OR
12. Design and implement a full adder using Verilog HDL.
a) gate level modelling
b) Structural modelling( using half adder)
13. Simplify the given Boolean function F(A,B,C,D) = m(0,1,2,8,10,11,14,15) using
Quine Mc Clusky algorithm.
OR
14. a) With a neat block diagram, explain PLA.
( 4 marks)
b) Implement the functions, f1(x,y,z) = m(1,2,3,7) and f2(x,y,z) = m(0,1,2,6)
using 3X4X2 PLA ( true/compliment method).
(8 marks)
15. Design a clocked synchronous sequential circuit which detects the following sequence
0110/1001.
OR
16. Design and implement a serial binary adder as a Mealy network.

17. Explain state table reduction and state assignment technique using the state table
given below.
Next State
Out put (z)
Present
Input (x)
Input (x)
State
X =0
X=1
X=0
X=1
*A
A
B
0
0
B
D
C
0
1
C
F
E
0
0
D
D
F
0
0
E
B
G
0
0
F
G
C
0
1
G
A
F
0
0
OR
18. a) Write notes on ASM charts.
b) Draw the ASM chart for a MOD 8 UP/DOWN counter.
19. Model a 4 bit linear feedback shift register using Verilog HDL.
OR
20. Model a 4 bit binary multiplier using Verilog HDL

************************

(5 marks)
(7 marks)