Compal La-9981p r0.2 Schematics

A
MODEL NAME : VBW00

PROJECT CODE : ANRVBW0100
PCB NO : DA8000WK000 LA-9981P M/B
DA40001FO00 LS-9101P POWER BUTTON/B
DA40001FP00 LS-9102P USB/B
DA40001FQ00 LS-9103P TP BUTTON/B
Dell / Compal Confidential

Schematic Document
Intel Shark Bay ULT

OAK Value2
UMA/DIS AMD Sun XT
2013-03-09
Rev: 0.2
X76@ : 76 level
46@ : 46 level
@ : Nopop component
CONN@ : Connector component
XDP@ : XDP function
UMA@ : Only for UMA
DIS@ : Only for Discrete
SUN@ : SUN XT
EMI@ : EMI parts
@EMI@ : Reserve EMI parts
ESD@ : ESD parts
RF@ : RF parts
BOM config
UMA : UMA@,EMI@,ESD@,RF@,XDP@
DIS SUN : SUN@,DIS@,EMI@,ESD@,RF@,XDP@
ZZZ
R1@
PCB VBW01 LA9981P/LS9101P/LS9102P/LS9103P

DA8000WK000
Compal Secret Data
Security Classification
Issued Date
2013/03/09
Deciphered Date
2014/04/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Compal Electronics, Inc.

Cover Page
Size
Document Number
Custom
Rev
0.2
LA-9981P
Date:
Saturday, March 09, 2013
Sheet
E
of
55
128M*16
GDDR5*8
Fan Control
128M*16
GDDR5*8
P.34
P.27
Memory Bus (DDR3L)
AMD
Venus Pro , 25W
P.36
P.28~33
Venus Pro(HD8850M)2GB GDDR5 (128Mx16x8pcs)
P.17~18
8GB Max
SATA3.0
Port 0
SATA HDD Conn. P.42
Port 1
USB 3.0
LVDS Conn.
LVDS
P.41
RTD2136R
eDP
P.19
USB2.0
SATA ODD Conn. P.42
Port 1,2
Port 0,1
Port 2,3
HDMI
HDMI Conn.
PCI-E
Mini Card
WLAN/BT4.0
Half
P.26
Intel
Lynx Point-LP
Port 1
P.24
USB 2.0 Conn. 3

USB 2.0 Conn. 4
P.25
Digital Camera
(With Digital MIC) P.41
Port 8
Mini Card
WLAN (Half)
P.26
Card Reader
RTS5179/5170
P.23
Port 10
Ethernet
RTL8106E
USB 3.0 Conn. 1

USB 3.0 Conn. 2
Port 11
P.20
Port 2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1.35V DDR3 1600 MHz
Intel
Haswell
Processor
15W DC
BGA1168
PEG 2.0 x4
64bit
P.37
CPU XDP
Conn. P.6
DDRIII-DIMM X2
Dual Channel
128M*16
GDDR5*8
P.35
64bit
128M*16
GDDR5*8
Port 9
Touch Screen
Daughter board
3 in 1 Socket
P.23
P.41
(OAK 15" only)

P.21
RJ45
Digital Mic.
P.21
HD Audio
SPI ROM
64M
Audio Codec
ALC3223
SPI
P.9
P.22
Headphone Jack / Mic. Jack combo
P.22
Int. Speaker R / L
P.22
P6~16
LPC Bus
SMBus
33MHz
Int.KBD
P.27
ENE KBC
KB9012 P.40
PS/2
Touch Pad
P.27
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
A
Title
Block diagram
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
E
of
55
Compal Confidential
Project Code : VAW00 / VAW01
File Name : LA-9981P / LA-9982P
1
LS-9101P (PWR/B)
UE5
(SA00003VQ00)
Lid
4 pin-Hot Bar
SW1
(SN100004Y00)
PBATT
Battery
JMINI
PWR-BTN FFC
PJPDC
5 pin
MINI Card
4 pin
JLVDS
40 pin
JKB
30 pin
JFAN
3 pin
JHDMI
JTP
6 pin
JTOUCH
6 pin
JLAN
RJ-45
JUSB1
USB
TP-MB FFC
6 pin
LS-9102P (USB/B)
HDMI
JUSB2
USB
JUSB3
USB
JODD
JPWR
4 pin
USB
USB-DB FFC
LA-9981P M/B
LA-9982P M/B
XDP
JXDP
8 pin
JUSB4
8 pin
Hot Bar
JHDD
Top Side
Bottom Side
JDB
8 pin
(OAK 15")
JRTC
2 pin
JSPK
4 pin
JREAD
RTC
JHP
TP-Module
Card
Reader
HP
Led1
Led3
Led2
Led4
TP-BTN FFC
4 pin
LS-9103P (TP-BTN/B)
4 pin
Hot Bar
SW2
SW3
Issued Date
Compal Secret Data
2013/03/09
2014/04/01
Deciphered Date
A
Title
DB block diagram
Size
Date:
Document Number
Rev
0.2
LA-9981P
Sheet
E
of
55
Board ID Table for AD channel

Vcc
Ra
Board ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
3.3V +/- 1%
100K +/- 1%
Rb
0
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%
NC
USB3.0
V AD_BID min
0.000V
0.347V
0.423V
0.541V
0.691V
0.807V
0.978V
1.169V
1.398V
1.634V
1.849V
2.015V
2.185V
2.316V
2.395V
2.521V
2.667V
2.791V
2.905V
3.000V
V AD_BID typ
0.000V
0.354V
0.430V
0.550V
0.702V
0.819V
0.992V
1.185V
1.414V
1.650V
1.865V
2.031V
2.200V
2.329V
2.408V
2.533V
2.677V
2.800V
2.912V
3.300V
V AD_BID max
0.300V
0.360V
0.438V
0.559V
0.713V
0.831V
1.006V
1.200V
1.430V
1.667V
1.881V
2.046V
2.215V
2.343V
2.421V
2.544V
2.687V
2.808V
2.919V
3.300V
EC
0x00
0x0C
0x1D
0x27
0x31
0x3C
0x47
0x55
0x65
0x77
0x88
0x97
0xA4
0xAE
0xB8
0xC1
0xCA
0xD4
0xDD
0xE7
AD3
- 0x0B
- 0x1C
- 0x26
- 0x30
- 0x3B
- 0x46
- 0x54
- 0x64
- 0x76
- 0x87
- 0x96
- 0xA3
- 0xAD
- 0xB7
- 0xC0
- 0xC9
- 0xD3
- 0xDC
- 0xE6
- 0xFF
EC_SMB_CK1
EC_SMB_DA1
KB9012
EC_SMB_CK2
EC_SMB_DA2
KB9012
SMBCLK
SMBDATA
ULT
SML0CLK
SML0DATA
ULT
SML1CLK
SML1DATA
ULT
Charger
RTD2136S
VGA
DDR3L
XDP
WLAN
mini card
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol Note :
0.1
: means Digital Ground
0.2
: means Analog Ground
CLKOUT_PCIE2
10/100 LAN
CLKOUT_PCIE3
MINI Card (WLAN)
Port4
MINI Card (WLAN)
Port5
Touch Screen Panel
Port6
Card Reader
Port7
Camera
Lane 3
10/100 LAN
Lane 4
MINI Card (WLAN)
Lane 5
PEG (N14P)
Lane 6
PEG (N14P)
CLKOUT_PCIE4
dGPU (N14P)
SATA0
HDD
SATA1
ODD
SATA2
SATA3
0.3
0.3
USB connector 4 (DB)
SATA
CLKOUT_PCIE1
0.2
0.3
Port3
CLKOUT_PCIE0
0.2
0.2
USB connector 3
Lane 2
Venus XT
0.1
Port2
Lane 1
CLOCK SIGNAL
0.1
USB connector 1
PCI EXPRESS
V V
Venus Pro
Port1
V
Link
Sun XT
USB connector 2
0.1
Port0
Touch pad
PCB Revision
UMA
USB connector 1
USB2.0
BOARD ID Table
ID
Port2
Port4
ULT
BATT
USB connector 2
Port3
SMBUS Control Table

SOURCE
Port1
CLKOUT_PCIE5
0.3
1.0
1.0
1.0
Issued Date
Compal Secret Data
1.0
2013/03/09
Deciphered Date
2014/04/01
A
Title
Notes List
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
of
55
2.2K
SMBUS Address [0x9a]
2.2K
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
10K
+3.3V_ALW_PCH
+3VS
10K
N-MOS
N-MOS
DDR_XDP_WLAN_TP_SMBCLK
202
DDR_XDP_WLAN_TP_SMBDAT
200
DIMMA
SMBUS Address [A0]
1K
DIMMB
202
+3.3V_ALW_PCH
1K
MCH
Shark bay
AN1
SML0CLK
AK1
SML0DATA
0 ohm
0 ohm
2.2K
2.2K
AN1
SML1_SMBCLK
AK1
SML1_SMBDATA
SMBUS Address [A4]
200
DDR_XDP_SMBCLK_R1
53
DDR_XDP_SMBDAT_R1
51
XDP1
SMBUS Address [TBD]
JMINI
SMBUS Address [TBD]
JTP
SMBUS Address [TBD]
+3.3V_ALW_PCH
30
N-MOS
N-MOS
32
EC_SMB_CK2
EC_SMB_DA2
5
6
2.2K
2.2K
79
EC_SMB_CK2
80
EC_SMB_DA2
+3VALW
0 ohm
N-MOS
0 ohm
N-MOS
0 ohm
CSCL
0 ohm
CSDA
CIICSCL
13
CIICSDA
14
UV28
LVDS
Translator SMBUS Address [TBD]
2.2K
+3VS_VGA
2.2K
N-MOS
N-MOS
VGA_SMB_CK2
T4
VGA_SMB_DA2
T3
UV28
GPU
SMBUS Address [0xXX]
2.2K
2.2K
KBC
KB9012A4
77
EC_SMB_CK1
78
EC_SMB_DA1
+3VALW
0 ohm
0 ohm
SCL
11
SDA
10
PU701
POWER
Charger
SMBUS Address [0x12]
100 ohm
100 ohm
PD1
BAT_ALERT
BATT_PRS
PBATT1
BATT
CONN
SMBUS Address [0x16]
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
2014/04/01
5
Title

SMBus block diagram
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
of
55
UC1
4200Ui5G2R1@
i5-4200U-15W-GT2-QS
CL8064701477702-QEVE-C0-1.6G_BGA1168~D
SA00006SM0L
UC1
4010Ui3G2R1@
HASWELL_MCP_E
UC1A
i3-4010U-15W-GT2-QS
CL8064701478202-QEVG-C0-1.7G_BGA1168~D
SA00006SX0L
D
UC1
<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>
4500Ui7G2R1@
i7-4500U-15W-GT2-QS
CL8064701477202-QEVD-C0-1.8G_BGA1168~D
C54
C55
B58
C58
B55
A55
A57
B57
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
C51
C50
C53
B54
C49
B50
A53
B53
SA00006SL0L
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
DDI
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
C45
B46
A47
B47
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1
<19>
<19>
<19>
<19>
C47
C46
A49
B49
COMPENSATION PU FOR eDP
A45
B45
EDP_CPU_AUX#
EDP_CPU_AUX
D20
A43
EDP_COMP
EDP_DISP_UTIL
EDP_CPU_AUX#
EDP_CPU_AUX
+VCCIOA_OUT
<19>
<19>
2
1
EDP_BIA_PWM
24.9_0402_1%~D
<10,19>
@
RC72
0_0402_5%
RC71
CAD Note:Trace width=20 mils ,Spacing=25mil,

Max length=100 mils.
Rev1p2
1 OF 19
+1.05VS
+3VS
UC4
0.1U_0402_10V7K
14
<8>
PCH_JTAG_TDO
PCH_JTAG_TDO
2 TDO_XDP
0_0402_5%
RC43
2
1
RUNPWROK
<8>
PCH_JTAG_TDI
2
TDI_XDP
0_0402_5%
RC44
2 TDI_XDP_R
0_0402_5%
RC45
5
4
RUNPWROK
<8>
PCH_JTAG_TMS
RC46
<30>
TMS_XDP
0_0402_5%
RUNPWROK
10
TRST#_XDP
12
RUNPWROK
RUNPWROK
13
VCC
1A
1B
XDP_TDO
+1.05VS
XDP@
CC15
0.1U_0402_10V7K
XDP@
CC14
0.1U_0402_10V7K
CC13
XDP_PREQ#
XDP_PRDY#
<16>
<16>
CFG0
CFG1
<16>
<16>
CFG2
CFG3
<16>
<16>
CFG4
CFG5
<16>
<16>
CFG6
CFG7
CFG0
CFG1
1OE
2A
2B
XDP_TDI
XDP_TMS
11
XDP_TRST#
Place near JXDP1
CFG2
CFG3
XDP_OBS0_R
XDP_OBS1_R
2OE
3A
3B
3OE
4A
4B
4OE
GND
GND PAD
H_CPUPWRGD
<10,30>
PBTN_OUT#
<13> CPU_PWR_DEBUG#
<10,30> SYS_PWROK
15
<17,18,19,26,27,9>
<17,18,19,26,27,9>
74CBTLV3126BQ_DHVQFN14_2P5X3
SYS_PWROK
+1.05VS
JXDP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
CFG4
CFG5
CFG6
CFG7
RC48
RC49
1 XDP@
1 XDP@
2 1K_0402_5%
2 0_0402_5%
H_VCCST_PWRGD_XDP
CFD_PWRBTN#_XDP
RC50
RC52
1 XDP@
1 XDP@
2 0_0402_5%
2 0_0402_5%
CPU_PWR_DEBUG#_R
SYS_PWROK_XDP
1
2
3
4
8
7
6
5
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
PCH_JTAG_TCK
XDP_TCLK
RP46
0_8P4R_5%
reference Shark Bay ULT Validation Customer Debug Port

Implementation Requirement Rev 1.0
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
CFG17
CFG16
<16>
<16>
C
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
<16>
<16>
CFG10
CFG11
<16>
<16>
CFG19
CFG18
<16>
<16>
CFG12
CFG13
<16>
<16>
CFG14
CFG15
RC139 1 XDP@
RC140 1 XDP@
CLK_XDP
CLK_XDP#
XDP_RST#_R
XDP_DBRESET#
<16>
<16>
2
2
0_0402_5%
0_0402_5%
CLK_CPU_ITP
CLK_CPU_ITP#
PLT_RST#
2
RC51
1K_0402_5%
TDO_XDP
TRST#_XDP
TDI_XDP
TMS_XDP
CFG3_R
PLT_RST#
+3VS
<9>
<9>
<10,21,26,30,48>
RC362
1K_0402_1%
XDP@
1
2
CFG3
1K_0402_5%
RC56
XDP@
SAMTE_BSH-030-01-L-D-A
CONN@
XDP@
CFG17
CFG16
CFG8
CFG9
2
CC17
0.1U_0402_10V7K
+3VALW_PCH
RC60
H_CATERR#
49.9_0402_1%
H_PROCHOT#
62_0402_5%
PCH_JTAG_RST#
0_0402_5%
<8>
PCH_JTAG_JTAGX
0_0402_5%
XDP_TRST#
RC57
@
RC64
1K_0402_5%
XDP_TCLK
RC59
XDP_DBRESET#
2
0_0402_5%
<8>
PCH_JTAG_TCK
TDO_XDP
RC62
TDI_XDP_R
RC63
XDP_TCLK
RC65
XDP@
PCH_JTAG_TDO
0_0402_5%
PCH_JTAG_TCK
0_0402_5%
XDP@
XDP@
SYS_RESET#
SYS_RESET#
<10>
RC26
0_0402_5%
SYS_PWROK_XDP
B
1
@ RC58
+1.05VS
XDP@
CC16
0.1U_0402_10V7K
Place near JXDP1.47
H_CPUPWRGD
HASWELL_MCP_E
UC1B
RC66
10K_0402_5%
<30>
CPU_DETECT#
H_CATERR#
PECI_EC
CPU_DETECT#
PECI_EC
PROC_DETECT
CATERR
PECI
MISC
<30>
D61
K61
N62
PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
JTAG
<30,36>
H_PROCHOT#
RC67
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC115
1 RC68
SM_RCOMP0
120_0402_1%
1 RC69
SM_RCOMP1
100_0402_1%
1 RC70
SM_RCOMP2
H_PROCHOT#_R
56_0402_5%
K63
H_CPUPWRGD
C61
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR3 COMPENSATION SIGNALS

200_0402_1%
<17>
DDR3_DRAMRST#_CPU
<17> DDR_PG_CTRL
AU60
AV60
AU61
AV15
AV61
PROCHOT
PROCPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
THERMAL
J62
K62
E60
E61
E59
F63
F62
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
J60
H60
H61
H62
K59
H63
K60
J61
XDP_OBS0_R
XDP_OBS1_R
PU/PD for JTAG signals

1
PCH_JTAG_RST#
PCH_JTAG_RST#
@
R2341
0_0402_5%
<8>
XDP_TMS
XDP_TDI
XDP_PREQ#
TDO_XDP
1
2
3
4
XDP_TDO
XDP_TCK
XDP_TRST#
1
2
3
4
+1.05VS
8
7
6
5
PWR
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
DDR3
RC141 1
@
@
@
@
@
@
2 0_0402_5%
RP44 @
51_8P4R_5%
T111
T112
T113
T114
T115
T116
8
7
6
5
RP45
51_8P4R_5%
Rev1p2
2 OF 19
A
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
5
Title
MCP(1,2/19) eDP,XDP,MISC
Size
Docum ent Num ber
Rev
0.2
LA-9981P
Date:
Sheet
1
of
55
<17>
DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
HASWELL_MCP_E
UC1C
<18>
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
DDR CHANNEL A
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
AU43
AW43
AY42
AY43
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
AP33
AR32
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
<17>
<17>
<17>
<17>
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
<17>
<17>
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
<17>
<17>
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
AU35
AV35
AY41
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AP49
AR51
AP51
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
<17>
<17>
<17>
DDR_A_BS0
<17>
DDR_A_BS1
<17>
DDR_A_BS2
<17>
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AP32
AY34
AW34
AU34
HASWELL_MCP_E
UC1D
DDR_B_D[0..63]
<17>
<17>
<17>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
DDR CHANNEL B
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
AY49
AU50
AW49
AV50
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
AM32
AK32
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
<18>
<18>
<18>
<18>
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
<18>
<18>
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
<18>
<18>
AL32
AM35
AK35
AM33
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
AL35
AM36
AU49
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
<18>
<18>
<18>
DDR_B_BS0
<18>
DDR_B_BS1
<18>
DDR_B_BS2
<18>
DDR_B_MA[0..15]
<18>
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
<18>
<18>
RC18
2.2_0402_1%
RC21
1.82K_0402_1%
change 22nF
CC9
0.022U_0402_16V7K
RC22
1.82K_0402_1%
change 22nF
RC24
24.9_0402_1%~D
RC19
2.2_0402_1%
CC10
0.022U_0402_16V7K
change 22nF
RC25
24.9_0402_1%~D
RC23
24.9_0402_1%~D
+SM_VREF_DQ0
RC20
1.82K_0402_1%
CC8
0.022U_0402_16V7K
RC17
2.2_0402_1%
RC16
1.82K_0402_1%
+SM_VREF_DQ0_DIMM1
+SM_VREF_DQ1
RC15
1.82K_0402_1%
+SM_VREF_DQ1_DIMM2
+SM_VREF_CA
RC14
1.82K_0402_1%
Rev1p2
+1.35V
+1.35V
+1.35V
+SM_VREF_CA_DIMM
4 OF 19
Rev1p2
3 OF 19
confirm by intel request PDG P141
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(3,4/19) DDR3
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
of
55
+RTCVCC
RTC Battery
RC1
330K_0402_1%
+RTCBATT
PCH_INTVRMEN
RC2
330K_0402_1%
JP12
+CHGRTC
W=20mils
@ RC3
PCH_AZ_SDOUT
1K_0402_5%
JUMP_43X39
INTVRMEN - INTEGRATED SUS 1.05V VRM

ENABLE
High - Enable Internal VRs
Low - Enable External VRs
For GCLK
+RTCVCC
1
+3VS
+3VLP
DC1
BAT54CW_SOT323-3
W=20mils
RC10
1K_0402_5%
+CHGRTC
W=20mils
CC26
1U_0603_10V6K
<29>
FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT)
HIGH = ENABLED
PCH_RTCX1
PCH_RTCX1
2
CC1
2
1
PCH_RTCX1
XTAL@
RC4
10M_0402_5%
1
1
C
+RTCVCC
RC5
RC6
PCH_RTCX2
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
2
1M_0402_5%
1
1
2
2
20K_0402_5%
20K_0402_5%
AW5
AY5
AU6
AV7
AV6
AU7
RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
RTC
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
1
@
ME1
@
CMOS1
SHORT PADS~D
1
CC3
1U_0402_6.3V6K
<22>
SHORT PADS~D
CC4
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_CODEC_SDIN0
<30>
ME_EN
RC8
PCH_AZ_SDOUT
1K_0402_5%
1U_0402_6.3V6K
AW8
AV11
AU8
AY10
AU12
AU11
AW10
AV10
AY8
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
AUDIO
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
CMOS place near DIMM

<6>
<6>
<6>
<6>
<6>
<6>
PCH_JTAG_RST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_JTAGX
PCH_JTAG_RST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_JTAGX
AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD
RSVD
JTAGX
RSVD
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
JTAG
J8
H8
A17
B17
J6
H6
B14
C15
SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C
SATA_PTX_DRX_N0_C
SATA_PTX_DRX_P0_C
<32>
<32>
<32>
<32>
SATA HDD
SATA_PRX_DTX_N1_C
SATA_PRX_DTX_P1_C
SATA_PTX_DRX_N1_C
SATA_PTX_DRX_P1_C
<32>
<32>
<32>
<32>
SATA ODD
PCH Rx side need use strap pin to update PCIE +/+3VS
F5
E5
C17
D17
RC107
10K_0402_5%
V1
U1
V6
AC1
EC_SMI#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37
A12
L11
K10
C12
U3
SATA_IREF
RC126
SATA_RCOMP
SATA_ACT#
RC131
EC_SMI#
ODD_DETECT#
SATA_ACT#
<30>
+1.05VS_ASATA3PLL
<32>
2 0_0603_5%
2 3.01K_0402_1%
<26>
SATA Impedance Compensation
within 500 mils

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
reference FFRD sch 0.5
5 OF 19
B
J5
H5
B15
A15
CC2
XTAL@
15P_0402_50V8J
RC7
HASWELL_MCP_E
UC1E
XTAL@
YC1
32.768KHZ_12.5PF_Q13FC1350000
15P_0402_50V8J
XTAL@
Rev1p2
B
+1.05VS
@
RC130
PCH_JTAG_JTAGX
1K_0402_1%
@
RC135
PCH_JTAG_TCK
51_0402_1%
CMOS_CLR1
Shunt
+1.05VS
1
2
3
4
8
7
6
5
+3VS
HDA for Codec

CMOS setting
Clear CMOS
Open
Keep CMOS
ME_CLR1
TPM setting
Shunt
Clear ME RTC Registers
Open
Keep ME RTC Registers
<22>
PCH_AZ_CODEC_SDOUT
<22>
PCH_AZ_CODEC_SYNC
<22>
<22>
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_BITCLK
EMI@ R2356
2 33_0402_5%
PCH_AZ_SDOUT
EMI@ R2357
2 33_0402_5%
PCH_AZ_SYNC
EMI@ R2358
2 33_0402_5%
PCH_AZ_RST#
EMI@ R2359
2 33_0402_5%
PCH_AZ_BITCLK
ODD_DETECT#
PCH_GPIO35
PCH_GPIO37
1
2
3
4
8
7
6
5
RP37
10K_8P4R_5%
1 @EMI@
CC5
27P_0402_50V8J
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
RP48
51_8P4R_5%
EMI depop location
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(5/19) RTC,SATA,HDA,JTAG
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
of
55
MEM Bus : DDR/XDP/WLAN/TP
+3VALW_PCH
+3VS
PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_WP#
PCH_SPI_HOLD#
C-LINK
2
SPI
CL_CLK
CL_DATA
CL_RST
@
@
@
<30>
<17,18,19,26,27,6>
<17,18,19,26,27,6>
QC1B
DMN66D0LDW-7_SOT363-6
5
PCH_HOT#
MEM_SMBCLK
SML0CLK
SML0DATA
PCH_HOT#
SML1_SMBCLK
SML1_SMBDATA
AF2
AD2
AF4
R2332
10K_0402_5%
8
7
6
5
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
1
2
3
4
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
R2331
10K_0402_5%
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
MEM_SMBDATA
T97
T98
T99
4
S
PCH_SPI_CLK
PCH_SPI_CS0#
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_WP1#
PCH_SPI_HOLD1#
SMBUS
EMI@
R2333
2 15_0402_1%
RP39
LPC
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74
@EMI@
C2326
68P_0402_50V8J
LAD0
LAD1
LAD2
LAD3
LFRAME
EMI
PCH_SPI_CLK_R
+3VS
HASWELL_MCP_E
UC1G
AU14
AW12
AY12
AW11
AV12
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
R2330
10K_0402_5%
R2329
10K_0402_5%
<30> LPC_LAD0
<30> LPC_LAD1
<30> LPC_LAD2
<30> LPC_LAD3
<30> LPC_LFRAME#
QC1A
15_8P4R_5%
+3VS
R2334 1
R2335 1
2 1K_0402_1%
2 1K_0402_1%
7 OF 19
Rev1p2
SML1 Bus : EC/Sensors

C
+3VALW_PCH
+3VS
QH1B
CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
8
7
6
5
PCH_SPI_HOLD1#
PCH_SPI_CLK_R
PCH_SPI_MOSI_1
SML1_SMBDATA
3
S
1
2
3
4
SML1_SMBCLK
8
7
6
5
EC_SMB_CK2
<19,30,49>
EC_SMB_DA2
<19,30,49>
U2302
PCH_SPI_CS0#
PCH_SPI_MISO_1
PCH_SPI_WP1#
1
2
3
4
RP40
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
2.2K_0804_8P4R_5%
SPI ROM ( 8MByte )
+3VALW_PCH
C2327
0.1U_0402_10V7K
QH1A
64M EN25Q64-104HIP SOP 8P

RP49
SML0CLK
SML0DATA
PN : SA000046400 ,64M,EN25Q64-104HIP
1
2
3
4
8
7
6
5
1K_0804_8P4R_5%
PAD~D
PAD~D
PAD~D
PAD~D
T183
T184
T185
T186
For GCLK
@
@
@
@
<29>
HASWELL_MCP_E
UC1F
RC12
1M_0402_5%
XTAL24_IN
XTAL24_IN
CC6
15P_0402_50V8J
Place T183, T184, T185, T186 close to

PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_CLK_R
PCH_SPI_CS0#
near U2302
C43
C42
U2
B41
A41
Y5
10/100 LAN ------->
<21> CLK_PCIE_LAN#
<21> CLK_PCIE_LAN
<21> LAN_CLKREQ#
WLAN(Mini Card)--->
<26> CLK_PCIE_WLAN#
<26> CLK_PCIE_WLAN
<26> WLAN_CLKREQ#
dGPU--->
<48> CLK_PEG_VGA#
<48> CLK_PEG_VGA
<49> PEG_CLKREQ#
CLK_PCIE_LAN#
CLK_PCIE_LAN
C41
B42
AD1
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
B38
C37
N1
A39
B39
U5
CLK_PEG_VGA#
CLK_PEG_VGA
B37
A37
T2
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
CLOCK
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
SIGNALS
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
A25
B25
K21
M21
C26
XTAL24_IN
XTAL24_OUT
CLK_BIASREF
AN15
AP15
8
7
6
5
CLKOUT_LPC0
XTAL@
+1.05VS_AXCK_LCPLL
10K_8P4R_5%
1
2
3
4
YC2
24MHZ_12PF_X3G024000DC1H
XTAL@
CC7
15P_0402_50V8J
RC13
3.01K_0402_1%
RP41
C35
C34
AK8
AL8
XTAL@
XTAL@
3
4
EC_SPI_MOSI_1
EC_SPI_MISO_1
EC_SPI_CLK_R
EC_SPI_CS0#
1
2
<30>
<30>
<30>
<30>
EC_SPI_MOSI_1
EC_SPI_MISO_1
EC_SPI_CLK_R
EC_SPI_CS0#
EMI@
R2336
22_0402_5%
B35
A35
CLK_PCI_LPC
<30>
CLK_CPU_ITP#
CLK_CPU_ITP
<6>
<6>
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
6 OF 19
+3VS
Rev1p2
RP42
1
2
3
4
8
7
6
5
10K_8P4R_5%
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(6,7/19) CLK,SMB,SPI,LPC
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
of
55
+3VS
+3VALW_PCH
@ CC11
ME_SUS_PWR_ACK
10K_0402_5%
2 SUSACK#
10K_0402_5%
2 SUS_STAT#/LPCPD#
10K_0402_5%
@ RC28
1
@ RC29
PCH_PLTRST#
PCH_BATLOW#
8.2K_0402_5%
AC_PRESENT
10K_0402_5%
2 PCIE_WAKE#_R
10K_0402_5%
RC32
1
RC34
PCH_DPWROK
PCH_RSMRST#_R
0_0402_5%
SUSACK#
0_0402_5%
RC33
ME_SUS_PWR_ACK_R
RC35
1
@
CLKRUN#
8.2K_0402_5%
OUT
PLT_RST#
PLT_RST#
UC3
MC74VHC1G08DFT2G_SC70-5
<21,26,30,48,6>
R159
100K_0402_5%
DSWODVREN - On Die DSW VR Enable

HEnable(DEFAULT)
LDisable
Note: SUSACK# and SUSWARN# can be tied together if

EC does not want to involve in the handshake mechanism
for the Deep Sleep state entry and exit
CAN be NC ,if not support Deep Sx
+3VS
RC36
IN2
IN1
+3VALW_PCH
RC31
0.1U_0402_10V7K
RC27
VCC
GND
DSWODVREN - ON DIE DSW VR ENABLE
+RTCVCC
DPWROK: Tired toghter with RSMRST#

that do not support Deep Sx
HASWELL_MCP_E
UC1H
HIGH = ENABLED (DEFAULT)

R2337 1
R2338 1
2 330K_0402_5%
2 330K_0402_5%
LOW = DISABLED
SYSTEM POWER MANAGEMENT
<30>
<30,6>
<30>
SUSACK#
SUSACK#
SYS_PWROK
SYS_PWROK
PCH_PWROK
<30>
ACIN
1
<6>
1
2
3
4
8
7
6
5
<30,6>
DH1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
PBTN_OUT#
RB751V-40_SOD323-2
<30>
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK_R
PM_APWROK_R
PCH_PLTRST#
SYS_RESET#
RP50
0_8P4R_5%
RC41
1
1
RC42
<30> EC_RSMRST#
ME_SUS_PWR_ACK
<30,36,37,49>
RC37
SIO_SLP_S0#
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
PBTN_OUT#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
AK2
AC3
AG2
AY7
AB5
AG7
AW6
AV4
AL7
AJ8
AN4
AF3
AM5
SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST
AW7
AV5
AJ5
DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29
PCH_BATLOW# Need pull high to VCCDSW3_3

(If no deep Sx , connect to VCCSUS3_3)
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
8 OF 19
DSWODVREN
PCH_DPWROK
PCIE_WAKE#_R
V5
AG4
AE6
AP5
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
AJ6
AT4
AL5
AP4
AJ7
SIO_SLP_S4#
SIO_SLP_S3#
@
@
@
PCIE_WAKE#
@
RC97
0_0402_5%
PCH_DPWROK
PCIE_WAKE#
<30>
<21,30>
C
T102
PAD~D @
SIO_SLP_S5#
T103 PAD~D @
T104 PAD~D @
SIO_SLP_S4#
SIO_SLP_S3#
T105
T106
T107
<30>
<30>
<30>
Rev1p2
+3VS
HASWELL_MCP_E
UC1I
+3VS
RC73
RC74
RC75
RC76
RC77
DGPU_PWROK
10K_0402_5%
TOUCHPAD_INTR#
10K_0402_5%
EDP_BIA_PWM
10K_0402_5%
TOUCH_RST_N_GYRO_INT1
10K_0402_5%
DGPU_HOLD_RST#
10K_0402_5%
<19,6> EDP_BIA_PWM
<30> PANEL_BKLEN
EDP_BIA_PWM
<19,30>
ENVDD_PCH
<30,44> DGPU_PWROK
<11,39,43,44,50>
PXS_PWREN
<48> DGPU_HOLD_RST#
EDP_BKLCTL
PANEL_BKLEN
ENVDD_PCH
DGPU_PWROK
PXS_PWREN
DGPU_HOLD_RST#
T117
@ RC87
@ RC88
TOUCHPAD_INTR#
TOUCH_RST_N_GYRO_INT1
ENVDD_PCH
100K_0402_5%
CODEC_IRQ
1K_0402_1%
CODEC_IRQ
B8
A9
C6
U6
P4
N4
N2
AD4
U7
L1
L3
R5
L4
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
1
2
3
4
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
@
RC81
0_0402_1%
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
eDP SIDEBAND
DISPLAY
GPIO
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
B9
C9
D9
D11
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
C5
B6
B5
A6
CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
C8
A8
D6
DPB_HPD
DPC_HPD
CPU_EDP_HPD#
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
RP52
2.2K_8P4R_5%
<20>
<20>
1
2
3
4
CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
DPC_HPD
DPB_HPD
<20>
+VCCIOA_OUT
Rev1p2
8
7
6
5
RP51
100K_8P4R_5%
eDP HPD INVERSION

9 OF 19
8
7
6
5
RC84
100K_0402_5%
RC78
10K_0402_5%
CPU_EDP_HPD#
2
1
CPU_EDP_HPD#
RC89
100K_0402_5%
D
<19>
EDP_CPU_HPD
QC3
@
2N7002K_SOT23-3
symbol OK
RC105
EDP_CPU_HPD
0_0402_5%
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
Reserve for debug

2014/04/01
5
CPU_EDP_HPD#
Title
MCP(8,9/19) DDI,EDP,GPIO
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
10
of
55
+1.05VS
HASWELL_MCP_E
UC1J
R2346
1K_0402_5%
WL_OFF#
+3VS
RC11
DEVSLP0
10K_0402_5%
SIO_EXT_SCI#
100K_0402_5%
HDD_DET#
100K_0402_5%
RC98
RC9
@ T174 PAD~D
@ T124 PAD~D
@ T125 PAD~D
@ T126 PAD~D
@ T127 PAD~D
PCH_GPIO9
EC_SCI#
DEVSLP0
<30> EC_SCI#
<32> DEVSLP0
<22>
SIO_EXT_SCI#
HDA_SPKR
HDA_SPKR
AM3
AM2
P2
C4
L2
N5
V2
LPIO
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
RC110
RC116
KB_DET#
10K_0402_5%
PCH_GPIO44
10K_0402_5%
SLATE_MODE_R
10K_0402_5%
PCH_AUDIO_EN
10K_0402_5%
+3VS
+3VS
PCH_GPIO66
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
T178 @
T179 @
PAD~D
PAD~D
T180 @
T181 @
+3VS
1
SUN@
RC112
10K_0402_5%
T177 @
T176 @
T175 @
UMA@
RC100
10K_0402_5%
VENUS@
RC113
10K_0402_5%
DIS@
RC99
10K_0402_5%
SERIRQ
10K_0402_5%
LCD_CBL_DET#
10K_0402_5%
CPPE#
100K_0402_5%
CPUSB#
100K_0402_5%
RC102
RC106
RC108
RC111
RP53
LCD_CBL_DET#
I2C1_SDA_TCH_PAD
I2C1_SCL_TCH_PAD
I2C0_SDA
I2C0_SCL
1
2
3
4
KB_RST#
TOUCH_PANEL_INTR#
8
7
6
5
I2C0_SDA
I2C0_SCL
I2C1_SDA_TCH_PAD
I2C1_SCL_TCH_PAD
8
7
6
5
2.2K_0804_8P4R_5%
RP43
PCH_GPIO66
+3VALW_PCH
BBS_BIT
1
2
3
4
10K_8P4R_5%
+3VS
@
RC121
1K_0402_5%
@
RC120
1K_0402_5%
RC123
1K_0402_5%
@
RC122
1K_0402_5%
HOST_ALERT1_R_N
HDA_SPKR
+3VS
PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
BBS_BIT
DGPU_PRSNT#
Project_ID
PCH_GPIO89
PCH_GPIO90
CPPE#
CPUSB#
PCH_GPIO93
PCH_GPIO94
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
Rev1p2
@
RC119
10K_0402_5%
@
RC118
1K_0402_5%
+3VS
+3VS
<30>
<30>
2
RC104
10 OF 19
RC103
KB_RST#
SERIRQ
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
GPIO
+3VALW_PCH
RC101
49.9_0402_1%
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
H_THERMTRIP#
KB_RST#
SERIRQ
PCH_OPI_COMP
<26>
AG6
AP1
AL4
SLATE_MODE_R
AT5
WL_OFF#
AK4
PCH_GPIO44
AB6
PCH_GPIO47
U4
PCH_GPIO48
Y3
PCH_GPIO49
TOUCH_PANEL_INTR# P3
Y2
AT3
AH4
PCH_GPIO14
AM4
PCH_GPIO25
AG5
AG3
PCH_GPIO46
HDD_DET#
D60
V4
T4
AW15
AF20
AB21
HDD_DET#
THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
CPU/
MISC
<32>
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
"KB_DET#" for OAK 17 only
P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
PCH_GPIO12
EC_LID_OUT#
ODD_EN#
ODD_DA#
BT_ON#
KB_DET#
HOST_ALERT1_R_N
PCH_AUDIO_EN
@ T182 PAD~D
<30> EC_LID_OUT#
<32> ODD_EN#
<32> ODD_DA#
<26> BT_ON#
KB_DET#
RP54
8
7
6
5
1
2
3
4
ODD_DA#
BT_ON#
WL_OFF#
PXS_PWREN
GPIO66
PXS_PWREN
<10,39,43,44,50>
8.2K_8P4R_5%
GPIO86
GPIO15
GPIO81
TOP-BLOCK SWAP OVERRIDE
BOOT BIOS STRAP BIT BBS
TLS CONFIDENTIALITY
NO REBOOT STRAP
HIGH depop RC288 (DEFAULT)

LOW pop RC288
HIGH
LOW(DEFAULT)
HIGH
LOW(DEFAULT)
HIGH
LOW(DEFAULT)
LPC
SPI
GPIO15 NOT Used

+3VALW_PCH
+3VALW_PCH
RC125
10K_0402_5%
RC124
10K_0402_5%
PCH_GPIO46
PCH_GPIO9
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(10/19) GPIO,LPIO,MISC
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
11
of
55
HASWELL_MCP_E
UC1K
<48>
<48>
<48>
<48>
<48>
<48>
<48>
<48>
<48>
<48>
<48>
<48>
C
10/100 LAN
<21>
<21>
<21>
<21>
WLAN (Mini Card)
<26>
<26>
<26>
<26>
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
PCIE_PRX_LANTX_N3
PCIE_PRX_LANTX_P3
PCIE_PTX_LANRX_N3
PCIE_PTX_LANRX_P3
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
F10
E10
PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
DIS@
DIS@
CC18 2
CC19 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_P0
F8
E8
PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
DIS@
DIS@
CC20 2
CC21 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_P1
DIS@
DIS@
CC22 2
CC23 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_P2
DIS@
DIS@
CC24 2
CC25 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_P3
B22
A21
G11
F11
PCIE_PRX_LANTX_N3
PCIE_PRX_LANTX_P3
PCIE_PTX_LANRX_N3
PCIE_PTX_LANRX_P3
B21
C21
E6
F6
PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
B23
A23
H10
G10
PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
C23
C22
CC32 1
CC40 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_PTX_LANRX_N3_C
PCIE_PTX_LANRX_P3_C
C29
B30
F13
G13
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
B29
A29
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
G17
F17
C30
C31
F15
G15
B31
A31
RC91
3.01K_0402_1%
+1.05VS_AUSB3PLL
@ T120PAD~D
@ T121PAD~D
PCH_PCIE_RCOMP
E15
E13
A27
B27
PERN5_L0
PERP5_L0
USB2N0
USB2P0
PETN5_L0
PETP5_L0
USB2N1
USB2P1
PERN5_L1
PERP5_L1
USB2N2
USB2P2
PETN5_L1
PETP5_L1
USB2N3
USB2P3
PERN5_L2
PERP5_L2
USB2N4
USB2P4
PETN5_L2
PETP5_L2
USB2N5
USB2P5
PERN5_L3
PERP5_L3
USB2N6
USB2P6
PETN5_L3
PETP5_L3
USB2N7
USB2P7
PERN3
PERP3
PETN3
PETP3
USB3RN1
USB3RP1
USB
PCIe
USB3TN1
USB3TP1
PERN4
PERP4
USB3RN2
USB3RP2
PETN4
PETP4
USB3TN2
USB3TP2
AN8
AM8
USB20_JUSB2_N0
USB20_JUSB2_P0
AR7
AT7
USB20_JUSB1_N1
USB20_JUSB1_P1
AR8
AP8
USB20_JUSB3_N2
USB20_JUSB3_P2
AR10
AT10
USB20_USBDB_N3
USB20_USBDB_P3
AM15
AL15
USB20_MINI1_N4
USB20_MINI1_P4
AM13
AN13
USB20_TOUCH_N5
USB20_TOUCH_P5
AP11
AN11
USB20_CR_N6
USB20_CR_P6
AR13
AP13
USB20_CAM_N7
USB20_CAM_P7
G20
H20
USB3RN1_JUSB2
USB3RP1_JUSB2
USB20_JUSB2_N0
USB20_JUSB2_P0
<24>
<24>
USB Conn JUSB2
USB20_JUSB1_N1
USB20_JUSB1_P1
<24>
<24>
USB Conn JUSB1
USB20_JUSB3_N2
USB20_JUSB3_P2
<25>
<25>
USB Conn JUSB3
USB20_USBDB_N3
USB20_USBDB_P3
<25>
<25>
USB20_MINI1_N4
USB20_MINI1_P4
USB20_TOUCH_N5
USB20_TOUCH_P5
USB20_CR_N6
USB20_CR_P6
USB Conn 4 (DB)
<26>
<26>
Mini Card (WLAN)
<31>
<31>
<23>
<23>
USB20_CAM_N7
USB20_CAM_P7
<31>
<31>
USB3RN1_JUSB2
USB3RP1_JUSB2
<24>
<24>
Touch screen panel
"USB20_TOUCH_N5/USB20_TOUCH_P5"
for OAK 15 only
Card Reader
Camera
C
C33
B34
USB3TN1_JUSB2
USB3TP1_JUSB2
E18
F18
USB3RN2_JUSB1
USB3RP2_JUSB1
B33
A33
USB3TN2_JUSB1
USB3TP2_JUSB1
AJ10
AJ11
AN10
AM10
USBRBIAS
USB3TN1_JUSB2
USB3TP1_JUSB2
<24>
<24>
USB3RN2_JUSB1
USB3RP2_JUSB1
<24>
<24>
USB3TN2_JUSB1
USB3TP2_JUSB1
<24>
<24>
USB Conn JUSB2
USB Conn JUSB1
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
USBRBIAS
USBRBIAS
RSVD
RSVD
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
11 OF 19
PAD~D
PAD~D
T118 @
T119 @
<48>
<48>
PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
RC90
22.6_0402_1%~D
AL3 USB_OC0#
AT1 USB_OC1#
AH2 USB_OC2#
AV3 USB_OC3#
USB_OC0#
USB_OC1#
<24>
<25>
<48>
<48>
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
Rev1p2
+3VALW_PCH
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
1
2
3
4
8
7
6
5
RP55
10K_8P4R_5%
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(11/19) PCIE,USB
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
12
of
55
+1.35V
+CPU_CORE
C40
1
D
+1.35V
ESD solution
L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
R286
10K_0402_5%
<30>
VCCST_PG_EC
VCCST_PG_EC
Define EC OD pin, need double confirm.
+VCCIO_OUT
+CPU_CORE
F59
N58
AC58
VCCSENSE
R245 @
0_0603_5%
T38
+VCCIO_OUT_R
+VCCIOA_OUT
SVID ALERT
+1.05VS
<42>
Place the PU
resistors close to CPU
R252
75_0402_5%
<42>
R254
43_0402_1%
VR_SVID_ALRT#
VR_SVID_CLK
<30,42> VR_ON
<42> H_VR_READY
<6>
H_CPU_SVIDALRT#
SVID DATA
SVID_DAT need to pull-up double side

( PWR_VR & CPU )
VR_SVID_DAT
2 R248
1
1
2 R250
2 R251
CPU_PWR_DEBUG#
T39
T40
T41
T42
T43
T44
T45
T46
T47
T48
T49
T50
T51
H_CPU_SVIDCLK
2
+1.05VS
@
@
@
@
@
@
@
@
@
@
@
@
@
H_CPU_SVIDDATA
AB57
AD57
AG57
C24
C28
C32
@
R253
150_0402_1%
2
1
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
12 OF 19
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
HSW ULT POWER
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
C74
10U_0603_6.3V6M
C45
10U_0603_6.3V6M
C42
10U_0603_6.3V6M
C72
10U_0603_6.3V6M
C41
10U_0603_6.3V6M
C39
10U_0603_6.3V6M
CAD Note: PD resistor on HW side
+1.35V : 470UF/2V/7343 *2 (PWR)

10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
VSSSENSE
C38
2.2U_0402_6.3V6M
VSSSENSE
C37
2.2U_0402_6.3V6M
<15,42>
C36
2.2U_0402_6.3V6M
VCCSENSE
C35
2.2U_0402_6.3V6M
<42>
VCC
RSVD
RSVD
VDDQ DECOUPLING
@
R255
10K_0402_5%
CAD Note: PU resistor on HW side
VCCSENSE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
+1.35V
R1
100_0402_1%
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Rev1p2
CPU_PWR_DEBUG#
+CPU_CORE
RSVD
RSVD
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
R253
INTEL Check list , XDP use only
+1.05VS
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
AC22
AE22
AE23
+CPU_CORE
L62
N63
L63
B59
F60
C59
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDATA
VCCST_PG_EC
VR12.5_VR_ON_R
VR_READY_R
R256
130_0402_1%
@
R257
0_0402_1%
<42>
RF@
C5212
68P_0402_50V8J
Place the PU
resistors close to CPU
0_0402_5%
0_0402_5%
CPU_PWR_DEBUG#
RF
+1.05VS
0_0402_5%
E63
AB23
A59
E20
AD23
AA23
AE59
+CPU_CORE
HASWELL_MCP_E
UC1L
22U_0603_6.3V6M
ESD@
+1.05VS
R2
100_0402_1%
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(12/19) Power
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet

1
13
of
55
Close to N8
C57 @1
+1.05VS
2 1U_0402_6.3V6K
+RTCVCC
C58
C59
1
1
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
HASWELL_MCP_E
UC1M
+1.05VS_ASATA3PLL
L21
C63
C65
1
1
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
+1.05VS
+1.05VS_AUSB3PLL
+1.05VS_ASATA3PLL
+1.05VS_APLLOPI
R267
0_0805_5%
K9
L10
M9
N8
P9
B18
B11
+1.05VS
2
1
@1
C69
C70
2
L31
@
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
Y20
AA21
W21
+1.05VS_APLLOPI
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
VCCSUS3_3
VCCRTC
DCPRTC
RTC
VCCSPI
OPI
VCCASW
VCCASW
1
1
C83
C84
L4 1
2
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
T55
1
1
C85
C86
2 1U_0402_6.3V6K
2 100U_1206_6.3V6M
+3VALW_PCH
+3VS
J13
AH14
+VCCHDA
+1.05VS_AXCK_LCPLL
2
L5 1
AH13
AC9
AA9
AH10
V8
W9
DCPSUS3
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
AXALIA/HDA
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VRM/USB2/AZALIA
CORE
GPIO/LCC
THERMAL SENSOR
+1.5VS
+3VS
+3VALW_PCH
+VCCHDA
RC127
RC128
RC129
C77
+VCCHDA
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
+1.05VS_AXCK_DCB
+1.05VS_AXCK_LCPLL
+1.05VS
+1.05VS
2 0.1U_0402_10V7K
Reserve for HDA issue, C77 close to AH14
+3VALW_PCH
J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
C50
C53
+3VALW_PCH
1
1
C81 1
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
2 0.1U_0402_10V7K
@
+3VALW_PCH
+RTCVCC
C52 1
+VCCRTCEXT
Y8
C68 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
AG14
AG13
VCCSDIO
VCCSDIO
+1.05VS
+1.05VS
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
C60
C61
C62
1
1
1
2 10U_0603_6.3V6M
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
1
R265
C66
C67
1
1
+PCH_VCCDSW_R
0_0402_5%
2 22U_0603_6.3V6M
2 1U_0402_6.3V6K
ESD solution
+1.05VS
+1.05VS
T58 @
T59 @
C71 1
22U_0603_6.3V6M
ESD@
C64
1U_0402_6.3V6K
+PCH_VCCDSW
+3VS
C44
+1.05VS
+1.35V
C43
2 0.1U_0402_10V7K
22U_0603_6.3V6M
ESD@
+1.5VS
+3VS
ESD solution
U8
T9
C73
1U_0402_6.3V6K
+3VS
LPT LP POWER
SUS OSCILLATOR
USB2
DCPSUS4
RSVD
VCC1_05
VCC1_05
AB8
T56 @
AC20
AG16
AG17
+1.05VS
C76
1U_0402_6.3V6K
Rev1p2
2 22U_0603_6.3V6M
Close to AC9/AA9/AE20/AE21
C82
2 22U_0603_6.3V6M
Close to V8
+1.05VS
C87
2 1U_0402_6.3V6K
Close to J17
+1.05VS
C88
2 1U_0402_6.3V6K
Close to R21
C75
1 0.1U_0402_10V7K
Close to AH14
+3VALW_PCH
1 R264
2 1U_0402_6.3V6K
Close to AH10
+3VS
Close to K9,M9
C78
+3VALW_PCH
VCCTS1_5
VCC3_3
VCC3_3
SDIO/PLSS
13 OF 19
+1.05VS
C51
USB3
VCCHDA
DCPSUS2
AH11
AG10
AE7
+3VS
SPI
+1.05VS_AXCK_DCB
T53
0_0603_5%
mPHY
0.1U_0402_10V7K
C56
0.1U_0402_10V7K
C55
+1.05VS_AUSB3PLL
L11
1U_0402_6.3V6K
C54
+1.05VS
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(13/19) Power
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
14
of
55
UC1O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 OF 19
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HASWELL_MCP_E
15 OF 19 Rev1p2
UC1P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
16 OF 19 Rev1p2 VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
VSSSENSE
<13,42>
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X@
RC163
100_0402_1%
UC1N
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
CAD Note: RC163 SHOULD BE PLACED CLOSE TO CPU
Rev1p2
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(14,15,16/19) VSS
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
15
of
55
HASWELL_MCP_E
UC1Q
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
@ T166PAD~D
@ T167PAD~D
DC_TEST_B62_B63
DC_TEST_C1_C2
AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2
DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
HASWELL_MCP_E
UC1R
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
17 OF 19 Rev1p2 DAISY_CHAIN_NCTF_AW63
A3
A4
DC_TEST_A3_B3
DC_TEST_A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A62
DC_TEST_AV1
DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
DC_TEST_AW63
RSVD
RSVD
RSVD
RSVD
PAD~D T168 @
PAD~D T169 @
PAD~D T170 @
PAD~D T171 @
PAD~D T172 @
@
T128 PAD~D
@
T132 PAD~D
@
T134 PAD~D
@
T135 PAD~D
RSVD_AT2
RSVD_AU44
RSVD_AV44
RSVD_D15
@
T138 PAD~D
@
T140 PAD~D
@
T143 PAD~D
RSVD_F22
RSVD_H22
RSVD_J21
AT2
AU44
AV44
D15
F22
H22
J21
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PAD~D T173 @
18 OF 19
N23
R23
T23
U10
RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10
PAD~D
PAD~D
PAD~D
PAD~D
@
T129
@
T130
@
T131
@
T133
AL1
AM11
AP7
AU10
AU15
AW14
AY14
RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
T136
T137
T139
T141
T142
T144
T145
@
@
@
@
@
@
@
Rev1p2
UC1S
HASWELL_MCP_E
CFG STRAPS for CPU
<6>
<6>
<6>
<6>
CFG16
CFG18
CFG17
CFG19
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
CFG16
CFG18
CFG17
CFG19
AA62
U63
AA61
U62
CFG_RCOMP
V63
@ T159PAD~D
A5
@ T161PAD~D
@ T163PAD~D
@ T164PAD~D
@ T165PAD~D
TDI_IREF
E1
D1
J20
H18
B12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RESERVED
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
CFG16
CFG18
CFG17
CFG19
RSVD
RSVD
CFG_RCOMP
VSS
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
19 OF 19
RC132
RC133
RSVD_TP
CFG_RCOMP
49.9_0402_1%
TDI_IREF
8.2K_0402_1%
AV63
AU63
PAD~D T146 @
PAD~D T147 @
C63
C62
B43
PAD~D T148 @
PAD~D T149 @
PAD~D T150 @
A51
B51
PAD~D T151 @
PAD~D T152 @
L60
PAD~D T153 @
N60
PAD~D T154 @
CFG4
W23
Y22
AY15
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
RC138
1K_0402_1%
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
PAD~D T155 @
PAD~D T156 @
Display Port Presence Strap
PROC_OPI_RCOMP
AV62
D58
PAD~D T157 @
PAD~D T158 @
1: Disabled; No Physical Display Port

attached to Embedded Display Port
0: Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
P22
N21
P20
R20
PAD~D T160 @
PAD~D T162 @
Rev1p2
PROC_OPI_RCOMP 1
49.9_0402_1%
2
RC134
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MCP(17,18,19/19) CFG,RSVD
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
16
of
55
+1.35V
+1.35V
DDR_A_DQS#3
DDR_A_DQS3
<7>
DDR_A_DQS#[0..7]
<7>
DDR_A_D[0..63]
<7>
DDR_A_DQS[0..7]
<7>
DDR_A_MA[0..15]
DDR_A_D30
DDR_A_D31
All VREF traces should

have 10 mil trace width
DDR_A_D44
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
Layout Note:
Place near JDIMM1
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
+1.35V
CD11
1U_0402_6.3V6K
CD10
1U_0402_6.3V6K
CD9
1U_0402_6.3V6K
CD8
1U_0402_6.3V6K
CD7
1U_0402_6.3V6K
CD6
1U_0402_6.3V6K
CD5
1U_0402_6.3V6K
CD4
1U_0402_6.3V6K
<7>
DDR_CKE0_DIMMA
DDR_CKE0_DIMMA
<7>
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
+1.35V
<7>
<7>
CD15
330U_D3_2.5VY_R6M
CD14
10U_0603_6.3V6M
CD13
1@
10U_0603_6.3V6M
CD20
10U_0603_6.3V6M
CD19
10U_0603_6.3V6M
CD18
1@
10U_0603_6.3V6M
CD12
10U_0603_6.3V6M
CD17
10U_0603_6.3V6M
CD16
10U_0603_6.3V6M
<7>
DDR_A_BS0
<7>
<7>
DDR_A_WE#
DDR_A_CAS#
<7>
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_CS1_DIMMA#
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
+0.675VS
DDR_A_D36
DDR_A_D33
CD29
10U_0603_6.3V6M
CD28
10U_0603_6.3V6M
CD27
0.1U_0402_10V7K
CD26
0.1U_0402_10V7K
CD25
0.1U_0402_10V7K
CD24
0.1U_0402_10V7K
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
RD6 1
2 10K_0402_5%
+3VS
10K_0402_5%
CD31
0.1U_0402_10V7K
CD30
2.2U_0402_6.3V6M
RD7
+0.675VS
205
G1
G2
1
2
<18>
DDR3_DRAMRST#
DDR_A_D27
DDR_A_D26
DDR_A_D45
DDR_A_D40
DDR_A_D42
DDR_A_D46
DDR_A_D52
DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR3_DRAMRST#
DDR3_DRAMRST#_CPU
<6>
@
RD5
0_0402_1%
@
CD3
0.1U_0402_10V7K
CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN
DDR_A_D54
DDR_A_D55
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA
<7>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR3L SODIMM ODT GENERATION
<7>
<7>
+5VALW
<7>
<7>
DDR_CS0_DIMMA#
+1.35V
QD2
BSS138-G_SOT23-3
<7>
1
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D7
R2347
220K_0402_5%~D
+SM_VREF_CA_DIMM
CD22
0.1U_0402_10V7K
DDR_A_D2
DDR_A_D6
Layout Note:
Place near JDIMM1.203,204
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
RD3
470_0402_5%
DDR_A_D25
DDR_A_D24
CD21
DDR_A_DQS#0
DDR_A_DQS0
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDR_A_D15
DDR_A_D11
2.2U_0402_6.3V6M
DDR_A_D0
DDR_A_D1
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
+1.35V
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D29
DDR_A_D28
2-3A to 1 DIMMs/channel
DDR_A_D9
DDR_A_D12
DDR_A_D14
DDR_A_D10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
M_ODT0
66.5_0402_1%
2
M_ODT1
66.5_0402_1%
R2348
1
R2349
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
DDR_A_D13
DDR_A_D8
CONN@
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CD2
0.1U_0402_10V7K
Populate RD1, De-Populate RD7 for Intel DDR3

VREFDQ multiple methods M1
CD1
2.2U_0402_6.3V6M
@
RD1
0_0402_1%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
R2350
66.5_0402_1%
1
@
RD4
0_0402_1%
JDIMM1
H=4mm
+DIMM1_VREF_DQ
+SM_VREF_DQ0_DIMM1
R2352
@
R2351
2M_0402_5%
66.5_0402_1%
0.675V_DDR_VTT_ON
M_ODT2
<18>
M_ODT3
<18>
0.675V_DDR_VTT_ON
<41>
DDR_A_D18
DDR_A_D19
DDR_A_DQS#2
DDR_A_DQS2
+1.35V
DDR_A_D22
DDR_A_D23
@
CD23
0.1U_0402_10V7K
U2303
DDR_A_D37
DDR_A_D32
<6>
DDR_PG_CTRL
2
3
DDR_A_D35
DDR_A_D39
NC
VCC
A
Y
0.675V_DDR_VTT_ON
GND
74AUP1G07GW_TSSOP5
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D56
DDR_A_D57
<18,19,26,27,6,9>
<18,19,26,27,6,9>
+0.675VS
206
LCN_DAN06-K4406-0102
+1.35V
+3VS
CD62
22U_0603_6.3V6M
ESD@
Compal Secret Data
ESD solution
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
DDRIII DIMMA
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
17
of
55
H=4mm
+DIMM2_VREF_DQ
+1.35V
+1.35V
JDIMM2
+SM_VREF_DQ1_DIMM2

CD33
0.1U_0402_10V7K
CD32
2.2U_0402_6.3V6M
@
RD8
0_0402_1%
D
DDR_B_D8
DDR_B_D14
DDR_B_D10
DDR_B_D11
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
<7>
DDR_B_DQS#[0..7]
<7>
DDR_B_D[0..63]
DDR_B_D26
DDR_B_D27
All VREF traces should

have 10 mil trace width
<7>
DDR_B_DQS[0..7]
<7>
DDR_B_MA[0..15]
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
Layout Note:
Place near JDIMM2
DDR_B_D46
DDR_B_D42
DDR_B_D56
DDR_B_D57
DDR_B_D59
DDR_B_D58
+1.35V
CD42
1U_0402_6.3V6K
CD41
1U_0402_6.3V6K
CD40
1U_0402_6.3V6K
CD39
1U_0402_6.3V6K
CD38
1U_0402_6.3V6K
CD37
1U_0402_6.3V6K
CD36
1U_0402_6.3V6K
CD35
1U_0402_6.3V6K
1
C
<7>
DDR_CKE2_DIMMB
DDR_CKE2_DIMMB
<7>
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
+1.35V
<7>
<7>
1
+
CD51
330U_D3_2.5VY_R6M
CD50
10U_0603_6.3V6M
CD49
10U_0603_6.3V6M
CD48
10U_0603_6.3V6M
CD47
10U_0603_6.3V6M
CD46
10U_0603_6.3V6M
CD45
10U_0603_6.3V6M
CD44
10U_0603_6.3V6M
CD43
10U_0603_6.3V6M
<7>
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#2
<7>
DDR_B_BS0
<7>
<7>
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_CS3_DIMMB#
DDR_B_D3
DDR_B_D7
Layout Note:
Place near JDIMM2.203,204
DDR_B_D21
DDR_B_D20
DDR_B_D22
DDR_B_D23
DDR_B_D36
DDR_B_D33
+0.675VS
DDR_B_DQS#4
DDR_B_DQS4
CD59
10U_0603_6.3V6M
CD58
10U_0603_6.3V6M
CD57
0.1U_0402_10V7K
CD56
0.1U_0402_10V7K
CD55
0.1U_0402_10V7K
CD54
0.1U_0402_10V7K
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
DDR_B_D48
DDR_B_D53
+3VS
+3VS
+0.675VS
CD61
0.1U_0402_10V7K
CD60
2.2U_0402_6.3V6M
RD13
10K_0402_5%
10K_0402_5%
2
RD12
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
CONN@
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G1
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
2-3A to 1 DIMMs/channel
DDR_B_D12
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D13
DDR_B_D15
DDR_B_D25
DDR_B_D24
DDR3_DRAMRST#
DDR3_DRAMRST#
DDR_B_D30
DDR_B_D31
DDR_B_D45
DDR_B_D44
DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
<17>
@
CD34
0.1U_0402_10V7K
CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN
DDR_B_D63
DDR_B_D62
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB
<7>
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
<7>
<7>
<7>
<7>
DDR_CS2_DIMMB#
M_ODT2 <17>
M_ODT3
<7>
<17>
+SM_VREF_CA_DIMM
1
DDR_B_D5
DDR_B_D0
1
DDR_B_D2
DDR_B_D6
CD53
0.1U_0402_10V7K
DDR_B_DQS#0
DDR_B_DQS0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CD52
2.2U_0402_6.3V6M
DDR_B_D4
DDR_B_D1
2
@
RD10
0_0402_1%
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
<17,19,26,27,6,9>
<17,19,26,27,6,9>
+0.675VS
206
LCN_DAN06-K4406-0102
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
DDRIII DIMMB
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
18
of
55
+AVCC33
+3VS
+DVCC33
+3VS_RT
30mil
+SWR_V12
+SWR_V12
UX4
RX169
4.7K_0402_5%
@
RX171
4.7K_0402_5%
17
60 mils
15
SWR_VDD
DP_V33
SWR_LX
TXO2+
TXO2TXO3+
TXO3-
DP_V12
EDP_CPU_LANE_P0
EDP_CPU_LANE_N0
<6>
<6>
EDP_CPU_LANE_P1
EDP_CPU_LANE_N1
EDP_CPU_LANE_P0
EDP_CPU_LANE_N0
CX42
CX46
1
1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CPU_EDP_P0_C
CPU_EDP_N0_C
7
8
EDP_CPU_LANE_P1
EDP_CPU_LANE_N1
CX38
CX39
1
1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CPU_EDP_P1_C
CPU_EDP_N1_C
9
10
EDP_CPU_AUX
EDP_CPU_AUX#
EDP_CPU_AUX
EDP_CPU_AUX#
1
1
CX43
CX44
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CPU_EDP_AUX_C
CPU_EDP_AUX#_C
LANE1P
LANE1N
4
3
AUX-CH_P
AUX-CH_N
EDP_CPU_HPD
EDP_CPU_HPD
LANE0P
LANE0N
DP
<6>
<6>
35
36
LVDS_ACLK+
LVDS_ACLK-
41
42
LVDS_A0+
LVDS_A0-
39
40
LVDS_A1+
LVDS_A1-
37
38
LVDS_A2+
LVDS_A2-
LVDS_ACLK+
LVDS_ACLK-
<31>
<31>
LVDS_A0+
LVDS_A0-
<31>
<31>
LVDS_A1+
LVDS_A1-
<31>
<31>
LVDS_A2+
LVDS_A2-
<31>
<31>
33
34
TXE2+
TXE2-
DP_HPD
RX5
21
2
12
EDP_BIA_PWM
EDP_BIA_PWM
12K_0402_1%
48
47
MIIC_SCL
MIIC_SDA
EDP_CPU_AUX#
EDP_CPU_AUX
MODE_CFG1
MODE_CFG0
<17,18,26,27,6,9>
<17,18,26,27,6,9>
EDP_BIA_PWM
RX6
RX31
1
1
@
@
2 0_0402_5%
2 0_0402_5%
13
14
CSCL
CSDA
CIICSCL1
CIICSDA1
DP_GND
@ RX36
100K_0402_5%
MIICSCL1
MIICSDA1
PANEL_VCC
PWMOUT
BL_EN
GND
LVDS@
OTHERS
PWMIN
TESTMODE
DP_REXT
25
26
LVDS_BCLK+
LVDS_BCLK-
31
32
LVDS_B0+
LVDS_B0-
29
30
LVDS_B1+
LVDS_B1-
27
28
LVDS_B2+
LVDS_B2-
LVDS_BCLK+
LVDS_BCLK-
<31>
<31>
LVDS_B0+
LVDS_B0-
<31>
<31>
LVDS_B1+
LVDS_B1-
<31>
<31>
LVDS_B2+
LVDS_B2-
<31>
<31>
23
24
46
45
EDID_CLK
EDID_DATA
20
19
44
TL_ENVDD
TL_INVT_PWM
TL_BKOFF#_R
EDID_CLK
EDID_DATA
<31>
<31>
TL_ENVDD
<31>
TL_INVT_PWM
<31>
1
1
<10,6>
TXE0+
TXE0-
TXE3+
TXE3-
@ RX35
100K_0402_5%
RX25
100K_0402_5%
TXEC+
TXEC-
TXE1+
TXE1-
EDP_CPU_HPD
RX30
100K_0402_5%
TXO1+
TXO1-
VCCK
11
<10>
+3VS_RT
TXO0+
TXO0-
SWR_VCCK
43
ROMLESS
<6>
<6>
60 mils
TXOC+
TXOC-
PVCC
GND
PAD
6
RX33 LVDS@
100K_0402_5%
16
2
LVDS@
18
LVDS
40 mils
RX170
4.7K_0402_5%
+SWR_V12
MIIC_SCL
MIIC_SDA
ROMLESS
22
2
1
LX7
+DVCC33
FBMA-L11-201209-221LMA30T_0805
2
1
LVDS@ LX8
+AVCC33
FBMA-L11-201209-221LMA30T_0805
1
2
LVDS@ LX9
+SW_LX
4.7UH_PG031B-4R7MS_1.1A_20%
LVDS@
PWR
LVDS@
+3VS_RT
EEPROM
LVDS@
RTD2136R
@
RX168
4.7K_0402_5%
Close to 43 pin
+3VS_RT
+DVCC33
EEPROM
LVDS@
LVDS@
Close to 11 pin
CX32
0.1U_0402_10V7K
CX47
0.1U_0402_10V7K
LVDS@
CX37
Close to 22 pin
0.1U_0402_10V7K
@
RX4
0_0805_1%
Close to 15 pin
+3VS_RT
30mil
CX48 LVDS@
22U_0805_6.3V6M
LVDS@
Close to 18 pin
LVDS@
CX34
CX40
0.1U_0402_10V7K
Close to 5 pin
0.1U_0402_10V7K
CX36 LVDS@
LVDS@
CX41
22U_0805_6.3V6M
LVDS@
0.1U_0402_10V7K
CX45 LVDS@
10U_0603_6.3V6M
CX31
LVDS@
CX33
0.1U_0402_10V7K
0.1U_0402_10V7K
CX35 LVDS@
10U_0603_6.3V6M
49
RTD2136R-CG_QFN48_6x6
AUX termination
RTD2136S : SA00004NW10
RTD2136R : SA000067100
+3VS_RT
EC_SMB_DA2
EC_SMB_DA2
<30,49,9>
Vendor advise reserve it

G
6
D
CSDA
EC_SMB_CK2
CX10 LVDS@
0.1U_0402_10V7K
<30,49,9>
+3VS_RT
RX37 1 eDP@
2 0_0402_5%
EDP_AUX#
RX38 1 eDP@
2 0_0402_5%
LVDS_B0-
CPU_EDP_AUX_C
RX39 1 eDP@
2 0_0402_5%
EDP_AUX
RX40 1 eDP@
2 0_0402_5%
LVDS_B0+
CPU_EDP_P0_C
RX41 1 eDP@
2 0_0402_5%
EDP_P0
RX42 1 eDP@
2 0_0402_5%
LVDS_B1-
CPU_EDP_N0_C
RX43 1 eDP@
2 0_0402_5%
EDP_N0
RX44 1 eDP@
2 0_0402_5%
LVDS_B1+
CPU_EDP_P1_C
RX45 1 eDP@
2 0_0402_5%
EDP_P1
RX46 1 eDP@
2 0_0402_5%
LVDS_B2-
CPU_EDP_N1_C
RX47 1 eDP@
2 0_0402_5%
EDP_N1
RX48 1 eDP@
2 0_0402_5%
for layout smoothly,

will swap NET on cable
5
+DVCC33
<30>
BKOFF#
TL_BKOFF#_R
EDID_CLK
EDID_DATA
8
7
6
5
IN1
IN2
1
2
3
4
OUT
TL_BKOFF#
<31>
1
2
3
4
CSDA
CSCL
EDP_BIA_PWM
RX49 1 eDP@
BKOFF#
RX50 1 eDP@
ENVDD_PCH
RX51 1 eDP@
EDP_CPU_HPD
RX52 1 eDP@
TL_INVT_PWM
ENVDD_PCH
2 0_0402_5%
TL_BKOFF#
TL_ENVDD
Close to UX4
2 0_0402_5%
EDP_HPD_PANEL
Close to UX4
8
7
6
5
EDP_HPD_PANEL
<31>
For eDP co-layout
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
4
2 0_0402_5%
Close to UX2
<10,30>
RP57 @
2.2K_8P4R_5%
2 0_0402_5%
Across to UX4.19 & UX4.21
UX2
LVDS@
RP56 LVDS@
2.2K_8P4R_5%
LVDS_B2+
VCC
EC_SMB_CK2
QX6A
LVDS@
GND
3
D
CSCL
CPU_EDP_AUX#_C
2
G
QX6B
LVDS@
Title
eDP to LVDS converter

Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
19
of
55
W=40mils
Place close to JHDMI1
+VDISPLAY_VCC
WCM-2012HS-900T_4P
DDI1_LANE_N1
DDI1_LANE_P1
<6>
<6>
DDI1_LANE_N0
DDI1_LANE_P0
CX14 2
CX15 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
TMDS_TX0N
TMDS_TX0P
CX16 2
CX17 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
TMDS_TX1N
TMDS_TX1P
CX18 2
CX19 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
TMDS_TX2N
TMDS_TX2P
TMDS_TXCN
TMDS_TXCP
4
LX2
TMDS_L_TXCN
TMDS_L_TXCP
+5VS
FX1
1.5A_6V_1206L150PR~D
EMI@
+3VS
10U_0603_6.3V6M
<6>
<6>
TMDS_TXCN
TMDS_TXCP
0.1U_0402_16V7K
DDI1_LANE_N2
DDI1_LANE_P2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
1
CX22
<6>
<6>
CX12 2
CX13 2
RX12
10K_0402_5%
WCM-2012HS-900T_4P
TMDS_TX0N
TMDS_TX0P
TMDS_L_TX0N
TMDS_L_TX0P
4
3
2
1
1
2
3
4
DDI1_LANE_N3
DDI1_LANE_P3
CX21
<6>
<6>
4
LX3
RP58
680_8P4R_5%
JHDMI
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_HPLUG
EMI@
CPU_DPB_CTRLDAT_R
CPU_DPB_CTRLCLK_R
5
6
7
8
8
7
6
5
RP59
680_8P4R_5%
TMDS_L_TXCN
WCM-2012HS-900T_4P
+3VS
TMDS_TX1N
TMDS_TX1P
4
LX4
TMDS_L_TX1N
TMDS_L_TXCP
TMDS_L_TX0N
TMDS_L_TX1P
TMDS_L_TX0P
TMDS_L_TX1N
EMI@
TMDS_L_TX1P
TMDS_L_TX2N
QX3
2N7002K_SOT23-3
TMDS_L_TX2P
RX13
100K_0402_5%
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
LOTES_ABA-HDM-022-K01
CONN@
LX5
TMDS_TX2P
TMDS_TX2N
EMI@
TMDS_L_TX2P
TMDS_L_TX2N
WCM-2012HS-900T_4P
TMDS_L_TXCN
@EMI@
CX23
2 3.3P_0402_50V8C
TMDS_L_TXCP
@EMI@
CX24
2 3.3P_0402_50V8C
TMDS_L_TX0N
@EMI@
CX25
2 3.3P_0402_50V8C
TMDS_L_TX0P
@EMI@
CX26
2 3.3P_0402_50V8C
TMDS_L_TX1N
@EMI@
CX27
2 3.3P_0402_50V8C
TMDS_L_TX1P
@EMI@
CX28
2 3.3P_0402_50V8C
TMDS_L_TX2N
@EMI@
CX29
2 3.3P_0402_50V8C
TMDS_L_TX2P
@EMI@
CX30
2 3.3P_0402_50V8C
+5VS
+3VS
+3VS
RX17
2.2K_0402_5%
RX16
2.2K_0402_5%
QX4B
CPU_DPB_CTRLCLK_R
6
D
CPU_DPB_CTRLCLK
QX5
MMBT3904_NL_SOT23-3
CPU_DPB_CTRLDAT_R
QX4A
RX15
150K_0402_5%
HDMI_HPLUG
DPB_HPD
<10>
CPU_DPB_CTRLDAT
<10>
<10>
CX20
220P_0402_50V8J
@
RX34
20K_0402_5%
RX14
100K_0402_5%
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
2014/04/01
5
Title

HDMI
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
20
of
55
W=40mils
JP3
+3VALW
W=40mils
+LAN_IO rising time : >1ms and <100ms
2MM
+LAN_IO
WOL_EN
4
RL27
100K_0402_5%
VIN
VOUT
1.5A
1
1
EN
CL15
SS
GND
APL3512ABI-TRG_SOT23-5
@
CL38
0.1U_0603_25V7K
1
CL19
2
0.1U_0402_10V7K
<30>
UL2
5
WOL_EN
W=40mils
0.1U_0402_10V7K
CL39
1U_0402_6.3V6K
2
1
These caps close to Pin 23,32

For 8106E pop the capacitor close pin 23,32
MCT0
RL19
75_0603_5%
1
2
MCT1
2
RL20
75_0603_5%
EMI@
CL33
10P_1206_2KV8J
Place close to TCT pin

1
CL22
2
1
CL26
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CL20
0.1U_0402_10V7K
+LAN_VDD
TL1
MDI1MDI1+
These caps close to Pin 8,30

For 8106E pop capacitor close to pin 8,30
MDI0MDI0+
2
UL1
<12>
<12>
PCIE_PRX_LANTX_P3
PCIE_PRX_LANTX_N3
PCIE_PTX_LANRX_P3
PCIE_PTX_LANRX_N3
CL30 1
CL31 1
2 0.1U_0402_10V7K PCIE_PRX_LANTX_P3_C
2 0.1U_0402_10V7K PCIE_PRX_LANTX_N3_C
13
14
PCIE_PTX_LANRX_P3
PCIE_PTX_LANRX_N3
<10,26,30,48,6>
<10,30>
19
PLT_RST#
PCIE_WAKE#
17
18
ISOLATEB
20
PCIE_WAKE#
21
26
PAD~D T96
@
3
6
7
9
10
11
22
24
+LAN_IO
PCIE_WAKE#
RL34
10K_0402_5%
HSOP
HSON
MDIP0
MDIP1
MDIN0
MDIN1
HSIP
HSIN
PERSTB
AVDD10
AVDD10
AVDD33
DVDD33
ISOLATEB
LANWAKEB
GPO
NC
NC
NC
NC
NC
NC
NC
NC
REFCLK_P
REFCLK_N
CLKREQB
CKXTAL1
CKXTAL2
LED0
LED1
RSET
GND
1
4
2
5
MDI0+
MDI1+
MDI0MDI1-
8
30
32
23
+LAN_IO
<29>
15
16
XTLO
XTLI
27
25
31
@
@
RL31 2
RX+
RXCT
NC
NC
CT
TX+
TX-
16
15
14
13
12
11
10
9
MDO1MDO1+
MCT0
MCT1
MDO0MDO0+
C
Change CPN to SP050007J00 only

Need CIS symbol
For GCLK
+LAN_VDD
12
28
29
RD+
RDCT
NC
NC
CT
TD+
TD-
X'FORM_ NS0014
CL41
0.01U_0402_16V7K
CL30, CL31 close to UL1 Pin 17, 18
<12>
<12>
1
2
3
4
5
6
7
8
CLK_PCIE_LAN
CLK_PCIE_LAN#
<9>
<9>
LAN_CLKREQ#
<9>
XTLI
XTLI
CL36
1
2
XTLI
10P_0402_50V8J
XTAL@
T94 PAD~D
T95 PAD~D
YL2
1
1 2.49K_0402_1%
33
CL37
1
2
RTL8106E-CG_QFN32_4X4
XTAL@
OSC
GND
OSC
GND
2
4
25MHZ_10PF_7V25000014
XTLO
10P_0402_50V8J
XTAL@
W=20mils
1
CL35
2
1U_0402_6.3V6K
1
CL34
0.1U_0402_10V7K
+LAN_VDD
JLAN
8
7
MDO1-
+3VS
6
5
+LAN_IO
4
RL33
1K_0402_5%
LAN_CLKREQ#
ISOLATEB
MDO1+
MDO0-
RL38 10K_0402_5%
1
2
@
MDO0+
PR4+
PR2PR3PR3+
PR2+
PR1PR1+
SHLD1
WOL_EN
@
RL37 10K_0402_5%
1
2
PR4-
SHLD2
RL35
15K_0402_5%
Reserve 10K pull LAN_IO
9
10
SANTA_130456-311
CONN@
Issued Date
Compal Secret Data

2013/03/09
Deciphered Date
2014/04/01
Title
Size
Date:
LAN RTL8106E
Document Number
Rev
0.2
LA-9981P

1
Sheet
21
of
55
Reserve for HDA issue

+1.5VS
2 0_0402_5%
RA9
Line1-VREFO-L
Line1-VREFO-R
2 0_0402_5%
RA165
4.7K_0402_5%
+5VA
JACK_PLUG Delay circutis
RA166
4.7K_0402_5%
RV59
0_0603_1%
1K_0402_1%
RA82
+3VS
@
RA1
100K_0402_5%
Line-IN-R
1K_0402_1%
CA59
4.7U_0603_6.3V6K
CA61
4.7U_0603_6.3V6K
RA130
PCH_AZ_CODEC_SDIN0
PCH_AZ_CODEC_SDOUT
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_SYNC
PCH_AZ_CODEC_RST#
2
2
CA24 1
CA25 1
CA62 1
CA63 1
CA64 1
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
SENSE B
SENSE A
CBP
CBN
CPVEE
SPK-OUT-R+
SPK-OUT-RSPK-OUT-LSPK-OUT-L+
MIC1-VREFO-L
MIC1-VREFO-R
MIC2-VREFO
27
39
7
SPDIF-OUT/GPIO2
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
DVSS
AVSS1
AVSS2
49
RA79 1
1K_0402_1%
PC_BEEP
JACK_PLUG#
16
1
@ CA69
24
23
@ RA81 2
22
21
LINE1-L
LINE1-R
20
19
MIC1-L
18
17
MIC_IN
RING2
CA74
1 10K_0402_5%
@
CA1
10U_0603_6.3V6M
RA51 1
45
44
43
42
INT-SPK-R+
INT-SPK-RINT-SPK-LINT-SPK-L+
33
32
HPOUT-R
HPOUT-L
@
QA5A
1
@
CA2
2 10U_0603_6.3V6M
10U_0603_6.3V6M
JACK_PLUG#
14
13
@
RA3
10K_0402_5% 1
2 100P_0402_50V8J
CA65 1
0.1U_0402_16V7K
12
@
QA5B
2 39.2K_0402_1%
RA4
2 0_0402_1%
JACK_SENSE#
Reserve for cancel Delay circutis
JACK_SENSE#
RA51, RA33 place close to UA1

C
+MIC2-VREFO
HPOUT-R(PORT-I-R)
HPOUT-L(PORT-I-L)
LDO1-CAP
LDO2-CAP
LDO3-CAP
4
25
38
@EMI@
CA21
22P_0402_50V8J
MIC2-R(PORT-F-R)
MIC2-L(PORT-F-L)
VREF
JDREF
31
30
29
2
1
MIC1-R(PORT-B-R)
MIC1-L(PORT-B-L)
37
35
34
Line1-VREFO-L
Line1-VREFO-R
+MIC2-VREFO
+MIC2-VREFO
LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)
SDATA-IN
SDATA-OUT
BCLK
SYNC
RESETB
28
15
2.2U_0603_6.3V6K
20K_0402_1%
LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)
DVDD-IO
AVDD2
8
5
6
10
11
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
@EMI@
R2355
0_0402_5%
2 22_0402_5%
MONO-OUT
DVDD
CPVDD
9
40
+CODEC_AVDD2
CA23
1
RA153 1
PCH_AZ_CODEC_BITCLK
1
36
CA57,CA58 close
to UA1 pin1
<8>
<8>
<8>
<8>
<8>
CA60
0.1U_0402_16V7K
AVDD1
PVDD1
PVDD2
PCBEEP
26
41
46
+3VS
JACK_SENSE#
CA57
4.7U_0603_6.3V6K
CA58
0.1U_0402_16V7K
@
RA2
100K_0402_5%
UA1
RA80
Line-IN-L
+5VS
RV54
0_0603_1%
1
@
2
+5VA
LINE1-L
CA67 1
4.7U_0603_6.3V6K
LINE1-R
CA68 1
4.7U_0603_6.3V6K
+5VS
CA71
4.7U_0603_6.3V6K
1
1
CA51
0.1U_0402_16V7K
CA53
4.7U_0603_6.3V6K
+3VS
1
1
CA54
0.1U_0402_16V7K
CA55
4.7U_0603_6.3V6K
CA56
0.1U_0402_16V7K
1
1
+3VS
+5V_PVDD
CA53, CA55 change Value

from 10U_0603_6.3V6M~D to
4.7U_0603_6.3V6K
+5V_PVDD
CA71, CA51 place close to Pin 26

+5V_PVDD
+CODEC_AVDD2
RA8
+3VS
PDB
48
MIC_IN
2.2K_0402_5%
RING2
2.2K_0402_5%
RA53
2
3
MIC_CLK_C
47
EC_MUTE#
MIC_DATA
<31>
RA1109
EC_MUTE#
RA29
0_0603_1%
RA30
0_0603_1%
RA31
0_0603_1%
RA32
0_0603_1%
<30>
GNDA
Thermal PAD
ALC3223-CG_MQFN48_6X6~D
GND
Place on the moat between GND & GNDA.

LA1 EMI@
MIC_CLK
MIC_CLK
BLM15BB221SN1D_2P
SM01000BV00
need CIS symbol
+3VALW
<31>
DA8
EC Beep
<30>
BEEP#
@EMI@
CA22
22P_0402_50V8J
MCU Beep
<11>
PC_BEEP
HDA_SPKR
MIC_CLK_C
BAT54C-7-F_SOT23-3
MIC_IN
@
RA19
10K_0402_5%
RA5
100K_0402_5%
PC Beep
close to Codec
MIC_IN
LA7
RING2
LA10 2
Line-IN-L
LA8
HPOUT-R
Line-IN-R
LA9
5
6
E&T_3703-Q04N-11R
CONN@
1000P_0402_50V7K
1000P_0402_50V7K
EMI@ CA32
1
2
3 GND
4 GND
RING2_R
AUD_HP_OUT_L_CN
3
1
JACK_PLUG#
AUD_HP_OUT_R_CN
MIC_IN_R
6
2
4
7
AUD_HP_OUT_R_CN
3
1
ESD@
DA12
AZ5125-02S.R7G_SOT23-3
ESD@
DA10
AZ5125-02S.R7G_SOT23-3
CA40 EMI@
100P_0402_50V8J
CA38 EMI@
100P_0402_50V8J
CA33 EMI@
100P_0402_50V8J
CA39 EMI@
100P_0402_50V8J
SINGA_2SJ3080-000111F
CONN@
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
JSPK
1
2
3
4
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
JHP
AUD_HP_OUT_L_CN
RA83
10K_0402_5%
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
RING2_R
RA84
10K_0402_5%
A
2
2
2
2
MIC_IN_R
8.2_0402_1%
RA56
1
1
1
1
HPOUT-L
40mil
40mil
RA55
8.2_0402_1%
LA3
LA4
LA5
LA6
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-RSpeaker 4 ohm : 40mil

Speaker 8 ohm : 20mil
iPhone and Nokia type Combo Jack

EMI@
FBMA-L10-160808-800LMT_2P
EMI@
FBMA-L10-160808-800LMT_2P
EMI@
FBMA-L10-160808-800LMT_2P
EMI@
FBMA-L10-160808-800LMT_2P
EMI@
EMI@
EMI@
EMI@
1000P_0402_50V7K
EMI@ CA31
INT-SPK-RINT-SPK-R+
INT-SPK-LINT-SPK-L+
1000P_0402_50V7K
EMI@ CA30
10K_0402_5%
CA29
RA7
+3VS
10K_0402_5%
EMI@
Close to UA1
Pin11,13,14,16
1
RA6
QA6A
@
PCH_AZ_CODEC_RST#
5
QA6B
Title
Audio Codec ALC3223

Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
22
of
55
SD_CD#
CR9
+3VS
0.1U_0402_10V7K
+VCC_3IN1
USB20_CR_P6
<12>
USB20_CR_N6
USB20_CR_P6
USB20_CR_N6
USB20_CR_P6_R
1 6.19K_0402_1%
RREF
USB20_CR_N6_R
2
3
USB20_CR_N6_R
USB20_CR_P6_R
DM
DP
22
21
20
19
18
16
15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SD_D2
MS_D1_SD_D3
close to chip side
SD_CMD
MS_D0
MS_D2_SD_CLK_R
MS_D2_SD_CLKConn pin 13 SD_CLK

Viapin 10 MS_D2
MS_D2_SD_CLK
SD_CD#
MS_D3
SD_D0
SD_D1
MS_INS#
MS_CLK_SD_WP_R
MS_CLK_SD_WP
EMI@
RR3
22_0402_5%
RTS5179-GR_QFN24_4X4
EMI@
CR6
5P_0402_50V8C
CR4
1U_0402_6.3V6K
CR3
1U_0402_6.3V6K
SDREG
V18
14
13
12
11
10
9
8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
2
EMI@
RR2
22_0402_5%
EMI@
CR5
5P_0402_50V8C
6
24
25
V18
Thermal pad
RTS5179-GR_QFN24
XD_CD#
XD_D7
GPIO0
MS_BS
WCM-2012HS-900T_4P
7
23
17
0.1U_0402_10V7K
RREF
3V3_IN
CARD_3V3
RR1
EMI@
LR2
<12>
CR10 EMI@
For EMI request. Place close to UR1
Trace width:40mil
UR1
MS_INS#
EMI@
MS_CLK_SD_WPConn pin 5 MS_CLK

Viapin 20 SD_W
+3VS
CR1
0.1U_0402_10V7K
CR2
+VCC_3IN1
4.7U_0603_6.3V6K
+VCC_3IN1
JREAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SD_D2
MS_D1_SD_D3
CR8
4.7U_0603_6.3V6K
MS_CLK_SD_WP
SD_CMD
MS_D3
MS_INS#
CR7
0.1U_0402_10V7K
MS_D2_SD_CLK
MS_D0
MS_D1_SD_D3
MS_D2_SD_CLK
MS_BS
Close to JREAD
SD_D0
SD_D1
SD_CD#
MS_CLK_SD_WP
23
24
T-SOL_143-2300302602_RV
CONN@
SD_CMD
EMI@
CR11
10P_0402_50V8J
SD-DAT2
MS-VSS1
SD-CD/DAT3 MMC-RSV
MS-VCC
MS-SCLK
SD-CMD MMC-CMD
MS-DATA3
MS-INS
SD-VSS MMC-VSS1
MS-DATA2
SD-VDD MMC-VDD
MS-DATA0
MS-DATA1
SD-CLK MMC-CLK
MS-BS
MS-VSS2
SD-VSS MMC-VSS2
SD-DAT0 MMC-DAT
SD-DAT1
SD-CD
SD-GND
GND1
SD-WP(SW)
GND2
For EMI request.

Place close to JREAD
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
Card Reader RTS5179

Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
23
of
55
+5VALW
CI18
LI1
<12>
USB3RN2_JUSB1
USB3RN2_JUSB1
EMI@
47U_0805_6.3V4Z
USB3RN2_JUSB1_R
CI12
4.7U_0805_10V4Z
CI14
2.0A
0.1U_0402_16V7K
+5V_USB_PWR1
USB connector1
USB20 port1
USB30 port2
1
2
3
4
USB3RP2_JUSB1_R
DLW21SN670HQ2L_4P
USB_EN#
USB_EN#
CI3
USB3TP2_JUSB1
USB3TP2_JUSB1
CI4
EMI@
USB3TN2_JUSB1_C
0.1U_0402_10V7K
USB3TN2_JUSB1_R
USB_OC0#
CI15
0.1U_0402_16V7K
JUSB1
USB3TP2_JUSB1_C
0.1U_0402_10V7K
CI1
USB3TP2_JUSB1_R
USB3TN2_JUSB1_R
USB20_JUSB1_P1_R
USB20_JUSB1_N1_R
USB3RP2_JUSB1_R
USB3RN2_JUSB1_R
ESD@
DI1
DLW21SN670HQ2L_4P
10
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
GND
GND
GND
GND
10
11
12
13
ACON_TARA4-9K1311
CONN@
DI2
USB3RN2_JUSB1_R
9
1
8
3
7
2
6
4
5
USB3TP2_JUSB1_R
220U_6.3V_M
+5V_USB_PWR1
AP2301MPG-13_MSOP8
CI2
0.1U_0402_16V7K
<12>
USB3TN2_JUSB1
USB3TN2_JUSB1
80mil
CI40
10U_0603_6.3V6M
LI3
<12>
VOUT
VOUT
VOUT
FLG
0.1U_0402_16V7K
CI13
<25,30>
GND
VIN
VIN
EN
8
7
6
5
USB3RP2_JUSB1
<12>
USB3RP2_JUSB1
EPAD
UI3
USB3RN2_JUSB1_R
L30ESDL5V0C3-2_SOT23-3
USB3RP2_JUSB1_R
USB3RP2_JUSB1_R
USB3TN2_JUSB1_R
USB3TN2_JUSB1_R
USB3TP2_JUSB1_R
USB3TP2_JUSB1_R
ESD@
3
EMI@
LI2
<12>
USB20_JUSB1_N1
<12>
USB20_JUSB1_P1
USB20_JUSB1_N1
USB20_JUSB1_P1
USB20_JUSB1_N1_R
USB20_JUSB1_P1_R
IP4292CZ10-TBR_XSON10_2.5X1~D
C
WCM-2012HS-900T_4P
+5VALW
CI6
LI4
<12>
USB3RN1_JUSB2
USB3RN1_JUSB2
EMI@
4.7U_0805_10V4Z
USB3RN1_JUSB2_R
CI7
2.0A
0.1U_0402_16V7K
+5V_USB_PWR2
USB connector2
USB20 port0
USB30 port1
1
2
3
4
USB3RP1_JUSB2_R
DLW21SN670HQ2L_4P
USB_EN#
LI6
<12>
USB3TP1_JUSB2
CI10
USB3TP1_JUSB2
CI11
EMI@
USB3TN1_JUSB2_C
0.1U_0402_10V7K
USB3TP1_JUSB2_C
0.1U_0402_10V7K
USB3TN1_JUSB2_R
USB_OC0#
USB_OC0#
<12>
CI17
AP2301MPG-13_MSOP8
0.1U_0402_16V7K
+5V_USB_PWR2
JUSB2
9
1
8
3
7
2
6
4
5
USB3TP1_JUSB2_R
USB3TP1_JUSB2_R
CI8
DLW21SN670HQ2L_4P
220U_6.3V_M
USB3TN1_JUSB2_R
USB20_JUSB2_P0_R
USB20_JUSB2_N0_R
USB3RP1_JUSB2_R
USB3RN1_JUSB2_R
ESD@
DI4
CI9
0.1U_0402_16V7K
USB3TN1_JUSB2
80mil
CI43
10U_0603_6.3V6M
<12>
USB3TN1_JUSB2
CI26
VOUT
VOUT
VOUT
FLG
0.1U_0402_16V7K
GND
VIN
VIN
EN
8
7
6
5
USB3RN1_JUSB2_R
10
USB3RN1_JUSB2_R
USB3RP1_JUSB2_R
USB3RP1_JUSB2_R
USB3TN1_JUSB2_R
USB3TN1_JUSB2_R
USB3TP1_JUSB2_R
USB3TP1_JUSB2_R
USB3RP1_JUSB2
<12>
USB3RP1_JUSB2
EPAD
UI2
CONN@
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
GND
GND
GND
GND
10
11
12
13
ACON_TARA4-9K1311
DI5
<12>
USB20_JUSB2_N0
<12>
USB20_JUSB2_P0
USB20_JUSB2_N0
USB20_JUSB2_P0
USB20_JUSB2_N0_R
USB20_JUSB2_P0_R
ESD@
EMI@
LI5
3
8
IP4292CZ10-TBR_XSON10_2.5X1~D
WCM-2012HS-900T_4P
A
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
USB3.0
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
24
of
55
+5VALW
CI27
47U_0805_6.3V4Z
CI23
4.7U_0805_10V4Z
CI22
2.0A
0.1U_0402_16V7K
+5V_USB_PWR3
USB connector3
USB20 port2
USB_EN#
8
7
6
5
80mil
USB_OC1#
CI24
AP2301MPG-13_MSOP8
0.1U_0402_16V7K
0.1U_0402_16V7K
+5V_USB_PWR3
+5V_USB_PWR3
JUSB3
WCM-2012HS-900T_4P
USB20_JUSB3_P2
USB20_JUSB3_N2
USB20_JUSB3_P2
USB20_JUSB3_N2
220U_6.3V_M
ACON_UARBG-4K1926
CONN@
ESD@
USB20_JUSB3_P2_R
USB20_JUSB3_N2_R
<12>
<12>
1
CI20
CI44
10U_0603_6.3V6M
DI7
VBUS
DD+
GND
GND
GND
GND
GND
CI19
0.1U_0402_16V7K
1
2
3
4
5
6
7
8
USB20_JUSB3_N2_R
USB20_JUSB3_P2_R
CI16
VOUT
VOUT
VOUT
FLG
USB_EN#
<24,30>
GND
VIN
VIN
EN
EPAD
UI4
1
2
3
4
Place close to JUSB3
LI7
EMI@
+5VALW
CI21
47U_0805_6.3V4Z
CI31
4.7U_0805_10V4Z
CI30
2.0A
0.1U_0402_16V7K
+5V_USB_PWR4
B
USB_EN#
<12>
USB20_USBDB_P3
<12>
USB20_USBDB_N3
USB20_USBDB_N3
USB20_USBDB_P3_R
USB20_USBDB_N3_R
VOUT
VOUT
VOUT
FLG
8
7
6
5
80mil
USB_OC1#
USB_OC1#
USB connector4
USB20 port3
<12>
CI32
AP2301MPG-13_MSOP8
0.1U_0402_16V7K
2
WCM-2012HS-900T_4P
USB20_USBDB_P3
CI25
GND
VIN
VIN
EN
1
2
3
4
EPAD
UI5
0.1U_0402_16V7K
+5V_USB_PWR4
JDB
1
2
3
4
5
6
7
8
USB20_USBDB_P3_R
USB20_USBDB_N3_R
LI10
EMI@
1
2
3
4
5
6
7
8
G1
G2
9
10
JESS_UCNR2210M008-0
CONN@
2nd: SP01001EX00
Main: SP01001AA00
Change CONN symbol for DFB
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
MB to USB2.0 DB
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
25
of
55
CC47wlan connector
+3V_WLAN
CM43
4.7U_0603_6.3V6K
CM48
0.1U_0402_10V7K
CM46
0.1U_0402_10V7K
CM40
0.047U_0402_16V4Z
@ CM47
0.1U_0402_10V7K
Mini WLAN/WIMAX H=6.7

+3V_WLAN
+3V_WLAN
+1.5VS
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
<12>
<12>
PCIE_PTX_WLANRX_N4
PCIE_PTX_WLANRX_P4
CM49
CM44
<30>
<30>
<11>
BT_ON#
BT_ON#
1
1
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
PCIE_PTX_WLANRX_N4_C
PCIE_PTX_WLANRX_P4_C
EC_TX
EC_RX
EC_TX
EC_RX
RM13
1 1K_0402_1%
53
GND1
54
GND2
+3VS
RM110
10K_0402_5%
WLAN_RADIO_DIS#_R
PLT_RST#
PLT_RST#
USB20_MINI1_N4
USB20_MINI1_P4
WL_OFF#
WL_OFF#
<11>
<17,18,19,27,6,9>
<17,18,19,27,6,9>
<12>
<12>
WL_BT_LED#
+3VS
+3V_WLAN
@
RM25
0_0805_1%
CONCR_525B01BE17A
CONN@
<10,21,30,48,6>
USB20_MINI1_N4
USB20_MINI1_P4
RM11
100K_0402_5%
QM30
2N7002K_SOT23-3
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
+3VS
<9>
<9>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WLAN_CLKREQ#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WLAN_CLKREQ#
<9>
<12>
<12>
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
WLAN_WAKE#
WLAN_WAKE#
JMINI
<30>
2
@
RM26
0_0805_1%
+3VS
+CPU_CORE
CM45
22U_0603_6.3V6M
ESD@
ESD solution
HDD LED
Battery LED
RD16
680_0402_1%
<8>
SATA_ACT#
SATA_ACT#
<30>
BATT_CHG_LED#
BATT_CHG_LED#
<30>
BATT_LOW_LED#
BATT_LOW_LED#
LED2
12-21C-T3D-CM2P1B18X-2C_WHITE
White
RD15
390_0402_5%
+5VS
RD17
390_0402_5%
+5VALW
Amber
LED3
HT-210UD5-BP5_AMBER-WHITE
10mils, All pins

+3VS
+5VALW
+5VALW
RD45
100K_0402_5%
Wireless LED
@ RD46
100K_0402_5%
LED1
WL_BT_LED#
RD18
680_0402_1%
QD18
2N7002K_SOT23-3
+5VALW
2
RD14
390_0402_5%
PWR_PWM_LED#
<30>
Power LED
LED4
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
Mini Card/LED
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
26
of
55
+FAN_POWER
D
2.2U_0603_6.3V6K
POWER/B
+3VALW
JPWR
<30>
1
2
3
4
LID_SW#
LID_SW#
ON/OFFBTN#
1
CE22
1
2
3
4
1000P_0402_50V7K
40mil
FAN Control circuit
1
CE23
+5VS
CE25
2.2U_0603_6.3V6K
UE3
GND
GND
5
6
<30>
1
2
3
4
EN_DFAN1
EN_DFAN1
HB_A090420-SAHR21
CONN@
VEN
VIN
VO
VSET
GND
GND
GND
GND
8
7
6
5
APE8873M SOP 8P
+3VS
+FAN_POWER
Power ON Circuit
RE50
10K_0402_5%
40mil
+3VLP
ON/OFF switch
FAN_SPEED1
<30>
CE24
0.01U_0402_16V7K
ON/OFFBTN#
1
2
3
GND
GND
ACES_85204-0300N
CONN@
SW1
SMT1-05-A_4P
4
5
RE49
100K_0402_5%
TOP Side
JFAN
1
2
3
<30>
6
5
CE20
0.1U_0402_16V7K
Bottom Side
SW2
SMT1-05-A_4P
INT_KBD Connector
6
5
JKB
CONN@
HB_A823020-SBHR21
Pop only before MP
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
KB_CAPS_PWR
<30>
<30>
KSI[0..7]
KSI[0..7]
KSO[0..16]
KSO[0..16]
Touch pad
+3VS
JTP
<30> TP_CLK
<30> TP_DATA
<17,18,19,26,6,9>
<17,18,19,26,6,9>
TP_CLK
TP_DATA
1
2
3
4
5
6
1
2
3
4
5 G1
6 G2
+5VS
RE60
1
7
8
240_0402_1%
<30>
CAPS_LED
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
GND
32
31
PS_HPF10052-06M000R
CONN@
2nd: SP01001BG00
Main: SP01000R910
Change CONN symbol for DFB
A
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
2014/04/01
5
Title

FAN/TP/PWR SW
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
27
of
55
+5VS and +3VS switch

1
+5VALW
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
Q8
2N7002K_SOT23-3
J511
10U_0603_6.3V6M
C2323
10U_0603_6.3V6M
C2324
R16
100K_0402_5%
@ JUMP_43X79
10U_0603_6.3V6M
C2305
10U_0603_6.3V6M
C2306
10U_0603_6.3V6M
C2318
10U_0603_6.3V6M
C2316
+3VS
SHORT DEFAULT
R10
100K_0402_5%
SUSP
SUSP#
15
+5VALW
3VS
10
9
8
TPS22966DPUR_SON14_2X3
11
GPAD
+3VALW
GND
@ JUMP_43X79
6
7
CT1
VBIAS
ON1
5VS
12
3VS_GATE
C2309 +3VALW
0.01U_0603_25V7K
0.01U_0603_25V7K
C2322
2 470K_0402_5%
10mil
14
13
VOUT1
VOUT1
10U_0603_6.3V6M
4
R2318
VIN1
VIN1
C2308
5VS_GATE
10U_0805_10V4Z
2 82K_0402_5%
C2307
SUSP#
J510
1
2
R2313
<30,39,40>
+5VALW
+5VS
SHORT DEFAULT
U2301
+3VALW_PCH switch
3
+3VALW
SHORT DEFAULT
6
7
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
11
@
10
9
8
+0.675VS
R2314
22_0603_5%
15
GPAD
+1.05VS
CT1
VBIAS
R2315
470_0603_5%
@
TPS22966DPUR_SON14_2X3
1 2
C2314
0.01U_0603_25V7K
10mil
ON1
SUSP
G
S
+3VALW
10U_0603_6.3V6M
C2313
10U_0603_6.3V6M
C2311
SUSP
G
Q2307
2N7002K_SOT23-3
R416
0_0402_5%
12
@ JUMP_43X79
10U_0603_6.3V6M
+3VALW_PCH_GATE
C2312
3VALW_PCH
10U_0805_10V4Z
PCH_PWR_EN
14
13
VOUT1
VOUT1
C2310
<30>
PCH_PWR_EN
J513
VIN1
VIN1
1 2
U2304
1
2
+3VALW_PCH
Q2308
2N7002K_SOT23-3
@
For Intel S3 Power Reduction
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
A
Title
DC/DC Interface
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
E
28
of
55
UG1
GCLKUMA@
UG2
GCLKDIS@
SLG3NB244VTR TQFN 16P CLK GEN SLG3NB244VTR TQFN 16P CLK GEN
SLG3NB3374V is for DIS by output 24M*1,25M*1, 27M*1, 32K*1

SLG3NB3375V is for UMA by output 24M81, 25M*1, 32K*1
+RTCBATT
+RTCVCC
+1.05VS
+LAN_IO
+3VLP
+3VALW
1
RG2 @
0_0402_5%
+1.8VGS
RG1
GCLK@
330_0402_5%
CG4
GCLK@
1
0.1U_0402_10V7K
CG3
GCLK@
1
0.1U_0402_10V7K
CG2
1 GCLK@
0.1U_0402_10V7K
CG1
0.1U_0402_10V7K
Depop if GCLK
with UMA
1 GCLK@
CG10
CG5
22U_0805_6.3V6M
GCLK@
1
1
2
2
UG1
GCLK_VRTC
Place close
to UG1.8
10
15
+3VLP
+3VALW
VBAT
VDD_RTC_OUT
14
RTC_VOUT
PCH_RTCX1_R
RG3
12
VGA_X1_R
RG4
LAN_X1_R
RG5
2.2U_0603_6.3V6K
CG6
0.1U_0402_10V7K
GCLKDIS@
GCLK@
CPU_RTC 32.768k(P.8)
Place RG3 close to YC1
+V3.3A
0_0402_5%
VDD
32kHz
PCH_RTCX1
GCLK@
<8>
GCLKDIS@
+1.05VS
CLK_X1
CLK_X2
CLK_X1
CG8
VDDIO_25M_B
25MHz_B
XTAL_IN
XTAL_OUT
1
YG1
1
3
2
25MHz_A
GCLK@
12P_0402_50V8J~D
CG9
1
16
VDDIO_25M_A
GCLK@
OSC
OSC
SLG3NB274VTR_TQFN16_2X3
GCLK@
GND
GND
2 10_0402_1%
PCH_X1_R
RG6
RG7
2 33_0402_5%
RG8
2 0_0402_5%
XTAL24_IN
GCLK@
2
GCLK@
<9>
CPU_CLK 24M(P.9)
Place RG6 close to YC2
XTALIN
0_0402_5%
XTLI_R
GCLK@
VGA 27M(P.29)
Place RG7 close to YV1
XTALIN_R
GCLKDIS@
GND4
27MHz
GND1
GND2
GND3
+LAN_IO
VDDIO_27M
GCLK@
CG7
5P_0402_50V8C
XTLI
0_0402_5%
<49>
<21>
LAN 25M(P.21)
Place RG8 close to YL2
RG3, RG7,RG8, RG6 0ohm_0402

for isolated CLK tail
17
11
4
7
13
+1.8VGS
25MHZ_10PF_7V25000014
1
XTALIN_R
12P_0402_50V8J~D
CLK_X2
1
B
@
CG11
5P_0402_50V8C
Reserve CG11 for vendor

Place close to RG4
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
2014/04/01
5
Title

GCLK
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
23
of
55
+3VALW
Board ID
+EC_VCCA
RE5
0.1U_0402_10V7K
12
13
37
20
38
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
<27>
+3VALW
<27>
KSI[0..7]
KSI[0..7]
KSO[0..16]
KSO[0..16]
LID_SW#
10K_0402_5%
RE71
WLAN_WAKE#
10K_0402_5%
RE70
+3VALW
RP36
5
6
7
8
4
3
2
1
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
2.2K_0804_8P4R_5%
<10>
<36,37>
<36,37>
<19,49,9>
<19,49,9>
Reserve for ESD

1
<10>
<10>
SIO_SLP_S3#
SIO_SLP_S5#
<8> EC_SMI#
<36> PS_ID
<31> CE_EN
<10,44> DGPU_PWROK
<10,19> ENVDD_PCH
<31> DBC_EN
<27> FAN_SPEED1
<10,21> PCIE_WAKE#
<26> EC_TX
<26> EC_RX
<10> PCH_PWROK
<10> ME_SUS_PWR_ACK
<6> RUNPWROK
SIO_SLP_S5#
CE28
ESD@
0.1U_0402_10V7K
Please close to EC
B
PCH_PWROK
RE18
10K_0402_5%
<40>
<13>
+1.05V_PGOOD
VCCST_PG_EC
FAN_SPEED1
220P_0402_50V8J
Please close to EC
+1.05V_PGOOD
VCCST_PG_EC
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
XCLKI/GPIO5D
XCLKO/GPIO5E
EC_VDD/AVCC
EN_INVPWR
EN_DFAN1
EC_ENVDD
LCD_TEST
83
84
85
86
87
88
EC_MUTE#
SIO_SLP_S4#
IMVP_PWRGD
SYS_PWROK
TP_CLK
TP_DATA
97
98
99
109
SUSACK#
WOL_EN
ME_EN
VCIN0_PH
AD_BID0
PANEL_BKLEN
SPI Flash ROM
GPIO
Bus
GPIO
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R
<36,37>
PCH_HOT#
PCH_HOT#
EC_MUTE#
<22>
SIO_SLP_S4#
<10>
IMVP_PWRGD
<42>
SYS_PWROK
<10,6>
TP_CLK <27>
TP_DATA <27>
EC_SPI_MOSI_1
EC_SPI_MISO_1
EC_SPI_CLK_R
EC_SPI_CS0#
VR_ON
VR_ON
C
CE34
73
74
89
90
91
92
93
95
121
127
WLAN_WAKE#
SIO_SLP_S0#
BATT_CHG_LED#
CAPS_LED
PWR_PWM_LED#
BATT_LOW_LED#
SYSON
VR_ON_EC
CPU_DETECT#
ACIN
EC_ON
ON/OFFBTN#
LID_SW#
SUSP#
65W/90W#
PECI_KB9012
124
+V18R
ESD@
Place DE1 close to UE1
<6>
RE12
+3VALW
EC_LID_OUT#
<11>
VCIN1_PH
<36>
VCOUT1_PH
<36>
VCOUT0_PH#
<38>
BKOFF#
<19>
PBTN_OUT#
<10,6>
1
PCH_PWR_EN
<28>
43_0402_1%
ACIN_65W
<49>
SYSON
VR_ON
0_0402_5%
EC_RSMRST#
RE36
110
112
114
115
116
117
118
DE1
L03ESDL5V0CG3-2_SOT-523-3
1
CPU_DETECT#
100K_0402_5%
2
ACIN_65W
Place CE34
between DE1 and RE12
WLAN_WAKE#
<26>
SIO_SLP_S0#
<10>
BATT_CHG_LED#
<26>
CAPS_LED
<27>
PWR_PWM_LED#
<26>
BATT_LOW_LED#
<26>
RE11
EC_RSMRST#
EC_LID_OUT#
VCIN1_PH
VCOUT1_PH
VCOUT0_PH#
BKOFF#
PBTN_OUT#
VCCST_PG_EC
ESD@
EC_SPI_MOSI_1
<9>
EC_SPI_MISO_1
<9>
EC_SPI_CLK_R
<9>
EC_SPI_CS0#
<9>
VR_ON
<10>
CE26
0.1U_0402_10V7K
RE2
10K_0402_5%
ESD@
LID_SW#
CE30
0.1U_0402_10V7K
ESD@
PCH_PWROK
CE31
PECI_EC
0.1U_0402_10V7K
ESD@
<6>
SYS_PWROK
RE43
43_0402_1%
CE32
0.1U_0402_10V7K
ESD@
CE16
CPU_DETECT#
CE33
KB9012QF-A4_LQFP128_14X14
<41>
<13,42>
@
RE1
10K_0402_5%
ACIN
<10,36,37,49>
EC_ON
<38>
ON/OFFBTN#
<27>
LID_SW#
<27>
SUSP#
<28,39,40>
65W#/90W
<36>
0.1U_0402_10V7K
4.7U_0805_10V4Z
LE2
1
ECAGND 2
FBMA-L11-160808-800LMT_0603
Place CE30,CE31,CE32,CE33 close to UE1
VCOUT1_PH
CE18
ACIN
1 100P_0402_50V8J
ME_EN
@
RE326
1K_0402_5%
NC
ME_FWP PCH has internal 20K PD.

(suspend power rail)
RE47
100K_0402_5%
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
2014/04/01
5
<9>
@
RE7
0_0402_5%
<10>
SUSACK#
<10>
WOL_EN
<21>
ME_EN
<8>
VCIN0_PH
<36>
RE10
EN_INVPWR
<31>
EN_DFAN1
<27>
EC_ENVDD
<31>
LCD_TEST <31>
119
120
126
128
100
101
102
103
104
105
106
107
108
RE9
1 100P_0402_50V8J ECAGND
<36,37>
PANEL_BKLEN
SPI Device Interface
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
CE19
47P_0402_50V8J
UE2
H_PROCHOT#
SN74LVC1G06DCKR_SC70-5
1
SIO_SLP_S3#
SIO_SLP_S5#
EC_SMI#
PS_ID
CE_EN
DGPU_PWROK
ENVDD_PCH
DBC_EN
FAN_SPEED1
PCIE_WAKE#
EC_TX
EC_RX
PCH_PWROK
ME_SUS_PWR_ACK
RUNPWROK
68
70
71
72
ADP_I
2
4.7K_0402_5%
BATT_TEMP
ADP_I
KB9012A3 change to
KB9012A4 SA00004OB30
2
H_PROCHOT#
CE15
0.1U_0402_10V7K
VR_HOT#
@
RE44
0_0402_1%
<36,6>
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
BATT_TEMP
20mil
+3VS
VR_HOT#
77
78
79
80
63
64
65
66
75
76
TP_DATA
KB_LED_PWM
BEEP# <22>
USB_EN#
<24,25>
ACOFF
<37>
0.1U_0402_10V7K
11
24
35
94
113
CE29
<42>
RE37
0_0402_5%
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
SIO_SLP_S3#
CE27
ESD@
0.1U_0402_10V7K
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
PS2 Interface
GND/GND
GND/GND
GND/GND
GND/GND
GND0
PCH_DPWROK
KB_LED_PWM
BEEP#
USB_EN#
ACOFF
CE9
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
21
23
26
27
2
4.7K_0402_5%
"KB_LED_PWM" for OAK 17 only

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
67
9
22
33
96
111
125
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
AD Input
"TOUCH_RST" for OAK 15 only
+3VS
PWM Output
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
SD034750280
<11> EC_SCI#
<31> TOUCH_RST
CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
TOUCH_RST
<36>
CE8
0.1U_0402_10V7K
<9> CLK_PCI_LPC
<10,21,26,48,6>
PLT_RST#
1 47K_0402_5%
2
CE11
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
ECAGND
RE5
33K_0402_1%
DIS@
Rb
TP_CLK
AGND/AGND
RE8
+3VALW
@EMI@
R2354
0_0402_5%
1
2
3
4
5
7
8
10
69
@EMI@
CE12
0.1U_0402_10V7K
KB_RST#
SERIRQ
LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
AD_BID0
75K_0402_1%
ECAGND
<11> KB_RST#
<11> SERIRQ
<9> LPC_LFRAME#
<9> LPC_LAD3
<9> LPC_LAD2
<9> LPC_LAD1
<9> LPC_LAD0
UMA@
CE7
0.1U_0402_10V7K
UE1
2
+3VLP
@EMI@
CE6
1000P_0402_50V7K
@EMI@
CE5
1000P_0402_50V7K
CE2
0.1U_0402_10V7K
RE3
100K_0402_1%
Ra
CE1
0.1U_0402_10V7K
+EC_VCCA
12K_0402_1%
27K_0402_1%
33K_0402_1%
43K_0402_1%
56K_0402_1%
75K_0402_1%
100K_0402_1%
+3VALW
1
D
Venus DIS@
UMA UMA@
EMI@
LE1
FBMA-L11-160808-800LMT_0603
+3VALW
SD034120280
SD034100300
SD034430280
SD034430280
SD034560280
SD034750280
SD034100380
Title

EC ENE-KB9012
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
30
of
55
eDP@
<19>
EDP_HPD_PANEL
RX53 1
EDP_HPD_PANEL
2 0_0402_5%
CE_EN_R
Close to JLVDS
For eDP co-layout
LCD PWR CTRL
LVDS Connector
JLVDS
+LCDVDD
W=60mils
<19>
<30>
TL_ENVDD
LVDS_A1LVDS_A1+
LVDS_A1LVDS_A1+
APL3512ABI-TRG_SOT23-5
<19>
<19>
LVDS_A2LVDS_A2+
LVDS_A2LVDS_A2+
<19>
<19>
LVDS_ACLKLVDS_ACLK+
LVDS_ACLKLVDS_ACLK+
<19>
<19>
LVDS_B0LVDS_B0+
LVDS_B0LVDS_B0+
USB20_CAM_P7_R
<19>
<19>
LVDS_B1LVDS_B1+
USB20_CAM_N7_R
<19>
<19>
LVDS_B2LVDS_B2+
<19>
<19>
LVDS_BCLKLVDS_BCLK+
WCM-2012HS-900T_4P
<12>
ENVDD_R
10K_0402_5%
RX9
USB20_CAM_P7
0_0402_5%
2
RX8
EN
RX7
EC_ENVDD
SS
<19>
<19>
DISPOFF#
RB751V-40_SOD323-2
CX8
4.7U_0805_10V4Z
GND
CX11
0.1U_0402_10V7K
TL_BKOFF#
FBMA-L11-201209-221LMA30T_0805
LX1
VIN
4
CX9
0.1U_0402_10V7K
CX7
4.7U_0805_10V4Z
VOUT
<19>
W=60mils
1
LVDS_A0LVDS_A0+
UX1
LVDS_A0LVDS_A0+
DX1
+LCDVDD_CONN
+3VS
<19>
<19>
<12>
0_0402_5%
Css
Tss
0.1uF
100mS
10nF
10mS
1nF
1mS
Open or
tied to
VIN
1mS
USB20_CAM_N7
LX6
EMI@
SS table
RX22
@EMI@
W=60mils
0_0402_5%
LVDS_B1LVDS_B1+
CE_EN_R
LVDS_B2LVDS_B2+
DBC_EN_R
LVDS_BCLKLVDS_BCLK+
+LCDVDD_CONN
+3VS
USB20_CAM_P7_R
USB20_CAM_N7_R
RX21
@EMI@
0_0402_5%
<22>
+3VS_CAM
MIC_CLK
MIC_CLK
MIC_DATA
LCD_TEST
<22> MIC_DATA
<30> LCD_TEST
<19> EDID_CLK
<19> EDID_DATA
CE_EN_R only for reserve.
TL_INVT_PWM
@
RX18
0_0402_5%
CE_EN_R
DBC_EN
DBC_EN_R
@
RX20
0_0402_1%
+3VS
CX3
10U_0805_10V6K
CX1
+INV_PWR_SRC
Place close to JLVDS
RX2
100K_0402_5%
CX5
0.1U_0603_25V7K
PWR_SRC_ON
CX4
1000P_0402_50V7K
6
5
2
1
+LCDVDD
0.1U_0402_10V7K
CX2
60mil
+INV_PWR_SRC
B+
0.1U_0402_10V7K
QX2
SI3457CDV-T1-GE3_TSOP6
41
42
43
44
45
46
STARC_107K40-000001-G2
CONN@
LCD backlight PWR CTRL

60mil
G1
G2
G3
G4
G5
G6
@
RX23
0_0402_5%
@
RX19
0_0402_1%
W=60mils
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DBC_EN
+INV_PWR_SRC
RX26
100K_0402_5%
CE_EN
<30>
CE_EN
<30>
DISPOFF#
<19>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RX3
100K_0402_5%
* Touch Screen Panel

+5VS
D
EN_INVPWR
QX1
2N7002KW_SOT323-3
<30>
+5VS_TOUCH
+5VS_TOUCH
2
@
RX28
0_0603_1%
CX6
0.1U_0402_16V7K
JTOUCH
ACES_88460-00601-P01
+5VS_TOUCH
Webcam PWR CTRL
<12>
<12>
1
+3VS
TOUCH_RST_R
RX24
100K_0402_5%
+3VS_CAM
<30>
1
A
USB20_TOUCH_N5
USB20_TOUCH_P5
1
2
3
4
5
6
USB20_TOUCH_N5
USB20_TOUCH_P5
TOUCH_RST
7
8
CONN@
SP010013W00
RX1
0_0402_5%
@
RX27
0_0603_1%
OAK 15 only
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
1
2
3
4
5 G1
6 G2
Title
LVDS/webcam/touch
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
31
of
55
SATA HDD Connector

JHDD
<8>
<8>
1
CS105
CS106
SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C
<8>
<8>
CS109
CS108
SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C
2
2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
2
2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
1
2
3
4
5
6
7
+3VS
<11>
DEVSLP0
+5V_HDD Source
<11>
RS7
RS8
2 0_0402_5%
@
2 0_0402_5%
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
JHDD_P10
HDD_DET#
HDD_DET#
+5V_HDD
+5V_HDD
@
JP13
+5VS
JUMP_43X79
GND
A+
AGND
BB+
GND
GND
GND
23
24
VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12
SANTA_193202-1
CONN@
SHORT DEFAULT
+5V_HDD
JP7
1
CS7
10U_0805_10V6K
ODD Power Control
1
CS6
0.1U_0402_25V6K
1000P_0402_50V7K
1
CS5
2
SATA ODD Connector

+5VS_ODD
Pleace near ODD Connector
JUMP_43X79
S
G
SI3456BDV-T1-E3 1N TSOP6
<8>
<8>
RS6
470K_0402_5%
<8>
<8>
SATA_PTX_DRX_P1_C
SATA_PTX_DRX_N1_C
SATA_PRX_DTX_N1_C
SATA_PRX_DTX_P1_C
ODD_EN
D
ODD_EN#
QS3
2N7002KW_SOT323-3
<11>
CS8
CS9
2
2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
CS14
CS15
2
2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
<8>
CS16
0.1U_0603_25V7K
<11>
1
2
3
4
5
6
7
8
9
10
11
12
13
ODD_DETECT#
ODD_DA#
JODD
B+
1U_0402_6.3V6K
1
CS13
CS12
10U_0805_10V6K
+5VS_ODD
CS11
0.1U_0402_25V6K
QS2
6
5
2
1
CS10
1000P_0402_50V7K
+5VS
CS17
0.1U_0402_25V6K
ESD@
GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
GND
GND
NPTH1
NPTH2
14
15
16
17
SANTA_202801-1
CONN@
Place CS17 close to JODD
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
Title
2014/04/01

HDD/ODD
Size
Document Number
Rev
0.2
LA-9981P
Date:
G
Sheet
32
H
of
55
Screw Hole
1
H32
H33
H_3P7
@
H_3P7
@
H6
H_2P8
@
H35
H_3P3
@
H_3P7X3P2N
@
H34
H_3P7
@
H31
H12
H_2P8
@
H_3P7
@
CPU bracket
H18
H_2P8
@
H11
H_2P8
@
H17
H_2P8
@
H9
H_2P8
@
H16
H8
H_2P8
@
1
C
H5
H_2P8
@
H4
H_2P8
@
H2
H7
H_3P3
@
VGA stand-off
H_3P3
@
H10
H_3P3
@
FAN stand-off
FD4
@ FIDUCIAL
FD3
@ FIDUCAL
FD2
@ FIDUCIAL
FD1
@ FIDUCAL
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
Screw Hole
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
33
of
55
Version Change List ( P. I. R. List )

Item Page#
1
34
Title
Card Reader
Date
Request
Owner
2012/04/27
HW
Page 1
Issue Description
Solution Description
The Card reader USB signal is incorrect.
SWAP UR1 USB signal
Rev.
P/N
0.2
2
D
3
4
5
6
7
8
9
10
11
12
13
14
C
15
16
17
18
19
20
21
22
23
24
25
26
27
B
28
29
30
31
32
33
34
35
36
37
38
A
39
40
41
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
2014/04/01
5
Title

HW-PIR Page.1
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
34
of
55

Item Page#
Title
Date
Request
Owner
Page 2
Issue Description
Rev.
40
41
D
42
43
44
45
46
47
48
49
50
51
52
53
C
54
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
2014/04/01
5
Title

HW-PIR Page.2
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
35
of
55
VIN
D
G
2
2
<30>
PSID@
PR3
PSID@
2.2K_0402_5%
+5VALW
+3VALW
PQ5
PSID@
MMST3904-7-F_SOT323~D
B
E
PSID@
PR9
15K_0402_1%
PS_ID
10K_0402_1%
PSID@
PR6
100K_0402_1%
PR8
1
2
PL2
C8B BPH 853025_2P
PSID-3
PQ6
PSID@
FDV301N_G 1N SOT23-3
PSID-2
PSID-1
ACES_50299-00501-003
CONN@
PSID
6
7
GND
GND
EMI@
PC4
100P_0402_50V8J
EMI@ PL4
C8B BPH 853025_2P
PC2
EMI@
100P_0402_50V8J
1
2
3
4
5
1
2
3
4
5
EMI@
PC1
1000P_0402_50V7K
PJPDC
PR4
PSID@
33_0402_5%
EMI@
PC3
1000P_0402_50V7K
PL1 EMI@
C8B BPH 853025_2P
ADPIN
EMI@
BATT+
BATT++
BATT+
EMI@
PL3
SMB3025500YA_2P
BATT++
PC8
EMI@
1000P_0402_50V7K
PC7
EMI@
0.01U_0402_25V7K
PD1
4
5
SMART
Battery:
01.GND1
02.GND2
03.BAT_ALERT
04.SYS_PRES
05.BATT_PRS
06.DAT_SMB
07.CLK_SMB
08.BATT1+
09.BATT2+
6
PBATT
1
2
3
4
5
6
7
8
9
GND
GND
1
2
3
4
5
6
7
8
9
10
11
EMI@
V I/O
V I/O
V BUS Ground
V I/O
V I/O
3
2
1
BATT_TEMP
<30,37>
AZC099-04S.R7G_SOT23
PR18
100_0402_5%
SUYIN_200028MR009G502ZL
CONN@
PR20
100_0402_5%
PR16
10K_0402_1%
PR15
100_0402_5%
BAT_ALERT
SYS_PRES
BATT_PRS
DAT_SMB
CLK_SMB
+3VALW
EC_SMB_CK1
<30,37>
EC_SMB_DA1
<30,37>
Other component (37.1)

ADP_I
ADP_I(with selector)
Delay adaptor OC H_PROCHOT#

2ms while hybrid power
transition
PH1 under CPU bottem side :

CPU thermal protection at 93 +/- 3 degree C
+EC_VCCA
PR23
150K_0402_1%
H_PROCHOT#
<30,6>
H_PROCHOT#
1
PR7
<10,30,37,49>
0.1U_0402_25V6
4
PR10
1M_0402_1%
PQ1B
L2N7002DW1T1G_SC88-6
1
6
2
1
PC5
1
200K_0402_1%
PR1
2
1
PC16
.1U_0402_16V7K
PQ2A
1M_0402_1%
PR28
10K_0402_1%
3 2
4
1M_0402_1%
ACIN
1
PQ2B
1
2
3
4
5
PR33
PQ3B
5
PR32
100K_0402_1%
2
1
BATT_PRS 1
1M_0402_1%
VIN
H_PROCHOT#
+3VALW
PR31
Erp lot6 Circuit
VIN
PC14
.1U_0402_16V7K
ECAGND
PR5
3.3K_1206_5%~D
asserts H_PROCHOT# when adaptor is

unplugged, keep low for 10ms
till SW PROCHOT# is issued by EC
<30>
3 2
Battery protection:
if battery removed, adaptor only,

then trigger the H_PROCHOT#,
keep @ in BOM since battery can not
be removed by end user
PH1
100K_0402_1%_TSM0B104F4251RZ
Adapter protection:
VCIN0_PH
<30>
<30>
VCOUT1_PH
PQ4
2N7002W-T/R7_SOT323-3
PQ3A
<30>
1
1
65W#/90W
PR29
100K_0402_1%
1
1
H_PROCHOT#
PR26
499K_0402_1%
PC13
@.1U_0402_16V7K
PC15
0.01U_0402_25V7K
2
PR27
392K_0402_1%
VCIN1_PH
<30>
PR24
12.1K_0402_1%
PR30
160K_0402_1%
PQ1A
<30,37>
+RTCBATT
Issued Date
Compal Secret Data

2013/03/09
Deciphered Date
2014/04/01
B
JRTC
LOTES_AAA-BAT-054-K01
CONN@
Title
PWR_DCIN/BATT CONN/OTP
Size
Document Number
Rev
0.2
LA-9981P
Date:

D
Sheet
36
of
55
Iada=0~3.33A(65W)
Iada=0~4.62A(90W)
CHG_B+
ADP_I = 40*Iadapter*Rsense
19
LX_CHG
4
1
PC724
100U_25V_M
1
2
PR710
IOUT
SRN
CELL
/BATDRV
12
3
2
1
0_0402_5%
TP
/BATDRV
PC722
0.1U_0402_25V6
@
PC719
0.1U_0402_25V6
PC720
100P_0402_50V8J
11
ADP_I
2
<30,36>
BQ24717
21
10
REGN
0_0402_5%
PC715
680P_0402_50V7K
@EMI@
PR722
4.7_1206_5%
@EMI@
13
PR708
SRP
14
PQ705
SIRA14DP-T1GE3_POWERPAK-SO8-5
+VCHGR
ACOK
0_0402_5%~D
PC713
10U_0805_25V5K~D
GND
@ PR714
<30,36> EC_SMB_CK1
DL_CHG
SCL
15
LODRV
SDA
PR716
0.01_1206_1%
PL701
2.2UH_FDVE1040-H-2R2M-P3_14.2A_20%
Near PL701
PC714
10U_0805_25V5K~D
PC712
10U_0805_25V5K~D
PHASE
DH_CHG
BST_CHGA
PC716
10U_0805_25V5K~D
ACDET
18
PQ704
MDU1516URH_POWERDFN56-8-5
HIDRV
BST
3
2
1
ACDRV
17
PR707
100K_0402_1%
ACDET
BTST
PC718
10U_0805_25V5K~D
0_0402_5%~D
PR713
10K_0402_1%
CMSRC
PC721
0.047U_0603_25V7K
PR712
158K_0402_1%
ACIN
<30,36> EC_SMB_DA1
PC705
EMI@
2200P_0402_25V7K
1
2
REGN
PQ703
MDU1516URH_POWERDFN56-8-5
16
REGN
ACIN <10,30,36,49>
@ PR715
ACDRV
B+
3
2
1
REGN
PR723
324K_0402_1%
1
ACN
VCC
ACP
20
CMSRC
PR711
49.9K_0402_1%
PR706
4.02K_0402_1%
/BATDRV
PC709
1U_0603_10V6K
PR709
2.2_0603_5%
VIN
PD701
BAT54HT1G_SOD323-2~D
VCC
PC711
0.01UF_0402_25V7K
2
1
PC708
0.1U_0402_25V6
PC717
0.1U_0402_25V6
PU701
2
BATT+
8
7
6
5
1
1
PC710
1U_0603_25V6K
1
2
3
PR704
0_0402_5%
1U_0603_25V6K
PR705
10_1206_5%
PC707
PR703
4.02K_0402_1%
For DT Mode
PC706 @EMI@
0.1U_0603_25V7K
VIN
PC704
10U_0805_25V6K
CSIN
PR721
4.02K_0402_1%
PC703
10U_0805_25V6K
PQ702
AO4407AL_SO8
+VCHGR
CSIP
2
2
1
2
PR701
4.7_0402_1%
1
2
PC701
0.1U_0603_25V7K
PR717
0_0402_5%
PQ706
2N7002KW_SOT323-3
PC702
0.1U_0402_25V6
EMI@
PL702
1UH_PCMB053T-1R0MS_7A_20%
PR702
0.01_1206_1%
D2
ACOFF
1
<30>
PR720
3.3K_1206_5%~D
D1
PQ701
CSD87312Q3E_SON8-4
VIN
3S2P : CV = 13.3V CC: 1.54A

4S1P: CV = 17.7V CC: 1.1A
2
G
PR724
0.01U_0402_25V7K
for LEARN mode disable

(pulse)
PQ708
2N7002KW_SOT323-3
100K_0402_1%
BATT_TEMP
PC723
<30,36>
PC720 Close EC pin
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
A
Title
PWR_CHARGER
Size
Document Number
Rev
0.2
LA-9981P
Date:

D
Sheet
37
of
55
+3VLP
PC109
1U_0603_10V6K
@ PC102
100P_0402_50V8J
PR109
6.49K_0402_1%
Output capacitor ESR need follow

below equation to make sure feed back
loop stability
ESR=20mV*L*fsw/2V
@ PC108
100P_0402_50V8J
PR104
15K_0402_1%
VFB=2V
VFB=2V
PR107
10K_0402_1%
PR106
10K_0402_1%
3/5V_B+
BST_3V
TPS51225CRUKR_QFN20_3X3
SW2
SW1
VBST2
DRVL1
UG_5V
5
3
2
1
1
2
PC106
1U_0603_10V6K
1
2
@ PC105
1U_0603_25V6K
1
2
@ PJP101
+3VALW
+5VALWP
PAD-OPEN 4x4m
@ PJP102
PAD-OPEN 4x4m
@ PJP103
2
PAD-OPEN 4x4m
Issued Date
+5VALW
5VALWP
TDC 5.96A
Peak Current 8.51A
OCP current 10.2A
TYP
MAX
H/S Rds(on):22mohm , 30mohm
L/S Rds(on):10.8mohm , 13.6mohm
Place PD101 close to PU100

C
Compal Secret Data

2013/03/09
Deciphered Date

2014/04/01
B
1
+
PAD-OPEN 4x4m
EMI@
PC100
4.7U_0603_6.3V6K
VCOUT0_PH#
PD101
+5VALWP
PR102
2.2K_0402_5%
EC_ON
Change to 4.7u for TPS51285
@ PJP100
VL
+3VALWP
5V_EN
PL101
2.2UH_PCMB063T-2R2MS_8A_20%
0_0402_5%~D
5V_EN
L03ESDL5V0CG3-2_SOT-523-3
0_0402_5%~D
1
@ PR101
<30>
15
VO1
VREG5
14
16
PR111
PC110
2.2_0402_5% 0.1U_0402_10V7K
+5VALWP
3V_EN
DRVH1
BST_5V
LG_5V
3/5V_B+
@ PR100
<30>
13
12
11
VIN
DRVL2
DRVH2
LX_5V
LG_3V
3V_EN
3VALWP
TDC 5.95A
Peak Current 8.5A
OCP current 10.2A
TYP
MAX
H/S Rds(on): 22mohm , 30mohm
L/S Rds(on):10.8mohm ,13.6mohm
10
1
2
3
UG_3V
PQ102
MDV1525URH 1N PDFN33-8
1
2
2
3
@EMI@ PC103
@EMI@ PR113
680P_0603_50V8J
4.7_1206_5%
1
+
ESR=17m ohm
PC101
220U_6.3V_M
VBST1
18
17
ESR=17m ohm
PC107
220U_6.3V_M
@EMI@ PC111
@EMI@ PR112
680P_0603_50V8J 4.7_1206_5%
LX_3V
PR103
2.2_0402_5%
PR114
@
200_0402_5%
PQ103
5V_EN
PC104
0.1U_0402_10V7K
20
19
VCLK
PGOOD
3
2
1
21
EN1
1
2
PAD
PC112
10U_0805_25V6K
CS1
1
CS1
FB_5V
2
VFB1
VREG3
FB_3V
VFB2
CS2
EN2
PQ104
3V_EN
1
2
3
PQ101
1
2
1
2
PC115
10U_0805_25V6K
EMI@ PC114
2200P_0402_50V7K
@EMI@ PC113
0.1U_0402_25V6
PL100
2.2UH_PCMB063T-2R2MS_8A_20%
+3VALWP
PU100
POK need pull high, it

will pull high on VS
transfer circuit
2
84.5K_0402_1%
CS2
3/5V_B+
PR108
90.9K_0402_1%
B+
PR105
EMI@
PL102
Title
PWR_3.3VALWP/5VALWP
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
E
38
of
55
PJP401
+1.5VSP
+1.5VS
JUMP_43X79
PR401
0_0402_5%
PR403
15K_0402_1%
Rup
FB_1.5VSP
SY8003DFC_DFN8_2X2
+1.5VSP
1
LX_1.5VSP
PC400
22U_0805_6.3VAM
NC
PL400
1UH_PH041H-1R0MS_3.8A_20%
PGND
LX
PC402
22U_0805_6.3VAM
PC405
22U_0805_6.3VAM
EN
IN
JUMP_43X79
PG
PC404
68P_0402_50V8J
9
8
<28,30,40>
Note:Iload(max)=2.5A
PGND
SGND
SUSP#
PR404
1M_0402_5%
FB
+3VALW
@EMI@ PR405
4.7_0603_5%
1
PJP400
SUSP#
PU400
0.1U_0402_16V7K
PC403
+1.5VSP_ON
@EMI@ PC401
680P_0402_50V7K
FB=0.6V
PR402
10K_0402_1%
Rdown
2
Note:Iload(max)=3A
PJP601
+1.8VSP
+1.8VS
JUMP_43X79
PR601
VGA@
0_0402_5%
1
FB_1.8VSP
VGA@
PR602
10K_0402_1%
Rdown
2
1
2
@EMI@ PC601
680P_0402_50V7K
FB=0.6V
Note:Iload(max)=3A
Rup
VGA@
PC600
22U_0805_6.3VAM
+1.8VSP
VGA@
PR603
20K_0402_1%
VGA@
SY8003DFC_DFN8_2X2
VGA@
PC602
22U_0805_6.3VAM
LX_1.8VSP
VGA@
NC
PL600
1UH_PH041H-1R0MS_3.8A_20%
PGND
LX
PC604
68P_0402_50V8J
EN
IN
Note:Iload(max)=2.5A
PC605
22U_0805_6.3VAM
VGA@
PG
JUMP_43X79
FB
<10,11,43,44,50>
PR604 VGA@
1M_0402_5%
3
1
+3VALW
9
8
PJP600
PGND
SGND
@EMI@ PR605
4.7_0603_5%
PXS_PWREN
PXS_PWREN
VGA@
PU600
0.1U_0402_16V7K
PC603
+1.8VSP_ON
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
A
Title
PWR_1.5VSP / 1.8VSP
Size
Document Number
Rev
0.2
LA-9981P
Date:

D
Sheet
39
of
55
EN pin don't floating

If have pull down resistor at HW side, pls delete PR301
PR300
0_0402_5%
SUSP#
<28,30,39>
@ PC300
0.22U_0402_10V6K
1M_0402_1%
PR301
@EMI@ PR302
@EMI@ PC301
4.7_1206_5%
680P_0603_50V7K
1
2SNB_1.05V 1
2
EMI@ PL302
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
+1.05VSP
@ PJP300
1
2
PL301
LDO_3V
SY8206DQNC_QFN10_3X3
+1.05VS
FB = 0.6V
1
2
Rup
+3VALW
PR307
Rdown
20K_0402_1%
@ PR306
0_0402_5%
PC311
22U_0805_6.3VAM
LDO
PC310
22U_0805_6.3VAM
PG
BYP
PC309
47U_0805_6.3V6M
PR308
10K_0402_5%
ILMT
ILMT_1.05V
+1.05V_PGOOD
+1.05VSP
LX_1.05V
PC313
4.7U_0603_6.3V6K
FB
10
LX
PC308
47U_0805_6.3V6M
GND
BST_1.05V 1
JUMP_43X118
PR303
PC302
0_0603_5% 0.1U_0603_25V7K
BS
PC307
330P_0402_50V7K
EN
PR305
15K_0402_1%
IN
1
2
10U_0805_25V6K
PC306
1
2
10U_0805_25V6K
PC305
1
2
+3VS
ILMT_1.05V
B+_1.05V
PC312
4.7U_0603_6.3V6K
@ PR304
0_0402_5%
2
@EMI@ PC304
0.1U_0402_25V6
LDO_3V
EMI@ PC303
2200P_0402_50V7K
B+
PU300
<30>
B
+1.05V_PGOOD
Pin 7 BYP is for CS.

Common NB can delete
The current limit is set to 6A, 8A or 12A when this pin

is pull low, floating or pull high
+3VALW and PC313
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V
+1.05VSP
TDC 5A
Peak Current 6.6A
OCP current 8A
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date
2014/04/01
5
Title

PWR_+VCCIO
Size
C
Date:
Document Number
Rev
0.2
Sheet
1
40
of
55
EMI@
0.675Volt +/- 5%
TDC 0.7A
Peak Current 1A
BOOT_1.35V
1
2
PC211
10U_0805_6.3V6K
VTTREF_1.35V
C
FB
+1.35VP
VTT
3
4
PC210
0.033U_0402_16V7K
S3
PR207
54.9K_0402_1%
+1.35VP
PC205
10U_0805_6.3V6K
20
19
18
1
1.35V_B+
21
1
FB_1.35V
PR208
1M_0402_1%
1.35VP
TDC 6A
Peak Current 8A
OCP current 10A
BOOT
17
+5VALW
EN_0.675VSP
PC209
1U_0603_10V6K
VDDQ
S5
VDD
TON
@EMI@ PR203
4.7_1206_5%
+5VALW
VTTREF
10
11
VDD_1.35V
RT8207MZQW_WQFN20_3X3
PQ201
AON7702A
GND
VDDP
12
1
2
3
PR201
0_0402_5%
SYSON
PR204
68.1K_0402_1%
<30>
@ PC202
0.1U_0402_10V7K
PAD
VTTSNS
CS
PR206
5.1_0603_5%
13
CS_1.35V
PC204
1U_0603_10V6K
PC213
330U_2.5V_M
@EMI@ PC207
680P_0402_50V7K
EN_1.35V
1
2
3
PU200
VTTGND
PGND
PR205
11.8K_0402_1%
2
1
VLDOIN
LGATE
PHASE
15
DL_1.35V
PGOOD
UGATE
16
PC200
0.1U_0603_25V7K
14
PL200
+0.675VSP
SW_1.35V
1
2
5
PQ200
AON7408L
+1.35VP
+1.35VP
DH_1.35V
1
2
BST_1.35V
PC212
10U_0805_25V6K
1
2
PR200
2.2_0603_5%
PC206
10U_0805_25V6K
1
2
EMI@
PC201
2200P_0402_50V7K
1.35V_B+
TON_1.35V
@EMI@
PC208
0.1U_0402_25V6
B+
PL201
PR202
0_0402_5%
0.675V_DDR_VTT_ON
<17>
@ PJP200
@ PC203
0.1U_0402_10V7K
+1.35VP
+1.35V
JUMP_43X118
@ PJP201
JUMP_43X118
@ PJP203
+0.675VSP
+0.675VS
JUMP_43X39
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
PWR_+1.35VP/0.675VSP
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
41
of
55
2
1
PR502
9.31K_0402_1%
2
1
2
1
B+
PL501
EMI@
+VCC_PWR_SRC
1
+
PC516
100U_25V_M
PC515
100U_25V_M
1
2
PC521
EMI@
2200P_0402_25V7K
1
2
PC519 @EMI@
0.1U_0402_25V6
1
2
PC518
10U_0805_25V6K
PC517
10U_0805_25V6K
PR506
150K_0402_1%
PR505
75K_0402_1%
F-IMAX
EMI Part (47.1)
O-USR
PR509
150K_0402_1%
B-RAMP
PR503
75K_0402_1%
PR507
75_0402_1%
2
1
PR501
523K_0402_1%
OCP_CPU
PC509
1000P_0402_50V7K
PR512
10K_0402_5%~D
2
1
PR513
39K_0402_5%
Near PU502.
B value:4250K
4700P_0603_50V7K
PC508
IMON_CPU
PH502
100K_0402_1%_TSM0B104F4251RZ
PR514
75_0402_1%
PR504
499K_0402_1%
VREF_CPU
THERM_CPU
PR522
0_0402_5%
SLEWA_CPU
VR_ENABLE
<13,30>
10
@
PR510
75_0402_1%
TI recommend 1nF
<13>
+3VS
B value:3435K
1
2
PR515
3.01K_0402_1%
CSN1_CPU
1
2
PR530
130_0402_1%
PC512
.1U_0402_16V7K
@
PR528
75_0402_5%
@
PR526
54.9_0402_1%
VR_HOT#
2
1
1
<13>
PR517
16.5K_0402_1%
PC511
0.082U_0402_16V7K
+1.05VS
PR533
56_0402_1%
<13>
Near PL502.
PC504
1U_0402_6.3V6K
PC506
47P_0402_50V8J
1
2
<13>
PH501
10K_0402_1%_TSM0A103F34D1RZ
PC505
1U_0603_10V6K
<30>
PR519
10_0603_1%
PR518
2.32K_0402_1%
CSP1_CPU
PC510
0.082U_0402_16V7K
+5VS
+CPU_CORE
10K_0402_1%~D
<30>
H_VR_READY
IMVP_PWRGD
+3VS
1_0603_5%
VR_SVID_DAT
PC507
0.33U_0402_10V6K
PC514
1500P_0402_50V7K
VR_SVID_ALRT#
VREF_CPU
1
PR529
5.76K_0402_1%
@EMI@
PR534
4.7_1206_5%
PAD
PC503
1U_0603_10V6K
PR524
PR516
2
VR_SVID_CLK
PR532
10K_0402_1%
CSD97374CQ4M_SON8_3P5X4P5
+5VS
6
5
0_0402_5%
2.2_0603_5%
SW_CPU2
SKIP#1
V5A_CPU
PR531
3.65K_0402_1%
PR536
PL502
0.22UH_PCMB104T-R22MS_35A_20%
4
3
2
1
PR540
2 @
1
PGND2
PWM
BOOT VSW
PGND1
BOOT_R VDD
VIN
SKIP#
@EMI@
PC520
680P_0402_50V7K
PC501 0.1U_0402_25V6
1000P_0402_50V7K
DROOP_CPU
COMP_CPU
PC502
PWM1
33
ALERT#
VCLK
PU502
9
8
7
SKIP#1
VDIO
32
VR_HOT#
VDD
31
VFB
1U_0402_6.3VX5R
9
O-USR
F-IMAX
B-RAMP
13
11
14
12
OCP-I
IMON
THERM
PGOOD
GFB
GND
24
N/C
30
23
N/C
29
22
PU3
SKIP#
PWM2
V5A
+3VS
Check are there a pair 100

at HW side and close to CPU.
@ PC513
390P_0402_50V7K
CPU_CORE
TDC 10A
Peak Current 32A
OCP current 40A
Load line -2mV/A
PWM1
PWM1
CSP2
VREF
VCCSENSE
21
PU501
TPS51622RSM_QFN32_4X4
CSN2
28
<13>
VR_ON
PR535 @
0_0402_5%~D
SKIP#
25
VSSSENSE
+3VS
VR_ON
CSN1
27
20
15
16
VBAT
19
CSP1
SLEWA
18
COMP
17
CSN1_CPU
DROOP
CSP1_CPU
<13,15>
PC522 @
VBAT_CPU
26
+VCC_PWR_SRC
PR508
10K_0402_5%~D
VR_SVID_CLK
VR_SVID_ALRT#
VR_SVID_DAT
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
PWR_VCORE
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
42
of
55
VGA@_EMI@ PL1100
HCB2012KF-121T50_0805
@
PR1110
100K_0402_5%
VFB
TST
V5IN
DRVL
SW
TP
UG_+1.2VSP
SW_+1.2VSP
1
2
+1.35VS_VGA
JUMP_43X118
+5VALW
LG_+1.2VSP
11
TPS51212DSCR_SON10_3X3
VGA@
PC1105
1U_0603_10V6K
+1.35VGPUP
PR1104 @EMI@
4.7_1206_5%
VGA@
PQ1101
AON7702A
PC1106 @EMI@
680P_0402_50V7K
1
+
3
2
1
PR1105 VGA@
470K_0402_1%
VGA@ PL1101
7
6
VGA@
PC1108
330U_2.5V_M
RF_+1.2VSP
EN
JUMP_43X118
@ PJP1101
DRVH
@ PJP1100
+1.35VGPUP
FB_+1.2VSP
VBST
TRIP
BST_+1.2VSP
PGOOD
10
B+
VGA@
PC1103
0.1U_0603_25V7K
EN_+1.2VSP
VGA@
@ PC1104
0.1U_0402_16V7K
PXS_PWREN
PR1102 VGA@
154K_0402_1%
1
2 TRIP_+1.2VSP
VGA@
PR1101
2.2_0603_5%
3
2
1
4
PU1100
PR1103 VGA@
0_0402_5%~D
VGA@
PQ1100
AON7408L
VGA@ PC1102
10U_0805_25V6K
TDC=9A
Peak Current=13A
OCP=16A
VGA@_EMI@ PC1101
2200P_0402_50V7K
+3VS
@EMI@ PC1100
0.1U_0402_25V6
+1.2VSP_B+
PR1107 VGA@
9.09K_0402_1%
PR1108 VGA@
10K_0402_1%
VDDCI_VID (GPIO_6)
VGA@ PR1206
0_0402_5%
PXS_PWREN
PXS_PWREN
<10,11,39,44,50>
High
0.95V
Low
0.9V
@ PC1200
0.22U_0402_10V6K
1M_0402_1%
PR1201
VGA@
+VDDCIP
VGA@_EMI@ PL1201
IN
EN
BS
9
GND
LX
ILMT
BYP
BST_VDDCI1
10
+VDDCIP
120K_0402_1%
<49>
PR1214 @
100K_0402_5%
@ PC1214
4700P_0402_25V7K
Deciphered Date

2014/04/01
3
GPU_GPIO6
PQ1201 VGA@
2N7002W-T/R7_SOT323-3
Compal Secret Data

2013/03/09
Issued Date
PR1213 VGA@
10K_0402_5%
PR1212 VGA@
10K_0402_5%
VGA@ PC1206
22U_0805_6.3VAM
VGA@ PR1210
0_0402_5%~D
+3VALW and PC1205
<52>
VGA@
PR1204
20K_0402_1%
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=0.9V
VDDCI_SEN
Rdown
VGA@ PC1201
22U_0805_6.3VAM
1
2
VGA@ PC1207
47U_0805_6.3V6M
1
2
VGA@ PC1211
47U_0805_6.3V6M
+3VGS
VGA@
+VDDCIP
TDC 7A
Peak Current 13A
OCP current 16A
PR1211
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
FB = 0.6V
VGA@
PR1208
10_0402_5%
Pin 7 BYP is for CS.

Common NB can delete
VGA@ PR1209
10K_0402_1%
@ PR1202
0_0402_5%
+3VALW
LDO
PG
Rup
5LDO_3V_VDDCI
4
7
VGA@ PC1205
4.7U_0603_6.3V6K
FB
ILMT_VDDCI
+VDDCI
VGA@ PL1200
LX_VDDCI
SY8208DQNC_QFN10_3X3
VGA@
VGA@
VGA@
PR1200
PC1210
0_0603_5% 0.1U_0603_25V7K
1
6
JUMP_43X118
10U_0805_25V6K
VGA@ PC1204
1
2
1
2
VGA@ PC1213
4.7U_0603_6.3V6K
ILMT_VDDCI
B+_VDDCI
10U_0805_25V6K
VGA@ PC1202
VGA@ PR1203
0_0402_5%
PU1200
2
@EMI@ PC1203
0.1U_0402_25V6
LDO_3V_VDDCI
VGA@_EMI@ PC1209
2200P_0402_50V7K
B+
@ PJP1200
@EMI@ PR1207
@EMI@ PC1212
4.7_1206_5%
680P_0603_50V7K
1
2SNB_1.05V 1
2
Title
PWR_+1.35VGPU/VDDCIP
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
43
of
55
GPU_B+
MDU1516URH 1N POWERDFN56-8
VGA@
1
2
VGA@
PC808
10U_0805_25V6K
909
1.4K
PR821
97.6K
143K
PR825
976
1.5K
+VGA_CORE
0.36UH_MMD-12CE-R36M-M1L_34A_20%
PR829 VGA@
3.65K_0402_1%
@EMI@ PC815
680P_0603_50V7K
VGA@ PL802
@EMI@ PR805
4.7_1206_5%
MDU1511RH 1N POWERDFN56
1
2
3
VGA@
PQ802
1
2
3
2ISUM-2 1
PR816 VGA@
2.61K_0402_1%
2
PH800
VGA@
10KB_0402_5%_ERTJ0ER103J
GPU_VID1
GPU_VID2
GPU_VID3
GPU_VID4
GPU_VID5
<49>
<49>
<49>
<49>
<49>
PR803 VGA@
PXS_PWREN
<10,11,39,43,50>
2
1
ISUM-1
@
@
@
@
@
@
@
PC820
VGA@
0.033U_0402_16V7K
PR811
PR810
PR812
PR807
PR809
PR806
PR804
1
1
1
1
1
1
1
PC819
VGA@
0.15U_0402_10V6K
25W@ PR825
976_0402_1%
2
2
2
2
2
2
2
VGA_CORE
Frequency 300kHz
TDC 23A(25W)/33A(32W)
Peak Current 30A(25W)/47A(32W)
OCP current 36A(25W)/56A(32W)
TYP
MAX
H/S Rds(on) :12.2mohm , 15mohm
L/S Rds(on) :2.75mohm ,
3.5mohm
Choke DCR 1.1mohm(Typ)/1.3mohm(Max)
Load line : -1.5mV/A
PC821
VGA@
.1U_0402_16V7K
PR827 VGA@
11K_0402_1%
VGA@ PC869
0.1U_0402_10V7K
MDU1511RH 1N POWERDFN56
+5VALW
62881_VID0
62881_VID1
62881_VID2
62881_VID3
VGA@
PC805
10U_0805_25V6K
PC804
10U_0805_25V6K
VGA@_EMI@
1
5
PC803 VGA@
2.2U_0603_6.3V6K
21
PR814 VGA@
0_0603_5%
20
VID2
VID3
VID4
2
13
IMON
14
19 62881_VCCP 1
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
VGA@
PQ801
18
+3VS
Core Voltage Level
VGA@
PQ803
PR813
17
DGPU_PWROK
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
(GPIO_10) (GPIO_14) (GPIO_15) (GPIO_16) (GPIO_20)
32W@
PQ800
32W
16 SW_VGA_CORE
PR808 @
10K_0402_1%
15 UG_VGA_CORE
0_0402_5%
BOOT
12 62881_VIN
VIN
ISUM+
11
VDD
ISUM-
10
9
ISUM
PR817 VGA@
8.06K_0402_1%
+3VS
<10,30>
22
23
VID1
24
VID0
62881_VID4
PGOOD
CLK_EN#
1
1
2
PR818 VGA@
715_0402_1%
VCCP
62881_VID5
1GFX_FB-2
2
LGATE
RBIAS
62881_VID6
2
VGA@ PC817
1000P_0402_50V7K
VW
VID5
VGA@ PC814
56P_0402_50V8
VSSP
25
VGA@ PC806
390P_0402_50V7K
2
47K_0402_1%
VGA@ PR815
PC818 VGA@
1000P_0402_50V7K
25W
VGA@ PR830
0_0402_5%
PR821 25W@
97.6K_0402_1%
1
2GFX_FB-1
1
2
COMP
VID6
62881_VW 4
3
62881_RBIAS
PR813 25W@
909_0402_1%
PC807 VGA@
0.1U_0603_25V7K
UGATE
26
62881_COMP 5
VGA@ PR802
0_0603_5%
BST_VGA_CORE
PU800 VGA@
ISL62881CHRTZ-T_QFN28_4X4 PHASE
FB
un-pop
3
2
1
PR824
0_0402_5%
LL@
VSEN
VR_ON
7
62881_FB 6
ISUM+
10_0402_5%
62881_VR_ON
27
PC809 @
330P_0402_50V7K
29
RTN
PC813
@
330P_0402_50V7K
AGND
PR846 VGA@
0_0402_5%
DPRSLPVR
2
PR820 @
28
VCCSENSE_VGA
1000P_0402_50V7K
<52>
Need
pop
VSSSENSE_VGA
VGA@
<52>
PC816
1K_0402_1%
PR842 VGA@
PR845 VGA@
0_0402_5%
VENUS PRO/XT
No need
+5VALW
10_0402_5%
+VGA_CORE
PR824
PR833 @
SUN XT
Load line
3
2
1
PR823 VGA@
PC811 VGA@
1U_0603_10V6K
GPU_B+
62881_VDD
GPU_B+
1
1
1_0603_5%
0_0603_5%
VGA@ PC810
0.22U_0603_25V7K
VGA@ PR822
@EMI@
PC831
0.1U_0402_25V6K~D
B+
+5VALW
PL800 VGA@_EMI@
FBMA-L11-453215-800LMA90T_1812
PC832
2200P_0402_50V7K~D
MDU1516URH 1N POWERDFN56-8
ISUM+
ISUMPR813
32W@
PR821
32W@
PR825
32W@
1.2V
1.175V
1.15V
1.125V
1.4K_0402_1%
+3VGS
143K_0402_1%
1.5K_0402_1%
PR828 @
0.975V
0.95V
0.925V
10K_0402_1%
PR837 VGA@
0.9V
0.875V
0.85V
0.825V
0.8V
VGA@ PR1301
10K_0402_1%
Vout=0.95V
10K_0402_1%
PR839 VGA@
GPU_VID5
PJP1300
10K_0402_1%
PR840 @
+VGA_PCIEP
1
5
1
2
1
2
VGA@ PC1308
22U_0805_6.3VAM
VGA@
VGA@
PC1306
1
22P_0402_50V8J
+VGA_PCIE
TDC 3A
Peak Current 4.2A
OCP current 6A
+VGA_PCIE
JUMP_43X79
10K_0402_1%
Compal Secret Data
PG
GPU_VID4
10K_0402_1%
PR838 @
1
A
PR1302
5.9K_0402_1%
1
1
@ PR1304
47K_0402_5%
VGA@ PC1305
22U_0805_6.3VAM
2EN_PCIE
200K_0402_5%
PXS_PWREN
GPU_VID3
VGA@ PC1303
22U_0805_6.3VAM
2
10K_0402_1%
PR836 VGA@
1V
VGA@ PC1300
22U_0805_6.3VAM
PR1303
4.7_1206_5%
@EMI@
@EMI@ PC1304
680P_0402_50V7K
10K_0402_1%
PR835 @
1.025V
FB_PCIE
SY8036LDBC_DFN10_3x3
SNUB_PCIE
FB
EN
+VGA_PCIEP
VGA@ PR1300
+VGA_PCIEP
LX
SVIN
1.05V
PVIN
LX
0.1U_0402_10V7K
VGA@
PC1301
22U_0805_6.3VAM
SS
JUMP_43X79
GPU_VID2
TP
2
10K_0402_1%
PR834 SUN@
LX_PCIE
1.075V
PC1302
LX
VGA@
PVIN
11
VGA@ PL1300
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
PU1300
10
PCIE_B+
10K_0402_1%
PR826 VENUS@
1.1V
PJP1301
+3VALW
PC1307 VGA@
0.1U_0402_10V7K
VGA@
GPU_VID1
2
10K_0402_1%
PR819 VGA@
Initial voltage:0.85V(Venus)
0.9V(Sun)
0.775V
4
Issued Date
2013/03/09
Deciphered Date

2014/04/01
3
Title
PWR_VGA_CORE/PCIE
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
44
of
55
Issued Date
2013/03/09
Deciphered Date
1U_0402_6.3V6K
PC862
PC836
2014/04/01
1
1
25W@
330U_D2_2V_Y
PC837
Compal Secret Data
Date:
Size
25W@
330U_D2_2V_Y
PC838
32W@
470U_D2_2VM_R4.5M~D
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
1U_0402_6.3V6K
PC848
PC916
22U_0805_6.3V6M
1U_0402_6.3V6K
PC849
1U_0402_6.3V6K
PC850
1U_0402_6.3V6K
PC851
1U_0402_6.3V6K
PC852
1U_0402_6.3V6K
PC873
1U_0402_6.3V6K
PC853
1U_0402_6.3V6K
PC854
1U_0402_6.3V6K
PC855
1U_0402_6.3V6K
PC856
32W@
470U_D2_2VM_R4.5M~D
32W@
470U_D2_2VM_R4.5M~D
PC915
22U_0805_6.3V6M
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
1U_0402_6.3V6K
PC840
PC908
22U_0805_6.3V6M
PC907
22U_0805_6.3V6M
PC906
22U_0805_6.3V6M
PC905
22U_0805_6.3V6M
PC904
22U_0805_6.3V6M
PC903
22U_0805_6.3V6M
PC902
22U_0805_6.3V6M
PC901
22U_0805_6.3V6M
1U_0402_6.3V6K
PC841
1U_0402_6.3V6K
PC842
1U_0402_6.3V6K
PC843
1U_0402_6.3V6K
PC844
1U_0402_6.3V6K
PC845
1U_0402_6.3V6K
PC846
1U_0402_6.3V6K
PC847
1U_0402_6.3V6K
PC871
1U_0402_6.3V6K
PC872
32W@
470U_D2_2VM_R4.5M~D
1U_0402_6.3V6K
PC866
PC914
22U_0805_6.3V6M
1U_0402_6.3V6K
PC865
1U_0402_6.3V6K
PC864
PC913
22U_0805_6.3V6M
1U_0402_6.3V6K
PC863
VGA@
1
1U_0402_6.3V6K
PC861
PC912
22U_0805_6.3V6M
VGA@
VGA@
1
1U_0402_6.3V6K
PC860
VGA@
1U_0402_6.3V6K
PC859
VGA@
1U_0402_6.3V6K
PC858
VGA@
1U_0402_6.3V6K
PC857
PC911
22U_0805_6.3V6M
VGA@
VGA@
VGA@
VGA@
PC923
22U_0805_6.3V6M
PC922
22U_0805_6.3V6M
PC921
22U_0805_6.3V6M
PC920
22U_0805_6.3V6M
10U_0603_6.3V6M
PC835
VGA@
PC919
22U_0805_6.3V6M
PC910
22U_0805_6.3V6M
10U_0603_6.3V6M
PC870
10U_0603_6.3V6M
PC868
PC918
22U_0805_6.3V6M
PC909
22U_0805_6.3V6M
VGA@
10U_0603_6.3V6M
PC867
PC839
VGA@
PC838
PC837
PC836
VGA@
PC917
22U_0805_6.3V6M
5
2
1
+CPU_CORE
+VGA_CORE
1
D
25W@
330U_D2_2V_Y
PC839

1
25W@
330U_D2_2V_Y
B
B
A
A
Title
PWR_PROCESSOR DECOUPLING
Document Number
LA-9981P
Sheet
45
of
55
Rev
0.2
Power block
CPU OTP
Page 45
Turn Off
Input
Switch Page 46
DC IN
B+
+3VALWP: TDC:5.4A
+5VALWP: TDC:5.6A
TPS51225CRUKR
+3VALW
EC_ON
Page 47
+1.8VSP: TDC:2.5A
SY8003DFC
PXS_PWREN
Page 48
CHARGER
CC:0A~1A(4cell) or 2.1A(6cell)
CV:17.7V(4cell) / 13.3V(6cell)
BQ24717
+3VALW
+1.5VSP: TDC:2.5A
SY8003DFC
SUSP#
Page 46
Page 48
+3VALW
Battery
+VGA_PCIEP: TDC:3A
SY8036LDBC
PXS_PWREN
Page 53
PXS_PWREN
+VDDCIP: TDC:7A
SY8208DQNC
+VGA_CORE
TDC: 23A / 33A
ISL62881CHRTZ-T
PXS_PWREN
Page 52
Page 53
SUSP#
+VCCIO: TDC:5A
SY8206DQNC
VR_ON
+CPU_CORE
TDC: 14A
TPS51622RSM
Page 49
+1.35VP/+0.675VSP: TDC:6A/0.7A
RT8207MZQW
Page 51
SYSON
Page 50
+1.35VGPUP: TDC:9A
TPS51212DSCR
PXS_PWREN
Page 52
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
PWR_POWER BLOCK DIAGRAM

Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
46
of
55

D
Item Page#
1
45
50
Title
CHARGER
VCORE
Date
13/01/30
13/01/30
Request
Owner
Morris
Morris
Page 1
Issue Description
adjust design parameter from vendor recommend
delete
change
change
change
change
change
change
adjust design parameter from vendor recommend
PD702
PC712
PQ704
PC707
PC720
PC711
PQ705
Rev.
0.2
to unpop
to unpop
from 0.1uF_0402 to 1uF_0603
from 0.1uF to 100pF
from 1000pF to 0.01uF
from SB00000SD00 to SB00000WY00
change PC509 from 0.1uF to 1000pF

change PR529 from 3.83K to 5.76K
change PR504 from 523K to 499K
0.2
44
DCIN/BATT CONN/OTP
13/01/30
Morris
change from ESD request
change PD1 from SC300002E00 to SC300001G00
0.2
46
3.3VALWP/5VALWP
13/02/01
Morris
add ESD diode from ESD request
add PD101(SCA00002A00)
0.2
50
VCORE
13/02/21
Morris
adjust design parameter from fine tune result

0.2
52
VGA_CORE/PCIE
13/02/21
Morris
unpop from EE request
unpop PR808
0.2
52
VGA_CORE/PCIE
13/03/05
Morris
adjust output voltage from vender request
unpop PR826 and pop PR834 (only for Sun XT)
0.2
Compal Secret Data
Issued Date
2013/03/09
Deciphered Date

2014/04/01
5
Title
PWR-PIR
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
47
of
55
GFX PCIE LANE REVERSAL

D
UV1A
<12>
<12>
PEG_CTX_GRX_P0
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
PEG_CTX_GRX_N0
AA38
Y37
<12>
<12>
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
Y35
W36
<12>
<12>
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
W38
V37
<12>
<12>
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
V35
U36
U38
T37
R38
P37
P35
N36
N38
M37
M35
L36
L38
K37
K35
J36
J38
H37
H35
G36
G38
F37
F35
E37
B
PCIE_TX0P
PCIE_TX0N
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCI EXPRESS INTERFACE
T35
R36
PCIE_RX0P
PCIE_RX0N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
Y33
Y32
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
2
1 CV43 DIS@
1 CV44 DIS@
PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
<12>
<12>
W33 PCIE_CRX_C_GTX_P1
W32 PCIE_CRX_C_GTX_N1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
2
1 CV45 DIS@
1 CV46 DIS@
PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
<12>
<12>
U33 PCIE_CRX_C_GTX_P2
U32 PCIE_CRX_C_GTX_N2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
2
1 CV47 DIS@
1 CV48 DIS@
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
<12>
<12>
U30 PCIE_CRX_C_GTX_P3
U29 PCIE_CRX_C_GTX_N3
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
2
1 CV49 DIS@
1 CV50 DIS@
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
<12>
<12>
LVDS Interface
UV1G
LVDS CONTROL
T33
T32
VARY_BL
DIGON
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
T30
T29
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
P33
P32
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
P30
P29
TXOUT_U3P
TXOUT_U3N
N33
N32
AK27
AJ27
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36
LVTMDP
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
N30
N29
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
L33
L32
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
L30
L29
TXOUT_L3P
TXOUT_L3N
K33
K32
J33
J32
AP34
AR34
AW37
AU35
AR37
AU39
AP35
AR35
AN36
AP37
216-0833000-A11-THAMES-XT-M2_FCBGA962~D
VENUS@
K30
K29
H33
H32
B
CLOCK
+3VGS
PCIE_REFCLKP
PCIE_REFCLKN
AH16
1K_0402_5%
AA30
PCIE_CALRN
+VGA_PCIE
Y29
+VGA_PCIE
2 DIS@
CV326
0.1U_0402_25V6K
PERSTB
<10>
DGPU_HOLD_RST#
<10,21,26,30,6>
PLT_RST#
THAMES XT M2
IN1
IN2
VENUS@
DIS@
RV66
100K_0402_5%
DIS@
RV203
1K_0402_1%
GPU_RST#
PWRGOOD
Y30
PCIE_CALRP
DIS@
1
RV64
Place CV326 Close to UV13
DIS@
RV198
1.69K_0402_1%~D
CALIBRATION
VCC
CLK_PEG_VGA
CLK_PEG_VGA#
AB35
AA36
GND
<9>
<9>
CLK_PEG_VGA
CLK_PEG_VGA#
OUT
GPU_RST#
UV13
DIS@
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
5
Title
ATI_Sun XT_M2_PCIE/LVDS
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
48
of
55
CONFIGURATION STRAPS
UV1B
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE

GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET
AU24
AV23
TXCAP_DPA3P
TXCAM_DPA3N
AT25
AR24
TX0P_DPA2P
TX0M_DPA2N
1
2
3
4
2
2
2
2
@
@
@
@
@
RV81 GPU_GPIO11
RV82 GPU_GPIO12
RV83 GPU_GPIO13
RV85 AC_BATT
8
7
6
5
GPIO24_TRSTB
GPIO25_TDI
GPIO27_TMS
GPIO26_TCK
RP47
10K_8P4R_5%
AK24
+1.8VGS
R
RB
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6
G
GB
B
BB
DAC1
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
1U_0402_6.3V6K
DIS@
CV83
0.95V@Venus
+DPLL_PVDD AM32
AN32
DPLL_PVSS
20mil
+DPLL_VDDC AN31
+3VGS
XTALIN
XTALOUT
XTALIN
Voltage Swing: 1.8 V
RV235
10K_0402_5%
@
+DPLL_VDDC
AW35
GPU_THERMAL_D+ AF29
GPU_THERMAL_D- AG29
Add 12/6 for MLPS

AK32
TS_FDO
(5mA)
AL31
(1.8V@20mA TSVDD)
1
2
BLM15BD121SN1D_0402
+1.8VGS
GND
GND
4
3
CV94
10P_0402_50V8J
CV95
10P_0402_50V8J
DIS@
10mil
AJ32
+TSVDD
1
AJ33
DIS@ CV93
0.1U_0402_16V7K
XTALIN
YV1
DIS@
27MHZ_10PF_7V27000050
DIS@ CV92
1U_0402_6.3V6K
XTALOUT
DIS@ CV91
10U_0603_6.3V6M
DIS@
LV16
RV97 DIS@
1M_0402_5%
GPIO[13:11]
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
XXX
V2SYNC
IGNORE VIP DEVICE STRAPS
1
1
2
2
C/NC
Y/NC
COMP/NC
AE36
AD35
GPU_VGA_G
T86
AF37
AE38
GPU_VGA_B
T87
AC36
AC38
GPU_VGA_HSYNC
GPU_VGA_VSYNC
AB34
VENUS@
RV84 1
0: disable
1: enable
+AVDD
AC33
AC34
+VDD1DI
4
6
1
RSVD
GENERICC
AUD[1]
HSYNC
AUD[0]
VSYNC
T88
T89
H2SYNC
(1.8V@65mA AVDD)
1
@
Transmitter Power Saving Enable

GPIO0 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
TX_DEEMPH_EN
PCI Express Transmitter De-emphasis Enable

GPIO1 0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)
+1.8VGS
RV237
8.45K_0402_1%
@
CV329
GPU_GPIO6
A2VDDQ/NC
RV238
4.75K_0402_1%
SUN@
AF33
SUN@
RV207
RV242
4.75K_0402_1%
SUN@
Hynix 2Gb
SA00006H40L(R1)
SA00006H41L(R3)
128MX16 (1GB)
DDR3
RV242
Bits [3:1]
NC
4.75K
000
8.45K
2K
001
4.75K
NC
111
K4W2G1646E-BY11
Samsung 2Gb
SA00005SH0L(R1)
SA00005SH1L(R3)
128MX16 (1GB)
DDR3
MT41K128M16JT-107G:K
Micron 2Gb
SA00005XB0L(R1)
SA00005XB1L(R3)
128MX16 (1GB)
DDR3
AN20
AM20
AUX2P
AUX2N
RV241
H5TC2G63FFR-11C
AM19
AL19
XO_IN
AL30
AM30
AL29
AM29
DDCCLK_AUX4P
DDCDATA_AUX4N
AN21
AM21
DDCCLK_AUX5P
DDCDATA_AUX5N
TS_FDO
For DGPU output display Debug

(For Venus ASIC)
AJ30
AJ31
DDC6CLK
DDC6DATA
AK30
AK29
DDCCLK_AUX7P
DDCDATA_AUX7N
TSVDD
TSVSS
RV240
4.75K_0402_1%
SUN@
CV333
Vendor
2
0_0402_5%
NC_TSVSSQ should be tied to GND
AM27
AL27
AUX1P
AUX1N
TS_A/NC
RV241
8.45K_0402_1%
@
PS_3
<43>
AM26
AN26
DDC1CLK
DDC1DATA
DDC2CLK
DDC2DATA
THERMAL
CV331
SUN@
DPLL_PVDD
DPLL_PVSS
XO_IN2
RV239
10K_0402_1%
@
PS_2
+1.8VGS
PS_3
AA29
R2SET/NC
XTALIN
XTALOUT
AG33
AD33
VREFG
PLL/CLOCK
DPLL_VDDC
+1.8VGS
PS_1
A2VDD/NC
DDC/AUX
GPIO8
T80
T81
PS_2
GPU_GPIO6
GPIO2
SUN@
LV12
BLM15BD121SN1D_0402
2 +DPLL_PVDD
0_0402_5%
RV247
1
2 DPLL_PVSS
@
0_0402_5%
AG31
AG32
11
TX_PWRS_ENB
RV246
GENLK_CLK
GENLK_VSYNC
0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
GENERICC
+1.8VGS
65mA
2
+1.8VGS
SUN@
LV13
BLM15BD121SN1D_0402
ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET
GPIO21
100mA
10mil
(1.8V@100mA VDD1DI) 1
PS_1
H2SYNC
AMD RESERVED CONFIGURATION STRAPS
2 499_0402_1%
10mil
AD34
AE34
AD29
AC29
H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC
HPD1
DPLUS
DMINUS
T85
RSVD
DAC2
GPU_VGA_DDCCLK
GPU_VGA_DDCDAT
T90
T91
SUN Internal VGA Thermal Sensor

Address 0x714
VENUS@
GPU_VGA_R
AC32
AD32
AF32
DDCCLK_AUX3P
DDCDATA_AUX3N
RV236
10K_0402_5%
DIS@
ROMIDCFG(2:0)
AF30
AF31
B2/NC
B2B/NC
1U_0402_6.3V6K
DIS@
CV87
10U_0603_6.3V6M
DIS@
CV86
TS_FDO
1
AV33
AU34
AW34
2
1
BLM15BD121SN1D_0402
LV15
0.1U_0402_16V7K
DIS@
CV88
DIS@
AH13
For DGPU output display Debug

(For Venus ASIC)
AD39
AD37
AD30
AD31
G2/NC
G2B/NC
A2VSSQ/TSVSSQ
RV248
0_0402_1%
(125mA)
+VGA_PCIE
+VREFG_GPU
ACIN_65W
AT23
AR22
AC30
AC31
R2/NC
R2B/NC
20mil
2
1
CV81 0.1U_0402_16V7K
1
SUN@
@
ENABLE EXTERNAL BIOS ROM
TX5P_DPD0P
TX5M_DPD0N
SCL
SDA
VDD2DI/NC
VSS2DI/NC
+DPLL_PVDD
0.1U_0402_16V7K
DIS@
CV84
(75mA)
10U_0603_6.3V6M
DIS@
CV82
DIS@
2
1
BLM15BD121SN1D_0402
LV14
<30>
AU22
AV21
TX4P_DPD1P
TX4M_DPD1N
20mil
SUN@
2 RV93
1 499_0402_1%
SUN@
2 RV95
1 249_0402_1%
RESERVED
GPIO_22_ROMCSB
VIP_DEVICE_STRAP_ENA
AT21
AR20
TX3P_DPD2P
TX3M_DPD2N
DPD
ACIN
RV250
0_0402_5%
@
AU20
AT19
TXCDP_DPD3P
TXCDM_DPD3N
SWAPLOCKA
SWAPLOCKB
<10,30,36,37>
AT17
AR16
TX2P_DPC0P
TX2M_DPC0N
0.60 V level, Please

VREFG Divider ans
cap close to ASIC
+1.8VGS
GPIO21
BIOS_ROM_EN
10K_0402_5% 1
10K_0402_5% 1
10K_0402_5% 1
10K_0402_5% 1
RSVD
RP60
10K_8P4R_5%
0.68U_0402_10V
GPU_VID1
VGA ENABLED
<44>
GPIO9
RV89 1
GPU_GPIO8
GPU_GPIO9
BIF_VGA DIS
GPU_GPIO2
RESERVED
GPU_VID3
GPU_VID2
GPIO8
0.68U_0402_10V
<44>
<44>
RSVD
GPU_GPIO0
GPU_GPIO1
0: 2.5GT/s
1: 5GT/s
8
7
6
5
Advertises PCIE speed

when compliance test
2 RV75
2 RV76
@
@
@
GPU_VID5
GPIO2
1
2
3
4
<44>
RSVD
0.68U_0402_10V
10K_0402_5% 1
10K_0402_5% 1
GPU_VID4
AU16
AV15
TX1P_DPC1P
TX1M_DPC1N
DIS@
QV14B
1
2
2
10U_0603_6.3V6M
VENUS@
CV77
STRAPS
+3VGS
<44>
AT15
AR14
1U_0402_6.3V6K
VENUS@
CV76
@
RV252
0_0402_5%
AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
GPU_GPIO8
AH15
GPU_GPIO9
AJ16
GPU_VID5
AK16
GPU_GPIO11
AL16
GPU_GPIO12
AM16
GPU_GPIO13
AM14
AM13
GPU_VID3
AK14
GPU_VID2
AG30
THM_ALERT#
AN14
2 10K_0402_5%
AM17
AL13
GPU_VID1
AJ14
GPIO21_BBEN
AK13
T78
VGA_CLKREQ#_R AN13
GPIO24_TRSTB AM23
AN23
GPIO25_TDI
AK23
GPIO26_TCK
AL24
GPIO27_TMS
AM24
GPIO28_TDO
T79
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
VGA_SMB_DA2_R
VGA_SMB_CK2_R
AC_BATT
GPU_VID4
PACIN#
0.1U_0402_16V7K
VENUS@
CV75
@
RV251
0_0402_5%
2
2
1
1
0: disable
1: enable
AC_BATT
QV14A
DIS@
10U_0603_6.3V6M
VENUS@
CV80
DPC
GENERAL PURPOSE I/O
VGA_SMB_DA2
VGA_SMB_CK2
PCIE TRANSMITTER DE-EMPHASIS
AU14
AV13
TX0P_DPC2P
TX0M_DPC2N
I2C
AK26
AJ26
PCIE FULL TX OUTPUT SWING
GPIO1
10K_0402_5%
DIS@
1U_0402_6.3V6K
VENUS@
CV79
AJ21
AK21
RV73
4.7K_0402_5%
AT33
AU32
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
RV85 PU
chg to @
RV74
AR32
AT31
TX4P_DPB1P
TX4M_DPB1N
0.1U_0402_16V7K
VENUS@
CV78
GPU_GPIO1
GPU_GPIO2
N.C
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
N.C
N.C
DPB
+3VGS
AV31
AU30
TX3P_DPB2P
TX3M_DPB2N
GPIO0
TX_DEEMPH_EN
GPIO1
GPIO2
GPIO7
GPIO11
GPIO12
GPIO13
GPIO14
GPIO18
TXCBP_DPB3P
TXCBM_DPB3N
TX_PWRS_ENB
0: 50% swing
1: Full swing
+3VGS
AR30
AT29
SUN GPIO N.C. PIN
AT27
AR26
TX2P_DPA0P
TX2M_DPA0N
RECOMMENDED
SETTINGS
DESCRIPTION OF DEFAULT SETTINGS
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
PIN
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
STRAPS
AU26
AV25
TX1P_DPA1P
TX1M_DPA1N
DPA
MUTI GFX
DIS@
VGA Thermal Sensor SMB

+3VGS
+3VGS
For GCLK
1
2
DIS@
QV15B
4
3
S
VGA_SMB_DA2
QV28 @
2N7002K_SOT23-3
EC_SMB_CK2
<19,30,9>
EC_SMB_DA2
<19,30,9>
VGA_CLKREQ#_R
PEG_CLKREQ#
VGA_SMB_CK2
<9>
DIS@
RV91
10K_0402_5%
2
DIS@
RV90
10K_0402_5%
@
RV199
2.2K_0402_5%
+3VGS
+3VGS
XTALIN
XTALIN
<29>
DIS@
QV15A
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
5
Title
ATI_Sun XT_M2_Main_MSIC
Size
Docum ent Num ber
Rev
0.2
LA-9981P
Date:

1
Sheet
49
of
55
PX_MODE=1 for Normal Operation

PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail
Switch circuits in BACO desingns for Thames/Seymour only

55mA@1.0V, in BACO mode
Note:
PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON
PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF
PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF
+3VALW
+VGA_PCIE
+3VGS
1
PXS_PWREN
PXS_PWREN
+VGA_CORE
60mil
2
0_0805_5%
RV234
SUN@
PXS_PWREN#
0_0603_5%~D
for PX5.0
2
<10,11,39,43,44>
1
RV103
VENUS@
@
RV105
20K_0402_5%
+BIF_VDDC
60mil
DIS@
RV109
100K_0402_5%
QV25 DIS@
2N7002K_SOT23-3
DIS@
CV97
22U_0805_6.3V6M
C
for PX4.0 and PX5.0
+1.8VS TO +1.8VGS
Power seguence of Sun XT,Venus Pro,Venus XT
+1.8VS
+3VS TO +3VGS
+1.8VGS
+3VS
+3VGS
JP8 @
1
2MM
2MM
+VGA_CORE
+5VALW
+VDDCI(+VGA_PCIE)
DIS@
RV107
DIS@
RV108
1
20K_0402_5%
+1.35VS_VGA TO +1.35V_MEM_GFX
2
3
+1.35V_MEM_GFX
G
+1.35VS_VGA
CV102
1U_0603_10V6K
QV22 DIS@
AP2301GN-HF_SOT23-3
D
PXS_PWREN
+1.8VGS
1K_0402_5%
+1.35V_MEM_GFX
+1.0VGS
1 DIS@
CV101
10U_0603_6.3V6M
SHORT DEFAULT
1 DIS@
J9
+3VGS
QV24
DIS@
CV103
0.1U_0603_25V7K
DIS@
2N7002K_SOT23-3
<20ms
JP9 @
1
2MM
SHORT DEFAULT
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
5
Title
ATI_Sun XT_M2_BACO POWER

Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
50
of
55
UV1F
(30mA)
+DPAB_VDD18
1.8V@300mA DPAB_VDD18)
20mil
@ CV119
0.1U_0402_16V7K
@ CV118
1U_0402_6.3V6K
@ CV117
10U_0603_6.3V6M
AP13
AT13
20mil
AP22
AP23
(330mA)
2
AP14
AP15
1 RV122 AW18
VENUS@ CV120
10U_0603_6.3V6M
20mil
1.0V@240mA DPEF_VDD10)
0.95V@Venus
@ CV125
0.1U_0402_16V7K
@ CV124
1U_0402_6.3V6K
@VENUS@
RV126
0_0402_1%
VENUS@ CV109
1U_0402_6.3V6K
+VGA_PCIE
2
@
RV120
0_0402_1%
20mil
DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2
DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2
DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2
DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2
AP25 130mA
AP26
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
20mil
DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5
DPCD_CALR
DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5
DPAB_CALR
AN33 110mA
AP33
AN29
AP29
AP30
AW30
AW32
VENUS@
RV123
150_0402_1%
AW28
20mil
+DPAB_VDD18
AH34
AJ34
DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2
20mA
DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS
10mil
AU28
AV27
+DPAB_VDD18
AL33
AM33
20mA
DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2
DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS
DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4
DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS
10mil
AV29
AR28
+DPCD_VDD18
AN34
AP39
AR39
AU37
20mA
20mil
1
AF34
AG34
20mil
20mA
20mA
DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS
AK33
AK34
PS_0
10mil
AM37
AN38
+DPEF_VDD18
DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2
20mA
DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS
AF39
AH39
AK39
AL34
AM34
10mil
AV19
AR18
+DPEF_VDD18
DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2
+DPEF_VDD10
10mil
AU18
AV17
+DPCD_VDD18
DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS
+DPEF_VDD18
+DPEF_VDD10
+DPAB_VDD10
+DPAB_VDD10
AN27
AP27
AP28
AW24
AW26
+DPEF_VDD10
+DPEF_VDD10
@ CV123
10U_0603_6.3V6M
VENUS@ CV122
0.1U_0402_16V7K
+DPEF_VDD18
@VENUS@
RV124
0_0402_1%
VENUS@ CV121
1U_0402_6.3V6K
DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5
AP31
AP32
+DPEF_VDD18
1.8V@300mA DPEF_VDD18)
(330mA)
+DPAB_VDD10
20mil
150_0402_1% 2 DIS@
+VGA_PCIE
DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5
DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2
2
@
RV118
0_0402_1%
0.95V@Venus
+DPCD_VDD10
(220mA)
DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2
+1.8VGS
+DPAB_VDD18
AN19
AP18
AP19
AW20
AW22
+1.8VGS
110mA
+DPCD_VDD18
+DPCD_VDD10
AN24
AP24
20mil (1.0V@220mA DPAB_VDD10)
AN17
AP16
AP17
AW14
AW16
+DPCD_VDD10
@VENUS@
RV121
0_0402_1%
DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2
+DPCD_VDD10
130mA
DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2
10U_0603_6.3V6M
VENUS@ CV116
20mil
DP A/B POWER
1U_0402_6.3V6K
VENUS@ CV115
CV113
0.1U_0402_16V7K
1.0V@220mA DPCD_VDD10)
0.95V@Venus
CV112
1U_0402_6.3V6K
CV111
10U_0603_6.3V6M
(220mA)
AP20
AP21
+DPCD_VDD18
DP C/D POWER
VENUS@ CV114
0.1U_0402_16V7K
2
@VENUS@
RV119
0_0402_1%
+VGA_PCIE
20mil
+DPCD_VDD18
1.8V@300mA DPCD_VDD18)
1
VENUS@ CV108
0.1U_0402_16V7K
UV1H
(30mA)
+1.8VGS
VENUS@ CV110
10U_0603_6.3V6M
+DPAB_VDD18
AL38
AM35
10mil
DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5
+1.8VGS
AM39
VENUS@
RV127
150_0402_1%
SUN@
RV243
8.45K_0402_1%
DPEF_CALR
VENUS@
MLPS Bit
PS_0
@
CV335
0.68U_0402_10V
SUN@
RV201
2K_0402_1%
Thames/Seymour Only
AMD recommended setting

strap
R_PU
R_PD
PS0:
11001
RV243=8.45K
RV201=2K
CV335=NC
PS1:
11000
RV237=NC
RV238=4.75K
CV329=NC
PS2:
00000
RV239=NC
RV240=4.75K
CV331=0.68u
PS3:
11000
RV241=NC
RV242=4.75K
CV333=NC
GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35
@
RV125
4.7K_0402_5%
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
A39 MECH#1
AW1 MECH#2
AW39MECH#3
T82 PAD
T83 PAD
T84 PAD
VENUS@
Do not install for Heathrow/Mars Pro

PS_0 Should be tied to GND on Thames/Seymour
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
5
Title
ATI_Sun XT_M2_PWR_GND
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
51
of
55
(440mA)
+1.8VGS
@
(1.8V@504mA PCIE_VDDR)
+PCIE_VDDR
LV17
10mil
AF23
AF24
AG23
AG24
2
+1.8VGS
VENUS@
LV20
20mil
2
+VDDR4 AF13
AF15
AG13
AG15
(150mA)
+1.8VGS
0.1U_0402_16V7K
VENUS@
CV194
1U_0402_6.3V6K
VENUS@
CV193
BLM15BD121SN1D_0402
AD12
AF11
AF12
AG11
M20
M21
LV21 DIS@
DIS@
+VDDCI
<44>
VCCSENSE_VGA
<43>
+SPV10
AN9
AN10
RV202
10_0402_1%
DIS@
VCCSENSE_VGA
VDDCI_SEN
VDDCI_SEN
DIS@
SPV18
SPV10
SPVSS
VOLTAGE
SENESE
AF28
FB_VDDC
10mil
VSSSENSE_VGA
VSSSENSE_VGA
MPV18#1
MPV18#2
10mil
<44>
+SPV18 AM10
+VGA_CORE
RV215
10_0402_1%
DIS@
NC_VDDRHB
NC_VSSRHB
PLL
H7
H8
0.1U_0402_16V7K
DIS@
CV217
1U_0402_6.3V6K
DIS@
CV216
10U_0603_6.3V6M
DIS@
CV215
MCK1608471YZF 0603
NC_VDDRHA
NC_VSSRHA
20mil
10mil
20mil
(120mA SPV10)
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6
+MPV18
0.95V@Venus
LV23
(100mA)
+VGA_PCIE
VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8
0.1U_0402_16V7K
DIS@
CV202
1U_0402_6.3V6K
DIS@
CV201
10U_0603_6.3V6M
DIS@
CV200
BLM15BD121SN1D_0402
V12
U12
(1.8V@75mA SPV18)
0.1U_0402_16V7K
DIS@
CV199
1U_0402_6.3V6K
DIS@
CV198
DIS@
10U_0603_6.3V6M
DIS@
CV197
LV22
MCK1608471YZF 0603
(50mA)
I/O
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
(M97, Broadway and Madison: 1.8V@150mA MPV18)

1
+1.8VGS
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
RV204
10_0402_1%
AG28
AH29
FB_VDDCI
FB_GND
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22
1U_0402_6.3V6K
DIS@
CV133
10U_0603_6.3V6M
DIS@
CV134
0.1U_0402_16V7K
DIS@
CV132
(PCIe 3.0 => 1.8V@80mA PCIE_PVDD)

2
1U_0402_6.3V6K
DIS@
CV150
10U_0603_6.3V6M
DIS@
CV151
1U_0402_6.3V6K
@
CV130
1U_0402_6.3V6K
@
CV129
1U_0402_6.3V6K
@
CV128
10U_0603_6.3V6M
@
CV131
1U_0402_6.3V6K
DIS@
CV149
1U_0402_6.3V6K
DIS@
CV148
1U_0402_6.3V6K
DIS@
CV147
(SUN) (VENUS)
(PCIe 2.0 => +0.95V@1920mA PCIE_VDDC)

(PCIe 3.0 => +0.95V@2.5A PCIE_VDDC)
+VGA_CORE
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
(20.5A)
1
CV327
330U_D2_2.5V_R6M
X@
55mA
+BIF_VDDC
For non-BACO designs, connect BIF_VDDC to VDDC.

For BACO designs - see BACO reference schematics
(GDDR3/DDR3 1.12V@4A VDDCI)

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
+VDDCI
(GDDR5 1.12V@16A VDDCI)
+VGA_CORE
LV25
4A
1
BLM15BD121SN1D_0402
LV26 @
BLM15BD121SN1D_0402
10U_0603_6.3V6M
DIS@
CV323
AF26
AF27
AG26
AG27
LEVEL
TRANSLATION
VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator
VENUS@
Issued Date
2013/03/09
Deciphered Date
2014/04/01
4
Compal Secret Data
(PCIe 2.0 => 1.8V@50mA PCIE_PVDD)
22U_0603_6.3V6M
DIS@
CV214
20mil
(SUN) (VENUS)
10U_0603_6.3V6M
DIS@
CV322
0.1U_0402_16V7K
DIS@
CV174
1U_0402_6.3V6K
DIS@
CV173
1U_0402_6.3V6K
DIS@
CV172
1U_0402_6.3V6K
DIS@
CV171
+1.8VGS
MBK1608121YZF_0603
10U_0603_6.3V6M
DIS@
CV324
10U_0603_6.3V6M
DIS@
CV213
1U_0402_6.3V6K
DIS@
CV325
1U_0402_6.3V6K
DIS@
CV212
1U_0402_6.3V6K
DIS@
CV190
1U_0402_6.3V6K
DIS@
CV189
1U_0402_6.3V6K
DIS@
CV188
10U_0603_6.3V6M
DIS@
CV187
(60mA)
POWER
10U_0603_6.3V6M
DIS@
CV170
+3VGS
1U_0402_6.3V6K
DIS@
CV211
BLM15BD121SN1D_0402
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE
1U_0402_6.3V6K
DIS@
CV210
(1.8V@110mA VDD_CT)
40mA
DIS@ LV18
1U_0402_6.3V6K
DIS@
CV209
DIS@ LV19
+VGA_PCIE
1U_0402_6.3V6K
DIS@
CV208
+BIF_VDDC
1U_0402_6.3V6K
DIS@
CV207
+PCIE_PVDD
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
1U_0402_6.3V6K
DIS@
CV146
0.1U_0402_16V7K
DIS@
CV156
+VDDC_CT
(50mA)
1
0.1U_0402_16V7K
DIS@
CV155
0.1U_0402_16V7K
DIS@
CV154
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
1U_0402_6.3V6K
DIS@
CV206
+1.8VGS
0.1U_0402_16V7K
DIS@
CV153
0.1U_0402_16V7K
DIS@
CV152
+1.35V_MEM_GFX
1
2
@
RV245
0_0402_5%
1U_0402_6.3V6K
DIS@
CV196
@
1
2 +PCIE_VDDR
RV244
0_0402_5%
1U_0402_6.3V6K
DIS@
CV205
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37
1U_0402_6.3V6K
DIS@
CV195
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD
1U_0402_6.3V6K
DIS@
CV204
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34
1U_0402_6.3V6K
DIS@
CV203
1U_0402_6.3V6K
DIS@
CV145
1U_0402_6.3V6K
DIS@
CV144
1U_0402_6.3V6K
DIS@
CV143
1U_0402_6.3V6K
DIS@
CV142
1U_0402_6.3V6K
DIS@
CV141
10U_0603_6.3V6M
DIS@
CV140
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
40mil
PCIE
10U_0603_6.3V6M
DIS@
CV139
10U_0603_6.3V6M
DIS@
CV138
(1.7)A
10U_0603_6.3V6M
DIS@
CV137
10U_0603_6.3V6M
DIS@
CV136
220U_B2_2.5VM_R35
CV135
MEM I/O
0.1U_0402_16V7K
@
CV127
UV1E
For GDDR5 MVDDQ = 1.35V

+1.35V_MEM_GFX
0.1U_0402_16V7K
@
CV126
MBK1608121YZF_0603
Title
ATI_Sun XT_M2_Power
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
52
of
55
L18
L20
L27
N12
AG12
RV206
1 DIS@
2 120_0402_1%
M12
M27
AH12
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1
WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
DDBIA0_0/QSA_0B/WDQSA_0
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
MVREFDA
MVREFSA
CKEA0
CKEA1
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
WEA0B
WEA1B
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
A32
C32
D23
E22
C14
A14
E10
D9
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
C34
D29
D25
E20
E16
E12
J10
D7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
A34
E30
E26
C20
C16
C12
J11
F8
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
J21
G19
ODTA0
ODTA1
H27
G27
CLKA0
CLKA0#
J14
H14
CLKA1
CLKA1#
K23
K19
RASA0#
RASA1#
K20
K17
CASA0#
CASA1#
K24
K27
CSA0#_0
M13
K16
CSA1#_0
K21
J20
CKEA0
CKEA1
K26
L15
WEA0#
WEA1#
<54>
MDA[0..63]
MDA[0..63]
MAA[14..0]
A_BA[2..0]
DQMA#[7..0]
QSA[7..0]
QSA#[7..0]
ODTA0
ODTA1
MAA[14..0]
<54>
A_BA[2..0]
<54>
<54>
<54>
<54>
<54>
<54>
CLKA0 <54>
CLKA0# <54>
<55>
MDB[0..63]
RASA0#
RASA1#
<54>
<54>
CASA0#
CASA1#
<54>
<54>
CSA0#_0
<54>
CSA1#_0
<54>
CKEA0
CKEA1
<54>
<54>
WEA0#
WEA1#
<54>
<54>
MDB[0..63]
MAB[14..0]
CLKA1 <54>
CLKA1# <54>
B_BA[2..0]
MAB[14..0]
<55>
B_BA[2..0]
<55>
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
+VDD_MEM15_REFDB
+VDD_MEM15_REFSB
Y12
AA12
DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63
DDR2
GDDR5/GDDR3
DDR3
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
DDBIB0_0/QSB_0B/WDQSB_0
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
MVREFDB
MVREFSB
WEB0B
WEB1B
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
H3
H1
T3
T5
AE4
AF5
AK6
AK5
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
T7
W7
ODTB0
ODTB1
L9
L8
CLKB0
CLKB0#
AD8
AD7
CLKB1
CLKB1#
T10
Y10
RASB0#
RASB1#
W10
AA10
CASB0#
CASB1#
P10
L10
CSB0#_0
AD10
AC10
CSB1#_0
U10
AA11
CKEB0
CKEB1
N10
AB11
WEB0#
WEB1#
DQMB#[7..0]
ODTB0
ODTB1
<55>
QSB[7..0]
<55>
QSB#[7..0]
<55>
<55>
<55>
C
CLKB0 <55>
CLKB0# <55>
CLKB1 <55>
CLKB1# <55>
RASB0#
RASB1#
<55>
<55>
CASB0#
CASB1#
<55>
<55>
CSB0#_0
<55>
CSB1#_0
<55>
CKEB0
CKEB1
<55>
<55>
WEB0#
WEB1#
<55>
<55>
DIS@
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
MAA0_8
MAA1_8
H23
J19
RV133 1
MAA13
MAA14
AD28
TESTEN
5.11K_0402_1%
AK10
AL10
TESTEN
T8
W8
MAB0_8
MAB1_8
GDDR5
+VDD_MEM15_REFDA
+VDD_MEM15_REFSA
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
GDDR5
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
UV1D
DDR2
GDDR3/GDDR5
DDR3
DDR2
GDDR5/GDDR3
DDR3
MEMORY INTERFACE A
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MEMORY INTERFACE B
UV1C
DDR2
GDDR3/GDDR5
DDR3
CLKTESTA
CLKTESTB
AH11
DRAM_RST
MAB13
MAB14
DRAM_RST#_R
VENUS@
@
CV218
0.1U_0402_16V7K
This basic topology should be used for DRAM_RST for DDR3/GDDR5.These

Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2
VENUS@
route 50ohms single-ended/100ohms diff

and keep short
Debug only, for clock observation, if not needed, DNI
5mil 5mil
@
RV137
51.1_0402_1%
@
RV136
51.1_0402_1%
@
CV219
0.1U_0402_16V7K
+1.35V_MEM_GFX
RV138
4.7K_0402_5%
@
DRAM_RST#_R
1
2
1
2
RV149
100_0402_1%
DIS@
+VDD_MEM15_REFSB
CV224
0.1U_0402_16V7K
DIS@
CV221
0.1U_0402_16V7K
DIS@
2
2
RV147
100_0402_1%
DIS@
CV223
0.1U_0402_16V7K
DIS@
RV148
100_0402_1%
+VDD_MEM15_REFSA
1
RV146
100_0402_1%
DIS@
RV142
40.2_0402_1%
DIS@
+VDD_MEM15_REFDB
DIS@
RV145
4.99K_0402_1%
DIS@
CV220
0.1U_0402_16V7K
DIS@
RV141
40.2_0402_1%
DIS@
10_0402_1%
DIS@
DIS@
CV222
120P_0402_50V9
+VDD_MEM15_REFDA
1 RV144
RV140
40.2_0402_1%
DIS@
RV139
40.2_0402_1%
DIS@
1 RV143 2
51.1_0402_1%
DIS@
DRAM_RST#
<54,55>
+1.35V_MEM_GFX
+1.35V_MEM_GFX
+1.35V_MEM_GFX
+1.35V_MEM_GFX
Issued Date
Compal Secret Data
2013/03/09
Deciphered Date
2014/04/01
5
Title
ATI_Sun XT_M2_MEM IF
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
53
of
55
CHANNEL A: 256MB DDR3

M8
H1
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
<53>
MDA[0..63]
<53>
MAA[14..0]
MDA[0..63]
MAA[14..0]
UV19
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA29
MDA27
MDA30
MDA26
MDA28
MDA24
MDA31
MDA25
D7
C3
C8
C2
A7
A2
B8
A3
MDA3
MDA5
MDA1
MDA6
MDA0
MDA4
MDA2
MDA7
VREFC_A2
VREFD_Q2
M8
H1
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
X76@
UV20
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA18
MDA22
MDA19
MDA23
MDA17
MDA20
MDA16
MDA21
D7
C3
C8
C2
A7
A2
B8
A3
MDA15
MDA10
MDA13
MDA11
MDA12
MDA8
MDA14
MDA9
+1.35V_MEM_GFX
CLKA0
CLKA0#
CKEA0
<53>
<53>
<53>
<53>
<53>
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
J7
K7
K9
K1
L2
J3
K3
L3
QSA3
QSA0
F3
C7
DQMA#3
DQMA#0
E7
D3
QSA#3
QSA#0
G3
B7
<53,55>
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
RESET
L8
NC
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
M2
N8
M3
CLKA0
CLKA0#
CKEA0
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
K1
L2
J3
K3
L3
QSA2
QSA1
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#2
DQMA#1
E7
D3
QSA#2
QSA#1
G3
B7
DRAM_RST#
T2
+1.35V_MEM_GFX
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
X76@
UV21
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA47
MDA42
MDA46
MDA43
MDA44
MDA41
MDA45
MDA40
D7
C3
C8
C2
A7
A2
B8
A3
MDA49
MDA52
MDA48
MDA53
MDA50
MDA54
MDA51
MDA55
+1.35V_MEM_GFX
A_BA0
A_BA1
A_BA2
J1
L1
J9
L9
M7
RV151
240_0402_1%
VENUS@
96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D
VENUS@
CLKA0 1
RV154
ZQ
J1
L1
J9
L9
M7
RV150
240_0402_1%
VENUS@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
T2
DRAM_RST#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE
ODT
CS
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ
NC
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
<53>
<53>
+1.35V_MEM_GFX <53>
A1
A8
C1
C9
D2
E9
F1
H2
H9
QSA5
QSA6
F3
C7
DQMA#5
DQMA#6
E7
D3
QSA#5
QSA#6
G3
B7
DRAM_RST#
T2
ODT
CS
RAS
CAS
WE
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ
J1
L1
J9
L9
M7
96-BALL
SDRAM DDR3L
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
L8
RV152
240_0402_1%
VENUS@
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE
K1
L2
J3
K3
L3
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
BA0
BA1
BA2
J7
K7
K9
CLKA1
CLKA1#
CKEA1
<53>
<53>
<53>
<53>
<53>
B1
B9
D1
D8
E2
E8
F9
G1
G9
VREFC_A4
VREFD_Q4
M8
H1
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
X76@
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA35
MDA38
MDA36
MDA37
MDA32
MDA39
MDA33
MDA34
D7
C3
C8
C2
A7
A2
B8
A3
MDA60
MDA58
MDA63
MDA56
MDA61
MDA59
MDA62
MDA57
+1.35V_MEM_GFX
M2
N8
M3
A_BA0
A_BA1
A_BA2
QSA#[7..0]
QSA#[7..0]
<53>
<53>
<53>
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
M8
H1
<53>
QSA[7..0]
QSA[7..0]
BA0
BA1
BA2
<53>
DQMA#[7..0]
DQMA#[7..0]
A_BA0
A_BA1
A_BA2
<53>
M2
N8
M3
<53>
<53>
<53>
VREFC_A3
VREFD_Q3
NC
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
M2
N8
M3
CLKA1
CLKA1#
CKEA1
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
K1
L2
J3
K3
L3
QSA4
QSA7
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#4
DQMA#7
E7
D3
QSA#4
QSA#7
G3
B7
DRAM_RST#
T2
+1.35V_MEM_GFX
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.35V_MEM_GFX
A_BA0
A_BA1
A_BA2
VREFC_A1
VREFD_Q1
X76@
J1
L1
J9
L9
M7
RV153
240_0402_1%
VENUS@
UV18
96-BALL
SDRAM DDR3L
BA0
BA1
BA2
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
RESET
ZQ
NC
NC
NC
NC
NC
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
+1.35V_MEM_GFX
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
96-BALL
SDRAM DDR3L
2
56_0402_1%
VENUS@
CLKA0# 1
RV155
1
2
1
VREFD_Q4
1
2
RV173
4.99K_0402_1%
VENUS@
1
2
RV172
4.99K_0402_1%
VENUS@
CV233
VENUS@
1
CV232
VENUS@
15mil
VREFC_A4
RV171
4.99K_0402_1%
VENUS@
1
CV231
VENUS@
1
2
2
1
CV230
VENUS@
1
2
1
2
1
CV229
VENUS@
1
1
2
CV227
VENUS@
1
2
1
2
CV226
VENUS@
RV170
4.99K_0402_1%
VENUS@
15mil
VREFD_Q3
0.1U_0402_16V7K
RV169
4.99K_0402_1%
VENUS@
15mil
VREFC_A3
RV163
4.99K_0402_1%
VENUS@
0.1U_0402_16V7K
RV168
4.99K_0402_1%
VENUS@
15mil
VREFD_Q2
+1.35V_MEM_GFX
RV162
4.99K_0402_1%
VENUS@
0.1U_0402_16V7K
15mil
VREFC_A2
+1.35V_MEM_GFX
RV161
4.99K_0402_1%
VENUS@
0.1U_0402_16V7K
RV167
4.99K_0402_1%
VENUS@
+1.35V_MEM_GFX
RV160
4.99K_0402_1%
VENUS@
0.1U_0402_16V7K
CV234
0.01U_0402_16V7K
VENUS@
15mil
0.1U_0402_16V7K
56_0402_1%
RV166
4.99K_0402_1%
VENUS@
+1.35V_MEM_GFX
RV159
4.99K_0402_1%
VENUS@
VREFC_A1
0.1U_0402_16V7K
0.1U_0402_16V7K
CLKA1# 1
RV165
15mil
VREFD_Q1
56_0402_1%
VENUS@
+1.35V_MEM_GFX
RV158
4.99K_0402_1%
VENUS@
15mil
VENUS@
RV157
4.99K_0402_1%
VENUS@
RV156
4.99K_0402_1%
VENUS@
CLKA1 1
RV164
+1.35V_MEM_GFX
+1.35V_MEM_GFX
CV228
VENUS@
+1.35V_MEM_GFX
CV225
0.01U_0402_16V7K
VENUS@
56_0402_1%
+1.35V_MEM_GFX
+1.35V_MEM_GFX
2013/03/09
Deciphered Date
2014/04/01
5
Title
1U_0402_6.3V6K
VENUS@
CV271
1U_0402_6.3V6K
VENUS@
CV270
1U_0402_6.3V6K
VENUS@
CV269
1U_0402_6.3V6K
VENUS@
CV268
1U_0402_6.3V6K
VENUS@
CV267
1U_0402_6.3V6K
VENUS@
CV266
1U_0402_6.3V6K
VENUS@
CV265
1U_0402_6.3V6K
VENUS@
CV264
1U_0402_6.3V6K
VENUS@
CV263
Compal Secret Data
Issued Date
1U_0402_6.3V6K
VENUS@
CV262
1U_0402_6.3V6K
VENUS@
CV261
1U_0402_6.3V6K
VENUS@
CV260
1U_0402_6.3V6K
VENUS@
CV259
1U_0402_6.3V6K
VENUS@
CV258
1U_0402_6.3V6K
VENUS@
CV257
1U_0402_6.3V6K
VENUS@
CV256
1U_0402_6.3V6K
VENUS@
CV255
+1.35V_MEM_GFX
1U_0402_6.3V6K
VENUS@
CV254
1U_0402_6.3V6K
VENUS@
CV253
1U_0402_6.3V6K
VENUS@
CV252
10U_0603_6.3V6M
VENUS@
CV251
10U_0603_6.3V6M
VENUS@
CV250
10U_0603_6.3V6M
VENUS@
CV249
10U_0603_6.3V6M
VENUS@
CV248
0.1U_0402_16V7K
VENUS@
CV247
0.1U_0402_16V7K
VENUS@
CV246
0.1U_0402_16V7K
VENUS@
CV245
0.1U_0402_16V7K
VENUS@
CV244
0.1U_0402_16V7K
VENUS@
CV243
0.1U_0402_16V7K
VENUS@
CV242
0.1U_0402_16V7K
VENUS@
CV241
0.1U_0402_16V7K
VENUS@
CV240
0.1U_0402_16V7K
VENUS@
CV239
0.1U_0402_16V7K
VENUS@
CV238
0.1U_0402_16V7K
VENUS@
CV237
0.1U_0402_16V7K
VENUS@
CV236
0.1U_0402_16V7K
VENUS@
CV235
+1.35V_MEM_GFX
2
A

ATI_Sun XT_M2_VRAM_A
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
54
of
55
CHANNEL B: 256MB DDR3
DQMB#2
DQMB#0
E7
D3
QSB#2
QSB#0
G3
B7
56_0402_1%
CV272
0.01U_0402_16V7K
DIS@
<53,54>
T2
DRAM_RST#
L8
1
DIS@
CLKB1 1
RV180
2
56_0402_1%
RV176
240_0402_1%
DIS@
DIS@
56_0402_1%
2
1
CLKB1# 1
RV181
J1
L1
J9
L9
M7
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ
NC
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CV273
0.01U_0402_16V7K
DIS@
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#
K1
L2
J3
K3
L3
QSB3
QSB1
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMB#3
DQMB#1
E7
D3
QSB#3
QSB#1
G3
B7
DRAM_RST#
T2
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
M7
RV177
240_0402_1%
DIS@
96-BALL
SDRAM DDR3L
RV191
4.99K_0402_1%
DIS@
RV192
4.99K_0402_1%
DIS@
ZQ
NC
NC
NC
NC
NC
CLKB1
CLKB1#
CKEB1
<53>
<53>
<53>
<53>
<53>
ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
K1
L2
J3
K3
L3
QSB6
QSB5
F3
C7
DQMB#6
DQMB#5
E7
D3
QSB#6
QSB#5
G3
B7
DRAM_RST#
T2
L8
J1
L1
J9
L9
M7
RV178
240_0402_1%
DIS@
15mil
+1.35V_MEM_GFX
15mil
RV193
4.99K_0402_1%
DIS@
CK
CK
CKE
ODT
CS
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ
NC
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDB38
MDB35
MDB36
MDB34
MDB39
MDB33
MDB37
MDB32
D7
C3
C8
C2
A7
A2
B8
A3
MDB63
MDB59
MDB58
MDB62
MDB57
MDB61
MDB56
MDB60
M2
N8
M3
CLKB1
CLKB1#
CKEB1
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#
K1
L2
J3
K3
L3
QSB4
QSB7
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMB#4
DQMB#7
E7
D3
QSB#4
QSB#7
G3
B7
DRAM_RST#
T2
+1.35V_MEM_GFX
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
15mil
J1
L1
J9
L9
M7
RV179
240_0402_1%
DIS@
15mil
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
RESET
ZQ
NC
NC
NC
NC
NC
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
+1.35V_MEM_GFX
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
RV189
4.99K_0402_1%
DIS@
15mil
15mil
VREFC_A4_B
RV196
4.99K_0402_1%
DIS@
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
+1.35V_MEM_GFX
VREFD_Q3_B
RV195
4.99K_0402_1%
DIS@
BA0
BA1
BA2
96-BALL
SDRAM DDR3L
RV188
4.99K_0402_1%
DIS@
VREFC_A3_B
+1.35V_MEM_GFX
B_BA0
B_BA1
B_BA2
+1.35V_MEM_GFX
RV187
4.99K_0402_1%
DIS@
RV194
4.99K_0402_1%
DIS@
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
+1.35V_MEM_GFX
VREFD_Q2_B
BA0
BA1
BA2
96-BALL
SDRAM DDR3L
RV186
4.99K_0402_1%
DIS@
RESET
J7
K7
K9
<53>
<53>
<53>
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
DML
DMU
VREFC_A2_B
0.1U_0402_16V7K
DIS@
CV275
VREFC_A1_B
0.1U_0402_16V7K
DIS@
CV274
1
2
RV190
4.99K_0402_1%
DIS@
DQSL
DQSU
RV185
4.99K_0402_1%
DIS@
0.1U_0402_16V7K
DIS@
CV276
15mil
VREFD_Q1_B
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
+1.35V_MEM_GFX
RV184
4.99K_0402_1%
DIS@
15mil
ODT
CS
RAS
CAS
WE
+1.35V_MEM_GFX
+1.35V_MEM_GFX
RV183
4.99K_0402_1%
DIS@
RV182
4.99K_0402_1%
DIS@
CK
CK
CKE
X76@
VREFCA
VREFDQ
+1.35V_MEM_GFX
M2
N8
M3
B_BA0
B_BA1
B_BA2
96-BALL
SDRAM DDR3L
+1.35V_MEM_GFX
+1.35V_MEM_GFX
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
VREFD_Q4_B
0.1U_0402_16V7K
DIS@
CV281
DIS@
CLKB0# 1
RV175
DQSL
DQSU
CLKB0
CLKB0#
CKEB0
+1.35V_MEM_GFX
BA0
BA1
BA2
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
F3
C7
MDB44
MDB43
MDB47
MDB40
MDB45
MDB41
MDB46
MDB42
M8
H1
QSB2
QSB0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
D7
C3
C8
C2
A7
A2
B8
A3
VREFC_A4_B
VREFD_Q4_B
2
56_0402_1%
ODT
CS
RAS
CAS
WE
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
MDB51
MDB52
MDB50
MDB53
MDB49
MDB54
MDB48
MDB55
DIS@
CLKB0 1
RV174
C
K1
L2
J3
K3
L3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
E3
F7
F2
F8
H3
H8
G2
H7
ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#
CK
CK
CKE
M2
N8
M3
<53>
<53>
<53>
<53>
<53>
J7
K7
K9
UV25
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
+1.35V_MEM_GFX
B_BA0
B_BA1
B_BA2
CLKB0
CLKB0#
CKEB0
B2
D9
G7
K2
K8
N1
N9
R1
R9
<53>
<53>
<53>
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
MDB15
MDB10
MDB14
MDB11
MDB12
MDB9
MDB13
MDB8
QSB#[7..0]
BA0
BA1
BA2
0.1U_0402_16V7K
DIS@
CV277
QSB#[7..0]
M2
N8
M3
B_BA0
B_BA1
B_BA2
<53>
<53>
<53>
<53>
QSB[7..0]
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
X76@
VREFCA
VREFDQ
+1.35V_MEM_GFX
QSB[7..0]
<53>
M8
H1
D7
C3
C8
C2
A7
A2
B8
A3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VREFC_A3_B
VREFD_Q3_B
RV197
4.99K_0402_1%
DIS@
MDB0
MDB4
MDB1
MDB6
MDB3
MDB7
MDB2
MDB5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
MDB27
MDB30
MDB26
MDB29
MDB25
MDB28
MDB24
MDB31
0.1U_0402_16V7K
DIS@
CV280
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
UV24
E3
F7
F2
F8
H3
H8
G2
H7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
D7
C3
C8
C2
A7
A2
B8
A3
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
X76@
VREFCA
VREFDQ
DQMB#[7..0]
DQMB#[7..0]
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
M8
H1
0.1U_0402_16V7K
DIS@
CV279
<53>
MAB[14..0]
VREFC_A2_B
VREFD_Q2_B
<53>
MAB[14..0]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
MDB20
MDB19
MDB21
MDB17
MDB23
MDB16
MDB22
MDB18
E3
F7
F2
F8
H3
H8
G2
H7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MDB[0..63]
MDB[0..63]
UV23
VREFCA
VREFDQ
M8
H1
<53>
VREFC_A1_B
VREFD_Q1_B
X76@
0.1U_0402_16V7K
DIS@
CV278
UV22
+1.35V_MEM_GFX
+1.35V_MEM_GFX
2013/03/09
Deciphered Date
2014/04/01
5
Title
1U_0402_6.3V6K
DIS@
CV318
1U_0402_6.3V6K
DIS@
CV317
1U_0402_6.3V6K
DIS@
CV316
1U_0402_6.3V6K
DIS@
CV315
1U_0402_6.3V6K
DIS@
CV314
1U_0402_6.3V6K
DIS@
CV313
1U_0402_6.3V6K
DIS@
CV312
Compal Secret Data
Issued Date
1U_0402_6.3V6K
DIS@
CV311
1U_0402_6.3V6K
DIS@
CV310
1U_0402_6.3V6K
DIS@
CV308
1U_0402_6.3V6K
DIS@
CV307
1U_0402_6.3V6K
DIS@
CV306
1U_0402_6.3V6K
DIS@
CV305
1U_0402_6.3V6K
DIS@
CV304
1U_0402_6.3V6K
DIS@
CV303
1U_0402_6.3V6K
DIS@
CV302
+1.35V_MEM_GFX
1U_0402_6.3V6K
DIS@
CV301
1U_0402_6.3V6K
DIS@
CV300
1U_0402_6.3V6K
DIS@
CV299
10U_0603_6.3V6M
DIS@
CV298
10U_0603_6.3V6M
DIS@
CV297
10U_0603_6.3V6M
DIS@
CV296
10U_0603_6.3V6M
DIS@
CV295
0.1U_0402_16V7K
DIS@
CV294
0.1U_0402_16V7K
DIS@
CV293
0.1U_0402_16V7K
DIS@
CV292
0.1U_0402_16V7K
DIS@
CV291
0.1U_0402_16V7K
DIS@
CV290
0.1U_0402_16V7K
DIS@
CV289
0.1U_0402_16V7K
DIS@
CV288
0.1U_0402_16V7K
DIS@
CV287
0.1U_0402_16V7K
DIS@
CV286
0.1U_0402_16V7K
DIS@
CV285
0.1U_0402_16V7K
DIS@
CV284
0.1U_0402_16V7K
DIS@
CV283
0.1U_0402_16V7K
DIS@
CV282
+1.35V_MEM_GFX
2
A

ATI_Sun XT_M2_VRAM_B
Size
Document Number
Rev
0.2
LA-9981P
Date:
Sheet
1
55
of
55
www.s-manuals.com

Compal La-9981p r0.2 Schematics

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Compal La-9981p r0.2 Schematics

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A

MODEL NAME : VBW00

Dell / Compal Confidential

Intel Shark Bay ULT

PCB VBW01 LA9981P/LS9101P/LS9102P/LS9103P

Compal Secret Data

Compal Electronics, Inc.

Saturday, March 09, 2013

Memory Bus (DDR3L)

Venus Pro(HD8850M)2GB GDDR5 (128Mx16x8pcs)

SATA HDD Conn. P.42

SATA ODD Conn. P.42

USB 2.0 Conn. 3

USB 3.0 Conn. 1

1.35V DDR3 1600 MHz

(OAK 15" only)

Headphone Jack / Mic. Jack combo

Compal Electronics, Inc.

Compal Secret Data

Saturday, March 09, 2013

Compal Electronics, Inc.

Compal Secret Data

Saturday, March 09, 2013

Board ID Table for AD channel

MINI Card (WLAN)

MINI Card (WLAN)

Touch Screen Panel

MINI Card (WLAN)

USB connector 4 (DB)

SMBUS Control Table

Compal Electronics, Inc.

Compal Secret Data

Saturday, March 09, 2013

SMBUS Address [0x9a]

SMBUS Address [A0]

SMBUS Address [A4]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [0xXX]

SMBUS Address [0x12]

SMBUS Address [0x16]

Compal Secret Data

Compal Electronics, Inc.

Saturday, March 09, 2013

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils ,Spacing=25mil,

Place near JXDP1

reference Shark Bay ULT Validation Customer Debug Port

Place near JXDP1.47

DDR3 COMPENSATION SIGNALS

PU/PD for JTAG signals

Compal Electronics, Inc.

Compal Secret Data

Docum ent Num ber

Saturday, March 09, 2013

confirm by intel request PDG P141

Compal Secret Data

Compal Electronics, Inc.

Saturday, March 09, 2013

INTVRMEN - INTEGRATED SUS 1.05V VRM

FLASH DESCRIPTOR SECURITY OVERRIDE

CMOS place near DIMM

PCH Rx side need use strap pin to update PCIE +/+3VS