Code No: A6802

Jawaharlal Nehru Technological University Hyderabad

M. Tech I-Semester Supplementary Examinations September – 2009
ANALOG AND DIGITAL IC DESIGN
(Common to Embedded Systems & VLSI Design and VLSI & Embedded Systems)
Time : 3 Hours Max. Marks: 60
Answer Any Five Questions
All Questions Carry Equal marks
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1.a] Discuss the noise modes for the following circuit elements.
i) Resistor
ii) Diode
iii) BJT
iv) MOSFET.
b] Consider the cascade warrant mirror where I in = 100μ A , and each transistor has
W / L = 100 μ m /1.6 μ m . Given that
μ nCox = 92 μ A / V 2 , Vtn = 0.8v and rds = [800 Lμ m ] / ⎡⎣ I D ( mA ) ⎤⎦ find rout for the
current mirror ( body effect 0.29m) . Also find the minimum output voltage at
Vout such that the output transistors remain in the active region.

2.a] Distinguish between one-stage op-amps and two stage op-amps.

b] With neat sketch explain the role of phase-detector in PLL and derive the
equation for PLL in the locked condition.

Cont…2
Code No: A6802 ::2::

3.a] Explain about parasitic insensitive integrators.

b] Discuss about Peak-detectors.

4.a] Write VHDL Model of 2n to n priority encoder.

b] Write VHDL Model of J-K flip-flop.

5.a] Distinguish between TTL, and ECL logic families.

b] Explain the use of Barrel shifter in the digital design.

6.a] Give an account of XC 4000 series family architecture.

b] Define charge injection error. How can you overcome this problem briefly
explain.

7. With neat sketch explain the function of

i) Folded resistor string D/A converter.
ii) R-2R based A/D converter.

8. Write short notes on:

a) Slew rate
b) Thermometer code.
c) Applications of ROM.

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