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-Introduction
Lecture 3
Amit Degada
Asst Prof, EC
IT-NU
Amit.degada@nirmauni.ac.in
www.adsignals.wordpress.com
DSD
Presentation Outline
Detailed Verilog Program structure
Verilog Lexical Convention
Verilog Behavioral Modeling
DSD
Begins
Beginswith
withkeyword
keywordmodule
module
and
andends
endswith
withendmodule
endmodule
The<module
The<modulename>is
name>isan
an
identifier
identifierthat
thatuniquely
uniquelynames
names
the
themodule.
module.All
Allthe
therules
rulesof
ofCC
identifier
identifierare
areapplicable.
applicable.i.e.
i.e.itit
Must
Muststart
startwith
withalphabets,
alphabets,
should
shouldnot
notstart
startwith
withnumb
numbor
or
special
specialcharacter.
character.ItItshould
shouldnot
not
End
Endwith
withspecial
specialcharacter
character
endmodule
2016
The<port
The<portlist>is
list>isaalist
listof
ofinput,
input,
inout
inoutand
andoutput
outputports
portswhich
which
are
areused
usedto
toconnect
connectto
toother
other
modules.
modules.
e.g.
e.g.a,b,c
a,b,c
Circuit Functionality
Timing Specification
endmodule
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In
Inport
portdeclaration
declarationregion,
region,the
the
Ports
Portsspecified
specifiedin
in<port_list>
<port_list>are
are
Specifically
Specificallymention
mentionas
asinput,
input,
output
outputand
andinout
inout
e.g
e.g input
inputa;
a;
output
outputb;
b;
input
inputc;
c;
Timing Specification
endmodule
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Port Declaration
module <module_name> (<port_list>);
Port Declaration
endmodule
Syntax:
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Port Declaration
Examples:
Examples
Notes
input a,b,sel;
3 scalar ports
Port Declaration
Data type Declaration
Circuit Functionality
Timing Specification
endmodule
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endmodule
Syntax:
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Rule to Remember
General Rules For Choosing The Correct Data
Type Class
when a signal is driven by a module output, a
primitive output, or a continuous assignment
use a net type
when a signal is assigned a value in a Verilog
procedure use a variable type
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Variable
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Functionality
unsigned variable of any bit size
signed 32-bit variable
unsigned 64-bit variable
double-precision
variable
floating
point
Functionality
Simple interconnecting wire
supply0
supply1
trireg
13
Examples
Data Type Examples
Notes
wire a, b, c;
3 scalar nets
14
Functionality
event
15
Examples
Data Type Examples
parameter [2:0] s1 = 3b001,
s2 = 3b010,
s3 = 3b100;
parameter integer period = 10;
Notes
three 3-bit constants
an integer constant
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Port Declaration
Data type Declaration
Circuit Functionality
Timing Specification
endmodule
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This
Thisisisbeyond
beyondthe
thescope
scopeof
ofthe
the
syllabus,
syllabus,will
willbe
beexplored
exploredififtime
time
permits
permitsat
atlater
laterpart
partof
ofthe
the
semester
semester
Timing Specification
endmodule
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endmodule
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Explicit
Implicit
module module_name
(port_name,
port_name, ... );
module_items
module_items
endmodule
endmodule
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always
and
assign
attribute
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endattribute
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
ifnone
initial
inout
input
integer
join
medium
module
large
macromodul
e
nand
negedge
nmos
nor
not
notif0
notif1
or
output
parameter
pmos
posedge
primitive
pull0
pull1
pulldown
pullup
rcmos
real
realtime
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
signed
small
specify
specparam
strength
strong0
strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
trireg
unsigned
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor
21
DSD
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1. White Space
blanks, tabs,
newlines (carriage return),
formfeeds
EOF (end-of-file).
23
2. Comments
// begins a single line
terminated by a newline.
comment,
/* begins a multi-line
terminated by a */
comment,
24
3. Case sensitivity
Verilog is case sensitive.
Lower case letters are unique from
upper case letters
All keywords we write in small letters
25
4. Identifiers (names)
Must begin with alphabetic or underscore
characters a-z, A-Z, _
May contain the characters a-z, A-Z, 0-9, _ and $
Examples
adder
Notes
legal identifier name
XOR
uppercase identifier
from xor keyword
is
unique
\reset*
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Escaped Identifier
Verilog HDL allows any character to be used in an identifier by
escaping the identifier. Escaped identifiers provide a means of
including any of the printable ASCII characters in an
identifier (the decimal values 33 through 126, or 21 through 7E
in hexadecimal).
Escaped identifiers begin with the back slash ( \ )
Entire identifier is escaped by the back slash.
Escaped identifier is terminated by white space (Characters such
as commas, parentheses, and semicolons become part of the
escaped identifier unless preceded by a white space)
Terminate escaped identifiers with white space, otherwise
characters that should follow the identifier are considered as part
of it.
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Escaped Identifier
// There must be white space after the
// string which uses escape character
module \1dff (
q,
\q~ ,
d,
cl$k,
\reset*
);
//
//
//
//
//
Q output
Q_out output Escaped Identifier
D input
CLOCK input
Reset input Escaped identifier
endmodule
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5. Logic Values
The Verilog HDL has 4 logic values.
Logic Value
Description
z or Z
x or X
unknown or uninitialized
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6. Logic Strengths
The Verilog HDL has 8 logic strengths: 4 driving, 3 capacitive, and high impedance (no
strength).
Strength
Level
Strength Name
Specification
Keyword
Display
Mnemonic
Supply Drive
supply0
supply1
Su0
Su1
Strong Drive
strong0
strong1
St0
St1
Pull Drive
pull0
pull1
Pu0
Pu1
Large Capacitive
La0
La1
Weak Drive
We0
We1
Med. Capacitive
medium
Me0
Me1
Small Capacitive
small
Sm0
Sm1
High Impedance
HiZ0
HiZ1
large
weak0
highz0
weak1
highz1
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31
Symbol
Legal Values
binary
or
0, 1, x, X, z, Z, ?, _
octal
or
0-7, x, X, z, Z, ?, _
decimal
or
0-9, _
hexadecimal
or
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Size
unsized
Base
decimal
Binary Equivalent
0...01010 (32-bits)
'o7
unsized
octal
1'b1
1 bit
binary
8'Hc5
8 bits
hex
11000101
6'hF0
6 bits
hex
110000
(truncated)
6'hF
6 bits
hex
001111
(zero filled)
6'hZ
6 bits
hex
ZZZZZZ
(Z filled)
0...00111
(32-bits)
33
34
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Verilog
-Behavioral Modeling
DSD
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Behavioral Modeling
In complex digital design, some decision
(e.g. trade-offs of various architecture
and algorithms) need to be made earlier
Verilog has the feature to specify the
design functionality (or may be called
behavior) in algorithmic manner
Behavioral constructs are similar to any
HLL like C, and Verilog has reach
behavioral construct
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Learning Objective
Significance of structured procedures: always and
initial
Define blocking and non-blocking procedural assignment
Use of
level-sensitive Timing control
Conditional statements like if and else
Multiway branching, using case, casex and casez
Looping statements, such as while, for, repeat and
forever
Understand the delay based timing control mechanism
(regular delays, intra-assignment delay, zero delay)
Define sequential and parallel blocks
Naming of blocks and disabling of named blocks
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Structured Procedures
Two basic structured procedure statements
always
initial
All behavioral statements appear only inside these
blocks
Each always or initial block has a separate activity
flow (multithreading, concurrency)
Start from simulation time 0
No nesting
Structured Procedures:
initial statement
Starts at time 0
Executes only once during a simulation
Multiple initial blocks, execute in parallel
All start at time 0
Each finishes independently
Syntax:
initial
begin
// behavioral statements
end
Structured Procedures:
initial statement (contd)
Example:
module stimulus;
reg x, y, a, b, m;
initial
#50 $finish;
endmodule
initial
m= 1b0;
initial
begin
#5 a=1b1;
#25 b=1b0;
end
initial
begin
#10 x=1b0;
#25 y=1b1;
end
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Initializing variables
Ordinary style, using initial block
reg clock;
//the clock variable is defined first
initial clock = 0; //the value of clock is set to 0
Structured Procedures:
always statement
Start at time 0
Execute the statements in a looping
fashion (Digital Hardware engineer
consider as repeated activity in digital
circuit)
Example
Example 7.5
44
Procedural Assignments
Assignments inside initial and
always
To update values of register data
types
The value remains unchanged until
another procedural assignment updates it
Compare
to
continuous
assignment
(Dataflow Modeling)
Procedural Assignments
(contd)
Syntax
<lvalue> = <expression>
<lvalue> can be
Blocking Procedural
Assignments
The two types of procedural assignments
Blocking assignments
Non-blocking assignments
Blocking assignments
count=0;
reg_a= 16b0; reg_b = reg_a;
executed at time 15
#15 reg_a[2] = 1b1;
#10 reg_b[15:13] = {x, y, z};
count = count + 1;
All executed at time 25
end
Non-Blocking Procedural
Assignments
Non-blocking assignments
Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial begin
x=0; y=1; z=1;
count=0;
Non-Blocking Assignments
(contd)
Application of non-blocking assignments
Used to model concurrent data transfers
Example: Write behavioral statements to swap
values of two variables
always
begin
reg1
reg2
reg3
end
@(posedge clock)
<= #1 in1;
<= @(negedge clock) in2 ^ in3;
<= #1 reg1;
The old value of reg1 is used
Race Condition
When the final result of simulating two (or more)
concurrent processes depends on their order of
execution
Example:
always
b =
always
a =
@(posedge clock)
a;
@(posedge clock)
b;
Solution:
True is 1 or non-zero
False is 0 or ambiguous (x or z)
More than one statement: begin end
Example 7-18
53
Notes:
Examples:
To be provided in the class
Example: 7-21
Loops (contd)
The for loop
Similar to C
Syntax:
for( init_expr; cond_expr; change_expr)
statement;
Example:
Provided in the class
Loops (contd)
The repeat loop
Syntax:
repeat(
number_of_iterations )
statement;
Loops (contd)
The forever loop
Syntax:
forever
statement;
Equivalent to while(1)
Timing Control
63
at
Timing Controls in
Behavioral Modeling
Introduction
No timing controls No advance in
simulation time
Three methods of timing control
1. delay-based
2. event-based
3. level-sensitive
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Intra-assignment Delay
Control
Symbol: non-zero delay to the right of
the assignment operator
Example: 7-11
Operation sequence:
1. Compute the RHS expression at current
time.
2. Defer the assignment of the above
computed value to the LHS by the
specified delay.
Intra-assignment Delay
Control
Intra-assignment Delay
Control
Zero-Delay Control
Symbol: #0
Different initial/always blocks in the same
simulation time
Execution order non-deterministic
@(<event>)
Events to specify:
posedge sig
negedge sig
sig
event
event calc_finished;
->
->calc_finished
@()
end
always@(received_data)
begin
/*---Do Something---*/
end
Event OR control
Used when need to trigger a block upon
occurrence of any of a set of events.
The list of the events: sensitivity list
Keyword:
or
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Event OR control
Simpler syntax
always @( reset or clock or d)
always @( reset, clock, d)
@* and @(*)
Level-sensitive Timing
Control
Level-sensitive vs. event-based
event-based: wait for triggering of an
event (change in signal value)
level-sensitive: wait for a certain
condition (on values/levels of signals)
Keyword:
wait()
always
wait(count_enable)
#20 count=count+1;
Parallel Blocks
Parallel Blocks
Keywords: fork, join
Statements
in
the
blocks
are
executed
concurrently
Timing controls specify the order of execution of
the statements
All delays are relative to the time the block was
entered
The written order of statements is not important
The join is done when all the parallel statements
are finished
initial
fork
x=1b0;
#5
y=1b1;
#10 z={x,y};
#20 w={y,x};
join
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Nested Blocks
Sequential and parallel blocks can be mixed
initial
begin
x=1b0;
fork
#5 y=1b1;
#10 z={x,y};
join
#20 w={y,x};
end
Named blocks
Syntax:
begin: <the_name>fork: <the_name>
end
join
Advantages:
Can have local variables (local variables are static)
Are part of the design hierarchy.
Their local variables can be accessed using
hierarchical names
Can be disabled
Loops
reg
[2:0]
i;
reg
[3:0]
out;
wire [3:0] a,b;
always @ (a or b)
begin
for (i=0; i<=3; i=i+1)
out[i] = a[i] & b[i];
end
endmodule
Example Unrolled:
out[0]
out[1]
out[2]
out[3]
=
=
=
=
a[0]
a[1]
a[2]
a[3]
&
&
&
&
b[0];
b[1];
b[2];
b[3];
Generate Statements
Generate Loop
Generate loops can be used to create multiple instances of
instances within a for loop.
The for loop in a generate statement is similar to the regular for
loop except for the following conditions:
Conditional Generates
if else statements
case statements
Note: The expression inside the if statement must evaluate to a static value.
Conditional Generates
The following example uses the case statement
to determine which adder is used, based on the
parameter WIDTH:
// case
parameter WIDTH=1;
generate
case (WIDTH)
1: adder1 x1 (c0, sum, a, b, ci);
2: adder2 x1 (c0, sum, a, b, ci);
default: adder # WIDTH x3 (c0, sum, a, b, ci);
endcase
endgenerate
Behavioral Modeling
Some Examples
4-to-1 Multiplexer
4-bit Counter
Introduction
Procedures/Subroutines/Functions in
SW programming languages
The same functionality, in different
places
Verilog equivalence:
Tasks and Functions
Used in behavioral modeling
Part of design hierarchy Hierarchical
name
Functions
Keyword: function, endfunction
Can be used if the procedure
does not have any timing control constructs
returns exactly one single value
has at least one input argument
one input
Example:
function my_not;
input in;
my_not= ~in;
endfunction
reg ni;
initial
ni = my_not(i);
Function Semantics
much like function in Pascal or C
An internal implicit reg is declared
inside the function with the same name
The return value is specified by setting
that implicit reg
<range_or_type> defines width and
type of the implicit reg
<type> can be integer or real
default bit width is 1
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Tasks
Keywords: task, endtask
Must be used if the procedure has
any timing control constructs
zero or more than one output arguments
no input arguments
Task Examples
Use of input and output arguments
Use of module local variables
Keyword
automatic
Example
function automatic integer factorial;
task automatic bitwise_xor;
Differences between...
Functions
Tasks
DSD
Structured Procedure
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Thanks
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