PhDEE-109

Roll No.________________
PhD-ECE
END SEMESTER EXAM I SEM
JAN 2016
LOW POWER VLSI DESIGN

Time: 3 Hrs.
Maximum Marks: 70
Instructions:
(a) Working Notes should form part of answer copy.
(b) Use of pencil or pen other than blue or black is not permitted.
(c) Use of Non Programmable Scientific calculator only is permitted
SECTION - A
[30 Marks]
Attempt any 5 questions.
All questions carry equal marks.
Q1. Why low power has become an important issue in the present day VLSI circuit realization?
Q2. Discuss about the hot carrier tunneling effects in detail.
Q3. What is short circuit power dissipation? On what parameters does it depend?
Q4. What do you mean by transistor sizing in CMOS design? Also discuss about the effects of
transistor sizing on the characteristics of CMOS devices.
Q5. What do you mean by scaling of MOSFET? Also discuss about the CMOS power supply
voltage scaling
Q6. A 32 bit off chip bus operating at 5 V and 66MHz clock rate is driving a capacitance of
25pF/bit. Each bit is estimated to have toggling probability of 0.25 at each clock cycle. What
is the power dissipation in operating bus?
SECTION - B
[20 Marks]
Attempt any 2 questions.
All questions carry equal marks.
Q7. Write a short note on SPICE circuit simulator. Also discuss about Monte- Carlo simulation.
Q8. What are the technology and device innovations available to reduce total capacitance?
Discuss any one with the help of proper block diagram.
Q9. What do you mean by Probabilistic power analysis techniques? Discuss about Instruction
level power analysis.
SECTION C
[20 Marks]
(Compulsory)
Q10. (a)What do you mean by reduction of switching activity of the nodes? Determine the
switching activity at the output of the following gates when the inputs are equi-probable:
AND2,NAND2,AND3,NAND3,NOR2.
[10 Marks]
Q10. (b) Discuss about the power consumption phenomena in flip-flops and latches with suitable
examples.
[10 Marks]

Dr Vikas Maheshwari