Building A Home Security System With BeagleBone (2013) - Pretty

zao ASSEMBL Y LANGUAGE PROGRAMMING MANUAL
Copyright 1977 by 2ilog, Inc. All rights reserved. No part of this

publication may be reproduced, stored in a retrieval system, or transmitted,
in any form or by any means, electronic, mechanical, photocopying,
recording, or otherwise, without the prior written permission of Zilog.

Zilog assumes no responsibility for the use of any circuitry other than
circuitry embodied in a Zilog product. No other circuit patent licenses
are implied.
3.00.5,
REL. 2il
TABLE OF
CONTENTS
PAGE
I.
INTRODUCTION
IL.
SPECIFICATION OF ZaD ASSEMBLY LANGUAGE

A.
THE ASSEMBLY LANGUAGE '
B.
OPERANDS.
C.
RULES FOR WRITING ASSEMBLY STATEMENT~ (SYNTAX)
D.
ASSEMBLY LANGUAGE CONVENTIONS...................
E.
ASSEMBLER COMMANDS
7
13
III.
MACROS
15
IV.
SUBROUTINES
18
v.
ZaG CPU FLAGS
20
VI.
zaD INSTRUCTION SET
24
2
4
INSTRUCTION INDEX 275

APPENDIX:
A.
C.
C.
ERROR MESSAGES 280

INSTRUCTION SORT LISTING (ALPHABETICAL) 284
INSTRUCTION SORT LISTING (NUMERICAL) 290
JANUARY 1978
Z80 ASSEMBLY LANGUAGE PROGRAMMING MANUAL
INTRODUCTION:
The assembly language provides a means for writing a

program without having to be concerned with actual
memory addresses or machine instruction formats.
It
allows the use of symbolic addresses to iden~ify memory
locations and mnemonic codes (opcodes and operands) to
represent the instructions themselves.
Label,s (symbols)
can be assigned to a particular instruction step in a
source program to identify that step as an entry point
for use in subsequent instructions.
Operands' following
each instruction represent storage locations, registers,
or constant values.
The assembly language also includes
assembler directives that supplement the machine
instruction.
A pseudo-op, for example, is a 8tatement
which is not translated into a machine instru~tion, but
rather is interpreted as a directive that controls the
assembly process.
A program written in assembly language is called a
source program. It consists of symbolic commands called
statemen~s.
Each statement is written on a single line
and may consist of from one to four entries:
A label
field, an operation field, an operand field and a
comment field.
The source program is processed by the
assembler to obtain a machine language program (object
program) that can be executed directly by the Z80-CPU.
Zilog provides several different assemblers which differ
in the features offered.
Both absolute and relocatable
assemblers are available with the Development and
Microcomputer Systems.
The absolute assemble
is
contained in ba~e level software operating in a 16K
memory space while the relocating assembler i
part of
the RIO environment operating in a 32K memory space.
II
SPECIFICATION OF THE Z80 ASSEMBLY LANGUAGE

A. THE ASSEMBLY LANGUAGE
The assembly language of the Z80 is de$igned to
minimize the number of different opcod~s
corresponding to the set of basic machtne
operations and to provide for a consistent
description of instruction operands.
~he
nomenclature has been defined with special emphasis
on mnemonic value and readability.
The movement of data is indicated prim4rily by a
single opcode, LD for example, regardl~ss of
whether the movement is between different registers
or between registers ~nd memory locatiOns.
The first operand of an LD instruction is the
destination of the operation, and the $econd
operand is the source of the operation.
For
example:
LD A,B
indicates that the contents of the second operand,
register B, are to be transferred to the first
operand, register A.
Similarly,
LD C,3FH
indicates that the constant 3FH is to be loaded
into the register C.
In addition, enclosing an
operand wholly in parentheses indicate$ a memory
location addressed by the contents of the
parentheses.
For example,
LD HL,(1200)
indicates the contents of memory locations 1200 and
1201 are to be loaded into the 16-bit register pair
HL.
Similarly,
LD
(IX+6),C
indicates the contents of the register C are to be

stored in the memory location addressed by the
current value of the 16-bit index register IX plus
6.
The regular formation of assembly instructions

minimizes the number of mnemonics and format rules
that the user must learn and manipulate.
Additionally, the resulting programs are easier to
interpret which in turn reduces programming errors
and improves the maintainability of the software.
B. OPERANDS
Operands modify the opcodes and provide the
information needed by the assembler to perform the
designated operation.
Certain symbolic names are reserved as key words in
the assembly language operand fields.
They are:
I) The contents of 8-bit registers are
specified by the character corresponding
to the register names.
The register names
are A,B,C,D,E,H,L,I,R.
2)
The contents of 16-bit double registers

and register pairs consisting of two 8-bit
registers are specified by the two
characters corresponding to the register
name or register pair.
The names of
double registers are IX,IY and SP.
The
names of registers pairs are AF,BC,DE and
HL.
3) The contents of the auxiliary register

pairs consisting of two 8-bit registers
are specified by the two characters
corresponding to the register pair names
followed by an apostrophe.
The auxiliary
register pair names are AF',BC',DE' and
HL'. Only the pair AF' is actually allowed
as an operand, and then only in the EX
AF,AF' instruction.
4) The state of the four testable flags is

specified as follows:
FLAG
CONDITION
Carry
Zero
Sign
Parity
ON CONDITION
C
Z
NC
NZ
M (minus)
P (pI us)
PO (odd)
PE (even)
OPERAND NOTATION
The following notation is used in the description
of the assembly language:
1) r specifies anyone of the following
registers: A,B,G,D,E,H,L.
(HL) spe~ifies the contents of memory at
the location addressed by the contents of
the register pair HL.
3) n specifies a one-byte expression in the
range (0 to 255) nn specifies a two-byte
expression in the range (0 to 65535).
4) d specifies a one-byte expression in the
range (-128,127).
5) (nn) specifies the contents of memory at
the location addressed by the two-byte
expression nn.
6) b specifies an expression in the range
2)
(0,7).
7) e specifies a one-byte expression in the

range (-126,129).
8) cc specifies the state of the Flags for
conditional JR, JP, CALL and RET
instructions.
9) qq specifies anyone of the register pairs
BG, DE, HL or AF.
10) ss specifies anyone of the following
register pairs: BG,DE,HL,SP.
11) pp specifies anyone of the following
register pairs: BG,DE,IX,SP.
12) rr specifies anyone of the following
register pairs: BG,DE,IY,SP.
13) s specifies any of r,n,(HL),(IX+d),(IY+d).
14) dd specifies anyone of the following
register pairs: BG,DE,HL,SP.
15) m specifies any of r, (HL), (IX+d), (IY+d).
C. RULES FOR WRITING ASSEMBLY STATEMENTS (SNTAX)

An assembly language program (source program)
consists of labels. opcodes. operands. cpmments and
pseudo-ops in a sequence which defines the user's
program.
There are 74 genericopcodes (such as LD). 25
operand key words (such as A). and 694 legitimate
combinations of opcodes and operands in the zao
instruction set.
ASSEMBLER STATEMENT FORMAT:
Statements are always written in a particular
format.
A typical Assembler statement is shown
below:
LABEL
LOOP:
OPCODE
LD
OPERANDS
HL.VALUE
COMMENT
;GET VALUE
In this example. the label. LOOP, provides a means

for assigning a specific name to the instruction
LOAD (LD), and is used to address the statement in
other statements.
The operand field contains one
or two entries separated by one or more commas.
tabs or spaces. Th~ comment field is use' by the
programmer to quickly identify the actio$ defined
by the statement.
Comments must begin with a
semicolon and labels must be terminated by a colon,
unless the label starts in column No.1.
ASSEHBLY LANGUAGE CONVENTIOnS

LABELS
A label is a syubol representing up to 16 bits of
information and is used to specify an address or
data.
By using labels effectively, the uSer can
write assembly language programs more rapidly and
make fewer errors.
If the programmer attempts to
use a symbol that has been defined as greater than
8 bits for an 8-bit data constant, the assembler
will generate an error message.
A label is composed of a string of one or more
characters, of which the first six must be. unique.
For exar,lple, the labels' longname' and
'longnamealso' will be considered to be the same
label.
The first character must be alphabetic and
any following characters Dust be either
alphanumeric, the question mark (?) or the under
ba~ character ( ) .
Any other characters with~n a
label will caus; an error.
A label tan start in
any column if immediately followed by a colon.
It
does not require a colon if started in column one.
The assembler maintains a location counter to
provide addresses for the symbols in the label
field.
When a symbol is found in the label field,
the assembler places the symbol and the
corresponding location counter value in a symbol
tab Ie.
The symbol table normally resides in RAM, but it
will automatically overflow to disk, so there is
limit to the number of labels that can be
processed.
EXPRESSIONS
An expression is an operand entry consisting of
either a single term (unary) or a combination of
termS (binary).
It contains a valid series of
constants, variables and functions that can be
connected by operation symbols.
The Z80 Assembler
will accept a wide range of expressions involving
arithmetic and logical operations.
The assembler
will evaluate all expressions from left to right in
the order indicated in the table below:
OPERATOR
FUNCTION
UNARY PLUS
UHARY l1I1WS
LOGICAL NOT
RE SU 1'i
EXPONENTIATION
liUL TI1'L I CATION
DIVISION
1l0DULO
LOGICAL SUlfT RIGHT
LOGICAL SHIFT LEFT
ADDITION
SUBTRACTION
LOGICAL AND
LOGICAL OR
LOGICAL XOR
EQUALS
GREATER THAN
LESS THAN
UNS~GNED GREATER THAN
UNSIGNED LESS THAN
.NOT. or \
.RES.
**
*/
.110D.
.SHR.
.SaL.
+
.AND. or &
.OR. or
.XOR.
.EQ. 0 r
.GT. or
.LT. or
.UGT.
.ULT.
Parenthesis can be used to ensure correct

expression evaluation.
Note, however, that
enclosing an expression wholly in parenthesis
indicates a memory address.
Delimiters such as spaces or commas are not allowed
within an expression since they serve to separate
the expression from other portions of the
statement.
16-bit integer arithmetic is used
throughout.
Note that the negative of an expression can be

formed by a preceding minus sign -.
For example:
LD HL,-OEA9H.
The five comparison operators (.EQ., .GT., .LT.,
.UGT.and.ULT.) will evaluate to a logical True (all
ones) if the comparison is true logical False
(zero) otherwise.
The operators .GT. and .LT. deal
with signed numbers whereas .UGT. and .ULT. assume
unsigned arguments.
The Result operator (.RES.)
causes overflow to be
suppressed during evaluation of its argum~nt, thus

overflow is not flagged with an error message.
For example:
LD BC,7FFFH+l would cause an error message,
whereas LD BC,.RES.(7FFFH+l) would not.
The l1odulo operator (.MOD.)
is defined as:
X.MOD.Y. = X-Y*(X/Y) where the division (X/Y)

is integer division.
The Shift operator (.SllR.,.SllL.) shifts the first
argument right or left by the number of positions
given in the second argument. Zeros are shifted
into the high-order or low-order bits,
respec tively.
In specifying relative addressing with either the
JR (Jump Relative) or DJNZ (Decrement and Jump if
Not Zero) instructions, the Assembler automatically
subtracts the value of the next instruction's
reference counter from the value given in the
operand field to form the relative address for the
jump instruction.
For example:
JR C,LOOP
will jump relative to the instruction labeled LOOP
if the Carry flag is set.
The limits on the range
of a relative address is 128 bytes in either
direction from the reference counter of the next
instruction.
An error message will be generated if
this range is exceeded.
The symbol $ is used to represent the value of the
reference counter of the current instruction, and
can be used in general expressions.
An expression
which evaluates to a displacement in the range
<-126,+129> can be added to the reference counter
to form a relative address.
For example:
JR
C,$+5
will jump relative to the instruction which is

bytes beyond the current instruction.
PSEUDO-OPS
(ASSEMBLER DIRECTIVES)
There are several pseudo-ops which the various

2ilog assemblers will recognize.
These assembler
directives, although written much like processor
instructions, are commands to the assembler instead
of to the processor. They direct the assembler to
perform specific tasks during the assembly process
but have no meaning to the Z80 processor.
These
assembler pseudo-ops are:
ORG
nn
Sets value of a label to nn in the

program: can occur only once for
any label.
EQU
DEFL
Sets address reference counter to

the value nne
nn
END
Sets value of a label to nn and can

be repeated in the prog.ram with
different values for the same
1 ab el
Signifies the end of the source
program so that any follOWing
statement will be ignored.
If
there is no end statement, then the
end-of-file mark in the last source
file will designate the end of the
source program.
DEFB
Defines the contents of a byte at

the current reference counter to be
DEFB
's'
Defines the content of pne byte of

memory to be the ASCII
representation of character s.
DEFW
Defines the contents of a two-byte

word to be nne
The least
significant byte is located at the
current reference counter while the
most significant byte is located at
the reference counter plus one.
DEFS
Reserves nn bytes of memory

starting at the current value of
the reference counter.
10
DEFll
's'
Defines the content of n bytes of

memory to.be the ASCII
representation of string s, where n
is the length of s and must be in
the range O<=n<-63.
BACRG
flpo
lip 1 IIPn
Declares the label
to be a macro name with formal
parameters Po through Pn.
Subsequent statements deffne the
body of the macro.
ENDl!
Harks the end of a macro

definition.
Pseudo-ops are assembled exactly like executable

instructions, and may be preceded by a label and
followed by a comment.
(The label is required for
EQU, DEFL and MACR pseudo-ops.)
In the above
pseudo-op definitions, the reference counter
corresponds to the program counter and is used to
assign and calculate machine-language addresses for
the 0 b j e c t f 11 e
CONDITIONAL PSEUDO-OPS
Conditional pseudo-ops prOVide the programmer with
the capability to conditionally include or not
include portions of his source code in the assembly
process.
Conditional pseudo-ops are:
COND
ENDC
nn
Evaluates expression nn.

If the
expression is true (non-zero)~ the
COND pseudo-op is ignored. If the
expression is false (zero), the
assembly of subsequent statements
is disabled.
COND pseudo-ops
cannot be nested.
Re-enables assembly of subsequent
statements.
DELIUITERS
A delimiter is used to specify the bounds of a
certain related group of characters in a s~urce
program.
The delimiters recognized by the
assembler are commas or spaces.
A d~limiter cannot
11
occur within an expression.

COUMENTS
Comments are not a functional part of an ~ssembly
program, but instead are used for program
documentation to add clarity, and to facilitate
software maintenance. A comment is defined as any
string following a semicolon in a line, amd is
ignored by the assembler.
Comments can begin in
any column.
I/O BUFFERS
The zao Assembler uses a buffered I/O technique for
handling the assembly language source file, listing
file, ~bject file and temporary files.
The
assemble~ automatically determines the available
work space and allocates the buffer sizes
accordingly.
Hence there are no constraints on the
size of the assembly language source file that can
be assembled.
UPPER/LOWER CASE
The assembler processes source text which.contains
both upper and lower case alphabetic char4cters in
the following manner. All opcodes and keywords,
such as register names or condition codes, must be
either all capitals or all lower case.
Label names
may consist of any permutation of upper and lower
case, however, two names which differ in case will
be treated as two different names.
Thus, LABEL,
label and LaBel will be considered as three
different names.
Notice that one could use a
mixture of case to allow definition of labels or
macros which look similar to opcodes, such as Push
or LdiR, without redefining the meaning of the
opcode. All assembler commands, such as*List or
*Include (see below) can be in either upper or
lower case, as can arithmetic operators suc~ as
NOT.,.AND. or .EQ., and numbers can be any mixture
of case, such as Off~fh, OAbCdH or OllOOlb.
NUMBER BASES
The Assembler will accept numbers in several
12
different bases:
binary, octal, decimal and
hexadecimal.
Numbers must always start with a
digit (leading zeros are sufficient), and may be
followed immediately by a single letter which
signifies the base of the number ('B' for binary,
'0' or 'Q' for octal, 'D' for decimal and 'H' for
hexadecimal).
If no base is specified decimal is
assumed.
For example, the same nucber is
represented in each of the four bases:
1011100B, 134Q, 1340, 92, 92D, OSCll

E. ASSEMBLER COMMANDS
The zao Assembler recognizes several commands to
modify the listing format.
An assembler cOmmand is
a line of the source file beginning with an * in
column one.
The character in column two identifies
the type of command.
Arguments, if any, are
separated from the command by any number of blanks
or commas.
The following commands are recognized
by the assembler:
*Eject
Causes the listing to advance to a

new page starting with this line.
*Heading
Causes string s to be taken as a

heading to be printed at the top of
each new page.
Strings s may be
any string of zero to 28
characters, not containing le~ding
blanks.
This cocrnand does an
automatic Eject.
*List OFF
Causes listing and printing to be

suspended, starting with this line.
*List ON
Causes listing and printing to

resume, starting with this line.
*Uaclist OFF
Causes listing and printing of

cacro expansions to be suspended,
starting with this line.
*Uaclist ON
Causes listing and printing of

macro expansions to resume,
starting with this line.
*Include filename
Causes the source file filenace to

be included in the source stream
follOWing the command statement.
13
The expected use of *Include is for files of macro

definitions, lists of EQUates, or commonly uSed
subroutines, although it can be used anywher~ in a
program that the other commands would be legal.
The filename must follow the normal convention for
specifying filenames, and furthermore only file
types 'F' through 'T' are allowed.
The default
type is '5'.
The included file may also contain a
*Include command, up to a nested level of four.
*Include will always try to shoe-horn the file in
inside a macro definition, and although the
*Include statement will appear in a macro
expansion, the file will not be included again at
the point of expansion.
*Include works in the
expected manner in conjunction with conditional
assembly.
For example:
COND exp
*Include FILEl
ENDC
;FILEl is included only if the value of exp is
non-zero.
14
III.
MACROS
Macros provide a means for the user to define his

own opcodes, or to redefine existing opcodes.
A
macro defines a body of text which will be
automatically inserted in the source strea~ at each
occurrence of a macro call.
In addition,
parameters provide a capability for making limited
changes in the macro at each call.
If a macro is used to redefine an existing opcode,
a warning message is generated to indicate that
future use of that opcode will always be processed
as a macro call.
If a program uses macros, then
the asembly option M must be specified.
MACRO DEFINITION
The body of text to be used as a macro is tiven in
the macro definition.
Each definition begins with
a MACRO statement and end with an ENDM statement.
The general forms are:
<name> MACRO [#<PO>,#<Pl>, ,#<Pn>]
[<label>]
ENDH
The label <name> is required, ~nd must obey all the

usual rules for forming labels.
The quantity in
brackets is an optional set of parameters.
There can be any number of parameters, each
starting with the symbol #.
The rest of the
parameter name can be any string not containing a
delimiter (blank, comma, semicolon) or the symbol
#. However, parameters will be scanned left to
right for a match, so the user is cautioned not to
use parameter names which are prefix substrings of
later parameter names. Parameter names are not
entered in the symbol table.
The label on an ENDM is optional, but if ona is
given it must obey all th.e usual rules for forming
labels.
Each statement between the MACRO and ENDM
statements is entered into a temporary macro file.
The only restriction on these statements is that
they do not include another macro definition.
(Nested definitions are not allowed.)
They may
15
include macro calls.
(Recursion is allowed.)
The statements of the macro body are not assembled

at definition time, so they will not define labels,
generate code, or cause errors.
Exceptions are the
assembler commands such as *List, which are
executed wherever they occur.
Within the macro
body text, the formal parameter names may occur
anywhere that an expansion-time substitution is
desired.
This includes comments and quoted
strings.
The symbol # may not occur except as the
first symbol of a parameter name.
Macros must be defined before they are called.
MACRO CALLS AND MACRO EXPANSION
A macro ~s called by using its name as an opcode at
any point after the definition.
The general form
is:
[<label
<name>
[<SO>,<Sl>', 'Sn>')
The <label> is optional, and <name> must be a

previously defined macro.
There may be any number
of argument strings, <Sn>, separated by any number
of blanks or commas.
Commas do not serve as
parameter place holders, only as string delimeters.
If there are too few parameters, the missing ones
are assumed to be null.
If there are too many, the
extras are ignored.
The position of each string in
the list corresponds with the position of the macro
parameter name it is to replace.
Thus, the third
string in a macro call statement will be
substituted for each occurrence of the third
parameter name.
The strings may be of any length and may contain
any characters. The outer level quotes around the
string are generally optional, but are required if
the string contains delimiters or the quote
character itself.
The quote character is
represented by two successive quote marks at the
inner level.
The outer level quotes, if present,
will not occur in the substitution.
The null
string, represented by two successive quote marks
at the outer level, may be used in any parameter
position.
After processing the Dacro call statement, the
assembler switches its input from the source file
16
to the macro file.

Each statement of the macro
body is scanned for occurrences of parameter names,
and for each occurrence found, the corresponding
string from the macro call statement is
substituted.
After substitution, the statement is
assembled normally.
SYllBOL GENERATOR
Every macro definition has an implicit parameter
named #$YM. This may be referenced by the user in
the macro body, but should not explicitly appear in
the lIACRO statement.
At expansion time, each
occurrence of {!$YU in the definition is r,eplaced by
a string representing a 4-digit bexadecim~l
constant.
This string is constant over a given level of macro
expansion, but increases by one for each new macro
call.
The most common use of {!$Yl1 is to provide
unigue labels for different expansion of the same
macro.
Otherwise, a macro containing a Label would
cause multiple definition errors if it were called
more than once.
LISTING FORHAT
By default, each expanded statement is listed with
a blank STMT field.
If the liaclist flag is turned
off by the NOH option or *11 OFF, then only the
macro call is listed.
17
IV.
SUBROUTINES
Subroutines are blocks of instructions that can be
called during the execution of a sequence ot
instructions.
Subroutines can be called from main
programs or from other subroutines. A subroutine is
entered by the CALL opcode as in:
CALL REWIND
Parameters such as those used by the macros are not
used with subroutines.
When a call instruction is
encountered during execution of a program, the PC
is changed to the first instruction of the
subroutine.
The subsequent address of the invoking
program is pushed on the stack.
Control will
return to this point when the subroutine is
finished.
The processor continues to execute the
subroutine until it encounters a RET (return)
instruction.
At this point the return address is
popped off the stack into the PC, and the processor
returns to the address of the instruction following
the CALL, to continue execution from that point.
Subroutines of any size can be invoked from
programs or other subroutines of any size, without
restriction.
Care must be taken when nesting
subroutines (subroutines within subroutines) that
pushes and pops remain balanced at each lev~l. If
the processor encounters a RET with an un-popped
push on the stack, the PC will be set to a
meaningless address rather than to the next
instruction following the CALL.
Tradeoffs must be considered between:
a)
b)
using a block of code repetitively in line,

and
calling the block repetitively as a
subroutine.
Program size can usually be saved by using the

subroutine. If the repetitive block contains N
bytes and it is repeated on " occasions in the
program,
a)
b)
MxN bytes would be used in direct

programming, while
3M
(for CALLS)
18
+
+
N (for the block)

1
(for the RET)
3M+N+1 bytes would be required if using a
subroutine.
For example, for a block of 20 bytes used 5 times,

in-line programming would require 100 bytes while a
subroutine would require 36.
An added advantage of subroutines is that with
careful naming, program structures become clearer,
easier to read and easier to debug and maintain.
Subroutines written for one purpose can be employed
elsewhere in other programs requiring the same
function.
Subroutines differ from Macros in several ways:
a)
Subroutine code is assembled into an object

program only once although it may be called
many times.
Macro code is assembled in
line every place the macro is used.
b)
Registers and pointers required by a

subroutine must be set up before the
CALL.
No parameters are used and no
argument string can be issued.
Macros,
through their use of parameters, can modify
the settings of registers on each
occurrence.
19
V.
Z80 STATUS INDICATORS
(FLAGS)
The flag register (F and F') supplies information to the

user regarding the status of the Z80 at any given time.
The bit positions for each flag is shown below:
WHERE:
C ..
N ..
p/V ..
H ..
Z ..
S ..
X
CARRY FLAG
ADD/SUBTRACT FLAG
PARITY/OVERFLOW FLAG
HALF-CARRY FLAG
ZERO FLAG
SIGN FLAG
NOT USED
Each of the two Z-80 Flag Registers contains 6 bits of

status information which are set or reset by CPU
operations.
(Bits 3 and 5 are not used.)
Four of these
bits are testable (C,p/V,Z and S) for use with
conditional jump, call or return instructions.
Two
flags are not testable (H,N) and are used for BCD
arithmetic.
CARRY FLAG (C)
The ~arry bit is set or reset depending on the operation
being performed.
For 'ADD' instructions that generate a
carry and 'SUBTRACT' instructions that generate a
borrow, the Carry Flag will be set. The Carry Flag is
reset by an ADD that does not generate a carry and a
'SUBTRACT' that generates no borrow.
This saved carry
facilitates software routines for extended precision
arithmetic.
Also, the "DAA" instruction will set the
Carry Flag if the conditions for making the decimal
adjustment are met.
For instructions RLA, RRA, RLS and RRS, the carry bit is
used as a link between the LSB and MSB for any register
or memory location.
During instructions RLCA, RLC sand
SLA s, the carry contains the last value shifted out of
bit 7 of any register or memory location.
During
20
instructions RRCA, RRC s,

SRA sand SRL s
the carry
contains the last value shifted out of bit 0 of any
register or memory location.
For the logical instructions AND s,
the carry will b~ reset.
OR sand XOR s,
The Carry Flag can also be set (SCF) and complemented

(CCF).
ADD/SUBTRACT FLAG (N)
This flag is used by the decimal adjust accumulator
instruction (DAA) to distinguish between 'ADD' and
'SUBTRACT' instructions. For all 'ADD' instructions, N
will be set to an '0'.
For all 'SUBTRACT' instructions,
N will be set to a '1'.
PARITY/OVERFLOW FLAG
This flag is set to a particular state depending on the
operation being performed.
For arithmetic operations, this flag indicates an
overflow condition when the result in the Accumulator is
greater than the maximum possible number (+127) or is
less than the minimum possible number (-128).
This
overflow condition can be determined by examining the
sign bits of the operands.
For addition, operands with different signs will never
cause overflow.
When adding operands with like signs
and the result has a different sign, the overflow flag
is set.
For example:
+120 = 0111 1000
+105
0110 1001
+225
1110 0001
ADDEND
AUGEND
(-95) SUM
The two numbers added together has resulted in a number

that exceeds +127 and the two positive operands has
resulted in a negative number (-95) which is incorrect.
The overflow flag is therefore set.
For subtraction, overflow can occur for operands of
unlike signs.
Operands of like sign will never cause
overflow.
For example:
+127
(-) '-64
+191
0111 1111
1100 0000
1011 1111
21
MINUEND
SUBTRAHEND
DIFFERENCE
The minuend sign has changed from a positive to a

negative, giving an incorrect difference.
Overflow is
therefore set.
Another method for predicting an overflow is to observe
the carry into and out of the sign bit.
If there is a
carry in and no carry out, or if there is no carry in
and a carry out, then overflow has occurred.
This flag is also used with logical operations and
rotate instructions to indicate the parity of the
result.
The number of '1' bits in a byte are counted.
If the total is odd, 'ODD' parity (P-O) is flagged. If
the total is even, 'EVEN' parity is flagged (P=I).
During search instructions (CPI,CPIR,CPD,CPD1) and block
transfer instructions (LDI,LDIR, LDD,LDDR) theP/V flag
monitors the state of the byte count register (BC).
When deerementing, the byte counter results in a zero
value, the flag is reset to 0, otherwise the flag is a
Logic 1.
During LD A,I and LD A,R instructions, the P/V flag will
be set with the contents of the interrupt enable
flip-flop (IFF2) for storage or testing.
When inputting a byte from an I/O device, IN r,(C), the
flag will be adjusted to indicate the parity of the
data.
THE HALF CARRY FLAG (H)
The Half Carry Flag (H) will be set or reset .depending
on the carry and borrow status between bits 3 and 4 of
an 8-bit arithmetic operation.
This flag is used by the
decimal adjust accumulator instruction (DAA) .to correct
the result of a packed BCD add or subtract operation.
The H flag will be set (1) or reset (0) according to the
following table:
H
ADD
SUBTRACT
There is a carry from

Bit 3 to Bit 4
There is
borrow from
bit 4
There is no carry
from Bit 3 to Bit 4
There 1s no
borrow from
Bit 4
THE ZERO FLAG (Z)

The Zero Flag (Z) is set or reset if the result
generated by the execution of certain instructions
is a zero.
For 8-bit arithmetic and logical operations, the Z
flag will be set to a '1' if the resulting byte in
the Accumulator is zero.
If the byte is not zero,
the Z flag is reset to '0'.
For compare (search) instructions, the Z flag will
be set to a '1' if a comparison is found between
the value in the Accumulator and the memory
location pointed to by the contents of the register
pair HL.
When testing a bit in a register or memory
location, the Z flag will contain the complemented
state of the indicated bit (see Bit b,s).
When inputting or outputting a byte between a
memory location and an I/O device (INlj!NDjOUTI and
OUTD), if the result of B-1 is zero, th~ Z flag is
set, otherwise it is reset. Also for byte inputs
from I/O devices using IN r,(C), the Z Flag is set
to indicate a zero byte input.
THE SIGN FLAG
(S)
The Sign Flag (S) stores the state of the most

significant bit of the Accumulator (Bit 7).
When
the Z80 performs arithmetic operations on signed
numbers, binary two's complement notation is used
to represent and process numeric information.
A
positive number is identified by a '0' in bit 7.
A
negative number is identified by a '1'.
The binary
equivalent of the magnitude of a positive number is
stored in bits 0 to 6 for a total range.Df from 0
to 127.
A negative number is represent~d by the
two's complement of the equivalent positive number.
The total range for negative numbers is from -1 to
-128.
When inputting a byte from an I/O device to a
register, IN r,(C), the S flag will indicate either
positive (S=O) or negative (S=I) data.
VI.
zao
INSTRUCTION SET
NOTE:
Execution time (E.T.) for each instruction is
given in nicroseconds for an assuned 4 MHZ clock.
Total
machine cycles (M) are indicated with total clock
periods (T States). Also indicated are the nubber of T
States for each M cycle.
For example:
M CYCLES:
T STATES:
7(4,3)
4 MHZ E.T.: 1.75
indicates that the instruction consists of 2 machine

cycles.
The first cycle contains 4 clock periods (T
States).
The second cycle contains 3 clock periods for
a total of 7 clock periods or T States. The instruction
will execute in 1.75 microseconds.
Register format is shown for each instruction with the
most si~nificant bit to the left and the least
significant bit to the right.
Z8G INSTRUCTION SET

TABLE OF CONTENTS
PAGE
-8 BIT LOAD GROUP 26
-16 BIT LOAD GROUP
52
-EXCHANGE, BLOCK TRANSFER

AND SEARCH GROUP
76
-8 BIT ARITHMETIC AND LOGICAL GROUP
99
-GENERAL PURPOSE ARITHMETIC

AND CPU CONTROL GROUPS 131
-16 BIT ARITHMETIC GROUP 146
-ROTATE AND S HI FT GROUP 163
-BIT SET,
RESET AND TEST GROUP
~2
-JUMP GROU P 219

-CALL AND RETURN GROUP 237
-INPUT AND OUTPUT GROUP 252
-INSTRUCTION INDEX 275
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
8 BIT LOAD GROUP
LD
r,
r'
Operation:
+-
Format:
Opcode
Operands
LD
r,r
Description:
The contents of any register r' are loaded into any
other register r. Note: r,r' identifies any of the
registers A, B, C, D, E, H, or L, assembled as follows
in the object code:
~'
Register
A
111
B 000
C 001
D 010
E
011
H 100
L 101
11 CYCLES:
T STATES: 4
Condition Bits Affected:
4 MHZ E. T .:
1. 0
None
Example:
If the H register contains the number 8AH, and the E
register contains 10H, the instruction
LD H, E
would result in both registers containing 10H.
27
LD
r~n
Operation:
Forma t:
Operands
r, n
LD
Ia: o~r~< <01
I" : In: : : .. I
Description:
The eight-bit integer n is loaded into any register r,
where r identifies register A, B, C, D, E, H or L.
assembled as follows in the object code:
Register
~I
A -
111
B
C
D
E
H
L
000
001
010
all
100
101
CYCLES: 2
Condition Bits
T STATES:
7(4,3)
~ffected:
None
4 MHZ E. T .:
Example:
After the execution of
LD E, ASH
the contents of register E will be ASH.
28
1. 7 S
r.
LD
r,
(HLJ
r +- (HL)
Operation:
Format:
Operands
LD
r. (HL)
Description:
The eight-bit contents of memory location (HL) are
loaded into register r. where r identifies register A.
B. C. D. E. H or L. assembled as follows in the object
code:
Register
A
B
C
D
r
- III
- 000
- 001
- 010
E -
011
H - 100
L - 101
11 CYCLES: 2
T STATES: 7(4.3)
4 MHZ E. T .:
1. 75
None
Example:
If register pair HL contains the number 75A1H. and
memory address 75A1H contains the byte 58H. the
execution of
LD C. (HL)
will result in 58H in register C.
29
LD
r,
CIX+dJ
r+-(IX+d)
Operation:
Format:
Operands
LD
r.
(IX+d)
I <<a: <<< d
0:17-7 7--7< <a I
I : : :d: : : :.
0:
DD
"I
Description:
The operand (IX+d) (the contents of the Index Register
IX summed with a two's complement displacement integer
d) is loaded into register r. where r identiies
register A. B. C. D. E. H or L. assembled as follows in
the object code:
Register
A
B
C
D
!.
= III
.. 000
.. 001
.. 010
E .. 011
H .. 100
L ~ 101
M CYCLES: 5 T STATES:
19(4.4.3.5.3) 4 MHZ E.T.:
4.75
None
Example:
If the Index Register IX contains the number 25AFH. the
instruction
30
LD B,
(IX+19H)
will cause the calculation of the sum 25AFH + 19H, which

points to memory location 25C8H.
If this address
contains byte 39H, the instruction will result in
register B also containing 39H.
31
LD
Operation: r
r,
(IY +dJ
(IY+d)
Format:
Operands
r,
LD
(IY+d)
11.> >>>>:a >I

I0:1~<-~.1 :1: 0I
I ..
:.\:< : : :
FD
Description:
The operand (IY+d)
(the contents of Jhe Index Register
IY summed with a two's complement diiplacement integer
d)
is loaded into register r, where r identifies
register A, B, C, D, E, H or L, assembled as follows in
the object code:
Register
!:.
A .. 111
B .. 000
C .. 001
DOlO
E .. 011
H .. 100
L .. 101
M CYCLES:
T STATES:
19(4,4,3,5,3)
None
32
4 MHZ E.T.: 4.75
Example:
If the Index Register IY contains the number 25AFH. the
instruction
LD B.
(IY+19H)
will cause the calculation of the sum 25AFH + 19H. which

points to memory location 25C8H.
If th~s address
contains byte 39H. the instruction will result in
register B also containing 39H.
33
LD
Operation: (HL)
CHL1,
Format:
Opcode
Operands
LD
(HL), r
0: 1 : 1 : 1 : 0
~r~1
Description:
The contents of register r are loaded into the memory
location specified by the contents of thellL register
pair.
The symbol r identifies register A, B, C, D, E, H
or L, assembled as follows in the object code:
Register
A -
111
B
C
D
E
H
L
000
001
010
all
100
101
M CYCLES: 2
T STATES: 7(4,3)
4 MHZ E. T .:
1. 75
None
Example:
If the contents of register pair HL specifies memory
location 2146H, and the B register contains the byte
29H, after the execution of
LD (HL), B
memory address 2146H will also contain 29H.
34
LD
(IX +dJ,
(IX+d)
Operation:
Format:
Opcode
Operands
LD
(IX+d), r
>: >>>: >I

1>>>:a :-7r~1
11
DD
I~<:: >1
Description:
The contents of register r are loaded into the memory
address specified by the contents of Index Register IX
summed with d, a two's complement displacement integer.
The symbol r identifies register A, B, C, D, E, H or L,
Register
A
r
111
B 000
C 001
D 010
E' 011
H 100
L 101
M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75
None
35
Example:
If the C register contains the byte lCH, and the Index
Register IX contains 3100H, then the instruction
LD
(IX+6H), C
will perform the sum 3100H + 6H and will load lCH into
memory location 3106H.
36
LD
CIY+dJ,
Operation:
(IY+d) +- r
Format:
Operands
LD
(IY+d), r
>>>>>:a >I
Ia: <<<o7---;r+-1
11
1< : :<
FD
::. I
Description:
The contents of register
address specified by the
Index Register IY and d,
integer. The symbol r is
following table.
r are loaded into the memory

sum of the contents of the
a two's complement displacement
specified according to the
Register
A -
111
B - 000
C - 001
D - 010
E -
011
H - 100
L - 101
U CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75
None
37
Example:
If the C register contains the byte 48H, and the Index
Register IY contains 2AIIH, then the instruction
LD (IY+4H), C
will perform the sum 2AIIH + 4H, and will load 48H into
memory location 2A15.
38
LD
(HLJ,
(HL) <-n
Operation:
Format:
Opcode
LD
Ia : a
Operand
(HL) ,n
>>:a >>:a I
I" : In: : : :
36
Description:
Integer n is loaded into the memory address specified by
the contents of the HL register pair.
M CYCLES: 3
T STATES:
10(4,3,3)
4 UHZ E. T .:
2. 50
None
Example:
If the HL register pair contains 4444H, the instruction
LD (HL), Z8H
will result in the memory location 4444a containing the
byte Z8H.
39
LD
Operation:
CIX+dJ,
(tX+d) ~n
Format:
Opcode
Operands
LD
(IX+d), n
< >>> >
I 1 :0
:a I
I a: a: <a: <0 I
I~<:: ;'1
1~n1 : : >1
< <
DO
36
Description:
The n operand is loaded into the memory address
specified by the sum of the contents of the Index
Register IX and the two's complement displacement
operand d.
M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75
Condition'Bits Affected:
None
Example:
If the Index Register IX contains the number 219AH the
instruc tion
LD (IX+5H), 5AH
would result in the byte 5AH in the memory address
219FH.
40
LD
(IY +dJ,
(IY+d) +-n
Operation:
Format:
Operands
(IY+d) ,n
LD
11>1
I >>>;a >>:a I
0
I'; : :<: : >1

II In: : : >1
FD
36
Description:
Integer n is loaded into the memory location specified
by the contents of the Index Register summed with the
two's complement displacement integer d.
M CYCLES:
T STATES:
19(4,4,3,5,3)
MHZ E.T.:
4.75
NONE
Example:
If the Index Register IY contains the number A940H,
instruction
LD (IY+10H),
97H
would result in byte 97 in memory location A950H.
41
the
LD
A,
A ~ (Be)
Operation:
Format:
Opcode
Operands
LD
A. (BC)
Description:
The contents of the memory location specified by the
contents of the BC register pair are loaded into the
Accumulator.
U CYCLES: 2
T STATES:
7(4.3)
4 MHZ E. T .:
1, 75
None
Example:
If the BC register pair contains the number 4747H. and
memory address 4747ll contains the byte 12H. then the
instruc tion
LD A.
(BC)
will result in byte 12H in register A.
42
(ESC)
LD
(DE)
A,
Operation:
+-
(DE)
Format:
Opcode
Operands
LD
A,
(DE)
Description:
The contents of the memory location specified by the
register pair DE are loaded into the Accumulator.
11 CYCLES:
T STATES:
7(4,3)
4 UHZ E. T .:
1. 75
None
Example:
If the DE register pair contains the number 30A2H and
memory address 30A2H contains the byte 22H, then the
instruction
LD A,
(DE)
will result in byte 22H in register A.
43
LD
A,
A ..... (nn)
Operation:
Format:
Operands
LD
I0 : 0
A,
(nn)
>>:
1 : '0 : 1 : 0
3A
I~n(::: I
I~n(
: : ;'1
Descript Lon:
The contents of
operands nn are
n operand after
two-byte memory
M CYCLES: 4
the memory location specified by the

loaded into the Accumulator.
The first
the op code is the low ordder byte of a
address.
T STATES:
13(4,3,3,3)
4 MHZ E.T.:
3.25
None
Example:
If the contents of nn is number 8832H, and the content
of memory address 8832H is byte 04H, after the
instruction
LD A,
(nn)
byte 04H will be in the Accumulator.
44
(nn)
LD
(BCl,
(BC) +- A
Operation:
Format:
Opcode
Operands
LD
(BC) ,A
Description:
The contents of the Accumulator are loaded into the
memory location specified by the contents of the
register pair BC.
11 CYCLES: 2
T STATES:
7(4,3)
411HZ E. T .: 1. 75
None
Example:
If the Accumulator contains 7AH and the BC register pair
contains 1212H the instruction
LD (BC),A
will result in 7AH being in memory location 12120.
45
LD
(DE),
(DE) +- A
Opera tion:
Format:
Operands
LD
(DE) ,A
Description:
memory location specified by the contents of the DE
register pair.
M CYCLES:
T STATES:
7(4,3)
4 MHZ E.T.: 1.75
None
Example:
If the contents of register pair DE are 1128H, and the
Accumulator contains byte AOH, the instruction
LD
will
(DE) ,A
result in AOH being in memory location 1128H.
46
LD
(nnJ,
(nn)+-A
Operation:
Format:
Operands
LD
I 0 ;a
(nn) ,A
>>;a ;a >: I
0
l~nJ
l~nJ
32
: : .. I
: : >1
Description:
memory address specified by the operand nn.
The first
operand after the op code is the low order byte of nn.
M CYCLES:
T STATES:
13(4,3,3,3)
4 MHZ E.T.:
3.25
None
Example:
If the contents of the Accumulator are byte D7H,
the execution of
LD
(3141H),A
D7H will be in memory location 3141H.
47
after
LD
A~I
Operation:
Format:
Operands
LD
A,
>:1: >>:
I
r:
11
0 :1:0 :1:0 :
0:
ED
1: 1
57
Description:
The contents of the Interrupt Vector Register I
loaded into the Accumulator.
H CYCLES:2
T STATES:
9(4,5)
4 HHZ
EoT.:
2.25

S:
Z:
H:
p/v:
N:
C:
Set if I-Reg. is negative;

reset otherwise
Set if I-Reg. is zero;
reset otherwise
Reset
Contains contents of IFF2
Reset
Not affected
Note:
If an interrupt occurs during execution of this
instruction, the Parity flag will contain a O.
48
are
A,
LD
A,
A+-R
Operation:
Format:
Operands
LD
\1
A,R
>>: >>: >I

0
Ia; <
0:
<<<< I
1
ED
5F
Description:
The contents of Memory Refresh Register R are loaded
into the Accumulator.
N CYCLES:
T STATES:
9(4,5)
4 MHZ EoT.:
2.25
S:
Z:
II:
P/V:
N:
c:
Set if R-Reg. is negative;

reset otherwise
Set if R-Reg. is zero;
reset otherwise
Reset
Contains contents of IFF2
Reset
Not affected
49
LD
I +-A
Operation:
Format:
Operands
LD
I,A
I<<<a: << >I

Ia: < a: a: << I
0
0:
ED
47
Description:
Interrupt Control Vector Register, I.
N CYCLES:
T STATES:
9(4,5)
None
50
4 NHZ EoT.:
2. 25
LD
R,
R+-A
Operation:
Format:
Operands
LD
R,A
I<<<a; <<a;
I0: <n: 0:
<<<1I
ED
4F
Description:
Memory Refresh register R.
M CYCLES:
T STATES:
9(4,5)
None
51
4 MHZ E.T.:
2.25
-16 BIT LOAD GROUP-
52
LD
dd,
nn
dd~nn
Operation:
Fo rma t:
Operands
dd,
LD
Ia : a : d: d: 0: a : a: 1I
I .. :
1
In: : : ..
In: : : ..
Description:
The two-byte integer nn is loaded into the dd register
pair, where dd defines the BC, DE, HL, or SP register
pairs, assembled as follows in the object code:
Pair
dd
BC
DE
HL
SP
00
01
10
11
The first n operand after

byte.
M CYCLES:
T STATES:
the op code is the low order
10(4,3,3)
4 MHZ
E.T.:
2.SO
None
Example:
After
the execution of
LD HL,
SOOOH
the contents of the 8L register pair will be SOOOH.
53
LD
IX,
IX +- nn
Operation:
Format:
Operands
LD
I X, nn
>: >>>: >I

<a: >I
0
DO
o: 0 :
0: 0: 0
21
.. I
., I
In: : : >1
In: II .. I
Description:
Integer nn is loaded into the Index Register IX.
The
first n operand after the op code is the low order byte.
H CYCLES:
T STATES:
14(4,4,3,3)
4 MHZ E.T.:
None

Example:
After the instruction
LD IX,45A2H
the Index Register will contain integer 45A2H.
54
3.50
nn
LD
IY,
nn
Operation:
IV
nn
Format:
Operands
IY,nn
LD
<1:1:1:1:1:0>1 FD
o: 0:<0:0:0:0
21
>
1
.. I In: : : >1
.. I
In: :: >1
Description:
Integer nn is loaded into the Index Register IY.
The
first n operand after the op code is the low order byte.
M CYCLES:
T STATES:
14(4,4,3,3)
4 MHZ E.T.:
3.50
None
Example:
After the instruction:
LD IY,7733H
the Index Register IY will contain the integer 7733H.
55
LD
Operation:
H ~ (nn+1).
HL,
L~ (nn)
Format:
Operands
LD
HL, (nn)
0: 0: 1: 0: 1: 0: 1:0
2A
l" : :n(
: : .. I
I .. : : n( : : .. I
Description:
The contents of memory address (nn) are loaded into the
low order portion of register pair HL (register L), and
the contents of the next highest memory address (nn+l)
are loaded into the high order portion of HL (register
H).
The first n operand after the op code is the low
order byte of nn.
M CYCLES:
T STATES:
16(4,3,3,3,3)
4 MHZ E.T.: 4.00
None
Example:
If address 4545H contains 37H and address 4546H contains
AIH after the instruction
LD HL,(4545H)
the HL register pair will contain A137H.
56
(nn]
LD
dd,
(nn)
ddH'~-(nn+1)
Operation:
ddL,*-(nn)
~:
Operands
LD
dd,(nn)
1:1:1:0':1:1:0:11
0:1:1:0:1:11
ED
.. : In: : : .. I
.. : In: : : .. I
Description
The contents of address (nn) are loaded into the low
order portion of register pair dd, and the contents of
the next highest memory address (nn+l) are loaded into
the high order portion of dd.
Register pair dd defines
BC, DE, HL, or SP register pairs, assembled as follows
in the object code:
Pair
dd
BC
DE
HL
SP
00
01
10
11
The first n operand after the op code is the low order

byte of (nn).
20(4,4,3,3,3,3) 4
None
57
MH~
E.T.: 5.00
Example:
If Address 2130H contains 65H and address 2131M contains
78H after the instruction
LD BC .. (2130H)
the BC register pair will contain 7865H.
58
LD
IX,
(nn)
Operation:
IXH
+-
(nn+lt IXL
+-
(nn)
Format:
Operands
IX, (nn)
LD
1: 1:0: 1: 1: 1:0: 1
DD
o: 0 :
2A
1 : 0: 1 : 0 : 1 : 0
': : : n: : : :
.; .. In: : : ;.
Description:
The contents of the address (nn) are loaded into the low
order portion of Index Register IX, .and the contents of
the next highest memory address (nn+l) are loaded into
the high order portion of IX. The first n operand after
the op code is the low order byte of nn.
M CYCLES:
T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00
None
Example:
DAH, after the instruction
LD IX,(6666H)
the Index Register IX will contain DA92H.
59
LD
Operation:
IY,
IYH+-(nn+1). IYL+-(nn)
Format:
Operands
LD
IY, (nn)
0>1
a; a; <a; <a; <
01
FD
2A
.; ; :n:: : >1
.;; In::: ;'1
Description:
The contents of address (nn) are loaded into the low
order portion of Index Register IY, and the contents of
-the next highest memory address (nn+l) are loaded into
the high order portion of IY. The first n operand afte.r
the op code is the low order byte of nne
M CYCLES:
T STATES:
20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00

None

Example:

DAH, after the instruction
LD !Y, (6666H)
t-he Index Register I'Y will contain DA92H.
60
(rnnJ
LD
HL
(nn],
Operation:
(nn+1) +- H .. (nn)+- L
Operands
LD
(nn).HL
0: 0: I; 0: .0;0: 1:01 22
I..
II n11 II II
I.. : :<1"1 .. I
Description:
The contents of the low order portion of register pair
HL (register L) are loaded into memory address (ntt) and
the contents of the high order portion of HL (register
H) are loaded into the next highest memory address
(nn+l).
The first n operand after the op code is t'he
low order byte of iln.
M CYCLES:
TS TATES: 16 (4,3.3.3,3)
Condition Bits
Afet~ed:
4 MHZ E.T.: 4.00
None
Example:
If the content of register pair HL is 483AH. aft,er' the
instruction
LD (B229H).HL
address B229H) will contain 3AH. "and address B22AH will
contain 48H.
61
LD
Operation:
(nn).
(nn+1)+-ddH. (nn)+-ddL
Format:
Operands
LD
(nn) ,dd
1> :1:0; 1:<0:
ED
0;1:0:0;1:
.. : In: : : ..
.; : In; : : ;.
Description:
The low order byte of register pair dd is loaded into
memory address (nn); the upper byte is loaded into
memory address (nn+l). Register pair dd defines either
BC, DE, HL, or SP, assembled as follows in the object
code:
BC
DE
HL
SP
00
01
10
11
The first n operand after the op code is the low order

byte of a two byte memory address.
M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ
None
62
E~T.:
5.00
de
Example:
If register pair BC contains the number 4644H,
instruction
the
LD (lOOOH),BC
will result in 44H in memory location lOOOH, and 46H in
memory location lOOlH.
63
LD
(nn+1)
Operation:
IXH. (nn)
(nn),
IXL
Format:
Operands
LD
(nn) ,IX
>: >:
o: 0:
0: 1
1 : 0: 1
DD
1: 0: 0: 0: 1: 0 1 22
.; : In: : : >1
.; : In: : : .. I
Description
The low order byte in Index Register IX is loaded into
memory address (nn); the upper order byte is loaded into
the next highest address (nn+1).
The first n operand
after the op code is the low order byte of nn.
M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00
None
Example:
If the Index Register IX contains 5A30H, after the
instruction
LD (4392H) ,IX
memory location 4392H will contain number 30H and
location 4393H will contain 5AH.
64
IX
LD
IV
(nnl,
Operation:
(nn+1)
IYH.
(nn)
IYL
~:
Operands
LD
(nn), IY
11 >>:1: 1>:0: 1
I0: 0: 1:0: 0; 0: 1:0
FD
22
I.. : :ni::"1
1< : In:: : ;.
Description:
The low order byte in Index Register IY is loaded into
memory address (nn); the upper order byte is loaded into
memory locat,ion (nn+l).
The first n operand after the
op code is the low order byte of nn.
M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00
None
Example:
If the Index Register IY contains 4174H after the
instruction
LJI (8838H), IY
memory location 8838H will cont.ain number 74Hand memory
location 8839H will contain 41H.
65
LD
Operation:
BP,
SP+-HL
Format:
Opcode
Operands
LD
SP,HL
Description:
The contents of the register pair HL are loaded into tht
Stack Pointer SP.
M CYCLES:
T STATES: 6
4 MHZ E. T .: L 50
None
Example:
If the register pair HL contains 442EH, after the
instruction
LD SP,HL
the Stack Pointer will also contain 442EH.
66
HL
LD
BP,
Operation:
IX
SP ~ IX
Format:
Operands
SP,IX
LD
>:a >>>;a >'

11 >>>>:a :a >I
11
DO
F9
Description:
The two byte contents of Index Register IX are loaded
into the Stack Pointer SP.
M CYCLES:
T STATES: 10(4,6)
4 MHZ E.T.: 2.50
None
Example:
If the contents of the Index Register IX are 98DAH,
after the instruction
LD SP,IX
the contents of the Stack Pointer will also be 98DAH.
67
LD
Operation:
BP,
SP ~ IV
Format:
Opcode
Operands
LD
SP,IY
>>>>>;a >I
I<<<<<a; >I
11
FD
F9
Description:
The two byte contents of Index Register IY are loaded
into the Stack Pointer SP.
H CYCLES:
T STATES: 10(4,6)
4 MHZ E. T .:
2 50
None
Example:
If Index Register IY contains the integer A227H, after
the instruc tion
LD SP,IY
the Stack Pointer will also contain A227H.
68
IV
qq
PUSH
PUSH qq
Operation:
(SP-2)~qqL. (SP-1)~qqH
Format:
Operands
qq
PUSH
11 :1:q : q :0 : 1:0 : 1 I
De!ilcription:
The contents of the register pair qq are pushed into the
external memory LIFO (last-in. first-out) Stack.
The
Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack.
This
instruction first decrements th~ ~p and loads the high
order byte of register pair qq into the memory address
now specified by the SP; then decrements the SP again
and loads the low order byte of qq into the memory
location corresponding to this new address in the SP.
The operand qq identifies register pair BC. DE. RL. or
AF. assembled as follows in the object code:
Pair
qq
BC
DE
HL
AF
00
01
10
11
M CYCLES:
T STATES:
11(5.3.3)
4 MHZ E. T.:
2.75
None

Example:
If the AF register pair contains 2233H and the Stack

Pointer contains 1007H. after the instruction
PUSH AF
memory address 1006H will contain 22H. memory address
1005H will contain 33H. and the Stack Pointer will
contain 1005H.
69
PUSH
Operation:
(SP-2) ~ IXL. (SP-1) ~ IXH
Format:
Opcode
Operands
PUSH
IX
>>>:a >I
>: >:a >I
11 :1:0
11 :1
0 :0
DO
E5
Description:
The contents of the Index Register IX are pushed into
the external memory LIFO (last-in, first-out) Stack.
The Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack. This
instruction first decrements the SP and loads the high
order byte of IX into the memory address now specified
by the SP; then decrements the SP again and loads the
low order byte into the memory location corresponding to
this new address in the SP.
M CYCLES:
T STATES: 15(4,5,3,3)
411HZ E. T .: 3. 75
None
Example:
If the Index Register IX contains 2233H and the Stack
Pointer contains 1007H, after the instruction
PUSH IX
memory address 1006H will contain 22H, memory address
1005H will contain 33H, and the Stack Pointer will
contain 1005H.
70
IX
PUSH
IV
Operation:
(SP-2) +-IYL, (SP-1) +-IYH
Format:
Opcode
Operands
PUSH
IY
>>: >I
11 :1>: >: >I
11 : 1 : 1 : 1
0 :0
FD
E5
Description:
The contents of the Index Register IY are pushed into
the external memory LIFO (last-in, first-out) Stack~
The Stack Pointer (SP) register pair holds the 16-bit
This
instruction first decrements the SP and loads the high
order byte of IY into the memory address now specified
by the SP; then decrements the SP again and loads the
low order byte into the memory location corresponding to
this new address in the SP.
M CYCLES:
T STATES: 15(4,5,3,3)
MHZ E. T .: 3. 75
None
Example:
If the Index Register IY contains 2233H and the Stack
Pointer contains 1007H, after the instruction
PUSH IY
memory address l006H will contain 22H, memory address
1005H will contain 33H, and the Stack Pointer will
contain 1005H.
71
POP qq
Operation:
qqH ~ (SP+1). qqL ~ (SP)
Format:
Operands
qq
POP
Description:
The top two bytes of the external memory LIFO (last-in,
first-out) Stack are popped into register pair qq.
The
This
instruction first loads into the low order portion of
qq, the byte at the memory location corresponding to the
contents of SP; then SP is incremented and the contents
of the corresponding adjacent memory location are loaded
into the high order portion of qq and the SP is now
incremented again.
The operand qq identifies register
pair BC, DE, HL, or AF, assembled as follows in the
object code:
Pair
BC
DE
HL
AF
M CYCLES:
!:.
00
01
10
11
T STATES: 10(4,3,3)
None
72
4 MHZ
E.T.:
2.50
Example:
If the Stack Pointer contains IOOOH, memory location
IOOOH contains 55H, and location IOOIH contains 33H, the
instruction
POP HL
will result in register pair HL containing 3355H, and
the Stack Pointer containing I002H.
73
POP IX
Operation:
IXH +- (SP+1), IXL +- (SP)
Format:
Operands
POP
IX
11 :1:0 >>>:0
P;1 >;0 ;0 ;0 ;0
>I
>,
DD
E1
Description:
first-out) Stack are popped into Index Register IX.
The
instruction first loads into the low order portion of IX
the byte at the memory location corresponding to the
into the high order portion of IX. The SP is now
incremented again.
M CYCLES:
T STATES: 14(4,4,3,3)
4 M8Z E. T .: 3. 50
None
Example:
If the Stack Pointer contains 10008, memory location
10008 contains 558, and location 10018 contains 338, the
instruc tion
POP IX
will result in Index Register IX containing 33558, and
the Stack Pointer containing 10028.
74
POP IY
Operation:
IYH +- (SP+1). IYL +- (SP)
Forma t:
Operands
IY
POP
10>1
1<0;0;0:0>1
FD
E1
Description:
first-out) Stack are popped into Index Register IY.
The
instruction first loads into the low order portion of IY
the byte at the memory location corresponding to the
into the high order portion of IY.
The SP is now
incremented again.
M CYCLES:
T STATES: 14(4,4,3,3)
4 MHZ E. T .: 3. 50
None
Example:
If the Stack Pointer contains 1000H, memory location
1000H contains 55H, and location 1001H contains 33H, the
instruc tion
POP IY
will result in Index Register IY containing 3355H, and
the Stack Pointer containing 1002H.
75
-EXGlAr'lJ[, BLOCK TRANSFER AND SEARGI GROUP-
76
EX
HL
DE.
DE
Operation:
HL
Format:
Operands
EX
DE.HL
Description:
The two-byte contents of register pairs DE and HL are
exchanged.
M CYCLES: 1
T STATES: 4
4 MHZ E.T.: LOO

None
Example:
If the content of register pair DE is the number 2822H.
and the content of the register pair HL is number 499AH.
after the instruction
EX DE.HL
the content of register pair DE will be 499AH and the
content of register pair HL will be 2822H.
77
EX
Operation:
AF,
AF ~ AF
Format:
AF,AF'
EX
Description:
The two-byte contents of the register pairs AF and AF'
are exchanged.
(Note: register pair AF' consists of
registers A' and F'.)
M CYCLES:
T STATES: 4
4 MHZ E.T.: l.00

None
Example:
If the content of register pair AF is number 9900H, and
the content of register pair AF' is number 5944H, after
the instr uc t ion
EX AF,AF'
the contents of AF will be 5944H, and the contents of
AF' will be 9900H.
78
AF'
EXX
Operation:
(BC)
+>
(BC'), (DE)
+>
(DE'), (HL)
+>
(HL')
Format:
Opcode
Operands
EXX
Description:
Each two-byte value in register pairs BC, DE, and HL is
exchanged with the two-byte value in BC', DE', and HL',
respectively.
M CYCLES: 1
4 MHZ E. T .: 1. 00
T STATES: 4
None
Example:
If the contents of register pairs BC, DE, and HL are the
numbers 445AH, 3DA2H, and 8859H, respectively, and the
contents of register pairs BC', DE', and HL' are 0988H,
9300H, and OOE7H, respectively, after the instruction
EXX
the contents of the register pairs will be as follows:
BC: 0988H; DE: 9300H; HL: OOE7H; BC': 445AH; DE': 3DA2H;
and HL': 8859H.
79
EX
Operation:
(SPJ,
H+>(SP+1) .. l+>(SP)
Format:
Operands
(SP) ,HL
EX
Description:
The low order byte contained in register pair HL is
exchanged with the contents of the memory address
specified by the contents of register pair SP (Stack
Pointer), and the high order byte of HL is exchanged
with the next highest memory address (SP+l).
M CYCLES: 5
T STATES: 19(4,3,4,3,5)
4 MHZ E.T.: 4.75
None
Example:
If the HL register pair contains 7012H, the SP register
pair contains 8856H, the memory location 8856H contains
the byte IIH, and the memory location 8857H contains the
byte 22H, then the instruction
EX (SP),HL
will result in the HL register pair containing number
2211H, memory location 8856H containing the byte 12H,
the memory location 8857H containing the byte 70H and
the Stack Pointer containing 8856H.
80
HL
EX
(SPJ,
IX
IXH
Operation:
-++ (SP+11,
IXL -++ (SP)
Format:
Opcode
Operands
EX
(SP),IX
I <<a: <<< >I

I <<<a: a: a: < I.
0
DD
E3
Description:
The low order byte in Index Register IX is exchanged
with the contents of the memory address specified by the
contents of register pair SP (Stack Pointer), and the
high order byte of IX is exchanged with the next highest
memory address (SP+1).
M CYCLES: 6
T STATES: 23(4,4,3,4,3,5)
4 MHZ E.T.: 5.75
None
Example:
If the Index Register IX contains 3988H, the SP register
the byte 90H, and memory location 0101H contains byte
48H, then the instruction
EX (SP),IX
will result in the IX register pair containing number
48908, memory location 0100H containing 88H, memory
location 0101H containing 39H and the Stack Pointer
containing 0100H.
81
EX
(SPJ.
IYH ~ (SP+1), IYL ~ (SP)
Operation:
Format:
Operands
(SP) .IY
EX
1<11
I <<<a; a; a; <
11
FD
E3
Description:
The low order byte in Index Register IY is exchanged
with the contents of the memory address specified by the
contents of register pair SP (Stack Pointer). and the
high order byte of IY is exchanged with the next highest
memory address (SP+l).
M CYCLES: 6
T STATES: 23(4.4.3.4.3.5)
4 MHZ E.T.: 5.75
None
Example:
If the Index Register IY contains 3988H. the SP register
pair contains OlOOR. the memory location OlOOH contains
the byte 90ll. and memory location OlOlH contains byte
48H. then the instruction
EX (SP). IY
will result in the IY register pair containing number
4890H. memory location OlOOH containing 88H. memory
location OlOlH containing 39H. and the Stack Pointer
containing OlOOH.
82
IY
LDI
(DE)+-(HLl. DE+-DE+l. HL+-HL+l. BC+-BC-l
Operation:
Format:
Ope ode
Operands
LDI
11
>: 1: >>: >

I
ED
11: 0: 1: 0: 0: 0: 0: 0I
AO
Description:
A byte of data is transferred from the memory location
addressed by the contents of the ilL register pair to the
memory location addressed by the contents of the DE
register pair.
Then both these register pairs are
incremented and the BC (Byte Counter) register pair is
decremented.
H CYCLES:
T STATES:
16(4,4,3,5)

-------------S:
Z:
li:
P/V:
N:
C:
Not affected
Not affected
Reset
Set if BC-1,O;
reset otherwise
Reset
Not affected
83
4 HHZ E. T .: 4. 00
Example:
If the HL register pair contains llllH, memory location
llllH contains contains the byte 88H, the DE register
byte 66H, and the BC register pair contains 7H, then the
instruction
LDI
will result in the following contents in register pairs
and memory addresses:
HL
(llllH)
DE
(2222H)
BC
11l2H
88H
2223H
88H
6H
84
LDIR
LDIR
Operation:
(DE)~(HLI. DE~DE+1. HL~HL+1. BC~BC-1
Forma t:
Operands
LDIR
11: 1: 1: 0:
r: 1: 0: 1I
I r: 0: 1: 1: 0: 0: 0: 0I
ED
BO
Description:
This two byte instruction transfers a byte of data from
the memory location addressed by the contents of the HL
register pair to the memory location addressed by the DE
register pair.
Then both these register pairs are
incremented and the BC (Byte Counter) register pair is
decremented. If decrementing causes the BC to go to
zero, the instruction is terminated.
If BC is not zero
the program counter is decremented by 2 and the
instruction is repeated.
Interrupts will be recognized
and two refresh eyeless will be executed after each data
transfer.
Note that if BC is set to zero prior to
instruction execution, the instruction will loop through
64K bytes.
For BC-O:
M CYCLES:
T STATES:
21(4,4,3,5,5)
T STATES:
16(4,4,3,5)
4 MHZ E.T.: 5.25
For BC=O:
M CYCLES:
85
4 MHZ E.T.: 4.00
s:
Z:
H:
P/V:
N:
C:
Not affected
Not affected
Reset
Reset
Reset
Not affected
Example:
If the HL register pair contains IIIIH, the DE register
pair contains 2222H, the BC register pair contains
0003H, and memory locations have these contents:
(llllH)
(l1l2H)
(l1l3H)
aaH
36H
A5H
(2222H)
(2223H)
(2224H)
66H
59H
C5H
then after the execution of

LDIR
the contents of register pairs and memory locations will
be:
HL
DE
BC
11l4H
2225H
oooon
(llllH)
(l1l2H)
(l1l3H)
a8H
36H
A5H
(2222H)
(2223H)
(2224H)
86
8aH
36H
A5H
LDD
(DE)~(HL), DE~DE-1. HL~HL-1. BC~BC-1
Operation:
Format:
Operands
Opcode
LDD
I <1: <0: 1: <0: 11
ED
I 1: 0: <0: 1: 0: 0: 0I
A8
Descripttion:
register pair to the memory location addressed by the
contents of the DE register pair.
Then both of these
register pairs including the BC (Byte Counter) register
pair are decremented.
~l
CYCLES: 4
T STATES: 16(4,4,3,5)

S:
z:
H:
p/v:
N:
C:
Not affected
Not affected
Reset
Set if BC-1~O;
reset otherwise
Reset
Not affected
87
4 MHZ E.T.: 4.00
Example:
If the HL register pair contains IIIIH, memory location
IIIIH contains the byte 88H, the DE register pair
contains 2222H, memory location 2222H contains byte 66H,
and the BC register pair contains 7H, then the
instruction
LDD
will result in the following contents in register pairs
and memory addresses:
HL
(UIIH)
DE
(2222H)
BC
UIOH
88H
222lH
88H
6H
88
LDDR
(DE)+-(HL)~
Operation:
DE+-DE-1,. HL+-HL-1. BC+-BC-1
~:
Operands
LDDR
10>1
I<a: <<<a: a: I
0
ED
B8
Description:
register pair to the memory location addressed by the
contents of the DE register pair.
Then both of these
registers as well as the BC (Byte Counter) are
decremented. If decrementing causes the BC to go to
zero, the instruction is terminated.
If BC is not zero,
the program counter is decremented by 2 and the
Interrupts will be recognized
and two refresh eyeless will be executed after each data
transfer.
Note that if BC is set to zero prior to
64K bytes.
For BC-O:
M CYCLES:
T STATES:
21(4,4,3,5,5)
T STATES:
16(4,4,3,5)
4 MHZ E.T.: 5.25
For BC-O:
M CYCLES:

S:
Z:
H:
P/V:
N:
Not affected
Not affected
Reset
Reset
Reset
89
4 MHZ E.T.: 4.00
Example:
If the HL register pair contains 1114H. the DE register
pair contains 2225H. the BC register pair contains
0003H. and memory locations have these contents:
( 1114H)
(l113H)
(l112H)
A5H
36H
SSH
(2225H)
(2224H)
(2223H)
C5H
59H
66H

LDDR
the contents of register pairs and memory locations will
be:
HL
DE
BC
lll1H
2222H
OOOOH
(l114H)
(l113H)
(l112H)
A5H
36H
SSH
(2225H)
(2224H)
(2223H)
A5H
36H
SSH
90
CPI
Operation:
A-(HLI.
HL~HL+1. BC~BC-1
Operands
CPI
I<<< >>:a >I

I<0: <a: a: a: 0>I
0
ED
Al
Description:
The contents of the memory location addressed by the HL
register pair is compared with the contents of the
Accumulator.
In case of a true compare, a condition bit
is set.
Then HL is incremented and the Byte Counter
(register pair BC) is decremented.
M CYCLES:
T STATES:
16(4,4,3,5)
4 MHZ E. T.:
4.
aa

S:
Z:
H:
P/V:
N:
C:
Set if result is negative;

reset otherwise
Set if A=(HL);
reset otherwise
Set if borrow from
Bit 4; reset otherwise
Set if BC-l=a;
reset otherwise
Set
Not affected
Example:
If the aL register pair contains IIIIH, memory location
IIIIH contains 3BH, the Accumulator contains 3BH, and
the Byte Counter contains aaalH, then after the
execution of
91
CPI
the Byte Counter will contain OOOOH, the HL register
pair will contain 1112H, the Z flag in the F register
will be set, and the P/V flag in the F register will be
reset.
There will be no effect on the contents of the
Accumulator or address IlllH.
CPIR
A-(HL). HL~HL+1. BC~BC-1
Operation:
Forma t:
Operands
CPIR
11:0:0>1
I<0 >:a :a :0 I
>
>
ED
B1
Description:
Accumulator.
is set.
The HL is incremented and the Byte Counter
(register pair BC) is decremented.
If decrementing
causes the BC to go to zero or if A-(HL), the
instruction is terminated.
If BC is not zero and
A-(HL), the program counter is decremented by 2 and the
instruction is repeated. Interrupts will be recognized
and two refresh cycles will be executed after each data
transfer.
Note that if BC is set to zero before
64K bytes, if no match is found.
For BC=O and A-(HL):
M CYCLES:
T STATES:
21(4,4,3,5,5)
4 MHZ E.T.: 5.25
For BC-O or A-(HL):

M CYCLES:
T STATES:
16(4,4,3,5)
93
4 MHZ E. T.: 4.00

S:
z:
H:
p/V:
N:
C:

reset otherwise
Set if A-(HL);
reset otherwise
Set if borrow from
Set if BC-I-O;
reset otherwise
Set
Not affected
Example:
If the HL register pair contains IlllH, the Accumulator
contains F3H, the Byte Counter contains 0007H, and
memory locations have these contents:
(llllH)
(1l12H)
(11l3H)
52H
OOH
F3H

CPIR
the contents of register pair HL will be 1114H, the
contents of the Byte Counter will be 0004H, the P/V flag
in the F register will be set and the Z flag in the F
register will be set.
94
CPO
A-(HLI. HL+-HL-1. BC+-BC-1
Operation:
~:
Operands
CPD
1<01
I< >;0 >;0 ;0 >I
0
ED
A9
Description:
Accumulator.
is set.
The HL and the Byte Counter (register pair BC)
are decremented.
M CYCLES:
T STATES:
16(4,4,3,5)
4 MHZ E. T.:
4.00

S:
Z:
H:
p/V:
N:
C:

reset otherwise
Set if A=(HL);
reset otherwise
Set if borrow from
Set if BC-l=O;
reset otherwise
Set
Not Affected
Example:
If the HL register pair contains IIIIH, memory location
IIIIH contains 3BH, the Accumulator contains 3BH, and
the Byte Counter contains 0001H, then after the
ex'ecution of
95
the Byte Counter will contain OOOOH, the HL register

pair will contain 1110H, the Z flag in the F register
will be set, and the P/V flag in the F register will be
reset.
There will be no effect on the contents of the
Accumulator or address llllH.
CPDR
A-(HL)I HL+-HL-1
Operation:
BC+-BC-1
Format:
Operands
CPDR
1<0:0>1
I<0 >>>:0 :0 >I
ED
B9
Description:
Accumulator.
is set.
The HL and BC (Byte Counter) register pairs are
decremented.
If decrementing causes the BC to go to
zero or if A=(HL), the instruction is terminated.
If BC
is not zero and A-(HL), the program counter is
decremented by 2 and the instruction is repeated.
Interrupts will be recognized and two refresh eyeless
will be executed after each data transfer.
Note that if
BC is set to zero prior to instruction execution, the
instruction will loop through 64K bytes, if no match is
found.
For BC-O and A-(HL):
M CYCLES: 5
T STATES:
21(4,4,3,5,5)
4 MHZ E.T.: 5.25
For BC-O or A-(HL):
M CYCLES: 4
T STATES:
16(4,4,3,5)
97
4 MHZ E.T.: 4.00

S:
reset otherwise
Z:i'tet i f A=(HL);
reset otherwise
H:
Set if borrow from
P/V:
Set if BC-I=O;
reset otherwise
N:
Set
C:
Not affected
Example:
If the HL register pair contains 1118H, the Accumulator
contains F3H, the Byte Counter contains 0007H, and
memory locations have these contents:
(lll8H)
(1l17H)
(lll6H)
52H
OOH
F3H

CPDR
the contents of register pair HL will be 1115H, the

contents of the Byte Counter will be 0004H, the P/V flag
in the F register will be set, and the Z flag in the F
register will be set.
98
-8 BIT ARIlHrrIC AND LCXJlCAL Gf{)UP-
99
ADD
A,
Operation:
+-
A +r
Format:
Operands
Opcode
A,r
ADD
Description:
The contents of register r are added to the contents of
the Accumulator, and the result is stored in the
Accumulator. The symbol r identifies the registers
A,B,C,D,E,H or L assembled as follows in the object
code:
Register
A
B
C
D
E
H
L
M CYCLES:
III
000
001
010
011
100
101
T STATES: 4
4 MHZ E.T. : 1. 00

S:
Z:
H:
p/V:
N:
C:
Set if resul t is negative;

reset otherwise
Set if result is zero;
reset otherwise
Set if carry from
Set if overflow;
reset otherwise
Reset
Set if carry from
100
Example:
If the contents of the Accumulator are 44H, and the
contents of register Care IlH, after the execution of
ADD A,C
the contents of the Accumulator will be 55H.
101
ADD A,
A+-A+n
Operation:
Format:
Operands
Opcode
ADD
A.n
I<<a: a: a: << I
I.. : In: : : .. I
0
C6
Description:
The integer n is added to the contents of the
Accumulator and the results are stored in the
Accumulator.
M CYCLES:
T STATES:
7(4.3)
4 MHZ E. T .: 1. 75
s:
Z:
H:
P/V:
N:
C:
Set if result is nega,tive;

reset otherwise
reset otherwise
Set if carry from
Set if overflow;
reset otherwise
Reset
Set i f car r y from
Example:
If the contents of the Accumulator are 23H. after the
execution of
ADD A.33H
102
ADD
Operation:
A,
A ~ A + (HL)
Format:
Operands
Opcode
A, (HL)
ADD
Description:
The byte at the memory address specified by the contents
of the HL register pair is added to the contents of the
Accumulator and the result is stored in the Accumulator.
M CYCLES:
T STATES: 7(4,3)
4 MHZ E. T .: 1. 75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if carry from
Bit 3; ~eset otherwise
Set if overflow;
reset otherwise
Reset
Set i f car r y from
Example:
---If the contents of the Accumulator are AOH, and the
content of the register pair HL is 2323ll, and memory
location 2323H contains byte 08H, after the execution of
ADD A, (HL)
the Accumulator will contain ABH.
103
(HLJ
ADD
(IX+dJ
A,
A~A+(IX+d)
Operation:
Format:
Operands
ADD
A, (IX+d)
11 :1: 0
>>>:a >I
<< I
: :< : : : I
11 :a: a: a: a:
I:
DD
86
Description:
The contents of the Index Register (register pair IX) is
added to a two's complement displacement d to point to
an address in memory.
The contents of this address is
then added to the contents of the Accumulator and the
result is stored in the Accumulator.
M CYCLES:
~TATES:
19(4,4,3,5,3)
4 MHZ E.T.:
4.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if carry from
Set if overflow;
reset otherwise
Reset
Set if carry from
If the Accumulator contents are 11H, the Index Register

IX contains 1000H, and if the content of memory location
104
lOOSH is 22H, after the execution of

ADD A, (IX+SH)
'105
ADD
(IY+dJ
A,
Operation:
A+-A+(IY+d)
~:
Operands
ADD
11
A, (IY+d)
>>>>>;a >I
11 :0
:a :a :a >>:
I~d:::
FD
86
.. ,
Description:
The contents of the Index Register (register pair IY) is
added to a two's complement displacement d to point to
an address in memory. The contents of this address is
then added to the contents of the Accumulator and the
result is stored in the Accumulator.
M CYCLES:
T STATES:
19(4,4,3,5,3)
4 MHZ E.T.:
4.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if carry from
Set if overflow;
reset otherwise
Reset
Set if carry from bit 7;
reset otherwise
Example:
If the Accumulator contents are IIH, the Index Register
pair IY contains 1000H, and if the content of memory
106
location lOOSH is 22H,
after the execution of
ADD A, (I Y+SH)
107
ADC
A,
Operation:
A+-A+s+CY
Format:
ADC
Operands
---A,s
The s operand is any of r,n,(HL),(IX+d) or (IY+d) as

defined for the analogous ADD instruction.
These
various possible opcode-operand combinations are
ADC A, r
>:0 >>~r*:
ADC A,n
:0
CE
.. : In: : I ;.
ADC A, (HL)
ADC A, (IX+d)
<0:0:0:<0
8E
>:0>
DO
;a:a;a
8E
.; : >: : : ..
ADC A, (IY+d)
>:0>
:0;0:0>:0
I: : :d:
FD
8E
: : ;.
*r identifies registers B,C,D,E,H,L or A assembled as

follows in the object code field above:
108
Register
B
C
D
000
001
010
all
H
L
100
101
111
Description:
The s operand, along with the Carry Flag ("C" in the F
register) is added to the contents of the Accumulator,
and the result is stored in the Accumulator.
INSTRUCTION
M CYCLES
T STATES
4 MHZ E.T.
ADC
ADC
ADC
ADC
ADC
1
2
2
5
5
4
7(4,3}
7(4,3}
19(4,4,3,5,3}
19(4,4,3,5,3}
LOa
L 75
L 75
A,r
A,n
A, (HL)
A, (IX+d)
A,(IY+d}
4.75
4.75

S:
Z:
H:
p/V:
N:
C:

reset otherwise
reset otherwise
Set if carry from
Set if overflow;
reset otherwise
Reset
Set if carry from
Example:
If the Accumulator contains 16H, the Carry Flag is set,
the HL register pair contains 6666H, and address 6666H
contains 10H, after the execution of
ADC A, (HL)
the Accumulator will contain 27H.
109
SUB
A+-A-s
Operation:
Format:
Operands
SUB
defined for the analogous ADD instruction.
These
SUB r
SUB n
SUB (HL)
SUB (IX+d)
<a; a; <~ r7<<a; <a; <<

0
.; : In: : : ..
:a: a: <a: <<
0
>;a >>>;a >

:a ;a >:a >>;a
.; : Id :
SUB (IY+d)
D6
96
DD
96
;.
11 : 1 : 1 : 1 : 1 : 1 : 0 : 1
FD
11 ; 0 : 0 : 1 : 0 ; 1 : 1 ; 0
96
I.: : :d: : ; :

110
Register
B
C
D
E
H
L
A
E...
000
001
010
011
100
101
III
Description:
The s operand is subtracted from the contents of the
Accumulator, and the result is stored in the
Accumulator.
INSTRUCTION
M CYCLES
STATES
4
7 (4,3)
7 (4,3)
19(4,4,3,5,3)
19(4,4,3,5,3)
SUB r
SUB n
SUB (HL)
SUB (I X+d)
SUB (I Y+d)
4 MHZ E. T.
1. 00
1. 75
1. 75
4.75
4.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if borrow from
Set if overflow;
reset otherwise
Set
Set if borrow;
reset otherwise
Example:
If the Accumulator contains 29H and register D contains
llH, after the execution of
SUB D
111
sac
A,
Operation:
A+-A-s-CY
Format:
Operands
Opcode
A,s
SBC

defined for the analogous ADD instructions.
These
SBC A,r
:O:0~r~
SBC A,n
>:0:0
DE
.; : In! : : ;.
>>>>:a
>:0 >>>:0 >
SBC A, (HL)
:0 :0
SBC A,(IX+d)
9E
DD
9E
I~:d:
SBC A,(IY+d)
11
1
: : ;.
>>>>> ;0 >
1::;1;1:1:1;
I : :
FD
9E
:< : : ..

112
Register
B
C
D
E
H
L
A
E..
000
00 1
010
all
100
101
III
Description:
The s operand, along with the Carry Flag ("C" in the F
register) is subtracted from the contents of the
Accumulator, and the result is stored in the
Accumulator.
INSTRUCTION
SBC
SBC
SBC
SBC
SBC
H CYCLES
STATES
A, r
A,n
A, (HL)
A, (IX+d)
A, (IY+d)
4
7(4,3)
7 (4,3)
19(4,4,3,5,3)
19(4,4,3,5,3)
4 MHZ EoT.
1. 00
1. 75
1. 75
4.75
4.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if borrow from
Set if overflow;
reset otherwise
Set
Set if borrow;
reset otherwise
Example:
If the Accumulator contains 16H, the carry flag is set,
the HL register pair contains 3433H, and address 3433H
contains 05H, after the execution of
SBC A, (HL)
113
AND
Operation:
A /\
Format:
Operands
Opcode
AND
The s operand is any of r,n,(HL),(IX+d) or (IY+d), as

These
AND r
AND n
l:a>:a :a~r~
>>:a :a >>:a
1
E6
.. : In: : : ;.
AND (HL)
AND (IX+d)
<a: <a: a: <<

>;a >>>;a >
<a: r: a: a: <<
a
AND (IY+d)
: : :< : :
>>>>>: a >
: a >:
r: r: a
.. : :< : : :
0 :0 :
A6
DO
A6
FD
A6
*r identifies registers B,G,D,E,D,L or A assembled as

114
Register
B
C
D
E
H
L
A
000
001
010
011
100
101
111
Description:
A logical AND operation is performed between the byte
specified by the s operand and the byte contained in the
Accumulator; the result is stored in the Accumulator.
M CYCLES
T STATES
4 MHZ E.T.
n
(HL)
(IX+d)
(IX+d)
7(4,3)
7(4,3)
19(4,4,3,5,3)
19(4,4,3,5,3)
1. 00
1. 75
1. 75
INSTRUCTION
AND
AND
AND
AND
AND
4.75
4.75

S:
Z:
H:
p/V:
N:
C:

reset otherwise
reset otherwise
Set
Set if parity even;
reset otherwise
Reset
Reset
Example:
If the B register contains 7BH (0111 1011) and the
Accumulator contains C3H (1100 0011) after the execution
of
AND B
the Accumulator will contain 43H (01000011).
115
OR
Operation:
A ..... A Vs
Format:
Operands
OR
The s operand is any of r,n,(HL),(IX+d) or (IY+d), as
defined for tqe analogous ADD instructions.
These
OR r
:o:o~r~
OR n
>>>: >>:
0
F6
.; : In: : : ..
OR (HL)
OR (IX+d)
>: <<
>: >>>:a:
>>: >>:
:0 :1
:0
OR (IY+d)
0 :
86
DD
86
.. : :< : : ..
>:a :
<a: <<a: <<
.; : :< : : ;.
:1 :1 :1 :1
FD
86

116
Register
B
C
D
E
H
L
A
E-..
000
001
010
011
100
101
111
Description:
A logical OR operation is performed between the byte
specified by the s operand and the byte contained in the
Accumulator; the result is stored in the Accumulator.
INSTRUCTION
OR
OR
OR
OR
OR
M CYCLES
r
n
(HL)
(IX+d)
(I Y+d)
T STATES
4 MHZ E.T.
4
7 (4,3)
7(4,3)
19(4,4,3,5,3)
19(4,4,3,5,3)
1. 00
1. 75
1. 75
4.75
4.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Reset
Set if parity even;
reset otherwise
Reset
Reset
Example:
If the H register contains 48H (010001000) and the
Accumulator contains 12H (00010010) after the execution
of
OR H
the Accumulator will contain 5AH (01011010).
117
XOR
Operation:
A+-Affis
Format:
Operands
XOR
The s operand is any of r,n, (HL),(IX+d) or (IY+d), as
These
XOR r
l:a>:a >7-: 7--
XOR n
<<<a; <<<
EE
.; : In: : : ;.
XOR (HL)
XOR (IX+d)
<a; <a; <<<
>;a >>>;a >
1:0: 1: 0:1:1:1:
AE
DO
AE
.; : :<: : ;.
XOR (IY+d)
<<<<<<a;
<a; <a; <1: <
'1 I :
<: I
FD
AE
I'

118
Register
E.
000
001
010
011
100
101
111
B
C
D
E
H
L
A
Description:
A logical exclusive-OR operation is performed between

the byte specified by the s operand and the byte
contained in the Accumulator; the result is stored in
the Accumulator.
INSTRUCTION
XOR
XOR
XOR
XOR
XOR
M CYCLES
r
n
(HL)
(IX+d)
(IY+d)
T STATES
4 MHZ E.T.
4
7(4,3)
7(4,3)
19(4,4,3,5,3)
19(4,4,3,5,3)
1. 00
1. 75
1. 75
4.75
4.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Reset
Set if parity even;
reset otherwise
Reset
Reset
Example:
If the Accumulator contains 96H (10010110), after the
execution of
XOR 5DH
(Note: 5DH = 01011101)
the Accumulator will contain CBH (11001011).
119
CP
Operation:
A-
Format:
Operands
CP
The s operand is any of r.n.(HL).(IX+d) or (IY+d). as
These
CP r
CP n
CP (HL)
CP (IX+d)
<0; <<<--:-r;<<<<<<<
0
FE
.; I In! : : ;.
<a; <<<<<
<<a; <<<a;
BE
DD
<a; <<1: 1: 1: 0 BE
.; : :< : : :
0> FD
I
CP (IY+d)
1: 0: 1: 1; 1: 1: 1; 0 BE
.; : :< : : ;.
*r identifies registers B.C.D.E.H.L or A assembled as
120
Register
B
C
D
E
H
L
A
!.
000
001
010
011
100
101
111
Description:
The contents of the s operand are compared with the
contents of the Accumulator.
If there is a true
compare. the Z flag is set.
The execution of this
instruction does not affect the contents of the
Accumulator.
INSTRUCTION
M CYCLES
T STATES
4 MHZ E.T.
CP
CP
CP
CP
CP
1
2
2
5
5
4
7(4.3)
7(4.3)
19(4.4.3.5.3)
19(4.4.3.5.3)
LOO
1.75
L 75
4.75
4.75
r
n
(HL)
(IX+cf)
(IY+d)

S:
Z:
H:
p/V:
N:
C:

reset otherwise
reset otherwise
Set if borrow from
Set if overflow;
reset otherwise
Set
Set if borrow;
reset otherwise
Example:
If the Accumulator contains 63H. the HL register pair
6000H and memory location 6000H contains 60H.
the instruction
c~ntains
CP (HL)
will result in the p/V flag in the F register being
reset.
121
INC
Operation:
r~r+1
Format:
Opcode
Operands
INC
Description:
Register r is incremented. r identifies any of the
registers A,B, C,D,E,H or L, assembled as follows in the
obj ect code.
Register
A
B
C
D
E
H
L
M CYCLES:
r
111
000
001
010
011
100
101
T STATES: 4
4 MHZ E.T.: LOO

S:
Z:
H:
P/v:
N:
C:

reset otherwise
reset otherwise
Set if carry from
Set ~f r was 7FH before
operation; reset otherwise
Reset
Not affected
122
Example:
If the contents of register Dare 280, after the
execution of
INC D
the contents of register D will be 29H.
123
INC
(HLJ
Operation:
(HL) ..... (HL)+1
Format:
Opcode
Operands
INC
(HL)
Description:
The byte contained in the address specified by the
contents of the HL register pair is incremented.
U CYCLES:
T STATES: 11(4,4,3)
4 MHZ E. T .: 2.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if carry from
Set if (HL) was 7FH before
Reset
Not Af f e c ted
Example:
If the contents of the HL register pair are 3434H, and
the contents of address 3434H are 82H, after the
execution of
INC (HL)
memory location 3434H will contain 83H.
124
INC
(IX+dJ
Operation: (IX+d) +- (IX+d)+1

Format:
Opcode
Operands
INC
(IX+d)
>:a >>>:a >I

Ia :a >>:a >:a :a I
11
I.. : :d:
DO
34
: : .. I
Description:
The contents of the Index Register IX (register pair IX)
are added to a two's complement displacement integer d
to point to an address in memory.
The contents of this
address are then incremented.
M CYCLES:
T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

S:
Z:
H:
p/V:
N:
C:

reset otherwise
reset otherwise
Set if carry from
Set if (IX+d) was 7FH before
Reset
Not affected
125
Example:
If the contents of the Index Register pair IX are 2020H,
and the memory location 2030H contains byte 34H, after
the execution of
INC (IX+I0H)
the contents of memory location 2030H will be 35H.
126
INC
Operation:
CIY+dJ
(IY+d)+- (IY+d)+1
Opcode
Operands
INC
(IY+d)
11
>:1>>>: >I
0
Ia; a: <<a: <a;
FD
34
1< : :<: : .. I
Desc r iption:
The contents of the Index Register IY (register pair IY)
are added to a two's complement displacement integer d
to point to an address in memory. The contents of this
address are then incremented.
l-l: CYCLES:
T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

S:
Z:
H:
p/v:
N:
C:

reset otherwise
reset otherwise
Set if carry from
Set if (IY+d) was 7FH before
Reset
Not Affected
127
Example:
If the contents of the InAex Register pair IY are 2020H.
and the memory location 2030H contain byte 34H. after
the execution of
INC (IY+l OH)
the contents of memory location 2030H will be 35H.
128
-GENERAL PURPOSE ARIlHfICAND CPU CONTROL GROUPS-
131
Register
B
C
D
E
H
L
A
!.
000
001
010
all
100
101
111
Description:
The byte specified by the m operand is decremented.
INSTRUCTION
M CYCLES
T STATES
4 MHZ E.T.
DEC
DEC
DEC
DEC
1
3
4
11(4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)
1. 00
r
(HL)
(IX+d)
(IY+d)
6
6
2.75
5.75
5.75

S:
Z:
H:
p/v:
N:
C:

reset otherwise
reset otherwise
Set if borrow from
Bit 4, reset otherwise
Set if m was 80H before
Set
Not affected
Example:
If the D register contains byte 2AH, after the execution
of
DEC D
register D will contain 29H.
130

S:
Z:
H:
p/v:
N:
C:
Set if most significant bit

of Acc. is 1 after operation;
reset otherwise
Set if Acc. is zero after operation;
reset otherwise
See instruc tion
Set if Acc. is even parity after
Not affected
See instruction
Example:
If an addition operation is performed between 15 (BCD)
and 27 (BCD). simple decimal arithmetic gives this
result:
15
+27
42
But when the binary representations are added in the

Accumulator according to standard binary arithmetic.
0001
+0010
0011
0101
0111
1100
3C
the SUg is agbiguous.

The DAA instruction adjusts this
result so that the correct BCD representation is
obtained:
0011
+0000
0100
1100
0110
0010 42
133
DAA
Operation:
Format:
DAA
Description:
This instruction conditionally adjusts the Accumulator
for BCD addition and subtraction operations.
For
addition (ADD, ADC, INC) Qr subtraction (SUB,
SBC,DEC,NEG), the following table indicates the
operation performed:
OPERATION
ADD
ADC
INC
HEX
VALUE
C
IN
BEFORE UPPER
DAA
DIGIT
(bit
7-4)
HEX
VALUE
H
IN
BEFORE LOWER
DAA
DIGIT
(bit
3-0)
0
0
0
0
0
0
0
0
1
1
1
SUB
SBC
DEC
NEG
0
0
M CYCLES:
1
1
0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3
0-9
0-8
7-F
6-F
0
0
1
0
0
1
0
1
0
1
T STATES: 4
0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3
00
06
06
60
66
66
60
66
66
0-9
6-F
0-9
6-F
00
FA
AO
9A
4 MHZ E.T.:
132
NUMBER
ADDED C
TO
AFTER
BYTE
DAA
LOO
0
0
0
1
1
1
1
1
1
0
0
1
1
N!EG
A+-O-A
Operation:
Forma t:
NEG
1<01
I >:a ;a ;a >;a :a I
0
ED
44
Description:
The contents of the Accumulator are negated (two's
complement). This is the same as subtracting the
contents of the Accumulator from zero.
Note that 80H is
left unchanged.
M CYCLES:
T STATES: 8(4,4)
4 MHZ E.T.: 2.00

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if borrow from
Set if Acc. was 80H before
Set
Set if Acc. was not OOH before
135
CPL
A~
Operation:
Format:
CPL
Description:
The contents of the Accumulator (register A) are
inverted (l's complement).
M CYCLES:
T STATES: 4
4 MHZ E. T.:
1.00

S:
Z:
H:
P/V:
N:
C:
Not
Not
Set
Not
Set
Not
affected
affected
affected
affected
Example:
If the contents of the Accumulator are 1011 0100, after
the execution of
CPL
the Accumulator contents will be 0100 1011.
134
CY~Cy
Operation:
Format:
CCF
Description:
The Carry flag in the F register is inverted.
T STATES:
M CYCLES:
4 MHZ E.T.:
1.00

S:
Z:
H:
P/V:
N:
C:
Not affec ted

Not affected
Previous carry will be copied
Not affected
Reset
Set if CY was 0 before
137
Example:
If the contents of the Accumulator are
NEG
the Accumulator contents will be
136
NOP
Operation:
Format:
Opcode
NOP
Description:
The CPU performs no operation during this machine cycle.
M CYCLES:
T STATES:
MHZ E.T.:
None
139
1.00
SCF
Operation:
CY~1
Format:
SCF
Description:
The Carry flag in the F register is set.
M CYCLES:
4 MHZ E.T.: 1. 00
T STATES:

S:
Z:
H:
P/V:
N:
C:
Not affected
Not affected
Reset
Not affected
Reset
Set
138
01
Operation: IFF +- 0
Format:
Opcode
DI
Description:
DI disables the maskable interrupt by resetting the
interrupt enable flip-flops(IFFl and IF12). Note that
this instruction disables the maskable interrupt during
its execution.
M CYCLES:
T STATES: 4
4 MHZ E.T.: l.00
None
Example:
When the CPU executes the instruction
DI
the maskable interrupt is disabled until it is
subsequently re-enabled by an EI instruction. The CPU
will not respond to an Interrupt Request (INT) signal.
141
HALT
Operation:
Opcode
HALT
Description:
The HALT instruction suspends CPU operation until a
subsequent interrupt or reset is received. While in the
halt state, the processor will execute NOP's to maintain
memory refresh logic.
M CYCLES:
T STATES: 4
4 MHZ E.T.: LOO
None
140
1M
Operation:
Format:
Operands
1M
11
>>: >>:a >I
>: :a : >>: I
ED
46
Description:
The 1M 0 instruction sets interrupt mode O.
In this
mode the interrupting device can insert any instruction
on the data bus for execution by the CPU.
The first
byte of a multi-byte instruction is read during the
interrupt acknowledge cycle.
Subsequent bytes are read
in by a normal memory read sequence.
M CYCLES:
T STATES:
8(4,4)
None
143
MH Z E. T .:
2 00
EI
Operation:
IFF +-1
Format:
EI
Description:
The enable interrupt instruction will set both interrupt
enable flip flops (IFFI and IFF2) to a logic '1'
allowing recognition of any maskable interrupt.
Note
that during the execution of this inBtruction ~nd the
following instruction, maskable interrupts will be
disabled.
M CYCLES:
T STATES: 4
4 MHZ E.T.:
1.00
None
Example:
When the CPU executes instruction
EI
RETI
the maskable interrupt will be enabled after the
execution of the RETI instruction.
142
1M
Operation:
Format:
Operands
1M
>:01
I >>>>;a I
1
0 :1 :0
ED
5E
Description:
The 1M 2 instruction sets the vectoreed interrupt mode
2.
Thi. mode allows an indirect call to any memory
location by an 8 bit vecto~ supplied from the peripheral
device.
This vector then becomes the least significant
8 bits of the indirect pointer while the I register in
the CPU provides the most significant 8 bits. This
address points to an addreess in a vector table which is
the starting address for the interrupt service routine.
101 CYCLES:
T STATES:
8(4,4)
None
145
MHZ EoT.:
2.00
1M
Operation:
Format:
Operands
1M
11
>>: >>:a >I

0
ED
>: >:a >>:a I

0
56
Description:
The 1M instruction sets interrupt mode 1.
In this mode
the processor will respond to an interrupt by executing
a restart to location 0038H.
M CYCLES:
T STATES: 8(4,4)
None
144
MHZ E.T.:
2.00
-16 BIT
ARIlH~TIC
146
GRruP-
Example:
If register pair HL contains the integer 4242ll and
register pair DE contains IlllH, after the execution of
ADD HL,DE
the HL register pair will contain 5353H.
ADD
HL,
Operation:
55
HL ...... HL+ss
Format:
Opcode
Operands
ADD
HL,ss
Description:
The contents of register pair ss (any of register pairs
BC,DE,HL or SP) are added to the contents of register
pair HL and the result is stored in ilL.
Operand ss is
specified as follows in the assembled object code.
Register
Pair
ss
BC
DE
HL
SP
M CYCLES:
00
01
10
11
T STATES:
11(4,4,3)
4 MHZ E.T.:

S
Z
H
p/v
N
C
Not affected
Not affected
Set if carry out of
Not affected
Reset
Set if carry from
147
2.75
Example:
If the register pair BC contains 2222H, register pair HL
contains 5437H and the Carry Flag is set, after the
execution of
ADC HL,BC
the contents of HL will be 765AH.
150
ADC
HL,
Operation:
88
HL+-HL+ss+CY
Format:
Operands
ADC
HL,ss
I<<< >>:a >I

0
ED
1<1
Description:
BC,DE,HL or SP) are added with the Carry Flag (C flag in
the F register) to the contents of register pair HL, and
the result is stored in HL.
Operand ss is specified as
follows in the assembled object code.
Register
Pair
BC
DE
HL
SP
M CYCLES:
00
01
10
11
4 T STATES: 15(4,4,4,3) 411HZ E.T.: 3.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if carry out of
Set if overflow;
reset otherwise
Reset
Set if carry from
149
Example:
If the contents of the ilL register pair are 9999H, the
contents of register pair DE are 1111H, and the Carry
Flag is set, after the execution of
SBC ilL,DE
the contents of ilL will be 8887H.
1~
sac
HL,
Op era t ion:
88
Hl<-Hl-ss-CY
Format:
Operands
SBC
HL,ss
1:1:<:1:1::11
1: 1:::<\
ED
Description:
The contents of the register pair ss (any of register
pairs BC,DE,HL or SP) and the Carry Flag (C flag in the
F register) are subtracted from the contents of register
pair HL and the result is stored in HL.
Operand ss is
Register
Pair
BC
DE
HL
SP
H CYCLES:
00
01
10
11
T STATES:
15(4,4,4,3)
4 HHZ LT.:

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Set if a borrow from
Bit 12;reset otherwise
Set if overflow;
reset otherwise
Set
Set if borrow;
reset otherwise
151
3.75
Example:
If the contents of Index Register IX are 333H and the
contents of register pair BC are 5555H, after the
execution of
ADD IX,BC
the contents of IX will be BBBBH.
154
ADD
IX,
pp
IX +-IX + pp
Operation:
Forma t:
Opcode
Operands
ADD
IX,pp
11 : 1 : 0
1
>>>: >
0
DO
0>:0:0>1
Description:
The contents of register pair pp (any of register pairs
BC,DE,IX or SP) are added to the contents of the Index
Register IX, and the results are stored in IX.
Operand
pp is specified as follows in the assembled object code.
Register
Pair
BG
DE
IX
SP
00
01
10
11
15(4,4,4,3) 4 HHZ E.T.: 3.75

S:
Z:
H:
p/v:
N:
C:
Not affected
Not affected
Set if carry out of
Not affected
Reset
Set if carry from
153
Example:
If the contents of Index Register IY are 333H and the
contents of register pair BC are 555H, after the
execution of
ADD IY,BC
the contents of IY will be 8888H.
156
ADD
rr
IY,
IY+-IY+rr
Operation:
Format:
Opcode
Operands
ADD
IY.rr
>>>>>:a >I
0:0>:0:0>1
11
1
FD
Description:
The contents of register pair rr (any of register pairs
BC.DE.IY or SP) are added to the contents of Index
Register IY. and the result is stored in IY. Operand rr
is specified as follows in the assembled object code.
Register
Pair
-!.!..
BC
DE
IY
SP
M CYCLES:
00
01
10
11
T STATES:
15(4.4.4.3)
4 MHZ E.T.:

S:
Z:
H:
P/V:
N:
C:
Not affected
Not affected
Set if carry out of
Not affected
Reset
Set if carry from
155
3.75
INC
Operation:
IX+-IX+1
Format:
Opcode
Operands
INC
IX
>:a >>>:a >I

I :a >:a :a :a >>I
11
DD
23
Description:
The contents of the Index Register IX are incremented.
11 CYCLES:
T STATES:
10(4,6)
4 MHZ E.T.:
2.50
None
Example:
If the Index Register IX contains the integer 3300H
INC IX
the contents of Index Register IX will be 3301H.
158
IX
INC
88
Operation:
ss~ss+1
Format:
Opcodes
Operands
INC
ss
Description:
BC, DE,HL or SP) are incremented. Operand ss is
Register
Pair
ss
BC
DE
HL
SP
M
CYCLES:
00
01
10
11
T STATES:
MHZ E. T.
1. 50
None
Example:
If the register pair contains 1000H, after the execution
of
INC HL
HL will contain lOOlH.
157
DEC
Op era t io n :
SS +-
ss -1
Format:
Opcode
Operands
DEC
ss
Description:
The contents of register pair ss {any of the register
pairs BC,DE,HL or SP) are decremented. Operand ss is
CYCLES:
Pair
ss
BC
DE
HL
SP
00
01
10
11
4 }.1HZ E.T. :
T STATES:
L50
None
Example:
If register pair HL contains 1001H, after the execution
of
DEC HL
the contents of HL will be 1000H.
160
ss
INC
IV
Operation:
IY~IY+1
Format:
Opcode
Operands
INC
IY
I<<<<<< I
I a: <a; a; a; < I
0: 1
FD
23
0:
Description:
The contents of the Index Register IY are incremented.
M CYCLES:
T STATES:
10(4,6)
4 MHZ E. T :
2 50
None
Example:
If the contents of the Index Register are 2977H, after
the execution of
INC IY
the contents of Index Register IY will be 2978H.
159
DEC
Operation:
IY~IY-1
Format:
Operands
DEC
IY
I<<<<< >I
I ;a >;a >;a >>I
1: 0
FD
2B
Description:
The contents of the Index Register IY are decremented.
M CYCLES:
T STATES:
10 (4,6)
4 MHZ E.T.:
2.50
None
Example:
If the contents of the Index Register IY are 7649H,
DEC IY
the contents of Index Register IY will be 7648H.
162
IY
DEC
IX
Operation: IX +-IX-1
Opcode
Operands
DEC
IX
11 : 1 : 0 : 1 : 1 : 1 : 0 : 1
DD
28
0 : 0 : 1: 0 : 1: 0 : 1: 1
Description:
The contents of Index Register IX are decremented.
M CYCLES:
T STATES:
10(4,6)
MHZ E. T :
2 50
None
Example:
If the contents of Index Register IX are 2006H, after
the execution of
DEC IX
the contents of Index Register IX will be 2005H.
161
-ROTATE JWD SHIFT GROJP-
163
Example:
If
the
contents of
the Accumulator are
I 0I
after
the
execution of
RLCA
the contents of
the Accumulator and Carry Flag will be
165
RLCA
Operation:
rEJJ
A
Format:
Operands
RLCA
Description:
The contents of the Accumulator (register A) are rotated
left one bit position.
The sign bit (bit 7) is copied
into the Carry Flag and also into bit O.
Bit 0 is the
least significant bit.
M CYCLES:
T STATES
4 MHZ E.T.:
1.00

S:
Z:
H:
P/V:
N:
C:
Not affected
Not affected
Reset
Not affected
Reset
Data from Bit
164
7 of Ace.
Example:
If the contents of the Accumulator and the Carry Flag
RLA
the contents of the Accumulator and the Carry Flag will
be
167
RLA
I~I
Operation: ~
A
Format:
Operands
RLA
Description:
left one bit position through the Carry Flag. The
previous content of the Carry Flag is copied into bit O.
Bit 0 is the least significant bit.
t1 CYCLES:
T STATES:
4 MH Z
E. T.:
s:
Z:
H:
P/V:
N:
C:
Not affected
Not affected
Reset
Not affected
Reset
Data fro~ Bit 7 of Ace.
166
1. 00
Example:
If the contents of the Accumulator are

RRCA
be
169
RRCA
CEJlEJ
Operation:
Format:
Operands
RRCA
Description:
right one bit position.
Bit 0 is copied into the Carry
Flag and also into bit 7.
Bit 0 is the least
significant bit.
M CYCLES:
T STATES:
4 MH Z E. T .:

S:
Z:
H:
P/v:
N:
C:
Not affected
Not a f f e c t.e d
Reset
Not affected
Reset
Data from Bit 0 of Acc.
168
1. 00
Example:
If the contents of the Accumulator and the Carry Flag
are
C

RRA
be
C
171
RRA
Operation:
Format:
Operands
RRA
Description:
right one bit position through the Carry Flag.
The
previous content of the Carry Flag is copied into bit 7.
Bit a is the least significant bit.
H CYCLES:
T STATES:
4 HHZ
E.T.:

S:
Z:
H:
p/v:
N:
C:
Not affected
Not affected
Reset
Not affected
Reset
Data froc Bit
170 ,
of Ace.
1.00

S:
z:
II:
P/V:
N:
C:
Set if result is negativc;

rcset otherwise
reset otherwise
Reset
Set if parity even;
reset otherwise
Resct
Data from Bit 7 of
source register
Example:
If the contents of register rare
4
after thc execution of

RLC r
the contents of register r and the Carry Flag will be
C
173
RLC
Operation:
Format:
Operands
RLC
11
>;a ;a >;a >>I
0 :0 :0 :0 :0
CB
~r71
Description:
The contents of register r are rotated left one bit
position. The content of bit 7 is copied into the Carry
Flag and also into bit O.
Operand r is specified as
follows in the assembled object code:
Register
L
A
T STATES:
8(4,4)
D
E
H
M CYCLES:
.E.000
001
010
011
100
101
III
B
C
172
4 MHZ E.T.:
2.00
Example:
If the contents of the ilL register pair are 2828H, and
the contents of memory location 2828H are
4

RLC
(HL)
the contents of memory location 2828H and the Carry Flag

will be
C
175
RLe (HLJ
WEJJ
Operation:
(HL)
Format:
Operands
RLC
11
(HL)
>;a ;a >;a >>,
0 : 0 : 0 :0 : 0
>>;a ,
CB
06
Description:
The contents of the memory address specified by the
contents of register pair HL are rotated left one bit
Flag and also into bit O.
Bit 0 is the least
significant bit.
M CYCLES:
T STATES:
15(4,4,4,3)
4 MH Z E. T .:

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Reset
Set if parity even;
reset otherwise
Reset
Data from Bit 7 of
source register
174
3. 75
Example:
If the contents of the Index Register IX are lOOOH, and
the contents of memory location l022H are

RLC (IX+2H)
the contents of memory location l002H and the Carry Flag
will be
C
177
RLe (IX+dJ
Operation:
aJBJ
(IX+d)
Format:
Operands
RLC
11 :
(IX+d)
< <<>I
11 : 1
0 :1 :
:0 :0
>:
0 :1 :1 ,
I~d:::
0 :0 :0 :0 :0
>:
DO
CB
.. l
1 :0
06
Description:
The contents of the memory address specified by the sum
of the contents of the Index Register IX and a two's
complement displacement integer d. are rotated left one
bit position. The content of bit 7 is copied into the
Carry Flag and also into bit O.
Bit 0 is the least
significant bit.
M CYCLES:
T STATES:
23(4.4.3.5.4.3)
MHZ E.T.:

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Reset
Set if parity even;
reset otherwise
Reset
Data from Bit 7 of
source register
176
5.75
Example:
If the contents of the Index Register IY are lOOOH, and
4

RLC (IY+2H)
will be
179
RLe
CIY+dJ
Operation:
WBJ
(IY+dl
Format:
Operands
RLC
(1Y+d)
11 : 1 : 1 : 1 : 1 : 1 : 0 : 1
FD
11 : 1 : 0 : 0 : 1 : 0 : 1 : 1
CB
ISd::: .. \
I
0 :0 :0 :0 :0 : 1
>: I
0
06
Description:
The contents of the memory address specified by the sum
of the contents of the Index Register IY and a two's
complement displacement integer d are rotated left one
bit position. The content of bit 7 is copied into the
Carry Flag and also into bit O.
Bit 0 is the least
significant bit.
M CYCLES:
6 T STATES:
23(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

S:
Z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Reset
Set if parity even;
reset otherwise
Reset
Data from Bit 7 of
source register
178
RL (IY+d)
1;1;1;1>:1:0;1
10;
1< :
FD
CB
:< : : ;.
1;0;0>
16
*r identifies registers B.C.D.E.H.L or A specified as

follows in the assembled object code above:
Register
000
001
010
011
011
101
111
D
E
H
L
A
Description:
The contents of the m operand are rotated left one bit

Flag and the previous content of the Carry Flag is
copied into bit O.
INSTRUCTION
M CYCLES
T STATES
4 MHZ E.T.
RL
RL
RL
RL
2
4
8(4.4)
15(4.4.4.3)
23(4.4.3.5.4.3)
23(4.4.3.5.4.3)
2.00
3.75
5.75
5.75
r
(HL)
(IX+d)
(I Y+d)
6
6
181
RL
Operation:
18BJ
m
Format:
Operands
RL
The m operand is any of r,(HL), (IX+d) or (IY+d), as

~efined for the analogous RLe instructions.
These
specified as follows in the assembled object code:
RL r
RL (HL)
1 : 1 :0 :0 : 1 :0
>>I
a: 0: a: <o~r~
.< a; a; <0; <
o:
>:a:<<
>:a >>>: >
1:
0: 0
RL (IX+d)
CB
16
1 : 1 :0 :0
>: >>
~<:
o: 0 : 0 ; 1 ; 0
180
CB
DD
CB
: ..
>;
1:0
16
RRC
lBLB
Operation:
Format:
Operands
RRC
The m operand is any of r,(HL), (IX+d) or (IY+d), as
defined for the analogous RLC instructions.
These
RRC r
>: :a >: >: I

0
:-7r:>: >: >>
o: 0 : a: 0:
RRC (HL)
0 :0
>>>:0
>: >>>;a >
>;a ;a >;a >>
:0 :0 :0
RRC (IX+d)
7:--7<:: ;.
;a :a; >>>:
o
183
CB
CB
OE
DO
CB
OE

S:
z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Reset
Set if parity even;
reset otherwise
Reset
Data from Bit 7 of
source register
Example:
If the contents of register D and the Carry Flag are

RL D
the contents of register D and the Carry Flag will be
182

S:
z:
H:
P/V:
N:
C:

reset otherwise
reset otherwise
Reset
Set if parity even;
reset otherwise
Reset
Data from Bit 0 of
source register
Example:
If the contents of register A are

RRC A
the contents of register A and the Carry Flag will be
C
185
RRC (IY+d)
II>
>:0:>:
1< : :< : : >
1;;0;>:
1
FD
CB
OE
*r identifies registers B,C,D,E,H,L or A specified as

Register
B
C
D
E
H
.E..
000
001
010
all
100
101
111
A
Description:
The contents of operand m are rotated right one bit

position. The content of bit a is copied into the Carry
Flag and also into bit 7. Bit a is the least significant
bit.
INSTRUCTION
M CYCLES
T STATES
4 MHZ E.T.
RRC
RRC
RRC
RRC
2
4
6
6
8(4,4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)
2.00
3.75
5.75
5.75
r
(HL)
(IX+d)
(IHd)
184
<>I
I<< :a >:a >>I
RR (IY+d)
11 : 1 : 1 : 1 : 1 :
I : : :< :
FD
CB
: .. I
I :a :a >>>>:a I
0
IE

Register
E.
B
C
D
E
H
L
A
000
001
010
011
100
101
111
Description:
The contents of operand m are rotated right one bit
position through the Carry flag. The content of bit 0 is
copied into the Carry Flag and the previous content of
the Carry Flag is copied into bit 7. Bit 0 is the least
significant bit.
INSTRUCTION
RR
RR
RR
RR
r
(HL)
(IX+d)
(IY+d)
H CYCLES
T STATES
4 HHZ E.T.
8(4,4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)
2.00
3.75
5.75
5.75
187
RR
Operation:
lEHjJ
m
Format:
RR
The m operand is any of r, (HL), (IX+d), or (IY+d), as

defined for the analogous RLe instructions. These
RR r
<<a: a: < >>I

0
o: 0 : 0:
RR (HL)
1: 1
~r~
<<a: a: <a: <
:a :a >>>>:a
<<a: <<<a:
<<a: a: <a: <d
.; : :< : : .. \
o: a: a: <<<< I
o
RR (IX+d)
186
CB
CB
IE
DD
CB
IE
SLA
Operation:
Format:
Operands
SLA
The m operand is any of r. (HL). (IX+d) or (IY+d). as
defined for the analogous RLe instructions.
These
SLA r
1
>:a :a >:a: < I

1
CB
a: a: <a: o~r~1
SLA (IlL)
1: 1: 0 : 0: 1: 0: 1: 1
a: a: <a: a: << I
>:a >>>:a :
<<a: a: <a: <
0
SLA (IX+d)
CB
26
DD
CB
.; : >: : : >
o: 0 :
1:0:0: 1: 1: 0
189
26

S:
z:
H:
P/V:
N:
C:
Se t i f result is negative;
reset otherwise
Set i f result is zero;
reset otherwise
Reset
Se t i f parity is even;
reset otherwise
Reset
Data from Bit 0 of
source register
Exampl e:
the contents of memory location 4343H and the Carry Flag
are

RR (HL)
the contents of location 4343H and the Carry Flag will
be
188

S:
z:
II:
p/V:
Ii:
C:

reset otherwise
reset otherwise
Re se t
Set if parity is even;
reset otherwise
Reset
Data from Bit 7
Exampl e:
If the contents of register L are
SLA L
the contents of register L and the Carry Flag will be
191
SLA (IY+d)
10:
FD
10:0:<0:<
CB
I': : :<: : ;.
1
0:0:<0:0:
26

follows in the assembled object code field above:
Register
E..
B
C
D
E
H
L
A
000
001
010
011
100
101
111
Description:
An arithmetic shift left one bit position is performed
on the contents of operand m. The content of bit 7 is
copied into the Carry Flag. Bit 0 is the least
significant bit.
INSTRUCTION
SLA
SLA
SLA
SLA
r
(HL)
(I X+d)
(IY+d)
M CYCLES
T STATES
4 }1HZ E.T.
8 (4,4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)
2. 00
3.75
5.75
5.75
190
1<1:1>:1:1:0:11
11 >:0: 0>:0: 1: 1I
I" : :< : : ;'1
I0: 0>:0: 1: 1: 1: 0I
SRA(IY+d)
FD
CB
2E

follows in the assembled object code field above:
Register
B
C
D
E
H
L
A
.E.
000
001
010
all
100
101
111
An arithmetic shift right one bit position is performed

on the contents of operand m. The content of bit a is
copied into the Carry Flag and .the previous content of
bit 7 is un~hanged. Bit a is the least significant bit.
INSTRUCTION
SRA
SRA
SRA
SRA
r
(HL)
(IX+d)
(IY+d)
M CYCLES
T STATES
4 MHZ E.T.
8(4,4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)
2.00
3.75
5.75
5.75
193
BRA
cS-m o~gt.:J
Operation:
Format:
Operands
SRA
The m operand is any of r, (HL), (IX+d) or (IY+d) ,as
These
SRA r
< < a: a: < a: < 1I CB

a;O:<O:l~r;-
SRA(HL)
SRA(IX+d)
<<a; a; <a; <

a; a; < <<<
<<a; <<<0:
CB
0:
2E
1: 1: 0: 0: 1: 0: 1:
DO
CB
.; : :< : : ;.
a; a; <a; <<<
2E
192
SRL
o~
Operation:
Format:
Operands
SRL
The operand m is any of r, (HL), (IX+d) or (IY+d), as

These
SRL r
1: 1: 0: 0: 1: 0: 1: 1I CB
0:
SRL (HL)
o;r;r: l;-;-r~1
1: 1; 0: 0: 1: 0: 1: 1I CB
0: 0: 1: 1: 1: 1: 1: 0I 3E
SRL (IX+d)
;r :a: r;
>: >I
0
DD
>:0:0>:0>>, CB
.. : :< : : : I
a; a; <<<<< I
0
195
3E

S:
z:
H:
p/v:
N:
C:

reset otherwise
Set i f result is zero;
reset otherwise
Reset
Set i f parity is even;
reset otherwise
Reset
Data from Bit 0 of
source register
Example:
If the contents of the Index Register IX are lOOOH, and
4

SRA (IX+3H)
will be
194

S:
Z:
H:
p/v:
N:
C:
Reset
reset otherwise
Reset
Set if parity ~s even;
reset otherwise
Reset
Data from Bit 0 of
source register
Example:
If the contents of register Bare

SRL B
the contents of register B and the Carry Flag will be
197
SRL
(I Y+d)
11>1
FD
11: <0: 0
CB
>: < I
0:
I.. : Ict: : : .. I
I a: a: <<<<< I
0
3E

follows in the assembled object code fields above:
Register
B
C
D
E
H
L
A
E.
000
001
010
all
100
101
111
Description:
The contents of operand m are shifted right one bit
position. The content of bit a is copied into the Carry
Flag, and bit 7 is reset. Bit a is the least significant
bit.
IN STRUCTION
SRL
SRL
SRL
SRL
r
(HL)
(IX+d)
(IY+d)
M CYCLES
T STATES
8( 4,4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)
196
MHZ E.T.
2. 00
3.75
5.75
5.75
Example:
the contents of the Accumulator and memory location
5000H are
Accumulator
o
(5000H)
RLD
5000H will be
Accumulator
o
(5000H)
199
RLD
Operation:
A~(HL)
Format:
Opcode
Operands
RLD
11>1
I0: 1: r: 0: 1: <<1I
ED
6P
Description:
The contents of the low order four bits (bits 3,2,1 and
0) of the memory location (HL) are copied into the high
order four bits (7,6,5 and 4) of that same memory
location; the previous contents of those high order four
bits are copied into the low order four bits of ihe
Accumulator (register A); and the previous contents of
the low order four bits of the Accumulator are copied
into the low order four bits of memory location (HL).
The contents of the high order bits of the Accumulator
are unaffected.
Note: (HL) means the memory location
specified by the contents of the HL register pair.
1'1 CYCLES:
5 T STATES: 18(4,4,3,4,3) 4 HHZ E.T.: 4.50

S:
Z:
H:
P/V:
N:
C:
Set if Ace. is negative after

Set if Ace. is zero after
Reset
Set if parity of Ace. is even
after operation; reset otherwise
Reset
Not affected
198
Example:
5000H are
Accumulator
(5000H)
RRD

5000H will be
o
Accumulator
o
(5000H)
201
RRD
Operation:
A~(HL)
Format:
Opcode
Operands
RRD
I<<< <<Q: I
I >>:a; >>>I
0:
ED
67
Description:
The contents of the low order four bits (bits 3,2,1 and
0) of memory location (HL) are copied into the low order
four bits of the Accumulator (register A); the previous
contents of the low order four bits Gf the Accumulator
are copied into the high order four bits (7,6,~ ~nd 4)
of location (HL); and the previous contents of the high
order four bits of (HL) are copied into the low order
four bits of (HL).
The contents of the high order bits
of the Accumulator are unaffected.
Note:
(HL) means
the memory location specified by the contents of the HL
register pair.
H CYCLES:
T STATES: 18(4,4,3,4,31
4 MHZ E.T.: 4.50

S:
Z:
H:
P/V:
N:
C:
Set if Ace. is negative after

Set if Ace. is zero after
Reset
Set if parity of Ace. is even after
Reset
Not affected
200
-BIT SEL RESET AND lEST GRa.lP-
202
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Example:
If bit 2 in register B contains 0, after the execution
of
BIT 2,B
the Z flag in the F register will contain 1, and bit 2
in register B will remain O. Bit 0 in register B is the
least significant bit.
BIT
b,
Operation:
Z~rb
Format:
Operands
BIT
b,r
I<<a: a: < >>I

I0: 1~b~:~r7-1
0
CB
Description:
This instruction tests Bit b in register r and sets the
Z flag accordingly. Operands band r are specified as
Bit Tested
E.
Register
B
C
D
E
000
001
010
011
100
101
110
000
001
010
011
100
101
111
III
o
1
2
3
4
5
M CYCLES:
L
A
T STATES: 8(4,4)
4 MHZ E.T.:

S:
Z:
H:
p Iv:
N:
C:
Unknown
Set if specified Bit is
0; reset otherwise
Set
Unknown
Reset
Not affected
203
2.00
Example:
If the HL register pair contains 4444H, and bit 4 in the
memory location 444H contains 1, after the execution of
BIT 4, (HL)
the Z flag in the F register will contain 0, and bit 4
in memory location 4444H will still contain 1. (Bit 0 in
memory location 4444H is the least significant bit.)
206
BIT
b. CHLJ
Operation:
Z~(HLlt,
Format:
Operands
BIT
11
1
b, (HL)
>:a: < >>I

>~b~1 >: I
0:
CB
Description:
This instruction tests bit b in the memory location
specified by the contents of the HL register pair and
sets the Z flag accordingly.
Operand b is specified as
Bit Tested
0
1
2
3
4
5
6
7
M CYCLES:
1?
000
001
010
011
100
101
110
111
T STATES:
12(4,4,4)
4 MHZ E.T.:

S:
Z:
H:
P/V
H
C
Unknown
0; reset otherwise
Set
Unknown
Reset
Not affected
205
3.00

S:
z:
H:
P/V:
N:
C:
Unknown
0; reset otherwise
Set
Unknown
Reset
Not affected
Example:
If the contents of Index Register IX are 2000H. and bit
6 in memory location 2004H contains 1. after the
execution of
BIT 6. (IX+4H)
the Z flag in the F register will contain O. and bit 6
in memory location 2004H will still contain 1.
(Bit 0
in memory location 2004H is the least significant bit.)
208
BIT
b,
CIX+dJ
Format:
Operands
b,(IX+d)
BIT
>: >>>:rJ >

0
1:
1: >: >>
0 :0
DO
CB
.. : :<: : "
o >:-+b~O
Description:

specified by the contents of register pair IX combined
with the two's complement displacement d and sets the Z
flag accordingly. Operand b is specified as follows in
the assembled object code.
Bit Tested
1?
0
1
2
3
4
5
000
001
010
011
100
101
110
111
6
7
M CYCLES:
T STATES:
20(4,4,3,5,4)

S:
Z:
Unknown
0; reset otherwise
207
4 MHZ E.T.: 5.00

S:
z:
H:
p/V:
N:
C:
Unknown
OJ reset otherwise
Set
Unknown
Reset
Not affected
Example:
If the contents of Index Register are 2000H, and bit 6
in memory location 2004H contains 1, after the execution
of
BIT 6, (IY+4H)
the Z flag in the F register sill contain 0, and bit 6
in memory location 2004H will still contain 1.
(Bit 0
in memory location 2004H is the least significant bit.)
210
BIT
b,
CIY+dJ
BIT b, (IY+d)
Format:
Operands
BIT
b, (IY+d)
:1:1
>: >:a >I
: 1 : a :0
>:
0 :1 :1
FD
CB
~d::: >1
o >7-7b~ 1>:0I
Description:
specified by the contents of register pair IY combined
with the two's complement displacement d and sets the Z
flag accordingly. Operand b is specified as follows in
the assembled object code:
M CYCLES:
Bit Tested
.!?
0
1
2
3
4
5
6
7
000
001
010
011
100
1 01
110
111
T STATES:
20(4,4,3,5,4)
209
4 MHZ E.T.:
5.00
SET
Operation:
b,
(HL1b ~ 1
Forma t:
Operands
b, (HL)
SET
>: a: < >>I

1< 1~b-;-;< <0I
11
0 :
CB
Description:
Bit b in the memory location addressed by the contents
of register pair HL is set.
Bit Tested
E-
O
1
000
001
010
011
100
101
110
3
4
5
6
7
M CYCLES:
III
T STATES: 15(4,4,4,3)
4 MHZ E. T.:
3.75
None
Example:
If the contents of the HL register pair are 3000H, after
the execution of
SET 4,(HL)
bit 4 in memory location 3000H will be 1.
(Bit 0 in
212
(HLJ
SET
b,
Ope ra tion:
rb +-1
Format:
Operands
SET
b,r
11 >:a :a : 1:a : 1:1I

11 >~b-;-:~r-:--
CB
Description:
Bit b in register r (any of registers B,C,D,E,H,L or A)
is set.
Operands band r are specified as follows in
the assembled object code:
Bit
M CYCLES:
Register
E..
000
001
010
011
100
101
110
111
B
C
D
E
H
L
A
000
001
010
011
100
101
111
T STATES:
8(4,4)
MHZ E.T. :
2.00
None
Example:
SET 4,A
bit 4 in register A will be set.
significant bit.)
211
(Bit 0 is the least
Example:
If the contents of Index Register are 2000H, after the
execution of
SET O,(IX+3H)
(Bit 0 in
214
SET
b,
CIX+dJ
(IX+d)~~1
Operation:
Format:
Operands
SET
b, (IX+d)
>: >>>:a >

>: >;a >>
0
DD
0 :0
CB
~d::::.
1>7-7b~l
>:a
Description:
Bit b in the memory location addressed by the sum of the
contents of the IX register pair and the two's
complement integer d is set.
M CYCLES:
5.75
Bit Tested
.Q.
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
T STATES:
23(4,4,3,5,4,3)
None
213
4 MHZ E.T.:
the execution of
SET O,(IY+3H)

(Bit 0 in
216
SET
b,
Operation:
(IY+dJ
(IY+d)b +-1
Format:
Operands
b,(IY+d)
SET
>>>>>:a >I
11 >
: >:a >>I
11
0 :0
CB
.I
l~<::
11 : 17-+b~1
FD
:1 :0
Description:
Bit b in the memory location addressed by the sum of the
contents of the IY register pair and the two's
complement displacement d is set.
Operand b is
M CYCLES:
5.75
Bit Tested
E.
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
T STATES:
23(4,4,3,5,4,3)
4 MHZ E.T.:
None
Example:
If the contents of Index Register IY are 2000H, after
215
Bit Reset
Register
0
1
000
001
010
011
100
101
110
111
B
C
D
E
H
L
A
3
4
5
6
7
r
000
001
010
011
100
101
111
Description:
Bit b in operand m is reset.
INSTRUCTION
M CYCLES
T STATES
4 MHZ E.T.
RES
RES
RES
RES
4
4
6
6
8/(4,4)
15(4,4,4,3)
23(4,4,3,5,4,3)
23(4,4,3,5,4,3)
3.75
5.75
5.75
r
(HL)
(IX+d)
(IY+d)
2.00
None
Example:
RES 6,D
bit 6 in register D will be reset.
is the least significant bit.)
218
(Bit 0 in register D
RES
b,
Operation:
m
sb +- 0
Operands
Opcode
p,m
RES
Operand b is any bit (7 through 0) of the contents of

the m operand,(any of r, (HL), (IX+d) or (IY+das
defined for the analogous SET instructions. These
RES b,r
t :1
:0 :0 :
<>>I
0
CB
1;0 :~b+-:~r71
RES b,(HL)
>: >: >>I

0 :0
:O~b~l
RES b, (IX+d)
CB
>:01
>:
0 : 1 : 1 : 1 :0 : 1
>;0 : >:a >>

0
DO
CB
I~d:::
11 :0 7--:b~1 >:0
RES b, (IY+d)
11 >>>>>: >
11 >: >:
0
0 :0
.
11 : 7--:b~ 1>:a
I~d:::
0
217
FO
CB
-JlJ'P GIUJP-
219
CC,
Operation:
IF cc TRUE, PC +- nn
Format:
Opcode
Operands
JP
cc.nn
11 :1~cc~ 0 : 1:0 I
I.. : In: : : .. I
1< :
:n; : : :1
Note:
The first n operand in this assembled object code
is the low order byte of a 2-byte memory address.
Description:
If condition cc is true. the instruction loads operand
nn into register pair PC (Program Counter). and the
program continues with the instruction beginning at
address nn.
If condition cc is false. the Program
Counter is incremented as usual. and the program
continues with the next sequential instruction.
Condition cc is programmed as one of eight status which
corresponds to condition bits in the Flag Register
(register F). These eight status are defined in the
table below which also specifies the corresponding cc
bit fields in the assembled object code.
cc
CONDITION
RELEVANT
FLAG
000
001
010
011
100
101
110
111
NZ non zero
Z zero
NC no carry
C carry
PO parity odd
PE parity even
P sign positive
U sign negative
Z
Z
C
C
p/v
p/V
221
S
S
nn
nn
Operation:
PC+-nn
Format:
Operands
JP
nn
I<< :a :a :a >>I
I.. : >: : : ;'1
I.. : ,n; : : .. I
0
C3
Note:
The first operand in this assembled
is the low order byte of a 2-byte address.
obje~t
code
Description:
Operand nn is loaded into register pair PC (Program
Counter). The next instruction is fetched from the
location designated by the new contents of the PC.
M CYCLES:
T STATES:
10(4,3,3)
None
220
4 MHZ E;T.: 2.50
~R
Operation:
PC+-PC+e
Forma t:
Ope ode
JR
I :a :a >>:a :a ;a I
0
1~~-2:
18
: : ;.1
Description:
This instruction provides for unconditional branching to
other segments of a program.
The value of the
displacement e is added to the Program Counter (PC) and
the next instruction is fetched from the location
designated by the new contents of the PC.
This jump is
measured from the address of the instruction opcode and
has a range of -126 to +129 bytes.
The assembler
automatically adjusts for the twice incremented PC.
M CYCLES:
T STATES: 12(4.3.5)
4 MHZ E. T .:
3. 00
None
Example:
To jump forward 5 locations from address 480. the
following assembly language statement is used:
JR $+5
The resulting object code and final PC value is shown
below:
Location
Instruction
480
i8
481
03
482
483
484
485
PC after jump
223
M CYCLES:
T STATES:
10(4,3,3)
4 MHZ E. T .:
2.50
None

Example:
If the Carry Flag (C flag in the F register) is set and

the contents of address 1520 are 03H, after the
execution of
JP C,1520H
the Program Counter will contain 1520H, and on the next
machine cycle the CPU will fetch from address 1520H the
byte 03H.
222
JR C,$-4
below:
Location
Instruction
47C
47D
47E
47F
480
481
+-
38
FA
225
PC after j UClp
(2's complement-6)
~R
c,
If C = 0, continue
IfC=1, PC+-PC+e
Operation:
Format:
Operands
JR
C,e
I >>>:
0: 0
I*:e-~
0: 0: 0
38
:: :.,
Description:
This instruction provides for conditional branching to
other segments of a program depending on the results of
a test on the Carry Flag.
If the flag is equal to a
'1', the value of the displacement e is added to the
Program Counter (PC) and the next instruction is fetched
from the location designated by the new contents of the
PC.
The jump is measured from the address of the
instruction opcode and has a range of -126 to +129
bytes. The assembler automatically adjusts for the
twice incremented PC.
If the flag is equal to a '0', the next instruction to
be executed is taken from the location following this
instruc tion.
If condition is met:
11 CYCLES: 3
T STATES: 12(4,3,5)
4 MHZ E. To : 3 00
If condition is not met:

11 CYCLES:
T STATES: 7(4,3)
MHZ E. T .:
1. 75
None
Example:
The Carry Flag is set and it is required to jump back 4
locations from 480.
The assembly language statement is:
224
JR NC. $
The resulting object code and PC after the jump are

shown below:
Location
Instruction
480
481
30 +00
227
PC after jump
~R
Ne,
Oper a tion:
If C = 1, continue
If C = 0, PC ~ PC + e
Fo rmat:
Opcode
Operands
JR
NC,e
I0:0
>>:
I-:-+-:e-~
0:0: 0:01
30
: : .. I
Description:
a test on the Carry Flag.
If the flag is equal to '0',
the value of the displacement e is added to the Program
Counter (PC) and the next instruction is fetched from
the location designated by the new contents of the PC.
The jump is measured from the address of the instruction
opcode and has a range of -126 to +129 bytes.
The
assembler automatically adjusts for the twice
incremented PC.
If the flag is equal to a '1', the next instruction to
be executed is taken from the location following this
instruc tion.
If the condition is met:
1-1
CYCLES:
T STATES: 12(4,3,5)
4 HHZ E.T.:
3.00
If the condition is not met:

11 CYCLES:
T STATES:
7(4,3)
MHZ E. T .:
1. 75
None
Example:
The Carry Flag is reset and it is required to repeat the
jump instruction.
The assembly language statement is:
226
JR Z,$ +5
below:
Location
Instruction
28
300
301
302
303
304
305
03
PC after jump
229
~R
z,
Operation:
If Z = O. continue
If Z = 1, PC +- PC + e
Format:
Operands
JR
Z,e
>: >: ;a:

1*:e-2: :: :1
0: 0
0,
28
Description:
a test on the Zero Flag.
If the flag is equal to a '1',
Th'e jump is measured from the address of the instruc tion
opcode and has a range of -126 to +129 bytes.
The
incremented PC.
If the Zero Flag is equal to a '0', the next instruction
to be executed is taken from the location following this
instr uc tion.
If the condition is met:
M CYCLES: 3
T STATES: 12(4,3,5)
4 MHZ E. T.:
3.00
If the condition is not net:

M CYCLES:
T STATES: 7(4,3)
MHZ E. T .:
1. 75
None
Example:
The Zero Flag is set and it is required to jump forward
5 locations from address 300. The following assembly
language statement is used:
228
JR NZ,$-4
below:
Location
Instruction
47C
47D
47E
47F
PC after jump
20
FA
480
481
231
(2' complement-6)
~R
NZ,
If Z = 1, continue
If Z = 0, PC +- PC + e
Operation:
Format:
Opcode
Operands
JR
NZ,e
I >:
1-7-+-:
0 :0
0 :0 :0 : 0
e 2
- :
:0 ,
:.
20
Description:
a test on the Zero Flag.
If the flag is equal to a '0',
The jump is measured from the address of the instruction
opcode and has a range of -126 to +129 bytes. The
incremented PC.
If the Zero Flag is equal to a '1', the next instruction
to be executed is taken from the location following this
instruc tion.
If the condition is Det:
M CYCLES: 3
T STATES: 12(4,3,5)
4 HHZ E.T.:
3.00
If the condition is not met:

H CYCLES:
T STATES:
7(4,3)
MHZ E. T .:
1. 75
None
Exampl e:
The Zero Flag is reset and it is required to jump back 4
locations frOD 480.
~he assembly language statement is:
230
(IX)
Operation:
PC+-IX
Format:
Operands
(IX)
JP
>:< >
11 :1:0
1:0 I
11 :1:1:0 >:0 : 0 >I
DD
E9
Description:
The Program Counter (register pair PC) is loaded with
the contents of the IX Register Pair. The next
instruction is fetched from the location designated by
the new contents of the PC.
M CYCLES:
T STATES: 8(4,4)
MHZ E.T.:
2.00
None
Example:
If the contents of the Program Counter are 1000H, and
the contents of the IX Register Pair are 4800H, after
the execution of
JP (IX)
the contents of the Program Counter will be 4800H.
233
(HLJ
Operation:
PC+-HL
Format:
Operands
JP
(ilL)
Description:
the contents of the HL register pair. The next
M CYCLES:
T STATES:
4 MHZ E. T.: 1.00
None
Example:
If the contents of the Program Counter are 1000H and the
contents of the HL register pair are 4800H, after the
execution of
JP (HL)
232
D~NZJ
Operation:
Format:
DJNZ
Ia; a; a; <a; a; a;
1*~-2:
::
10
:11
Description:
This instruction is similar to the conditional jump
instructions except that a register value is used to
determine branching. The B register is decremented and
if a non zero value remains, the value of the
displacement e is added to the Program Counter (PC).
The next instruction is fetched from the location
designated by the new contents of the PC.
The jump is
measured from the address of the instruction opcode and
has a range of -126 to +129 bytes. The assembler
automatically adjusts for the twice incremented PC.
If the result of decrementing leaves B with a zero
value, the next instruction to be executed is taken from
the location following this instruction.
If B"O:
M CYCLES:
T STATES: 13(5,3,5)
4 MHZ E. T .:
3. 25
I f B-O:
M CYCLES:
T STATES: 8(5,3)
MHZ E. T .:
2.
None
Example:
A typical software routine is used to demonstrate the
use of the DJNZ instruction.
This routine moves a line
from an input buffer (INBUF) to an output buffer
235
(IY)
Operation:
PC+-IY
Format:
Operands
(IY)
JP
10>1
I<<<a; <a;
>
1
FD
E9
Description:
the contents of the IY Register Pair. The next
M CYCLES:
T STATES: 8(4,4)
MHZ E.T.:
2.00
None
Example:
If the contents of the Program Counter are 1000H and the
contents of the IY Register Pair are 4800H, after the
execution of
JP
(IY)
234
-00 JV{)
REIU~
237
GIUJP-
(OUTBUF).
It moves the bytes until it finds a CRt or
until it has moved 80 bytes, whichever occurs first.
LOOP:
LD
LD
LD
B,80
HL,Inbuf
DE,Outbuf
;Set up counter
;Set up pointers
LD
A, (HL)
LD
CP
JR
INC
INC
DJNZ
(DE) ,A
ODH
Z,DONE
HL
DE
LOOP
;Get next byte from

;input buffer
;Store in output buffer
;ls it a CR?
;Yes finished
;Increment pointers
Loop back i f 80
bytes have not
been moved
DONE:
236
Example:
If the contents of the Program Counter are IA47H, the
contents of the Stack Pointer are 3002H, and memory
locations have the contents:
Location
Contents
lA47H
lA48H
lA49H
CDH
35H
2lH
then if an instruction fetch sequence begins, the

three-byte instruction CD352lH will be fetched to the
CPU for execution. The mnemonic equivalent of this is
CALL 2l35H
After the execution of this instruction, the contents of
memory address 300lH will be lAH, the contents of
address 3000H will be 4AH, the contents of the Stack
Pointer will be 3000H, and the contents of the Program
Counter will be 2l35H, pointing to the address of the
first opcode of the subroutine now to be executed.
239
CALL
nn
Format:
Operands
CALL
nn
I <<a: a: <<a:
CD
In: : : .. I
I.. : In: : : :'1
I .. :
Note:
The first of the two n operands in the assembled
object code above is the least significant byte of a
two-byte memory address.
Description:
The current contents of the Program Counter (PC) are
pushed onto the top of the external memory stack.
The
operands nn are then loaded into the PC to point to the
address in memory where the first opcode of a subroutine
is to be fetched.
(At the end of the subroutine,a
RETurn instruction can be used to return to the original
program flow by popping the top of the stack back into
the PC.)
The push is accomplished by first decrementing
the current contents of the Stack Pointer (register pair
SP), loading the high-order byte of the PC contents into
the memory address now pointed to by the SP; then
decrementing SP again, and loading the low-order byte of
the PC contents into the top of stack. Note:
Because
this is a 3-byte instruction, the Program Counter will
have been incremented by 3 before the push is executed.
M CYCLES:
T STATES:
17(4,3,4,3,3)
None
238
4 MH Z E. T .:
4. 25
the push is executed.

Condition cc is programmed as one
of eight status which corresponds to condition bits in
the Flag Register (register F).
These eight status are
~fined in the table below, which also specifies the
corresponding cc bit fields in the assembled object
code:
cc
Condition
Relevant
Flag
000
001
010
011
100
101
110
111
NZ non zero
Z zero
NC non carry
C carry
PO parity odd
PE parity even
P sign positive
M sign negative
Z
Z
C
C
p/V
p/V
S
S
If cc is true:
M CYCLES: 5
T STATES: 17(4,3,4,3,3)
4 MHZ E. T.: 4.25
If cc is false:
M CYCLES:
T STATES: 10(4,3,3)
4 MHZ E. T .: 2.50
None
Example:
If the C Flag in the F register is reset, the contents
of the Program Counter are 1A47H, the contents of the
Stack Pointer are 3002H, and memory locations have the
contents:
Location
Contents
1A47H
1A48H
1A49H
04n
35H
21n
then if an instruction fetch sequence begins, the

three-byte instruction 0435210 will be fetched to the
CPU for execution. The mnemonic equivalent of this is
CALL NC,2135H
241
CALL
nn
CC,
Operation:
Format:
IF cc TRUE: (SPt) +- PC H
(SP2) +- PC l - PC +- nn
Opcode
~erands
CALL
cC,nn
I < ~:cc7--+< a: I
I.. I In: : : >1
I.. I In: : : >1
1
Note:
The first of the two n operands in the assembled
object code above is the least significant byte of the
two-byte memory address.
Description:
If condition cc is true, this instruction pushes the
current contents of the Program Counter (PC) onto the
top of the external memory stack, then loads the
operands nn into PC to point to the address in memory
where the first opcode of a subroutine is to be fetched.
(At the end of the subroutine, a RETurn instruction can
be used to return to the original program flow by
popping the top of the stack back into PC.)
If
condition cc is false, the Program Counter is
incremented as usual, and the program continues with the
next sequential instruction.
The stack push is
accomplished by first decrementing the current contents
of the Stack Pointer (SP), loading the high-order byte
of the PC contents into the memory address now pointed
to by SP; then decrementing SP again, and loading the
low-order byte of the PC contents into the top of the
stack. Note:
Because this is a 3-byte instruction, the
Program Counter will have been incremented by 3 before
240
RET
Operation:
PCL+-(SP),
PCH+-(SP+l)
Format:
RET
Description:
The byte at the memory location specified by the
contents of the Stack Pointer (SP) register pair are
moved to the low order eight bits of the Program Counter
(PC).
The SP is now incremented and the byte at the
memory location specified by the new contents of the SP
are moved to the high order eight bits of the PC.
The
SP is now incremented again.
The next op code following
this instruction will be fetched from the memory
location specified by the PC.
This instruction is
normally used to return to the main line program at the
completion of a routine entered by a CALL instruction.
T STATES:
M CYCLES:
10(4,3,3)
4 MHZ E. T.:
2.50
None
Example:
If the contents
contents of the
memory location
memory location
of
of the Program Counter are 3535H, the

Stack Pointer are 2000H, the contents of
2000H are B5H, and the contents of
2001H are 1BH, then after the execution
RET
the contetns of the Stack Pointer will be 2002H and the
contents of the Program Counter will be 1BB5H, pointing
to the address of the next program opcode to be fetched.
243
After the execution of this instruction, the contents of

memory address 300lR will be lAR, the contents of
address 3000R will be 4AR, the contents of the Stack
Pointer will be 3000R, and the contents of the Program
Counter will be 2l35R, pointing to the address of the
first opcode of the subroutine now to be executed.
~2
M CYCLES: 3
T STATES: 11(5,3,3)
4 MHZ E. T.:
2.75
If cc is false:
~I
CYCLES:
T STATES: 5
4 MHZ E.T.: 1.25

None
Example:
If the S flag in the F register is set, the contents of
the Program Counter are 3535H, the contents of the Stack
Pointer are 2000H, the contents of memory location 2000H
are B5H, and the contents of memory location 2001H are
18H, then after the execution of
RET M
the contents of the Stack Pointer will be 2002H and the
contents of the Program Counter will be 18B5H, pointing
to the address of the next program opcode to be fetched.
245
RET
cc
Operation:
IF cc TRUE: PCl
+- (SPI, PC H+- (SP+I)
Format:
RET
cc
Description:
If condition cc is true, the byte at the memory location
specified by the contents of the Stack Pointer (SP)
register pair are moved to the low order eight bits of
the Program Counter (PC).
The SP ~s now incremented and
the byte at the memory location specified by the new
contents of the SP are moved to the high order eight
bits of the PC.
The SP is now incremented again.
The
next op code following this instruction will be fetched
from the memory location specified by the PC.
This
instruction is normally used to return to the main line
program at the completion of a routine entered by a CALL
instruction. If condition cc is false, the PC is simply
incremented as usual, and the program continues with the
next sequential instruction. Condition cc is programmed
as one of eight status which correspond to condition
bits in the Flag Register (register F).
These eight
status are defined in the table below, which also
specifies the corresponding cc bit fields in the
assembled object code.
Condition
000
001
010
011
100
101
110
111
Relevant
Flag
NZ non zero
Z zero
NC non carry
C carry
PO parity odd
PE parity even
P sign positive
M sign negative
If cc is true:
244
z
z
C
p/V
p/V
s
s
B generates an interrupt and is acknowledged.

(The
interrupt enable out. lEO. of B goes low. blocking any
lower priority devices from interrupting while B is
being serviced).
Then A generates an interrupt.
suspending service of B.
(The lEO of A goes 'low'
indicating that a higher priority device is being
serviced.)
The A routine is completed and a RETl is
issued resetting the lEO of A. allowing the B routine to
continue.
A second RETl is issued on completion of the
B roatine and the lEO of B is reset (high) allowing
lower priority devices interrupt access.
~7
RETI
Opera tion:
Return from interrupt
Format:
RETI
11>1
I >: :a >>:a >I
0
ED
40
Description:
This instruction is used at the end of a maskable
interrupt service routine to:
1. Restore the contents of the Program Counter (PC)
(analogous to the RET instruction)
2. To signal an I/O device that the interrupt routine

has been completed. The RETI instruction also
facilitates the nesting of interrupts allowing higher
priority devicess to temporarily suspend service of
lower priority service routines. Note:
This
instruction does not enable interrupts which were
disabled when the interrupt routine was entered.
Before doing the RETI instruction, the enable
interrupt instruction (EI) should be executed to
allow recognition of interrupts after completion of
the current service routine.
M CYCLES:
T STATES:
14(4,4,3,3)
4 MH Z Eo T .:
3.50
None
Example:
Given:
Two interrupting devices, A and
connected in a
daisy chain configuration with A having a higher
priority than B.
A
INT~
I_E_0-J~
I_IE_'I_-,-_ _
246
order-byte first. and 0066H will be loaded onto the

Program Counter.
That address begins an interrupt
service routine uhich ends with RETN instruction. Upon
the execution of RETN. the former Program Counter
contents are popped off the external memory stack.
low-order first. resulting in a Stack Pointer contents
again of lOOOH.
The program flow continues where it
left off with an opcode fetch to address lA45H.
249
RETN
Operation:
Return from non maskable interrupt
Format:
RETN
11 >>:a >>:a >I
I >:a :a :a >:a >I

0
ED
45
Description:
This instruction is used at the end of a non-maskable
interrupt service routine to restore the contents of the
Program Counter (PC) (analogous to the RET instruction).
The state of IFF2 is copied back into IFFl so that
maskable interrupts are enabled immediately following
the RETN if they were enabled before the non-maskable
interrupt.
M CYCLES:
T STATES:
14(4,4,3,3)
4 MHZ E.T.:
3.50
None
Example:
If the contents of the Stack Pointer are 1000H and the
contents of the Program Counter are lA45H when a non
maskable interrupt (NMI) signal is received, the CPU
will ignore the next instruction and will instead
restart to memory address 0066H. That is, the current
Program Counter contents of lA45H will be pushed onto
the external stack address of OFFFH and OFFEH, high
order-byte first, and 0066H will be loaded onto the
Program Counter.
That address begins an interrupt
service routine which ends with RETN instruction. Upon
the execution of RETN, the former Program Counter
contents are popped off the external memory stack,
low-order first, resulting in a Stack Pointer contents
again of 1000H.
The program flow continues where it
left off with an opcode fetch to address lA45H.
248
Example:
If the contents of the Program Counter are
the execution of
RST
18H
lSB3H,
after
(Object code 1101111)
the PC will contain 0018H, as the address of the next

opcode to be fetched.
251
RST
Format:
Opcode
RST
Description:
The current Program Counter (PC) contents are pushed
onto the external memory stack, and the page zero memory
lQcation given by operand p is loaded into the PC.
Program execution then begins with the opcode in the
address now pointed to by PC.
The push is performed by
first decrementing the contents of the Stack Pointer
(SP), loading the high-order byte of PC into the memory
address now pointed to by SP, decrementing SP again, and
loading the low-order byte of PC into the address now
pointed to by SP.
The ReSTart instruction allows for a
jump to one of eight addresses as shown in the table
below.
The operand p is assembled into the object code
using the corresponding T state. Note:
Since all
addresses are in page zero of memory, the high order
byte of PC is loaded with DOH.
The number selected
from the "p" column of the table is loaded into the
low-order byte of PC.
--L
DOH
08H
10H
18H
20n
2!ln
30Il
38H
11 CYCLES:
000
001
010
011
100
101
110
111
T STATES:
11(5,3,3)
260
MHZ E. T .: 2.75
-INPUT AND aJTPlJT GIUIP-
252
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IN
Operation:
r,
r ~ (C)
Format:
Operands
IN
11
r,(C)
>>: >>: >I

0
10 : 1
ED
~r~ 0 : 0 : 0 I
Description:
The contents of register C are placed on the bottom half
(AD through A7) of the address bus to select the I/O
device at one of 256 possible ports.
The contents of
Register B are placed on the top half (A8 through A15)
of the address bus at this time.
Then one byte from the
selected port is placed on the data bus and written into
register r in the CPU.
Register r identifies any of the
CPU registers shown in the following table, which also
shows the corresponding 3-bit "r" field for each.
The
flags will be affected, checking the input data.
Reg.
B
C
D
E
H
L
A
M CYCLES:
000
001
010
011
100
101
111
T STATES: 12(4,4,4)
254
~mz
E. T .: 3. 00
[CJ
IN
A,
(n)
Operation:
A.- (n)
Fo rmat:
Operands
IN
A, (n)
I<< >>;a >>I

0
DB
I~<::"I
Description:
The operand n is placed on the bottom half (AO through
A7) of the address bus to select the I/O device at one
of 256 possible ports.
The contents of the Accumulator
also appear on the top half (A8 through A15) of the
address bus at this time.
Then one byte from the
selected port is placed on the data bus and written into
the Accumulator (register A) in the CPU.
M CYCLES:
T STATES: 11(4,3,4)
4 MHZ E. T .:
2. 75
None
Exampl e:
If the contents of the Accumulator are 23H and the byte
7BR is available at the peripheral device mapped to I/O
port address 01R, then after the execution of
IN A,(OIH)
the Accumulator will contain 7BH.
253
INI
Operation: (HL)
(e) , B ~ B-1, HL ~ HL + 1
Format:
INI
11
>>: >>:a >I

0
11 :0
>: :a ;0 >: I
0
ED
A2
Description:
(AO through A7) of the address bus to select the I/O
Register B may be
used as a byte counter, and its contents are placed on
the top half (A8 through A15) of the address bus at this
time.
Then one byte from the selected port is placed on
the data bus and written to the CPU.
The contents of
the HL register pair are then placed on the address bus
and the input byte is written into the corresponding
location of memory.
Finally the byte counter is
decremented and register pair HL is incremented.
M CYCLES:
T STATES: 16(4,5,3,4)
4 MHZ E.T.: 4.00

S:
Z:
H:
ply:
N:
C:
Unknown
Set if B-l-O;
reset otherwise
Unknown
Unknown
Set
Not affected
Example:
If the contents of register Care 07H, the contents of
register Bare 10H, the contents of the HL register pair
are 1000H, and the byte 7BH is available at the
peripheral device mapped to I/O port address 07H, then
256

S:
z:
H:
P/V:
N:
C:
Set i f input data is negative;

reset otherwise
Se t i f input data is zero;
reset otherwise
Reset
Set i f parity is even;
reset otherwise
Reset
Not affected
Example:
register Bare lOH, and the byte 7BH is available at the
peripheral device mapped to I/O port address 07B, then
IN D,(C)
255
INIR
(HL)+-(C), 8+-8-1, HL+-HL+1
Operation:
Format:
INIR
I<>: >>: >I

1
Ir; 0 : r;
<
0 :a
>;a I
ED
82
Description:
Register B is used
as a byte counter, and its contents are placed on the
top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on
The contents of
the HL register pair are placed on the address bus and
the input byte is written into the corresponding
location of memory.
Then register pair HL is
incremented, the byte counter is decremented. If
decrementing causes B to go to zero, the instruction is
terminated.
If B is not zero, the PC is decremented by
two and the instruction repeated.
Interrupts will be
recognized and two refresh cycles will be executed after
each data transfer.
Note that if B is set to zero prior
to instruction execution, 256 bytes of data will be
input.
I f B=O:
H CYCLES:
T STATES:
21(4,5,3,4,5)
T STATES:
16(4,5,3,4)
4 HHZ E.T.:
5.25
I f B=O:
H CYCLES:
258
4 MHZ E.T.:
4.00
un
memory location lOOOH will contain 7BH, the HL register
pair will contain lOOlH, and register B will contain
OFH.
257
IND
Operation: (HL)+-(C), B +- B-1,
HL+-HL-1
Format:
IND
I<<< >>;a >I

0
1<0>:0>:0;<01
ED
AA
Description:
device at one of 256 possible ports. Register B may be
used as a byte counter, and its contents are placed on
the top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on
The contents of
location of memory. Finally the byte counter and
register pair HL are decremented.
M CYCLES: 4
T STATES: 16(4,5,3,4)
4 MHZ E.T.: 4.00

S:
Z:
H:
ply:
N:
C:
Unknown
Set if B-l-O;
reset otherwise
Unknown
Unknown
Set
Not affected
Example:
are 1000H, and the byte 7BH is available at the
260

S:
Z:
H:
p/V:
N:
C:
Unknown
Set
Unknown
Unknown
Set
llot affected
Example:
If the contents of register Care 07H. the contents of
register Bare 03H. the contents of the HL register pair
are lOOOH. and the following sequence of bytes are
available at the peripheral device mapped to I/O port of
address 07H:
SlH
A9H
03H
INIR
the HL register pair will contain l003H. register B will
contain zero. and memory locations will have contents as
follows:
Location
Contents
lOOOH
lOOlH
l002H
SlH
A9H
03H
259
INDR
Operation:
(HL)+-(C), 8+-8-1. HL+-HL-1
Format:
INDR
I<<<a: << >I

I<a: r; <<a; < I
0
ED
BA
Description:
(AD through A7) of the address bus to select the I/O
Register B is used
as a byte counter, and its contents are placed on the
top half (A8 through A15) of the address. bus at this
time.
Then one byte from the selected port is placed on
The contents of
location of memory.
Then HL and the byte counter are
decremented. If decrementing causes B to go to zero, the
If B is not zero, the PC is
decremented by t~o and the instruction repeated.
Interrupts will be recognized and two refresh cycles
will be executed after each data transfer.
Note that if
B is set to zero prior to instruction execution, 256
bytes of data will be input.
I f B=O:
M CYCLES:
T STATES:21(4,5,3,4,5)
4 MHZ E.T.: 5.25
I f B=O:
M CYCLES:
T STATES:
16(4,5,3,4)
262
4 UHZ E.T.:
4.00
peripheral device mapped to I/O port address 07H, then

IND
memory location 1000H will contain 7BH, the HL register
pair will contain OFFFH, and register B will contain
OFH.
OUT
Operation:
(n),
(n) +- A
Format:
Operands
(n),A
OUT
I<<a >;a ;a >>,
Description:
I~<::
03
;.)
The operand n is placed on the bottom half (AO through

A7) of the address bus to select the I/O device at one
of 256 possible ports.
The contents of the Accumulator
(register A) also appear on the top half (A8 through
A15) of the address bus at this time.
Then the byte
contained in the Accumulator is placed on the data bus
and written into the selected peripheral device.
M CYCLES:
T STATES: 11(4,3,4)
4 MHZ E.T.:
2.75
None
Example:
If the contents of the Accumulator are 23H, then after
the execution of
OUT (OIH),A
the byte 23H will have been written to the peripheral
device mapped to I/O port address 01H.
264

S:
Z:
H:
ply:
N:
C:
Unknown
Set
Unknown
Unknown
Set
Not affected
Example:
are lOOOH, and the following sequence of bytes are
available at the peripheral device mapped to I/O port
address 07H:
5111
A9H
03H
INDR
the HL register pair will contain OFFDH, register B will
contain zero, and memory locations will have contents as
follows:
Location
Contents
OFFEH
OFFFH
lOOOH
03H
A9H
5111
263
None
Example:
If the contents of register Care 01H and the contents
of register Dare SAH. after the execution of
OUT (C).D
the byte SAH will have been written to the peripheral
device mapped to I/O port address 01H.
266
OUT (el, r
Operation:
(e) +- r
Format:
Operands
(C) ,r
OUT
I<<< >>;a >I

0
ED
10: 1 ~r~o: 0: 11
Description:
device at one of 256 possible ports. 'The contents of
Register B are placed on the top half (A8 through A15)
of the address bus at this time.
Then the byte
contained in register r is placed on the data bus and
written into the selected peripheral device. Register r
identifies any of the CPU registers shown in the
following table, which also shows the corresponding
3-bit "r" field for each which appears in the assembled
object code:
Register
B
C
D
E
H
L
11 CYCLES:
000
001
010
011
100
101
111
T STATES: 12(4,4,4)
265
411HZ E. T.: 3.00
59H, then after the execution of

OUTI
register B will contain OFH, the HL register pair will

contain 1001H, and the byte 59H will have been written
to the peripheral device mapped to I/O port address 07H.
268
OUTI
Operation:
(C)~(HL). B~B-1, HL~HL+1
Format:
Opcode
OUT!
I<<< >>:a >I

0
I< >:a :a :a >>I

0
ED
A3
Description:
The contents of the HL register pair are placed on the
address bus to select a location in memory. The byte
contained in this memory location is temporarily stored
in the CPU. Then, after the byte counter (B) is
decremented, the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and its
decremented value is placed on the top half (A8 through
A15) of the address bus. The byte to be output is
placed on the data bus and written into selected
peripheral device. Finally the register pair HL is
incremented.
M CYCLES:
T STATES: 16(4,5,3,4)
4 MHZ E.T.: 4.00

S:
Z:
H:
ply:
N:
C:
Unknown
Set if B-1-0;
reset otherwise
Unknown
Unknown
Set
Not affected
Example:
are 1000H, and the contents of memory address 1000H are
267

S:
z:
H:
p /V:
N:
C:
Unknown
Set
Unknown
Unknown
Set
Not affected
Example:
are lOOOH. and memory locations have the following
contents:
Location
Contents
lOOOH
lOOlH
l002H
5iH
A9H
03H

OTIR
the HL register pair will contain l003H. register B will
contain zero. and a group of bytes will have been
written to the peripheral device mapped to I/O port
address 07H in the following sequence:
5iH
A9H
03H
270
OTIR
Operation:
(C)+-(HL), B+-B-H HL+-HL+1
Format:
OTIR
1<0:0>1
I <a: <<a; a: <11
ED
83
Description:
address bus to select a location in memory.
The byte
in the cpu.
Then, after the byte counter (B) is
decremented value is placed on the top half (AB through
Next the byte to
be output is placed on the data bus and written into the
selected peripheral device.
Then register pair HL is
incremented.
If the decremented B register is not zero,
the Program Counter (PC) is decremented by 2 and the
If B has gone to zero, the
instruction is terminated. Interrupts will be recognized
and two refresh cycles will be executed after each data
transfer. Note that if B is set to zero prior to
instruction execution, the instruction will output 256
bytes of data.
If B-O:
M CYCLES:
T STATES:
21(4,5,3,4,5)
T STATES:
16(4,5,3,4)
4 MHZ E. T.:
5.25
I f B-O:
M CYCLES:
269
4 MHZ E.!.:
4.00
register Bare IOH, the contents of the HL register pair

are IOOOH, and the contents of memory location IOOOH are
59H, after the execution of
OUTD
register B will contain OFH, the HL register pair will
contain OFFFH, and the byte 59H will have been written
to the peripheral device mapped to I/O port address 07H.
272
aUTO
(C)+-(HL),
Operation:
8+-8-1, HL+-HL-1
Format:
OUTDo
11
1
>>:>>: 1I
0:
1:0;1::1:;1;11
ED
AB
Description:
The byte
in the CPU.
Then, after the byte counter (B) is
decremented value is placed on the top half (AB through
Next the byte to
selected peripheral device.
Finally the register pair
HL is decremented.
M CYCLES:
T STATES:
16(4,5,3,4)
4 MHZ E.T.: 4.00

S:
Z:
H:
p/V:
N:
C:
Unknown
Set if B-1-0j
reset otherwise
Unknown
Unknown
Set
Not affected
Example:
271

S:
z:
H:
p /V:
N:
C:
Unknown
Set
Unknown
Unknown
Set
Not affected
Example:
are lOOOH. and memory locations have the following
contents:
Location
Contents
OFFEH
OFFFH
lOOOH
5lH
A9H
03H

OTDR
the HL register pair will contain OFFDH. register B will
contain zero. and a group of bytes will have been
written to the peripheral device mapped to I/O port
addres 07H in the following sequence:
03H
A9H
5lH
274
OTDR
Operation:
(C)+-(HL). 8+-8-1.
HL+-HL-1
Format:
OTDR
10:11
I <0: <<<0: <11
ED
BB
Description:
The byte
in the CPU.
Then. after the byte counter (B) is
decremented. the contents of register C are placed on
Register B may be used as a byte counter. and its
decremented value is placed on the top half (A8 through
Next the byte to
selected peripheral device. Then register pair HL is
decremented and if the decremented B register is not
zero, the Program Counter (PC) is decremented by 2 and
the instruction is repeated.
If B has gone to zero. the
Interrupts will be
recognized and two refresh cycles will be executed after
each data transfer. Note that if B is set to zero prior
to instruction execution, the instruction will output
256 bytes of data.
I f B-O:
M CYCLES:
T STATES:
21(4,5,3,4,5)
T STATES:
16(4.5.3,4)
4 MH Z E. T .:
5 25
I f B"O:
M CYCLES:
273
4 MHZ E. T.:
4.00
EX (SP),IX
EX (SP),IY
EX AF,AF'
EX DE,HL
EXX
HALT
1M 0
1M I
1M 2
IN Ii., (n)
IN r, (C)
INC
INC
INC
INC
INC
INC
INC
IND
(HL)
IX
(IX+d)
IY
(IY+d)
r
ss
INDR
INI
INIR
JP
JP
JP
JP
(HL)
(IX)
(IY)
cc,nn
JP nn
JR C,e
JR e
JR NC,e
Exchange the location (SP)

and IX
and IY
Exchange the contents of AF and AF'
Exchange the contents of DE and HL
Exchange the contents of
BC,DE,HL with contents of
BC' ,DE' ,HL' respectively
HALT (wai-t for interrupt or reset)
Set interrupt mode 0
Set interrupt mode I
,
Set interrupt mode 2
Load the Acc. with
input from device n
"
Load the Reg. r with
input from device (C)
Increment location (HL)
Increment IX
Increment location (IX+d)
Increment IY
Increment location (IY+d)
Increment Reg. r
Increment Reg. pair ss
Load location (HL) with
input from port (C),
decrement HL and B
decrement HL and decrement B,
rep eat un til B 0
input from port (C);
and increment HL and decrement B
increment HL and decrement B,
repeat until B.O
Unconditional Jump to (HL)
Unconditional Jump to (IX)
Unconditional Jump to (IY)
Jump to location nn
if condition cc is true
Unconditional jump to location nn
Jump relative to
PC+e if carry I
Unconditional Jump
relative to PC+e
~
Jump relative to
PC+e if carry.O
276
81
812
78
77
79
14P
143
1~
145
253
254
124
1513
125
159
12'7
122
15'7
260
.. .. . . 262
256
258
232
233
234
221
220
224
223
226
zao-cpu
ALPHABETICAL
ASSEMBLY MNEMONIC
ADC HL,ss
ADC A,s
ADD A,n
ADD A,r
ADD A, (HL)
ADD A, (IX+d)
ADD A, (IY+d)
ADD HL,ss
ADD IX,pp
ADD IY,rr
AND s
BIT b, (HL)
BIT b, (IX+d)
BIT b, (IY+d)
BIT b,r
CALL cc,nn
CALL nn
CCF
CP s
CPD
CPDR
CPI
CPIR
CPL
DAA
DEC m
DEC IX
DEC IY
DEC 88
DI
DJNZ e
EI
EX (SP),HL
INSTRUCTION SET
OPERATION
PAGE
Add wi th Carry Reg. pair ss to HL .............

Add with carry operand s to Acc .............
Add value n to Acc
Add Reg. r to Acc
Add location (HL) to Acc .......
Add location (IX+d) to Acc ......................
Add location (IY+d) to Acc ...........................
Add Reg. pair ss to Hr. .............................
Add Reg. pair pp to IX .................................
Add Reg. pair rr to I Y
Logical ' AND' of operand sand Acc .......
Test BIT b of location (HL) ........
Test BIT b of lociition (IX+d)
Test BIT b of location (IY+d)
Test BIT b of Reg. r
Call subroutine at location nn if
con d i t ion c c i s t rue
Unconditional call subroutine
at location nn
Complement carry flag
Compare operand s. wi th Acc
Compare location (HL) and Acc.
decrement HL and BC
decrement HL and BC,
repeat until BC.O
increment HL and decrement BC
increment HL, decrement BC
repeat until BCO,
Complement Acc. (l's comp)
Decimal adjust Acc
Decrement operand m
Decrement IX
Decrement IY
Decrement Reg. pair 88
Disable interrupts
Decrement B and Jump
relative if BO
Enable interrupts
and HL
275
149
108
102
100
103
104
106
147
153
155
114
205
207
209
203
240
238
137
120
95
97
91
93
134
132
129
161
162
160
141
235
142
80
LDI
LDIR
NEG
NOP
OR s
OTDR
OTIR
OUT (C),r
OUT (n),A
OUTD
OUTI
POP IX
POP IY
POP qq
PUSH IX
PUSH IY
PUSH qq
RES b,m
RET
RET cc
RETI
RETN
RL m
RLA
RLC (HL)
RLC (IX+d)
RLC (IY+d)
RLC r
RLCA
RLD
RR m
RRA
RRC m
Load location (DE) with location (HL),

increment DE,HL, decrement BC ............... ~ ..
increment DE,HL, decrement
BC and repeat until BC=O ............................
Negate Acc. (2's complement) ...............
No operation ................................
Logical 'OR' of operand sand Acc ..............
Load output port (C) with location (HL)
decrement HL and B,
rep eat un til B= 0
Load output port (C) with location (HL),
increment HL, decrement B,
rep eat un til B= 0
Load output port (C) with Reg. r ..............
Load output port (n) with Acc ................
decrement HL and B.................
increment HL and decrement B
Load IX with top of stack
Loa d I Y wit h top 0 f s t a c k .. . . . . . . . . . .. .. . . . . . . .. . ..
Load Reg. pair qq with top of stack
Load IX onto stack
Load IY onto stack .......................
Load Reg. pai.r qq onto stack
Reset Bit b of operand m ..........................
Return from subroutine
Return from subroutine if condition
c c i s t rue
Return from interrupt
Return from non maskable interrupt .........
Rota te left through carry operand m
Rotate left Acc. through carry ................
Rotate location (HL) left circular .........
Rotate location (IX+d) left circclar ..........
Rotate location (IY+d) left circular
Rotate Reg. r left circular
Rotate left circular Acc
Rotate digit left and right
between Acc. and location (HL) ....................
Rotate right through carry operand m
Rotate right Acc. through carry
Rotate operand m right circular
278
a3
85
13!l
139
116
273
269
26!/
264
271
267
74
75
72
70
71
69
217
243
244
246
248
180
166
174
176
178
172
164
198
186
170
183
JR NZ,e
JR Z,e
LD A, (BC)
LD A, (DE)
LD A,I
LD A,(nn)
LD A,R
LD (BC) ,A
LD (DE) ,A
LD (HL),n
LD dd,nn
LD dd,(nn)
LD HL, (nn)
LD (HL),r
LD I,A
LF IX,nn
LD IX, (nn)
LD (IX+d),n
LD (IX+d),r
LD IY,nn
LD IY,(nn)
LD (IY+d) ,n
LD (IY+d),r
LD (nn),A
LD (nn),dd
LD (nn),HL
LD (nn),IX
LD (nn),IY
LD R,A
LD r,(HL)
LD r,(IX+d)
LD r,(IY+d)
LD r,n
LD r , r '
LD SP,HL
LD SP,IX
LD SP,IY
LDD
LDDR
Jump relative to
PC+e if non zero (Z-O) ................................ 230
Jump relative to
PC+e if zero (Z-1) .......................................... 228
Load Ace. with location (BC) ...................... 42
Load Ace. with location (DE)
43
Load Ace. with I
48
Load Ace. with location nn ...................... 44
Load Ace. with Reg. R
49
Load location (BC) with Ace ......................... 45
Load location (DE) with Ace ......................... 46
Load location (HL) with value n
39
Load Reg. pair dd with value nn
53
Load Reg. pair dd with location (nn>.
57
Load HL with location (nn)
56
Load location (HL) with Reg. r ................... 34
Load I with Ace
50
Load IX with value nn
54
Load IX with location (nn)
59
Load location (IX+d) with value n
40
Load location (IX+d) with Reg. r ................ 35
Load IY with value nn
55
Load IY with location (nn)
60
Load location (IY+d) with value n
41
Load location (IY+d) with Reg. r
37
Load location (nn) wi th Ace.
47
Load location (nn) with Reg. pair dd
62
Load location (nn) with HL
61
Load location (nn) with IX
64
Load location (nn) with IY
65
Load R wi th Ace.
51
Load Reg.
with location (HL) .................... 29
Load Reg.
with location (IX+d)
30
Load Reg.
with location (IY+d)
32
Load Reg.
with value n
28
Lo ad Reg. r wi t h Reg. r'
27
Load SP with HL
66
Load SP with IX ........................................... 67
Load SP with IY
68
decrement DE,HL and BC ................................. 87
decrement DE,HL and BC;
repea t un til BC-O
89
277
APPENDIX A
ERROR MESSAGES AND EXPLANATIONS
1)
2)
3)
4)
5)
6)
7)
8)
WARNING - OPCODE REDEFINED

Indicates that an opcode has been redefined by
a macro so that future uses of the opcode will
~esult in the appropriate macro call.
This
message may be suppressed by the NOW option.
NAME CONTAINS INVALID CHARACTERS
Indicates that a name (either a label or an
operand) contains illegal characters.
Names
must start with an alphabetic character and
any following characters must be either
alphanumeric (A Z or 0 9), a question mark
(1) or an underbar ( ).
INVALID OPCODE
Indicates that the opcode was not recognized.
Occurs when the opcode contains an illegal
charac ter (incl ud ing no.n-pr in ting con tro 1
characters), when the opcode is not either all
upper case or all lower case, or when macros
are used and the M option is not specified.
INVALID NUMBER
Indicates an invalid character in a number.
Occurs when a number contains an illegal
character (including non-printing control
characters) or a number contains a digit not
allowed in the specified base (e.g., 8 or 9 in
an octal number or a letter in a hexadecimal
number where the trailing H was omitted.)
INVALID OPERATOR
Indicates use of an invalid operator in an
expression.
Occurs when an operator such as
AND or XOR is misspelled or contains illegal
characters.
SYNTAX ERROR
Indicates the syntax of the statement is
invalid.
Occurs when an expression is
incorrectly formed, unmatched parenthesis are
found in an operand field, or a DEFM string is
either too long (greater than 63 characters)
or contains unbalanced quotes.
ASSEMBLER ERROR
Indicates that the assembler has failed to
process this instruction.
Usually occurs when
an expression is incorrectly formed.
UNDEFINED SYMBOL
Indicates that a symbol in an operand field

280
RRCA
RRD
RST P
SBC A, s
SBC HL,ss
SCF
SET
SET
SET
SET
SLA
SRA
SRL
SUB
XOR
b,(HL)
b,(IX+d)
b, (IY+d)
b, r
m
m
m
s
s
Rotate right circular Acc ......................

Rotate digit right and left
between Acc. and location (HL) ...................
Restar t to location p ...................................
Subtract operand s
from Acc. with carry
Subtract Reg. pair ss from
HL with carry
Set carry flag (C-l)
Set Bit b 0 f l o cat ion ( HL)
Set Bit b of location (IX+d).
Set Bit b of location (IY+d)
Set Bit b of Reg. r
Shift operand m left arithmetic
Shift operand m right arithmetic
Shift operand m right logical
Subtract operand s from Acc
Exclusive 'OR' operand sand Acc
279
168
200
250
112
151
138
212
213
215
211
189
192
195
110
118
16)
17)
18)
19)
20)
21)
22)
bytes).
The line will be truncated.
MACRO STACK OVERFLOW
Indicates that the depth of nesting of macro
calls has exceeded the macro parameter stack
buffer capacity.
Occurs when the sum of the
parameter string lengths (plus some additional
information for each macro call) is longer
than the buffer (currently 256 bytes), which
often happens if infinitely recursive macro
calls are used.
The macro call which caused
the error will be ignored.
INCLUDE NESTED TOO DEEP
Indicates that a *Include command was found
which would have caused a nesting of included
source files to a depth greater than four,
where the original source file is considered
to be level one.
The command will be ignored.
GLOBAL DEFINITION ERROR
Indicates that either a label was present on a
GLOBAL pseudo-op statement, or there was an
attempt to give an absolute value to a GLOBAL
symbol in a relocatable module.
The latter
case is not allowed since all GLOBALs in a
relocatable module will be relocated'by the
Linker.
May occur either after a GLOBAL
pseudo-op or after an EQU or DEFL statement
which is attempting to absolutize a
relocatable GLOBAL symbol.
EXTERNAL DEFINITION ERROR
Indicates that either a label was present on
an EXTERNAL pseudo-op statement, or there was
an attempt to declare a symbol to be EXTERNAL
which had previously been defined within the
module to have an absolute value.
May occur
due to a misspelling or other oversight.
NAME DECLARED GLOBAL AND EXTERNAL
Indicates that the name was found in both a
GLOBAL pseudo-op and an EXTERNAL pseudo-op
which is contradictory.
May occur due to a
misspelling or other oversight.
LABEL DECLARED AS EXTERNAL
Indicates that a name has been declared in
both an EXTERNAL pseudo-op and as a label in
this module.
May occur due to a misspelling
or other oversight.
INVALID EXTERNAL EXPRESSION
Indicates that a symbol name which has been
declared in an EXTERNAL pseudo-op is
improperly used in an expression.
May occur
when invalid arithmetic ope~ators are applied
to an external expression or when the mode of
~2
9)
10)
11)
12)
13)
14)
15)
was never defined. Occurs when a name is

misspelled or not declared as a label for. an
instruction or pseudo-ope
INVALID OPERAND COMBINATION
Indicates that the operand combination for
this opcode is invalid. Occurs when a register
name or condition code is missspelled or
incorrectly used with the particular opcode.
EXPRESSION OUT OF RANGE
Indicates that the value of an expression is
either too large or too small for the
appropriate quantity.
Occurs on 16-bit
arithmetic overflow or division by zero in an
expression, incrementing the reference counter
beyond a 16-bit value, or trying to use a
value which will not fit into a particular
bit-field - typically a byte.
MULTIPLE DECLARATION
Indicates that an attempt was made to redefine
a label.
Occurs when a label is. misspelled,
or mistakenly used several times. The
pseudo-op DEFL can be used to assign a value
to a label which can then be redefined by
another DEFL.
MACRO DEFINITION ERROR
Indicates that a macro is incorrectly defined.
Occurs when the M option is not specified but
macros are used, when a macro is defined
within another macro definition, when the
parameters are not correctly specified, or an
unrecognized parameter is found in the macro
body.
UNBALANCED QUOTES
Indicates that a string is not properly
bounded by single quote marks or quote marks
inside a string are not properly matched in
pairs.
ASSEMBLER COMMAND ERROR
Indicates that an assembler command is not
recognized or is incorrectly formed: The
command must begin with an asterisk (*) in
column one, the first letter identifies the
command, and any parameters such as 'ON','OFF'
or a filename must be properly delimited.
The
command will be ignored.
MACRO EXPANSION ERROR
Indicates that the expansion of a single line
in a macro has overflowed the expansion
buffer.
Occurs when substitution of parameter
causes the line to increase in length beyond
the capacity of the buffer (currently 128
APPENDIX B
INSTRUCTION SET ALPHABETICAL ORDER
1.06
2-BO CRUSS ASSEMBLER
VERSION
OPCOOE
L ISTlNG
10=22 :47
07109176
STMT SOURCE STATEMENT
08J COOt:
LUC
0000
0001
0004
0007
0008
0009
OOOA
0008
OOOC
0000
OOOE
0010
0012
0014
0016
00111
0019
001C
001F
0020
0021
0022
0023
0024
0025
0026
0026
0029
002A
0028
002C
002E
0030
0032
0034
0030
0038
003A
003C
0030
0040
0043
0044
0045
0046
0041
0046
0049
004A
004C
004E
0052
0056
0056
005A
005C
005E
0060
0062
0064
0006
006A
006E
0010
0072
0014
0016
0078
007A
liE
DDlIE05
FD8E05
8F
118
89
BA
8B
8C
80
CE20
ED4A
ED5A
ED6A
ED7A
86
DOB605
FD8605
B7
80
61
62
63
84
85
C620
09
19
29
39
0009
0019
0029
0039
FOOII
F019
F029
F0311
A6
DOA605
FOA605
Al
AO
Al
A2
A3
A4
A5
H2O
CB46
DOCB05't6
FOCB0546
CB47
CB40
CB41
CB42
C843
CB't4
CB45
C84E
00CB05'tE
fOC805'tE
CB4F
CB4B
CB49
CB4A
CB4B
Cll4C
CB40
1
2
3
4
5
6
1
B
9
10
11
12
13
14
15
16
11
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
30
37
36
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
51
5B
59
60
61
62
63
64
65
66
67
68
69
ADC
ADC
ADC
AOC
ADC
ADC
ADC
ADC
AOC
ADC
ADC
AOC
AOC
ADC
ADC
ADD
ADO
ADO
ADO
ADO
ADO
ADO
AOD
ADO
ADD
ADO
ADD
ADD
ADO
ADD
ADD
ADD
ADD
ADO
ADD
ADO
ADO
ADO
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
BIT
BIT
BIT
BIT
8IT
BIT
BIT
61T
BIT
BIT
BIT
BIT
BIT
BIT
8IT
BIT
8IT
BIT
8IT
BIT
OF 06/18176
LOC
001C
007E
0082
0086
0088
OOBA
OOBC
OOBE
0090
0092
0094
0096
009A
009E
OOAO
00A2
00A4
00A6
00A8
OOAA
OOAC
OOAE
00B2
00B6
OOBB
OOBA
OOBC
OOBE
OOCO
00C2
00C4
00C6
OOCA
OOCE
0000
0002
0004
0006
0008
OOOA
OODC
OODE
00E2
00E6
00E8
OOEA
OOEC
OOEE
OOfO
00F2
00f4
00F6
OOFA
OOfE
0100
0102
0104
0106
0106
010A
010C
010f
0112
0115
0118
0118
011E
0121
012't
A,IHLl
A, CIX+INDI
A,CIY+INDI
A,A
A,8
A,C
A,D
A,E
A,H
A, L
A,N
HL,8C
HL,DE
HL,HL
HL, SP
A,IHL I
A,CIX+INDI
A,IIY+INDI
A,A
A,B
A ,C
A,D
A ,E
A,H
A,L
A,N
HL,8C
HL,OE
HL,HL
HL, SP
IX,BC
IX,OE
IX,IX
IX,SP
IY,BC
IY,OE
IV"V
IV,SP
CHLI
II X+INOI
IIY+INDI
A
8
C
0
E
H
L
N
O,IHLI
O,IIX+INOI
0,( IY+INOI
O,A
0,8
O,C
0,0
O,E
O,H
O,L
l,CHU
l,CIX+iNOI
l,CIY+INOI
l,A
l,B
l,C
I,D
l,E
l,H
l,l
284
08J CODE
CB56
DOC80556
FDCB0556
C851
CB50
CB51
CB52
C853
CB54
C855
C85E
ODCB055E
FDCB055E
C85F
C858
CB59
CB5A
CB5B
CB5C
C85D
CB66
DDC80566
FDCB0566
C8b7
CB60
CB61
CB62
CB63
CB64
CB65
CB6E
DDC8056E
FDC8050E
C86F
CBb6
C809
CB6A
CB6B
C86C
CB60
CB76
ODCB0576
FDCB0576
CB77
CB10
CBll
C872
CB13
Cll14
CB15
CB7E
00CB057E
FOCB057E
CBlf
C618
C879
CB1A
C618
CB1C
CBID
OC8405
FC8't05
048405
CDB405
C't8405
F48405
ECB405
E48't05
CC8405

70
71
72
13
74
75
76
71
78
79
80
Bl
82
B3
114
85
86
87
8B
69
90
91
92
93
94
95
96
97
96
99
100
101
102
103
104
105
106
101
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
8IT
BIT
BIT
BIT
BIT
BIT
BIT
8IT
BIT
8IT
8IT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
8IT
BIT
8IT
8IT
8IT
BIT
BIT
BIT
BIT
8IT
8IT
8IT
!lIT
81T
8IT
BIT
BIT
8IT
8IT
8IT
BIT
BIT
8IT
lilT
!lIT
!lIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
8IT
CAll
CALL
CAll
CALL
CAll
CAll
CAll
CAll
CAll
2,CHL!
2,CIX+INDI
2,IIY+INDI
2,A
2,B
2,C
2,0
2,E
2,H
2,L
3'Ct Ll
3,1 X+INDI
3,llY+INOI
3,AI
3,B
3,C
3,0
3,E
3,H
3,L
4,C!\tLl
4,IIX+INDI
4,IIY+INDI
4,A
4,8
4,C
4,0
4,E
4,H
4,L
5tllitLl
5,IIX+INDI
5, ClY+INDI
5,A
5,8
5,C
5,0
5, E
5,H
5,L
60lljiLl
6,IIX+INDI
6,IIY+INOI
6,A
6,B
6,C
6,0
6,E
6,H
6,L
7,CfiLl
7,IIX+INOI
l,IIV+INDI
7,A
7,B
7,C
1,0
l,E
l,H
l,l
C,~N
M,NN
NC,NN
NN
NZ,NN
P,~
PE,NN
PO,NN
Z,NN
23)
24)
25)
26)
an operand m~st be either absolute or

relocatable.
INVALID RELOCATABLE EXPRESSION
Indicates than an expression which contains a
relocatable value (either a label or the
reference counter sumbol $ in a relocatable
module) is improperly formed or used. May
occur when invalid arithmetic operators are
applied to a relocatable expression or when
the mode of an operand must be absolute.
Remember that all relocatable values
(addresses) must be represented in 16 bits.
EXPRESSION MUST BE ABSOLUTE
Indicates that the mode of an expression is
not absolute when it should be.
May occur
when a relocatable or external expression is
used to specify a quantity that must be either
constant or representable in less than 16
bits.
UNDEFINED GLOBAL(S)
Indicates that one or more sumbols which were
declared in a GLOBAL pseudo-op were never
actually defined as a label in this module.
May occur due to a misspelling or other
oversight.
WARNING - ORG IS RELOCATABLE
Indicates that an ORG statement was
encountered in a relocatable module.
This
warning is issued to remind the user that the
reference counter is set to a relocatable
value, not an absolute one.
May occur when
the Absolute option is not specified for an
absolute module.
This warning may be
suppressed by the NOW option.
283
VERSION 1.06
Z-80 CROSS ASSEMBLER
opeOOE
LISTING
01109176 10J22JIo7
08J CODE STMT SOURCE STATEMENT
Loe
022E
022F
0231
0232
0235
0238
0239
023A
0238
023e
0230
OnE
023F
02'01
0245
0210B
0249
0210e
0210F
0250
0251
0252
0253
0254
0255
0256
025B
0259
025e
025F
0260
0261
0262
02b3
02blo
02b5
0266
026B
026e
026F
0270
0273
0216
0277
0278
0279
027A
0278
027e
0210
027F
02'clO
0283
0286
0287
0288
0289
028A
028B
028e
0280
028F
0292
0295
0297
029B
029F
0243
02A7
70
3E20
'06
00'0605
FOlo605
'07
'00
'01
'02
'03
'0'0
'05
0620
EDitB81005
018'005
4E
00loE05
FOloE05
'oF
'08
49
loA
loB
Ioe
'00
OE20
56
OD5605
F05605
57
50
51
52
53
5'0
55
1620
E05BBIo05
118'005
5E
005E05
F05E05
SF
58
'59
5A
5B
5e
50
lE20
66
006605
F06605
67
60
61
62
63
6'0
65
2620
2A81005
218'005
EOIt7
002A8405
00218'005
F02A81005
FD2181005
6E
277
278
279
280
281
282
l83
28'0
285
286
287
'288
289
290
291
292
293
29'0
295
296
297
298
299
300
301
302
303
30'0
305
306
307
3011
309
310
311
312
313
31'0
315
316
317
318
319
320
321
322
323
)Z1o
325
326
327
328
329
330
331
332
333
33'0
335
336
337
338
339
3'00
3'01
3'02
3'03
3'0'0
310S
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LD
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LD
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
A,L
A,N
B,(HLI
B,(JX"INOI
B,II\'.. INOI
B,A
8,8
B,e
B,O
B,E
B,H,NN
B,L
B,N
Be,INNI
Be,NN
e,lHlI
e,( IXHNDI
e,IIYHNOI
e,A
e,B
e,e
e,o
e,E
e,H
e,L
e,N
O,lHlI
O,IIXHNDI
0,( IY+INOI
O,A
O,B
!;l,e
D,O
O,E
O,H
O,L
O,N
DE, (I'll'll
OE,NN
E,IHll
E,( IX+INOI
E,IIY+INOI
E,A
E,B
E,e
E,O
E,E
E,H
E,L
E,N
H,lHlI
H, (IX+INOI
H,( I Y+I NOI,
H,A
H,8
H,e
H,O
H,E
H,H
H,L
H,N
HL,INNI
HL,NN
I,A
IX,INNI
IX,NN
IY, (I'll'll
IY,NN
L,IHLJ
OF 06/18176
Loe
02 AS
02AB
02AE
02AF
0280
02B1
0282
02B3
02BIo
02B5
02B7
0288
028e
028E
02eo
02e3
02es
02e7
02e9
02e8
02eo
02eE
02eF
0202
0205
0206
02D7
0208
0209
020A
020B
020C
020E
02EO
02E2
02E1t
02E6
02E8
02EA
02Ee
02EE
02FO
02F2
02F1t
02F6
02F7
02F8
02F9
02FA
02Fe
02FE
02FF
0300
0301
0302
030'0
0306
0308
030e
0310
0312
031'0
0316
0318
031A
031C
031E
0320
032'0
286
OBJ eOOE
OD6E05
FD6E05
6F
68
69
6A
6B
6e
6D
2E20
ED7B81005
F9
OOF9
FDF9
318'005
EOU
ED88
EDAO
EOBO
EOIoIo
00
B6
00B605
FOB605
B7
BO
Bl
B2
B3
Bio
B5
Fb20
EOBB
EOB3
E079
EOlol
EDit9
E051
ED59
ED61
E069
0320
EOA8
EOA3
Fl
e1
01
El
OOEI
FOEI
F5
e5
05
E5
OOE5
FOES
CB86
00C80586
FDCB0586
eB87
C880
CB81
C882
C883
CB810
CB85
CB8E
ooeB058E
FOC8058E
3'06
3'07
3'08
3'09
350
351
352
353
35'0
355
356
357
358
359
360
361
362
363
36'0
365
3bb
361
368
369
370
371
372
373
37'0
375
376
377
378
379
380
381
382
383
38'0
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
'000
'001
'002
'003
'00'0
405
1o0b
'001
408
'009
'010
411
'012
'013
'olio
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LD
LO
LOO
LODR
LOI
LOIR
NEG
Nap
OR
OR
OR
OR
DR
OR
OR
OR
OR
OR
OR
DTOR
OUR
DUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTO
DUll
POP
POP
POP
POP
POP
POP
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
t:::~:::g:
L,A
L,8
L,e
L,O
L,E
L,H
L,L
L,N
SP,UINI
SP,H~
SP,Il(
SP, It
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(lY" NOI
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O,A
O,B
o,e
0,0
O,E
O,H
O,L
1,(HI-I
l,llXHNDI
1, I I"'''INOI
OF 06/18176
VERSION 1.06
%-80 CROSS ASS EMBLER
liStiNG
OPCOOE
u7l09176 10:22:47
LOC
0127
0128
0129
012C
012F
0130
0131
0132
0133
0134
0135
0136
0138
013A
013C
DUE
0140
01U
0142
0143
0146
0149
014A
0148
014C
0140
014E
014F
01S0
DIS 1
0152
0154
0156
0157
0158
01S9
0158
DISC
0150
015F
0161
0162
0163
010'"
0165
0161
0169
0168
016D
016F
0171
0173
0115
0117
0179
0178
011C
011F
0182
0183
018,.
0185
0186
0181
0188
0189
018A
0188
0180
3F
8E
008EOS
F08EOS
8F
88
89
8A
88
8C
80
FE20
EoA9
Eo1l9
EOA1
EOlll
2F27
35
003505
F03S05
3D
05
08
00
IS
18
10
25
28
0028
F028
20
38
F3
102E
F8
E3
00E3
FoE3
08
E8
09
16
EO"'o
EDS6
E05E
E0711
D820
ED40
ED"t8
E050
E058
ED60
ED68
3't
DD3... 05
F03it05
3C
04
03
OC
14
13
1C
24
23
OD23
FOB
139
140
141
142
143
144
14S
146
147
148
149
ISO
151
152
153
154
ISS
150
157
158
159
100
101
102
163
164
165
166
167
108
169
170
171
172
173
174
175
176
177
178
119
180
181
182
183
18...
185
186
187
188
189
190
191
192
193
19...
195
196
19'
198
199
200
201
202
203
204
20S
206
2117
CCF
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CPO
CPOR
CPI
CPIR
CPL
OAA
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
OJ
OJNZ
EJ
EX
EX
EX
EX
EX
EXX
HALT
JM
1M
1M
IN
IN
IN
IH
JH
IN
IN
IN
INC
INC
IHC
IHC
INC
IHC
INC
IHC
JHC
JHC
INC
INC
IHC
IHC
LOC
OUF
0190
0191
0193
0195
0197
0199
019A
019C
019E
OlAl
01A4
OlA7
OlAA
IHlI
IIX+INOI
IIY+INOI
A
8
C
0
E
H
L
N
DUO
IHlI
IIX+1NOI
IIY+INOI
A
8
8C
C
0
DE
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H
HL
IX
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SP
DIS
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ISPI,JX
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2
A.ICI
A,{N)
8.ICI
C,ICI
D,ICI
E,ICI
H,ICI
L,ICI
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IIX+JHDI
IIY+lHOI
A
8
8C
C
0
DE
E
H
HL
IX
IY
0180
0183
0180
0189
0188
0180
018F
01Cl
01C3
01C4
01C5
01C6
01C7
01C8
01C9
01CA
01C8
01CC
InCE
OlDl
0104
01D7
01DA
0100
DIED
01E3
OlE7
OlEA
OlEO
01FO
01F3
01F6
01F9
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0200
0203
0201
0208
020E
0212
0216
02lA
0218
021C
021D
0220
0223
0226
0227
0228
0229
022A
0228
022C
285
OtlJ CODE
2C
3j
EOU
E08A
EOA2
E082
E9
00E9
FoE9
OA8405
FA1I40S
028405
C38405
C28405
F28405
EA8405
E28405
CA8405
3112E
182E
302E
202E
282E
02
12
77
10
II
72
73
14
75
3620
001105
007U05
D07105
001205
OD7305
001405
007505
00360520
Fo1105
F01005
FOll05
F07205
F07305
FD7405
FD7505 .
F0360520
328405
ED438405
EDS3&...05
228405
DD228,.05
FD228...05
ED738,.05
UA
lA
7E
DD1EOS
F07E05
3A8... 05
lF
78
79
lA
78
lC
EDSl
5TMT SOURCE STATEMENT

208
209
210
211
212
213
214
215
210
217
218
219
220
221
222
223
224
225
220
227
228
229
230
231
232
233
234
235
230
231
238
239
2...0
241
2...2
243
2......
24S
246
2...1
2...&
2...9
250
251
252
253
25...
2S5
256
257
2S8
259
260
261
262
263
264
265
266
261
268
269
210
211
272
213
27"t
21!j
216
INC
INC
INO
INOR
INI
INIR
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JR
JR
JR
JR
JR
Lo
LO
LO
LO
LO
LO
LO
LO
LD
LO
LO
LD
LO
LO
LO
LO
LO
LO
Lo
LO
LO
LD
LD
LD
LD
LD
LD
Lo
LD
LD
LD
LD
LD
LD
LD
LD
LD
LO
LD
LD
LD
LD
LO
LD
LD
LD
L
SP
IHlI
(IX!
IIY I
C,NN
M,NN
NC,NH
NN
NZ,NH
P,NN
PE,NH
PO,NH
Z,NN
C,OIS
DIS
NC,OIS
HZ,OIS
Z,olS
18CI,A
IDE I ,A
I HL),A
IHlI,B
IHL),C
IHlI,O
I.HU,E
IHU,H
IHLI,L
IHU,N
IIX+IHOI,A
IIX+IHOI,8
I JX+lHDI,C
IJX+IHO),O
I JX+INOI,E
IIX+INOI,H
(lX+JNOI,L
IIX+INoI,N
IJY+INoI,A
IIY+1NoI,B
IJY+IHOI.C
IIY+JHD),D
IIY+JND),E
IJY+lHol,H
IIY+INDI.L
IIY+IHDI,N
INNI,A
IHNI,&C
INNI,DE
tNNl,HL
INNI,IX
INNI,IY
IHHI,SP
A,(8C)
A,IOEI
A.IHll
A. nX+INOI
A.IIY+INOI
A,INHI
A,A
A.8
A,C
A.D
A,E
A.H
A,I
VERSION 1.06
2-80 CROSS ASSEMBLER
OPCOOE
LISTING
10:22:47
01l0911b
STMT SOURCE ST ATEMENT
lot
OBJ COOl:
0440
U44E
04itF
0450
0451
0453
0455
0457
0459
045B
045C
045E
0462
046b
04b8
046A
046C
0'o6E
0470
0472
0474
0476
047A
047E
U480
0482
0484
0'086
0488
048A
048C
0'o8E
0492
0496
0498
049A
049C
049E
04AO
04A2
04A'o
0'oA6
0'oA8
O'oAC
0'080
0'082
0'oB4
04B6
0'oB8
04BA
O'oBC
O'oBE
04C2
0'oC6
04C8
O'oCA
O'oCC
04CE
0't00
0402
0'004
0'006
040A
O'oUE
04EO
04E2
04E'o
0'oE6
CBC6
00CB05C6
FOCB05C6
CBC7
CBCO
C8Cl
CBe2
CBC3
CBC4
CBC5
CIlCE
00CIl05CE
FOCB05CE
C8CF
C8ca
CIlC9
CllCA
CIlCB
C8ce
caCo
CIl06
00CB0506
FOCIl0506
CB07
CBOO
CBOI
CBu2
C803
C804
CB05
CIl08
CBOE
00C8050E
FOCB050E
CBOF
CB09
CBOA
CB08
CBOC
C8UO
C8E6
00C805E6
FOCB05E6
C8E7
CBEO
CBEI
CBE2
CBE3
CBEIt
CBES
CIlEE
OOCBOSEE
FOCB05EE
CBEf
C8E8
CBE9
C8EA
CIlE8
553
554
555
556
557
558
559
560
561
562
563
5b4
5b5
Sb6
5b7
568
Sb9
570
571
572
573
574
575
516
517
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
59'0
595
596
597
598
599
600
601
602
603
60'0
b05
606
607
608
609
610
611
612
613
61'0
615
616
617
618
619
620
04E8
CBEC
621
9A
9B
9C
90
OE20
EO'o2
E052
E062
E072
37
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SCf
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
A,O
A,E
A,H
A,l
A,N
Hl,BC
Hl,OE
Hl,Hl
Hl,SP
O,(HU
O,IIX+INOI
O,IIY+INOI
O,A
O,B
O,C
0,0
O,E
O,H
O,l
1,IHlI
1,( IX+INOI
1,IIY+INOI
I,A
1,8
1,C
1.0
I.E
1.H
1.l
2,IHU
2,(IX+JNOI
2,(IY+JNOI
2.A
2.B
2.C
2.0
2,E
2 . H
2.l
3 B
3.IHll
3,IIX+INOI
3,IIY+INOI
3,A
3,C
3.0
3. E
3.H
3.L
'o,IHU
'o.IIX+INOI
4.IIY+INOI
'o.A
4,B
'o.C
'0,0
4.E
'o.H
4,l
5.IHLI
s,IIX+lNOI
5,II.Y+INOI
5.A
5.B
5.C
5.0
5.E
5.H
288
OF 06/18116
lOC
OBJ CODE
04EA
UltEC
04EE
04f2
04F6
04f8
04FA
04fC
04fE
0500
0502
0504
0506
050A
050E
0510
0512
0514
OS16
0518
051A
051C
051E
0522
0526
0528
052A
052C
052E
0530
0532
0534
0536
053A
053E
0540
0542
0544
0546
0548
05/tA
05'oC
05'tE
0552
0556
0558
055A
055C
055E
0560
0562
056'0
0565
056B
056B
056C
0560
056E
056F
0570
0571
0572
057'0
0575
0578
0578
057C
0570
057E
CBED
C8F6
OOC805Fb
FOCB05F6
CBF7
CBfO
CBFl
CBF2
CBF3
C8F,.
CBf5
CBfE
00CB05FE
FOCB05fE
CBFF
CBF8
CBf9
CBfA
CBFB
CBFC
CBFO
CB26
00CB0526
FOCB0526
C827
CB20
CB21
CB22
CB23
C824
CB25
CB2E
00CB052E
fOCB052E
CB2F
CB28
CB29
CB2A
CB2B
CB2C
CB20
CUE
OOCB053E
FOCB05lE
CB3F
CB38
CB39
CB3A
ClUB
C53C
CB30
96
009605
F09605
97
90
91
92

SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SlA
SlA
SlA
SLA
SLA
SlA
SlA
SlA
SlA
SLA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRl
SRl
SRl
SRl
SRl
SRl
SRl
SRl
SRL
SRl
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SU8
SUIl
5,l
6,IHll
6,IIX+INOI
6,(IY+INOI
6,A
6,B
6,C
6,0
6,E
6,H
6,l
7,IHll
7, IIX~INOI
7,(IY+INOI
7,A
7,B
7,C
7,0
7,E
7,H
7,l
IHlI
II X+I NOI
IIY+INOI
A
8
C
0
E
H
l
IHlI
IIX+INOI
11Y+INOI
A
B
C
0
E
H
l
IHlI
IIX+1NOI
11Y+INDI
A
B
C
0
E
H
L
IHlI
11X+1~01
IIY+JNOI
A
B
C
0
94
95
0620
AE
00AE05
FOAE05
AF
A8
A9
622
b23
624
625
626
627
628
629
630
631
632
b33
b34
635
636
b37
638
639
640
641
642
643
644
645
646
b47
648
649
b50
651
652
653
65'0
655
656
657
658
659
660
bbl
662
663
66,.
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
6ao
681
682
683
68'0
685
686
687
688
689
XOR
XOR
XOR
XOR
XOK
XOR
AA
H
L
N
IHLI
11X+INOI
I JY+IliIOI
A
B
C
690
XOR
93
suu
VERS ION
1.06
2-80 (.1l0SS ASS EMBlEIl
LISTING
OPCODI:
10:U:41
07109116
lO(.
OIlJ CODE
0328
032A
032(,
OnE
0330
0332
0334
0336
0338
onc
0340
0342
0344
0346
0348
034A
034C
034E
0350
0354
0358
035A
035C
035E
0360
0362
03b4
0366
03b8
036C
0310
0372
0374
0376
0318
037A
037C
031E
0380
0384
0388
038A
038C
038E
0390
0392
0394
0396
0398
039C
03AO
03A2
03 A"
03A6
03A8
03AA
03AC
03AE
0380
0384
0388
038A
038C
038E
03CO
03C2
03C..
03C6
03C 1
(.B8F
(.B1I8
(.B1I9
(.BIIA
(,118 a
CIISC
CB80
(,896
00C80596
FOC80596
C8'H
CB90
C891
(,892
C893
C894
C895
CB9E
00CB059E
FOCB059E
CB9F
CB98
CB99
CB9A
CB9B
C89C
C890
CBA6
DOCII05A6
FOCB05A6
CIIA7
CBAO
CBAI
CBAZ
CBU
CBA4
CBA5
CBAE
00CB05AE
FOCBD5AE
CBAF
C8A8
CIIA9
CIIAA
CIlAIl
C8AC
C8AO
CIIB6
00C805Bb
FOCB05B6
CIIB7
CBBO
CBBI
CBB2
CB83
CB84
CBB5
CII8E
00CIl0511E
FOC8058E
CBIIF
C888
C889
CB8A
CB8B
C8BC
(.BBO
C9
DB
41!>
416
417
418
419
420
421
422
423
424
425
426
421
428
429
430
431
432
433
434
435
436
431
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
4bl
462
4b3
46..
465
4b6
..67
468
4b9
470
471
472
473
474
415
476
477
418
479
480
481
482
483
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
IlES
RES
RES
RES
IlES
RES
RES
RES
KES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RET
RET
I,A
l,B
1,(.
1,0
I, E
I,H
l,l
2,1 Hl I
2,IIX+INOI
2,lIY+INOI
2,A
2,8
2,C
2,0
2,E
2,H
2,l
3,IHLI
3,IIX+INOI
3,IIY+INOI
3,A
3,B
3,C
3,0
3,E
3,H
3,l
4,IHLI
4,IIX+INOI
4,IIY+lNOI
4,A
4,B
4,e
4,0
4, E
4,H
4,l
5,lHLI
5,IIX+INOI
5,IIY+INOI
5,A
5,8
5,C
5,0
5, E
5,H
5,l
b,lHLI
6,lIX+INUI
6,IIY+INOI
6,A
6,B
6,C
b,O
b, E
6,H
6,l
7,IHU
7,IIX+INOI
7,lIY+INOI
7,A
7,8
7,C
7,0
7, E
7,H
l,l
287
OF 06118176
lO(.
OBJ CODE
03(,11
03(.9
03(.A
03(,8
03(.C
03CO
03CE
03(.1'
0301
0303
0305
0309
0300
0301'
03El
03E3
03E5
03E7
03E9
03EB
03EC
03EE
031'2
031'6
031'8
03FA
03FC
03FE
0400
0402
0404
0405
0407
0409
0400
0411
0413
0415
0417
0419
041B
0410
0411'
0420
0422
0426
042A
042C
042E
0430
0432
0434
0436
0438
0439
043B
043C
0430
043E
0431'
0440
0441
0442
0443
0444
0447
044A
044B
0.. 4C
1'8
DO
CO
1'0
.E8
EO
C8
E040
E045
C816
00C80516
FOC80516
C817
C810
(.Bll
C812
CBl3
CB14
C815
11
CB06
00CB050b
FOC8050b
CBOl
C800
C801
CII02
CB03
CB04
CB05
07
EDbF
C8lE
00C8051E
FOC805lE
CBlF
CB18
CII19
CBLA
CBIB
CBIC
CBlO
LF
C80E
DOC8050E
FOC8050E
C80F
CB08
CB09
CBOA
CIl08
C80C
CBOO
01'
E061
C7
07
OF
E7
H
1'1
FF
CF
9E
DD9E05
F09E05
91'
9B
99
STMT SOURCE STATEIl4ENT

4114
485
4a6
487
488
489
490
491
492
493
494
495
49b
491
498
499
500
501
502
503
504
505
50b
507
508
509
510
511
512
513
514
515
H6
517
518
519
520
521
522
523
524
525
526
521
528
529
530
531
532
533
534
535
536
531
538
539
540
541
542
543
544
545
546
541
548
549
550
551
552
RET
RET
RET
RET
RET
RET
RET
RETI
RETN
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
Rl
RlA
RlC
RlC
RlC
RlC
RlC
RlC
RlC
RlC
RlC
RlC
RlCA
RlO
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RRA
RRC
RRC
RRC
RRC
RRC
RRC
RRC
RRC
RRe
RRC
RRCA
RRO
RST
RST
RST
RST
RST
RST
RST
RST
S8C
S8C
S8C
SIlC
S8C
SBC
M
N(.
NZ
P
PE
PO
Z
IHLl
lIX+INOI
IIY+INO I
A
8
C
0
E
H
l
IHLI
IIX+INOI
IIY+lNOI
A
8
C
0
E
H
l
IHLI
lIX+INO I
IIY+INOI
A
B
C
0
E
H
l
IHLl
IIX+INOI
IIY+INOI
A
B
C
0
E
H
l
0
10H
18H
20H
28H
30H
38H
8
A,IHLl
A, I IX+INOI
A,IIY+INOI
A,A
A,8
A,C
APPENDIX C
INSTRUCTION SET NUMERICAL ORDER
VERSION 1.04
1-80 CROSS ASSEM8LR
.opeODE LISTING
10:20: 50
OF 04/18174
07109174
LOC
0000
0001
000'0
0005
0006
0007
0008
OOOA
0008
OOOC
0000
OOOE
GOOF
0010
0011
0013
001'0
0016
0019
OOlA
0018
001C
0010
001F
0020
0022
0023
002'0
0025
0026
0027
0029
002A
002C
002F
0032
0033
003'0
0035
0037
0038
003A
0038
003E
003F
00'00
0041
0043
00'04
00'06
00'09
004C
00'00
OOltE
004F
0051
0052
0054
0055
0058
0059
005A
0058
0050
DOSE
005F
0060
0061
0062
00
018'005
02
03
0'0
05
0620
07
08
09
OA
08
OC
00
OE20
Of
102E
118'005
12
13
14
15
1620
17
182E
19
lA
18
IC
10
lE20
IF
202E
218405
228405
23
2'0
25
2420
27
282E
29
2A8405
28
2C
20
2ElO
2F
302E
318'005
328405
33
3'0
35
3620
37
382E
39
3A8405
38
3C
3D
3E20
3F
40
41
42
43
44
HOP
1
2
3
'0
5
4
7
8
9
10
11
12
13
1'0
15
14
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
3'0
35
36
37
38
:19
40
'01
42
43
4'0
'oS
46
47
48
49
50
51
52
53
5'0
55
56
57
58
59
60
61
62
63
64
65
66
67
68
LO 8CtNN
LO 18C),A
INC 8C
INC 8
DEC 8
Lo 8tN
RLCA
EX AF,AF'
ADO HL,8C
LO A t 18c)
DEC Be
INC C
DEC C
LO C,N
RRCA
OJNl DIS
LO oEtNN
Lo 10EI,A
INC DE
INC 0
DEC 0
Lo DtN
RLA
JR DIS
ADD HL,oE
Lo A,loEI
DEC DE
INC E
DEC E
LO E,N
RRA
JR Nl,olS
Lo HL,NN
Lo INNI,HL
INC HL
INC H
DEC H
LO H,N
DAA
JR l,OIS
ADO HL,HL
Lo HLtINN!
DEC HL
INC L
DEC L
Lo L,N
CPL
JR NC,DIS
Lo SP,NN
LD INNI tA
INC SP
INC IHLI
DEC IHlI
LIT IHl),N
SCF
JR C,DI S
ADD HL.SP
LD A.(NNI
DEC SP
INC A
DEC A
LD A,N
CCF
lo 8.a
lD 8,C
LD 8.0
lD 8.E
69
LO B.H,NN
LOC
0063
006'0
0045
0066
0067
0068
0069
006A
0068
006C
0040
004E
006F
0070
0071
0072
0073
007'0
0075
0076
0077
0078
0079
007A
0078
007C
0070
007E
007F
0080
0081
00112
0083
00114
0085
0086
0087
0088
0089
008A
0088
oose
0080
008E
008F
0090
0091
0092
0093
0094
0095
0096
0097
0091l
0099
009A
009a
009C
0090
009E
009F
OOAO
OOAI
00A2
00A3
00A4
00A5
00A6
GOA?
290
08J CODE
'05
'06
'07
'08
'09
loA
'08
4C
'00
4E
'oF
50
51
52
53
5'0
55
56
57
58
59
SA
58
5C
50
5E
SF
60
61
62
63
6'0
65
66
67
68
69
6A
68
4C
60
6E
6F
70
71
72
73
7'0
75
76
77
78
79
7A
7a
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
STMT SOURCE STATI!MENT
136
137
LO 8,L
LO 8r1"LJ
LO 8,A
LO C,8
LO C,C
LO C,O
LO C,E
Lo C,H
LO CtL
Lo CrlHl)
Lo etA
Lo 0,8
LO otC
LO 0,0
Lo OtE
LO o,H
Lo o,L
Lo OtIH!.,1
Lo o,A
Lo Et8
Lo E,C
LO ftO
Lo E,E
LO E,H
LD E,L
Lo E,h~LJ
LD Et~
LD H,a
Lo H,C
Lo H,D
Lo HtE
Lo H,H
Lo H,L
Lo H,IHILI
LD- H,A
Lo L,8
Lo L,C
LD L,O
Lo L,E
Lo LtH
Lo L,L
Lo L,IHlI
Lo LtA
Lo IHU,,8
LD IHlIi,C
Lo IHLhO
Lo IHLI,E
Lo IHlIi,H
LD IHL),L
HALT
LD IHLJ"A
lO A,a
Lo A.C
lD A.D
LD A,E
LD A.H
LD AtL
lD A.IHLI
lD A.A
ADD A.8
ADD A.e
ADD A,D
ADO A.E
ADD A.H
ADD AtL
ADD A.IHLI
ADD A.A
AOC A,8
138
AGe A.e
70
71
72
73
7'0
75
76
77
71l
79
80
81
82
83
8'0
85
86
87
88
89
90
91
92
93
9'0
95
"96
97
98
99
100
101
102
103
10'0
105
106
107
108
109
110
111
112
113
114
115
114
117
118
119
120
121
122
123
12'0
125
126
127
128
129
130
131
132
133
134
US
I-eo CROSS ASSEMBLER

VERSION
1.06
07/09116
10:22 :47
OPCOOI:
LISTING
LuC
UllJ CODE
::'TMT SOURCE S1 ATEMENT
057F
0~80
0581
0582
0584
AB
AC
AD
H2O
691
692
693
694
695
6\16
697
698
699
700
NN
INO
M
N
01 S
XOR
XOR
XUI<
XOR
DEFS
HIU
EIlU
EQU
EQU
END
E
H
L
N
2
5
10H
20H
30H
289
OF 06/18176
VERSION 1.06
2-80 CROSS ASSEII8lER
.OPCOOE LI STlNG
07109176 10:20:50
08J CODE STilT SOURCE STATEMENT
lOC
0178
011A
017C
017E
0180
0182
0181t
0186
Olaa
018A
018C
OlaE
0190
0192
019"
0196
0198
019A
019C
019E
0140
OlA2
OlA"
OlA6
OlA8
OlAA
OlAC
OlAE
1)180
01B2
OlB"
01B6
01B8
018A
01BC
OUE
01CO
01C2
01C"
UIC6
01U
01CA
UICC
OlCE
UIOO
Ol02
OlD"
0106
0108
010A
010e
010E
OlEO
OlE2
OlE"
01E6
01E8
OlEA
OLEC
OlEE:
UIFO
.01F2
01FIt
OlF6
01F8
01FA
OlFC
OlH
02(10
C818
C819
C8lA
t818
C81C
t8l0
C81E
C81F
t820
t821
C822
CII23
C82't
C825
C826
C827
C828
t829
C82A
CII28
C82t
C820
CII2E
C82f
CB38
CB39
CB3A
CBlB
CB3C
CB30
CB3E
CB3F
CBltO
CB"l
CBlt2
C8lt3
C8""
C8lt5
C8"6
CBIt7
CB"II
CB"9
C8"A
CB"B
C8"C
CB"U
C8"E
C8"F
CB50
CB51
eB52
C853
C854
C855
C856
CB57
C858
e859
CB5A
C858
C85e
C850
C85E
C85F
CB60
e861
CB62
eB63
eB61t
277
278
279
280
281
282
283
28"
285
286
2117
288
289
290
291
292
293
291t
295
296
297
298
299
300
301
302
303
30lt
305
306
307
308
309
310
311
312
313
31lt
315
316
317
318
319
32U
321
322
323
32"
325
326
327
328
329
330
331
332
333
3l"
335
336
337
318
339
3"0
3"1
3"2
3lt3
3't"
3lt5
Of 06/18176
laC
0202
020"
0206
0208
020A
020C
020E
0210
0212
021lt
0216
0218
02lA
021C
021E
0220
0222
0221t
0226
0228
022A
022C
022E
0230
0232
0231t
0236
023B
023A
023C
023E
02ltO
02lt2
021t"
02"6
02ltB
02ltA
02"C
02"E
0250
0252
025"
0256
0258
025A
025C
025E
0260
0262
026"
0266
0268
026A
026e
026E
0270
0272
027"
027t>
0278
027A
027C
027E
0280
0282
028"
0286
0288
028A
RR II
RR C
RR 0
RR E
RR H
RR l
RR (HlI
RR A
SU 8
SU t
SlA 0
SlA E
SlA H
SlA l
SlA (HlI
SU A
SRA 8
SRA C
SRA 0
SRA E
SRA H
SRA l
SRA (HLI
SRA A
SRl B
SRl C
SRl 0
SRl E
SRl H
SRl l
SRl (Hll
SRl A
81T O,B
BIT O,C
811 0,0
BIT O,E
8IT O,H
81T O,l
BIT O,(HlI
8IT O,A
81T 1,8
B11 1,C
8IT lt~
BJT 1,E
8IT ltH
B11 l,l
81T l,(HlI
8IT loA
81T 2,8
BIT 2,e
8IT 2,0
81T 2,E
811 2,H
8IT 2,l
BIT 2,(HlI
1111 2,A
811 3,8
81T 3,C
8ll 3,0
8IT 3,E
8ll 3,H
81T 3,l
8ll 3, (HlI
OIT 3,A
81T ",B
IIIT ",e
8IT ",0
BIT ",E
BIT ",H
292
08J COOl:
CB65
C866
C867
C86B
C869
t86A
C868
tB6C
t860
C86E
C86F
t870
C811
C872
C813
C871t
t875
t876
C877
C878
C879
C8lA
C878
CB7C
CB70
CUE
CB7F
CB80
CB81
CB82
CB83
CB81t
C885
CB86
CB87
C888
C889
CBU
CBBB
CBBC
CBIIO
CBBE
CB8F
C890
C891
CB92
CB93
CB9It
e895
eB96
e897
e898
CB99
C89A
C898
C89C
C890
CB9E
CB9F
ClIAO
C8Al
e8A2
C8A3
CBA"
eU5
C8A6
CBAl
CBA8
ellA9
STilT SOURCE STATE"ENT

3lt6
3lt7
3lt8
3't9
350
351
352
353
351t
355
356
357
3511
359
360
361
362
363
361t
365
366
367
368
369
370
371
372
373
37"
375
376
377
378
379
380
381
382
383
38"
385
386
387
388
389
390
391
392
393
39"
395
39t>
397
398
399
"00
"01
"02
"03
"04
"05
loOt>
"07
"08
"09
"10
"11
"12
"13
u.
81T
BU
lilT
81T
lilT
81T
8IT
8U
81T
8IT
8ll
81T
81T
8U
81T
8U
8IT
81T
8IT
8IT
81T
8ll
8IT
BIT
8ll
BIT
BIT
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
R.ES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
It,l
",(lfll
",A
5,8
5,C
5,0
5,E
5,H
5,l
5,(Mll
5,A
6,8
6,C
6,0
6,E
6,H
6,l
6,HIll
6,A
7,8
7,C
7,0
7,E
7,H
7,l
7,Cllll
7,A
O,B
O,C
0,0
O,E
O,H
O,l
O,(HlI
O,A
1,8
1,C
1,0
l,E
l,H
1,l
1,CHlI
1,A
2,8
2,C
2,0
2,E
2,H
2,l
2,(Hll
2,A
3,8
3,C
3,0
3,E
3,H
3,l
3,(H!ll
3,A
",8
",e
",0
",E
",H
",l
",(HLI
",A
5,8
5,e
VERS ION 1.06

1-80 CROSS ASS EM8lER
.OPCOOE LISTING
10=20=50
07109116
lOC
00A8
00A9
OOAA
00A6
OOAC
OOAO
OOAE
OOAF
OOBO
OOBI
00B2
00B3
00B4
00B5
00B6
0061
0088
00B9
OOBA
OOBB
OOBt
OOBO
OOBE
OOIlF
OOCO
OOCI
00C2
00C3
00C4
00C5
00C6
00C7
00C8
00C9
OOCA
OOCB
ootC
OOCO
OOCE
OOCF
0000
0001
0002
0003
000'0
0005
0006
0007
0008
0009
OOOA
0008
OOOC
DODD
OOOE
OOOf
OOEO
OOEl
00E6
00E9
DOE A
OOEC
OOEO
OOEE
OOEF
00f2
00F5
00F8
OOFA
aA
88
8C
80
8E
8f
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9f
AO
AI
A2
A3
A4
A5
A6
A7
A8
A9
AA
A8
AC
AD
AE
Af
BO
81
B2
B3
B4
85
116
B7
B8
B9
8A
BB
BC
BO
BE
BF
CO
Cl
C28405
OB405
C48405
C5
C620
C7
C8
C9
CA8405
CC8'o05
C08405
CE20
CF
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
111
172
173
174
175
176
117
178
179
180
181
182
183
184
185
186
187
18B
189
190
I'll
192
193
194
195
196
191
198
199
200
201
202
203
204
205
206
207
OF 06/18116
lOC
00F8
OOFC
OOFO
0100
0102
0105
0106
0108
0109
010A
010B
010E
0110
0113
OU5
OU6
0117
0118
DUB
OUC
OUF
0120
0122
0123
0124
0125
0128
0129
012C
012E
012F
0130
0131
0134
0135
0138
0139
013B
013C
0130
DUE
0141
0142
0145
0141
o lit 8
01'oA
014C
014E
0150
0152
0154
0156
0158
015A
015C
015E
0160
0162
0164
0166
0168
016A
016t
016E
0170
0172
011't
0176
AOC A,O
AOC A. E
AOC A,H
AOC A,l
AOC A,IHLI
AOC A,A
SU6 6
SU8 C
SU6 0
SUB E
SUB H
SUB l
SU8 (HLI
SUB A
SBC A, B
SBC AtC
SBC A,O
SBC At E
S8C A, H
SBC A, l
S8C A, I HLI
SBC A, A
AND B
AND C
AND 0
AND E
AND H
AND l
AND IHLI
AND A
XOR 8
XOR C
XOR 0
XOR E
XOR H
XOR l
XOR (Hl I
XOR A
OR B
OR C
OR 0
OR E
OR H
OR l
OR I HLI
OR A
CP B
CP t
CP 0
CP E
CP H
CP l
tP (HLI
CP A
RET NZ
POP BC
JP NZ,NN
JP NN
CAll NZ,NN
PUSH BC
ADD A,N
RST 0
RET Z
RET
JP Z,NN
CALL Z ,NN
CAll NN
AOC A,N
RST 8
291
OBJ CODE
DO
01
028405
0320
048405
05
0620
01
08
09
oA8405
OB20
OC6405
OE20
Of
EO
El
E28405
E3
E48405
E5
E620
E7
E8
E9
EA8405
EB
EC8405
EE20
EF
FO
F1
F28lt05
F3
F48405
F5
F620
F7
Fa
F9
FA8lt05
FB
FC8405
H2O
FF
CBOO
CBOI
C802
CB03
CB04
CB05
CB06
CB07
CB08
CB09
CBOA
CBOB
CBOC
CBOO
CBOE
CBOF
CB10
CBll
CB12
CB13
CB14
CB15
C816
C817
SIMT SOURCE STATEMENT

208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
2'08
249
250
251
252
253
25'0
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
RET NC
PDP DE
JP NC,NN
OUT N, A
CAll NC,NN
PUSH DE
SUB N
RST 10H
RET C
EXX
JP C,NN
IN A,N
CAllC,NN
SBC AtN
RST 18H
RET PO
POP Hl
JP PO,NN
EX I SPI ,Hl
CAll POtNN
PUSH Hl
AND N
RST 20H
RET PE
JP (HLI
JP PE,NN
EX OEtHl
CAll PE,NN
XOR N
RST 28H
RET P
POP AF
JP P tNN
01
CAll P,NN
PUSH AF
OR N
RST 30H
RET M
lO SPtHl
JP M,NN
EI
CALL MtNN
CP N
RST 38H
RlC B
RlC C
RlC 0
RlC E
RlC H
RlC l
RlC (HLI
RlC A
RRC B
RRC C
RRC 0
RRC E
RRC H
RRC l
RRC (HLI
RRC A
Rl B
Rl C
Rl 0
Rl E
Rl H
Rl l
Rl (HLI
Rl A
VERSION 1.06
1-80 CROSS ASS EM8LER
.OPCOO!: LISTING
10120150
OBJ CODE STHT SOURCE STATEMENT
07/09176
LaC
030A
Q30E
03E2
03E6
03EA
03EE
03F2
U3F6
03FA
03FE
0402
040.
040A
O'tOE
0'012
0416
041A
041E
0422
0424
0426
0428
042C
042E
0430
0432
043'0
0436
0'038
043A
043E
0440
04't2
0444
0446
0444
044C
044E
0450
0452
0454
0458
0'o5A
045C
045E
0460
0462
0464
0466
0468
046A
046C
0470
0472
0474
0476
047A
041C
047E
0't80
0'082
0484
0486
0488
048A
048C
O't8E
0490
0'092
00C80576
00CB057E
00CB0586
00C8058E
00C80596
00C8059E
OOC805A6
ODC805AE
00C80586
00C8058E
00C805C6
00C805CE
00C80506
00CB050E
00C805E6
00C805EE
00C805F6
00C805FE
E040
ED41
E042
E04384.:>5
E044
ED4S
E046
E047
E048
E049
E04A
ED4884U5
E040
E050
EOSI
ED 52
E0538405
E056
E057
E058
E059
E05A
E0588405
E05E
ED60
ED61
E062
ED67
E068
E069
ED6.
E06F
E072
E073a405
E078
E079
EOlA
ED 788'oU5
EOAO
EOAl
EOA2
EOA3
EOA8
EOA9
EOAl
EOAB
E080
E081
E082
EOU
EOB8
553
554
555
556
557
558
559
560
561
562
5.3
564
565
566
567
568
569
570
571
572
573
514
575
576
571
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
611
618
619
620
621
OF 06/18176
LOC
0494
0496
0498
U'o9A
049C
049E
04A2
04A6
04A8
04U
04AE
0480
0'083
0'oB6
0't8A
048C
048F
04C2
04C5
04t8
04C8
04CE
0401
0404
0407
040A
0400
04EO
04E3
04E6
04E9
04EC
04EF
04F2
O'tF5
04F8
04F8
04FE
0500
0502
05O't
0506
0508
050C
0510
051'0
0518
051C
0520
0524
0528
052C
0530
0534
0538
053C
0540
054'0
0548
054C
0550
0554
0558
055C
0560
0564
0568
056C
0510
81T6,IIX+INO)
8IT 7, I IX+INO)
RES 0,1 lX+INO.
RES l,IIX+INO.
RES 2,(lX+INO.
RES 3,IlX+INO.
RES 4,IIX+INO.
RES 5, I IX+INO.
RES 6,11 X+INO.
RES 7, I lX+INO.
SET 0, I JX+INO.
SET 1,1 lX+INO.
SET 2,1 lX+INO.
SET 3,1 IX+INO.
SET 4,C lX+INO.
SET 501 IX+lNO)
SET 6,(lX+INO.
SET 7,ClX+INOI
IN 8,IC)
OUT IC.,8
S8C HL,8C
LO CNNh8C
NEG
RETN
1M 0
LO I,A
IN C,CC)
OUT CC. ,C
AOCHL,8C
LO BC,INNI
RETl
IN O,IC.
OUT IC. ,0
S8C HL,OE
LO INNI,OE
1M 1
LO A,I
IN E,IC.
OUT IC. ,E
AOC HL,OE
LO OE,INIH
1M 2
IN H,IC.
OUT IC. ,H
S8C HL,HL
RRO
IN L,CC.
OUT ICI,L
AOC HL,HL
RLO
S8C HL,SP
LO INNhSP
IN A,IC.
OUT CC. ,A
AOC HL,SP
LO SP,INN.
LOI
CPI
INI
OUTl
LOO
CPO
INO
OUTO
LOIR
CPIR
INIR
OTiR
LOOR
294
08J COOf
E089
f08A
E088
FOO9
F019
F0218405
F0228405
F023
F029
F02U'o05
F028
F03'o05
F0350S
F0360520
F039
F04605
F04E05
F05605
F05EOS
FD6605
F06E05
FD7005
F07105
F07205
F0730S
F07405
F07505
F07705
F07E05
F08605
F08E05
F09605
F09E05
FOA605
FOAE05
F08605
F08E05
FOEI
FOE3
FOE5
FOE9
FOF9
FOC80506
FOC8050E
FDC80516
FOC8051E
FOC80526
FOC8052E
FDC8053E
FOC80546
FDC8054E
FOC80556
FOC8055E
FOC80566
FOC8056E
FOC80516
FOCB057E
FOCB0586
FOCB058E
FOCB0596
FDCB059E
FOCB05A6
FOCB05AE
FOC805B6
FDCB05BE
FDC805C6
FOCB05CE
FDCB05D6
FOC8050E
STMT SOURCESUTEMllNT
622
623
624
625
626
621
628
629
630
631
612
633
634
635
636
631
638
639
640
641
642
643
644
645
646
647
.48
649
.50
651
652
653
654
655
656
651
658
659
660
661
662
661
664
665
666
667
668
669
670
671
672
673
6\4
675
676
677
678
619
680
681
682
6413
68'0
685
686
687
688
6lJ9
690
CPaR
INOR
OTOR
ADD IY,8C.
ADD lY.OS
LO IY,NN
LO INNhl'Y
INC IY
ADD IY,JY
LO IY,INN)
DEC IY
INC ClY+liNO.
DEC IIY+~NO.
LO I IY+IO. ,N
ADD IY,SPi
LO 8,ClYtjINO.
LO C,IlY+'INO.
LO O,IlY+!INO)
LO E,llY+'IND.
LO H, I IY+!INO.
LO L, I Iy+',INO.
LO IlY+INbl,8
LO IIY+INbhC
LO I IY+IN ,0
LO IIY+IN .,E
LO (lY+lN hH
LO 1I.,+INp.,L
t~ ~~:~~~r.~o~
ADD A,IIY!+INO.
AOC A,ClY~INO.
SU8 IlY+INO.
S8C A,ClYi+lNO)
AND I IY+I~O.
XOR IlY+INO)
OR IIY+INIU
CP IIY+INIH
POP IY
EX ISPI,IY
PUSH IY
JP l i n
LO SP,IY
RLC IIY+IllO.
RRC IlY+ItO.
RL ClY+IN
RR I IY+IN~.
SLA IlY+I O.
SRA IlY+ItlO.
SRL IlY+I~O)
8IT O,ClYHNO.
8IT 1,IIYt!NO.
81T 2,IIYt!NO.
BIT 3, (lYt!NO.
8IT 4,IIYt!NO.
8IT 5, I IYt!NO.
8IT .6, II ytiNO.
8IT 1,1 IYHNO.
RES 0, I IYtINO)
RES l,ClYtINO.
RES 2~ I IYHNO.
RES 3,1 lYtINO.
RES 4,llYtlNO.
RES 5, I IY.... NO.
RES 6,ClVHNO.
RES 7, II V+INO.
SET 0, ClVtlNO.
se T l,IlV+INO.
SET 2,IIVHND.
SET 3,IIY+INDJ
VERSION 1.06
2-80 CROSS ASSEMBLER
.OPCOOE
LISTING
10:20:50
01109116
OBJ CODE STMT SOURCE STATEMENT
LOC
028C
028E
0290
0292
0294
0296
0298
029A
029C
029E
02AO
02A2
02A4
02A6
02A8
02AA
02AC
02AE
02BO
02B2
02114
02B6
0288
02BA
02BC
02BE
02CO
02C2
02C4
02CO
02C8
02CA
02CC
02CE
0200
0202
0204
0206
02011
020A
020C
020E
02EO
02E2
02E4
02E6
02E8
021:A
02EC
02EE
02FO
02F2
02F4
02F6
02F8
02FA
02FC
02FE
0300
0302
0304
0306
0308
030A
030C
030E
0310
0312
0314
CbAA
CBAB
CBAC
CBAO
CBAE
C8AF
CBBO
CBIlI
CBB2
CIlB3
CBB4
CIlB5
CBB6
CBBl
CIlBil
CBB9
CIl8A
CBBIl
CBBC
CBBO
CBBE
CIlBF
CBCO
CBCl
CBC2
CBC3
CBC4
CBC5
CBC6
CBC 1
CBC8
CBC9
CBCA
CIlCB
C8CC
C8CO
C8CE
C8CF
C800
CBol
CIl02
CB03
CB04
C805
C806
CBOl
CB08
C809
C80A
C80B
CBOC
CBOO
CBOE
CBOF
CBEO
CBEl
CBE2
CBE3
CBE4
CBE5
CBE6
CBEl
CBE8
CBE9
CBEA
CBeB
CBEC
CIlEO
CBEE
415
416
411
418
419
420
421
422
423
424
425
426
421
428
429
430
431
432
433
434
435
436
431
438
439
440
441
442
443
444
445
446
441
448
449
450
451
452
453
454
455
456
451
458
459
460
461
462
463
464
465
466
461
468
469
410
471
412
413
414
415
416
411
478
419
480
481
482
4lU
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SE T
SET
SET
SE T
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
OF 06/18176
LOC
0316
0318
031A
OllC
031E
0320
0322
0324
0326
0328
032A
032C
032E
0330
0332
0334
0336
0338
033A
033C
0340
0344
0346
0348
034C
034E
0351
0354
0358
035A
0350
0360
0363
0366
0369
036C
036F
0312
0315
0318
0318
OHE
0381
0384
0387
038A
0380
0390
0393
0396
0399
039C
039E
03AO
03A2
03A4
03A6
03AA
03AE
03B2
0386
03BA
03BE
03C2
03C6
03CA
03CE
0302
0306
5,0
5,E
5,H
5, L
5,IHlI
5,A
6,B
6,C
6,0
6, E
6.H
6,L
6,IHll
6,A
1,8
1.C
1,0
1, E
1,H
1,L
l,(HlI
1, A
0, Il
O,C
0,0
O,E
O,H
0, L
O,(HLI
O.A
I.B
I,C
1,0
I,E
I,H
I,L
1,IHlI
I,A
2,B
2,C
2,0
2,E
2,H
2, L
2,IHll
2,A
3 B
3,C
3,0
3, E
3,H
3,L
3,( Hll
3, A
4,B
4,C
4,0
4,E
4,H
4,L
4, I Hli
4,A
5,B
5. C
5,0
5,E
5,H
5,l
5,IHll
293
08J CODE
C8EF
CBFO
CBFl
CBF2
CBF3
CBF4
CBF5
CBF6
CBF1
CBF8
CBF9
CBFA
CIlFB
C8FC
CBFO
C8FE
CIlFF
0009
0019
00218405
00228405
u023
0029
002A8405
002B
003405
003505
00360520
0039
004605
004E05
005605
005EO,
006605
OOoE05
001005
001105
001205
001305
001405
001505
001105
001E05
008605
008E05
009605
009E05
00A605
00AE05
008605
00BE05
DOE 1
OOEl
00E5
00E9
00F9
00CB0506
00CB050E
00CIl0516
00CB05H
00CB0526
00CB052E
00CB053e
00C80546
00CB054E
00CB0556
00CB055E
00CB0566
OOCB056E
STMT SOURCE
484
485
486
481
488
489
490
491
492
493
494
495
496
491
498
499
500
501
502
,03
504
505
506
501
508
509
510
511
512
513
514
515
516
511
518
519
520
521
522
523
,24
525
526
521
528
529
530
531
532
533
534
535
536
531
538
539
540
541
542
543
544
545
546
541
548
549
550
551
552
STATEM~NT
SET 5, A
SET 6,8
SET 6,C
SET 6,0
SET 6,E
SET 6, H
SE T 6, L
SET 6,IHlI
SET 6,A
SET 1,B
SET 1.C
SET 1,0
SE T 1, E
SET 1, H
SET 1,L
SET 1,IHLI
SET 1,A
ADO IX,BC
ADO IX,OE
LO IX,NN
LO INNltlX
INC IX
ADO IX, IX
LO IX,INNI
DEC IX
INC IIX+INOI
DEC IIX+INOI
LO IIX+INOI,N
ADO IX,SP
LO B,IIX+INOI
LO C,IIX+INOI
LO 0,1 IX+INOI
LO E,lIX+INOI
LO H,IIX+INOI
LO L.lIX+INOI
LO IIX+INOI,B
LO IIX+INOI,C
LO IIX+INOI,O
LO IIX+INOI,E
LO IIX+INOI,H
LO IIX+lNOI,L
LO IlX+INOJ,A
LO A,IIX+INOJ
ADD A,lIX+INOJ
AOC A,(IX+INOI
SUB IIX+ INO I
SBC A,lIX+INOI
AND IIX+lNOI
XOR IIX+INOJ
OR IIX+lNOI
CP IIX+INOJ
POP IX
EX I SP I, I X
PUSH IX
JP IIXI
LO SP, IX
RLC IIX+INOJ
RRC lIX+INOI
RL IIX+INOI
RR IIX+INOI
SLA IIX+lNOI
SRA IIX+JNOJ
SRL IIX.+INOI
BIT O,lIX+INOI
81T 1,IIX+INOI
BIT 2,(IX+INOI
BIT 3,IIX+lNOI
BIT 4,IIX+INOI
BIT 5, II X+INOI
MAIN REG SET
ALTERNATE REG SET
~~
FLAGI
F
ACCUMULATOR
A
ACCUMULATOR
FLAGS
F'
A'
}--'
PURPOSE
REGISTERS
INTERRUPT
VECTOR
MEMORV
REFRESH
)R".
PURPOSE
REGISTERS
PROGRAM COUNTER PC
zao-cpu
REGISTER CONFIGURATION
ASCII CHARACTER SET (7-BIT OODE)

HEXADECIMAL COLUMNS
5
HEX=DEC
0
11,048,576
22.097,152
33,145,728
44,194,304
55,242.880
66,291,456
77.340,032
88.388,608
99,437.184
A 10,485.160
811,534.336
C12,582.912
013,631.488
E14.680,064
F15.728,640
HEX' DEC
o
0
166.536
2131,072
3196.808
4262.144
5321,680
6393,216
7458.152
8524,288
9581,824
0123
4567
A 865,380-
8120.896
C78432
D 86',II6lI
E9'7.604
F983.040
BYTE
HEX DEC HEX' DEC HEX' DEC HEX

o
0
0
0
o
00
14,086
1261
1
111
28.192
2612
2
32 2
312.288
3168
3
48 3
416,384
41.024
4
64 4
520,490
51,290
5
90 5
624,575
61,538
95 6
8
728,672
7',782
7
1121
832.168
82.048
8
'28 6
936,864
82,304
'44 8
9
A 40.960
A 2,680
A
160 A
845.058
82,81.
8
11. 8
C 49.152
C 3.072
C
192 C
D 53,248
D 3,328
D 206 D
E57,344
E3.664
E
224 E
F.1,440
F3.840
F
240 F
0123
4567
BYTE
LSD
DEC
0
1
2
3
4
5
6
1
8
8
10
11
12
'3
14
15
0123
4587
BYTE
POWERS OF 2
2"
256
512
1024
2048
4086
8192
18384
32788
lll5638
131072
262144
524288
1048578
2097152
4194304
838880S
18777218
0000
000
001
010
DLE
DCl
DC2
DC3
DC4
NAK
SP
0
1
2
3
4
5
0001
00'0
0011
0'00
0'0'
NUL
SOH
STX
ETX
EOT
ENG
8
7
8
9
A
0110
0111
1000
1001
'DID
ACK
BEL
BS
HT
LF
SYN
ETB
CAN
EM
SUB
B
C
D
E
F
'011
1100
1101
1110
1111
VT
FF
CR
SO
SI
ESC
FS
GS
RS
VS
#
S
'~"
(
.
-
POWERS OF 16
n
8
8
10
11
12
13
14
15
18
17
18
19
20
21
22
23
24
16"
zO '1s"
z4 "8'
z8 "82
2'2.,&3
2'6'1&4
:z3l.,&6
2'41&6
z26"87
z32188
z38,,&,
z40"8'o
z44',8"
z48"8 12
z82"8 13
zIi8'18'4
zSO',8 15
296
18
258
4086
lll5538
1048578
18777218
2884364158
4294987298
88 719478738
1099611 B27 778
17692188044418
28147497671011158
4 603 599 827 370 498
72057594 037 927 938
1152921 504 808 8415 978
2
3
4
5
8
7
8
9
10
11
12
13
14
16
3
0"
0
1
2
3
4
5
6
7
8
9
.
4
100
'01
"0
111
:
:
A
B
C
D
E
F
G
H
I
J
>
K
L
M
N
<
0
R
S
T
U
V
f
8
X
Y
Z
I
\
J
h
i
k
I
m
.
t
~
I
DEL,
,-80 CROSS ASSEM8LER

VERSION 1.06
01109116
10:20:50
.OPCOOE LISTING
LOC
08J COOE
0574
0518
057C
0580
0584
FOC805E6
FOC805EE
FOC805F6
FOC805FE
691
692
693
694
695
696
691
698
699
100
NN
IND
M
N
01 S
SET 401 IY+lNO)

SET 5,( IY+INOI
SET 6,IIY+INDI
SE T 7,11 Y+ I NO)
OEFS 2
EQU 5
EQU 10H
EQU 20H
EQU 30H
END
295
OF 06/18/16

Building A Home Security System With BeagleBone (2013) - Pretty

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Building A Home Security System With BeagleBone (2013) - Pretty

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zao ASSEMBL Y LANGUAGE PROGRAMMING MANUAL

Copyright 1977 by 2ilog, Inc. All rights reserved. No part of this

recording, or otherwise, without the prior written permission of Zilog.

SPECIFICATION OF ZaD ASSEMBLY LANGUAGE

ZaG CPU FLAGS

zaD INSTRUCTION SET

INSTRUCTION INDEX 275

ERROR MESSAGES 280

Z80 ASSEMBLY LANGUAGE PROGRAMMING MANUAL

The assembly language provides a means for writing a

SPECIFICATION OF THE Z80 ASSEMBLY LANGUAGE

indicates the contents of the register C are to be

The regular formation of assembly instructions

The contents of 16-bit double registers

3) The contents of the auxiliary register

4) The state of the four testable flags is

7) e specifies a one-byte expression in the

C. RULES FOR WRITING ASSEMBLY STATEMENTS (SNTAX)

In this example. the label. LOOP, provides a means

ASSEHBLY LANGUAGE CONVENTIOnS

Parenthesis can be used to ensure correct

Note that the negative of an expression can be

suppressed during evaluation of its argum~nt, thus

X.MOD.Y. = X-Y*(X/Y) where the division (X/Y)

will jump relative to the instruction which is

There are several pseudo-ops which the various

Sets value of a label to nn in the

Sets address reference counter to

Sets value of a label to nn and can

Defines the contents of a byte at

Defines the content of pne byte of

Defines the contents of a two-byte

Reserves nn bytes of memory

Defines the content of n bytes of

Harks the end of a macro

Pseudo-ops are assembled exactly like executable

Evaluates expression nn.

occur within an expression.

1011100B, 134Q, 1340, 92, 92D, OSCll

Causes the listing to advance to a

Causes string s to be taken as a

Causes listing and printing to be

Causes listing and printing to

Causes listing and printing of

Causes listing and printing of

Causes the source file filenace to

The expected use of *Include is for files of macro

Macros provide a means for the user to define his

The label <name> is required, ~nd must obey all the

include macro calls.

The statements of the macro body are not assembled

The <label> is optional, and <name> must be a

to the macro file.

using a block of code repetitively in line,

Program size can usually be saved by using the

MxN bytes would be used in direct

N (for the block)

For example, for a block of 20 bytes used 5 times,

Subroutine code is assembled into an object

Registers and pointers required by a

Z80 STATUS INDICATORS

The flag register (F and F') supplies information to the

Each of the two Z-80 Flag Registers contains 6 bits of