Ques : A very good interview question...

What is difference between setup and ho

ld time. The interviewer was looking for one specific reason , and its really a
good answer too..The hint is hold time doesn't depend on clock, why is it so...?
Ans: Setup violations are related to two edges of clock, i mean you can vary the
clock frequency to correct setup violation. But for hold time, you are only con
cerned with one edge and does not basically depend on clock frequency
Ques :What is Stuck-at fault ?
Ans: A Stuck-at fault is a particular fault model used by fault simulators and A
utomatic test pattern generation (ATPG) tools to mimic a manufacturing defect wi
thin an integrated circuit. Individual signals and pins are assumed to be stuck
at Logical '1', '0' and 'X'. For example, an output is tied to a logical 1 state
during test generation to assure that a manufacturing defect with that type of
behavior can be found with a specific test pattern. Likewise the output could be
tied to a logical 0 to model the behavior of a defective circuit that cannot sw
itch its output pin.
Ques : What is Clock Gating ?
Ans: Clock gating is one of the power-saving techniques used on many synchronous
circuits including the Pentium 4 processor. To save power, clock gating refers
to adding additional logic to a circuit to prune the clock tree, thus disabling
portions of the circuitry where flip flops do not change state. Although asynchr
onous circuits by definition do not have a "clock", the term "perfect clock gati
ng" is used to illustrate how various clock gating techniques are simply approxi
mations of the data-dependent behavior exhibited by asynchronous circuitry, and
that as the granularity on which you gate the clock of a synchronous circuit app
roaches zero, the power consumption of that circuit approaches that of an asynch
ronous circuit.