DEPARTMENT OF ELECTRICAL ENGINEERING

Academic Session : JUNE 2016

COURSE OUTLINE
Course and Code : DEE6113 CMOS Integrated Circuit Design
Program
: DEE
Course Lecturer
Contact No.

Course Credit hour: 2

Total Lecture Hour: 30
Total Practical Work Hour: 30

: Noorfozila binti Bahari

: 019-2772024 (HP), 09-5655386 (O)

Course Synopsis:
CMOS INTEGRATED CIRCUIT DESIGN course exposes the students to the basic integrated circuit (IC) fabrication
processes including MOS transistor and Microelectromechanical System (MEMS) fabrication process. This
course also covers the principles of CMOS inverter and CMOS integrated circuit design. Furthermore, the
students will be equipped with the knowledge of designing the inverter and simple to complex digital CMOS
gates. The students will experience developing the physical layout of integrated circuit using CAD tools
complying with specific design rules. Finally, this course will also cover the topic on design methodology that is
used in designing integrated circuit.

Learning Outcomes :
Upon completion of the course, students should be able to:
Course Learning Outcome (CLO)

Programme Learning
Outcome(s) Addressed

Assessment Methods

1.

apply the knowledge of integrated circuit

evolution, classification and design methodology in
CMOS IC design. (C3, PLO1)

PLO1

Q, T, E

2.

design the logic gates and Boolean functions for

static and dynamic CMOS and the stick diagram of
the IC layouts. (C5, PLO4)

PLO4

Q, EOC, T, E

3.

manipulate the layout design of a CMOS circuit

using layout design software based on specific
CMOS layout design rules. (P4, PLO5)

PLO5

PW

4.

demonstrate good oral communication skill in

group presentation on assigned topic(s) within a
stipulated time frame. (A3, PLO6)

PLO6

Pr

Legend for Assessment Methods:

Q : Quiz
FE : Final Exam
P : Project

T : Test
EOC : End of Chapter Problem
Pr : Presentation

PW : Practical Work
PT : Practical Test
E : Essay
A : Assignment

PLAN LECTURE WEEKLY SCHEDULE :

Week 1

Student Registration Week & Course Briefing

Week 2 3

Topic 1 INTRODUCTION TO INTEGRATED CIRCUIT (IC)

1.1 Know integrated circuit
1.2 Understand the evolution of integrated circuit
1.3 Understand the classification of integrated circuit

Week 4

Festival Break

Week 5 - 7

Topic 2- INTEGRATED CIRCUIT FABRICATION PROCESS

2.1 Know how single crystal silicon is formed
2.2 Understand the basic process steps for wafer preparation
2.3 Understand the integrated circuit basic fabrication process
2.4 Understand the fabrication process for CMOS integrated circuit
2.5 Know the concept of MEMS
2.6 Understand MEMS fabrication process

Week 8 - 9

Topic 3 CMOS INVERTER

3.1 Know NMOS and PMOS transistor
3.2 Understand static CMOS inverter
3.3 Apply the knowledge of inverter characteristics in CMOS inverter operation

Week 10 - 12

Topic 4 DESIGNING COMBINATIONAL LOGIC CIRCUITS

4.1 Know static CMOS logic circuits
4.2 Understand complementary CMOS circuit
4.3 Apply the knowledge of complementary CMOS circuit in logic gates
4.4 Design complementary CMOS circuit
4.5 Know pseudo-NMOS logic definition and advantages
4.6 Understand pseudo-NMOS inverter
4.7 Apply the knowledge of pseudo-NMOS inverter in logic circuits
4.8 Know pass-transistor logic circuits
4.9 Understand pass-transistor circuit operation
4.10 Apply the knowledge of pass-transistor logic in constructing logic gates
4.11 Design using pass-transistor logic
4.12 Know the basic principles of dynamic CMOS logic
4.13 Understand issues regarding dynamic CMOS logic design
4.14 Apply the knowledge of dynamic CMOS in designing logic gates
4.15 Design logic gate using dynamic CMOS

Week 13 - 15

Topic 5 - LAYOUT DESIGN

5.1 Understand integrated circuit layout
5.2 Apply the knowledge of integrated circuit layout in drawing stick diagram
5.3 Understand the integrated circuit design rules in designing the integrated circuit layout
5.4 Design the integrated circuit layout

Week 14

Semester Break

Week 16 - 18

Topic 6 - DESIGN METHODOLOGY

6.1 Know hierarchy design
6.2 Understand the design methodology
6.3 Understand Programmable Logic Devices (PLD)
6.4 Apply the knowledge of PLD architecture in constructing PLD array structure

Week 19 - 20

Final Exam Week

PLAN PRACTICAL WORK WEEKLY SCHEDULE

Week 1

Student Registration

Week 2

Briefing on Practical Works and Lab safety (OSHA)

Week 3

PW1: Introduction to Microwind 2.6a software

Week 4

Festival Break

Week 5 - 6

PW2: Designing NMOS and PMOS layout

Week 7 9

PW3: Designing Inverter layout

Week 10 12 PW4: Designing Basic Gates layout ( 2 input NAND/AND & NOR/OR)
Week 13

PW5: Designing XOR / XNOR layout

Week 14

Mid-Semester Break

Week 15 - 16

Continue PW5: Designing XOR / XNOR layout

Week 17 - 18

PW6: Designing Complex Function Layout

Week 19

Presentation

Week 20 - 21

Final Exam Week

Course Notes

References

Online lecture notes and practical work sheets are provided at CIDOS platform to
cover the theoretical and practical sessions. Practical works and presentation are
assigned in groups but assessed individually. Please refer to Assessment Specification
Table for the details.
1.

2.

3.

4.

Main:
Ki Bang Lee.(2011). Principles of Microelectromechanical Systems, John Wiley &
Sons. Inc, New Jersey.
Additional:
Adel S. Sedra and Kenneth Carless. Smith(2003). Microelectronic Circuits. Oxford
University Press
Michael Quirk & Julian Serda. (2001). Semiconductor Manufacturing Technology,
Prentice Hall, Inc.
Rabaey, J. M, Anantha Chandrakasan, Borivoje Nikolic. (2003). Digital Integrated
Circuit, Prentice Hall, Inc.
Uyemura, J. P. (2006). Chip Design for Submicron VLSI . Nelson, Thompson of
Canada Ltd.
Weste, N, Eshraghian.K. (2000). Principles of CMOS VLSI Design. Addison-Wesley

ASSESSMENT SPECIFICATION TABLE:

No

Assessment Task

Quantity

Criteria

% Total

Dates

1.

Quiz

Quiz 1 - Topics 1/2

Quiz 2 Topic 3/4/5

10%

Week

2.

Theory Test

Course topics 1 - 5

10%

Week

3.

End of Chapter Problem

Course topics 3/4/5

2.5%

Week

4.

Essay

Course topics 1 - 6

2.5%

Week

5.

Presentation

Course topics 1/2/6

Week

6.

Practical Work

Course topics 3 - 5

25%

Week 2-18

Overall Total

50%

Prepared by:

Endorsed by:

Name: NOORFOZILA BINTI BAHARI

Name:

Signature:

Signature:

Date: 12 / 06 / 2016

Date: