Saturn v LVDC Vol2 Jan65

ASA-CB-12^280)

LAUNCH VEHICLE

JJi'-LR

i-

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Laboratory Maintenance Instructions.

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(International Business Machines Corp.)

VOLUME II OF II

Laboratory Maintenance Instructions

SATURN V LAUNCH VEHICLE DIGITAL COMPUTER

Simplex Models

NASA Part No. 50M35010

IBM Part No. 6109030

(International Business Machines CorpOTOfthgV '

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Contract MAS 8-11561

LATEST CHANGED PAGES SUPERSEDE THE SAME PAGES OF PREVIOUS DATE

Insert changed pages into basic

publication.

VOLUME II

Destroy superseded pages.

MAINTENANCE DATA

30 NOVEMBER 1964

CHANGED 4 JANUARY 1965

LIST OF EFFECTIVE PAGES

INSERT LATEST CHANGED PAGES. DESTROY SUPERSEDED

PAGES.

TOTAL NUMBER OF PAGES IN VOLUME H IS 230 CONSISTING OF THE FOLLOWING:

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No.

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Issue

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65

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4 Jan 65

*The asterisk indicates pages changed, added, or deleted by the current change.

A Changed 4 January 1965

* )

^MÂ^Y ⁹ \1966

VOLUME II OF II

Laboratory Maintenance Instructions

SATURN V LAUNCH VEHICLE DIGITAL COMPUTER

Simplex

Models

NASA Part No. 50M35010'

r .-,&- -

IBM Part No .6109030

_f

^^

S^

'•

\

- -

'

J

•-

:',

'-K

-

'

.*

i

• '•' ~

•

i

*

"l;.*r"

(International Business Machines

Corporation]

Contrac t MAS 8-11561

VOLUME II

MAINTENANCE DATA

30 NOVEMBER 1964

Technical Library, Bellcomm, !nc _s

•r

LIST OF EFFECTIVE

PAGES

INSERT LATEST CHANGED

PAGES. DESTROY SUPERSEDED PAGES.

NOTE: The portion of the text affected by the changes is indicated by 3 vertical line in the outer margins of the page.

TOTAL NUMBER OF PAGES IN VOLUME H IS 228 CONSISTING OF THE FOLLOWING:

Page No.

_I_s_s_u_e

Title

Original

A

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i

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ii

Blank

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iii thru v

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vi

Blank,

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.

^Thc ;istcri.sk indicates pai;es chunked, added, or deleted bv the current clunije

Volume II

TABLE OF CONTENTS

Section

Title

Page

m

INTERFACE AND

,

3- 1

3-1.

Interface

.

3-1

3-3.

Adjustments

.

3-1

IV

TEST EQUIPMENT AND SPECIAL TOOLS

4-1

4-1.

Test Equipment

4-1

4-2.

Standard Test

4-1

4-4.

Special Test Equipment.

4-1

4-6.

Special Tools.

.

f 4-1

V

PREPARATION FOR USE, STORAGE AND SHIPMENT

.

5-1

5-1.

Preparation for Use

5-1

5-2A.

Inspection and Test

.".'

5-4

5-3.

Preparation for Storage

'.'

'

5-4

5-5.

Preparation for

5-5

5-7

General Computer Handling

5-7

Vl"

PREVENTIVE

6-1

VH

CHECKOUT

7-1

7-1.

Operating Test Procedures

7-1

VEQ

TROUBLE ISOLATION

8-1

IX

REPAIR

9-1

9-1.

Repair

9-1

X

DIAGRAMS

10-1

10-1.

Diagrams

10-1

10-3.

Signal Tracing

10-2

Changed 4 January 1965

i/ii

Volume

LIST OF

ILLUSTRATIONS

Figure

Title

Page

3-1

Computer Connectors By Signal

, 3-1

3-2

Computer

Interface Signals (8 Sheets)

3-2

3-3

Computer —Data Adapter Interconnection Block Diagram

. 3-10

3-4

3-5

Computer and LVDC-ME Interconnection Block Diagram

Computer - ATOM Interconnection Block Diagram

3-11

3-12

4-1

Standard Test Equipment

Special Test Equipment

Special Test

.

.

.

.'

-

.

.

4-1

4-2

;

;.'•.

4-2

4-3

•

.

.

.

.

.

.

.

4-3

4-4

Special

Tools Table

.

.

.

4-4

4-5

Special

Tools

"." 4-5

5-1

Reuseable Shipping

Removing Roll Chart from Shock Recorder

5-^ 2

5-2

5-2

5-3

Installing Roll

Chart in Shock Recorder

;

.

5-3

5-4

Computer Lift Handle, Mounted

5-8

9-1

Laboratory Replaceable Assemblies

Computer, Partially Disassembled

Page Assembly Location Guide.

Memory Handle Secured to Memory

9-1

9-2

9-2

9-3

9-3

9-4

9-6

10-1

Clock Drivers, Logic Diagram (4 Sheets)

10-4

10-2

Decoupling Capacitors (Channel 1), Logic Diagram

(4 Sheets)

.

10-8

10-3

Delay Lines,

Logic Diagram (2 Sheets)

10-12

10-4

Multiply-Divide Element, Logic Diagram (12 Sheets)

10-14

10-5

Add-Subtract Element, Logic Diagram (4

10-26

10-6

10-30

10-7

10-32

10-8

Transfer Register Bits 10 — TRS and Control,


Memory Buffer Control and Parity Counter,

Logic Diagram (2 Sheets).

Operation Code Register, Logic Diagram (4

10-34

10-9

Timing Gate Generator,

Logic Diagram (2

•.'

.

.

10-38

10-10

Phase Generator, Logic Diagram (2 Sheets)

10-40

10-11

10-42

10-12

Memory Module Registers, Logic Diagram (2 Sheets)

HOP Constant Serializer and Memory Read Latches,

Logic Diagram (2

Memory Timing, Logic Diagram (4

10-44

10-13

10-46

10-14

Memory Error Detector,


10-50

10-15

Transfer Register Bits'1 - 9, Logic Diagram (4Sheets)

10-58

10-16

Address Register and Memory Address Decoder,


Memory Sector Registers, Logic Diagram (2 Sheets)

10-62

10-17

10-66

10-18

Hi-Y Memory Address Decoder, Logic Diagram

(2 Sheets)

10-68


_i_i_i

Volume II

LIST OF ILLUSTRATIONS (Cont)

Figure

Title

Page

10-19 Decoupling Capacitors (Channel 4), Logic Diagram (4 Sheets)

10-70

10-20

Operation Code Voters, Logic Diagram (4 Sheets)

10-74

10-21

Timing Gate and Operation Code Voters,

Logic

Diagram (4 Sheets)

10-78

10-22

Timing and Add-Subtract Voters, Logic Diagram

(4 Sheets)

10-82

10-23

Timing Voters, Logic Diagram (4 Sheets)

10-86

10-24

Timing and Multiply-Divide Voters, Logic Diagram

(4 Sheets)

10-90

10-25

Oscillator and Buffer, Logic Diagram (2 Sheets)

10-94

10-26

Clock Generator Timing Logic, Logic Diagram

(4 Sheets)

10-96

10-27

Timing and Multiply-Divide Voters, Logic Diagram

(4 Sheets)

10-100

10-28

Multiply-Divide Voters, Logic Diagram (4 Sheets)

10-104

10-29

Decoupling Capacitors (Channel 5), Logic Diagram

(4 Sheets)

10-108

10-30 Memory

Timing Voters,


10-112

10-31 Memory Address Decoder Voters, Logic Diagram

(8 Sheets)

10-120

10-32

Memory Buffer Registers, Logic Diagram (12 Sheets)

10-128

10-33

Address Register and Memory Module Register

Voters,


10-140

10-34 . Transfer Register and Memory Module Register

Voters,


10-144

10-35

Transfer Register Voters,


10-148

10-36

Memory Clock Driver and TCV, Logic Diagram

(2 Sheets)

10-154

10-37 Memory Sense Amplifiers, Logic Diagram (2 Sheets)

10-156

10-38 Memory Inhibit Drivers, Logic Diagram (2 Sheets) _; 10-158

10-39

Memory Y-Address Drivers, Logic Diagram

(4 Sheets)

10-160

10-40

Memory Hi-X Address Drivers, Logic Diagram

(4 Sheets)

10-164

10-41

Memory Lo-X Address Drivers, Logic Diagram '

(2 Sheets)

10-168

10-42 X Memory Address

Diode Matrix, Schematic Diagram

(2 Sheets)

10-170

10-43 Y Memory Address

Diode Matrix,

Schematic Diagram

(2 Sheets)

10-172

10-44

Memory Input-Output Panel, Schematic Diagram

(2 Sheets)

10-174

10-45

Memory Distribution Panel, Schematic Diagram

(4 Sheets)

10-176

10-46

Signal Origin List (8 Sheets)

10-180

IV

LIST OF ILLUSTRATIONS (Cont)

Volume H

Figure

Title

Page

10-47

Interconnection Al

Back Panel, List for

LVDC

10-188

10-48

Interconnection A4 Back Panel,

List for

LVDC

10-189

10-49

Interconnection A5 Back

Panel,

List for

LVDC

10-190

10-50

Computer, Rear View

10-191

10-51

Terminal Block Pin Identification, Channels 1, 4, and

10-192

v/vi

SECTION III INTERFACE AND ADJUSTMENTS

3-1.

3-2

flow relative to the computer. Figure 3-2 lists the computer interface signal names and functions alphabetically by connector number. Figure 3-3 is a functional block diagram which shows the interconnection of groups of similar signals between the computer and the data adapter Figure 3-4 shows the interconnection of groups of similar signals between the computer and the LVDC-ME. Figure 3-5 shows the interconnection of

INTERFACE

Figure 3-1 shows the connector interface by function and the direction of signal

groups of similar signals between the computer and the ATOM.

NOTE

All the channel reference designations (Al through A3) have been left off the functional signal names in all diagrams in this section.

3-3.

3-4.

ADJUSTMENTS

No adjustments are made on the computer.

Misc.

Timing

LTE (only)

Module Switching Power

-OJ4

-OJ3

HOJ2

-»OJ1

LVDC

Figure 3-1.

Computer Connectors By Signal Function

J80-

J7o«-

Address Reg & TRS

• Memory Power

J604- Logic Power

J5o^- External Control

• Error Data

3-1

NAME

.*A1V4M1

*A2V4M1

*A3V4M1

*A1V4M2

*A2V4M2

*A3V4M2

*A1V4M3

*A2V4M3

*A3V4M3

*A1V4M4

*A3V4M4

*A1V4M5

*A2V4M5

*A3V4M5

*A1V4M6

*A2V4M6

*A3V4M6

*A1V4M7

*A2V4M7

*A3V4M7

*A1V5M1

*A2V5M1

*A3V5M1

*A1V5M2

*A2V5M2

*A3V5M2

*A1V5M3

*A2V5M3

*A3V5M3

*A1V5M4

*A2V5M4

*A3V5M4

*A1V5M5

*A2V5M5

*A3V5M5

*A1V5M6

*A2V5M6

*A3V5M6

*A1V5M7

*A2V5M7

*A3V5M7

INTRLK

INTRLK

SR01

SR02

SR03

SR04

SR05

SR06

SPARE

SPARE

SPARE

SPARE

SPARE

CONNECTOR PIN

Jl

Jl Jl

Ji ^Jⁱ Ji Ji Ji

Ji ^Jⁱ Ji Ji

.Ji _J_i ^Jⁱ Ji Ji Ji

Ji

^Jⁱ Ji

Ji Ji Ji ^Jⁱ Ji Ji Ji Ji Ji

^Jⁱ Ji Ji ^Jⁱ Ji Ji Ji Ji Ji ^Jⁱ Ji Ji Ji

^Jⁱ Ji Ji ^Jⁱ Ji ^Jⁱ Ji ^Jⁱ Ji ^Jⁱ Ji Ji

.

HH

J

FF

BB

nE

nw

AA

nF

nl

CC

0G

EE

nQ

no

nv

GG

K

nu

ny

DY

DD

Y

nT

np

nR

G

V

c

nC

W

H

H

A

nS

nA

ON

D

F

T

Z

nB

u

N

P

E

M

X

nM

nx

nZ

R

S

BH

nj

n<

FUNCTION

CHANNEL 1. 6 VDC» MODULE 1 SWITCHING

CHANNEL 2» 6 VDC» MODULE 1 SWITCHING

CHANNEL 3»

CHANNEL 1> 6 VDC» MODULE 2 SWITCHING

CHANNEL

6 VDC » MODULE 1 SWITCHING

2, 6 VDC. MODULE 2 SWITCHING


3 SWITCHING


3 SWITCHING

CHANNEL

CHANNEL 2/6 VDC. MODULE 4 SWITCHING CHANNEL 3> 6 VDC, MODULE 4 SWITCHING

CHANNEL 1> 6 VDC» MODULE 5 SWITCHING CHANNEL 2. 6 VDC» MODULE 5 SWITCHING CHANNEL 3. 6 VDC, MODULE 5 SWITCHING

CHANNEL 1, 6 VDC» MODULE 6 ': SWITCHING CHANNEL 2» 6 VDC» MODULE 6 SWITCHING

VDC » MODULE 6' SWITCHING

CHANNEL 1» 6 VDC» MODULE 7 SWITCHING

CHANNEL 2> 6 VDC, MODULE 7 SWITCHING

CHANNEL 3» 6 VDC, MODULE 7 SWITCHING

CHANNEL

CHANNEL

CHANNEL

1>

6 VDC » MODULE

VDC » MODULE VDC f MODULE

3» 6

1» 6

4 SWITCHING

3» 6

CHANNEL

CHANNEL 2, 12 VDC, MODULE 1 SWITCHING

CHANNEL 3,

CHANNEL 1, 12 VDC, MODULE 2 SWITCHING

CHANNEL 2, 12 VDC, MODULE 2 SWITCHING CHANNEL 3, 12 VDC, MODULE 2 SWITCHING

CHANNEL

CHANNEL 2, 12 VDC, MODULE 3 SWITCHING CHANNEL 3, 12 VDC, MODULE 3 SWITCHING CHANNEL 1, 12 VDC, MODULE 4 SWITCHING

CHANNEL 2, 12 VDC, MODULE 4 SWITCHING CHANNEL 3, 12 VDC, MODULE 4 SWITCHING

CHANNEL 1, 12 VDC, MODULE 5 SWITCHING CHANNEL 2, 12 VDC, MODULE 5 SWITCHING CHANNEL 3, 12 VDC, MODULE 5 SWITCHING CHANNEL 1, 12 VDC, MODULE 6 SWITCHING CHANNEL 2, 12 VDC, MODULE 6 SWITCHING CHANNEL 3, 12 VDC, MODULE 6 SWITCHING CHANNEL 1, 12 VDC, MODULE 7 SWITCHING CHANNEL 2, 12 VDC, MODULE 7 SWITCHING CHANNEL 3, 12 VDC, MODULE 7 SWITCHING

LTE

LTE INTERLOCK FOR

SIGNAL RETURN, LINE 01 A2V5I SIGNAL RETURN, LINE 02 A2V4I SIGNAL RETURN, LINE 03 A1V5! SIGNAL RETURN, LINE 04 A3V5I SIGNAL RETURN, LINE 05 A3V4I SIGNAL RETURN, LINE 06 A1V4I

1, 12 VDC, MODULE

1 SWITCHING

12 VDC, MODULE 1 SWITCHING

12 VDC, MODULE 3 SWITCHING

1,

INTERLOCK FOR LTE USE 01

LTE USE 01

NOTE ^DENOTES INPUTS TO COMPUTER* niNDICATES LOWER CASE LETTER

Figure 3-2. Computer Interface Signals (Sheet 1 of 8)

3-2

NAME

*A1CSTN

*A2CSTN

*A3CSTN .

*A1DIN

*A2DIN

*A3DIN

A1HOPC1V

A2HOPC1V

A3HOPC1V

*A1MCL

#A2MCL

*A1MCN

*A2MCN

A1MD7V

A2MD7V

A3MD7V

A1MR1V

A2MR1V

A3MR1V

A10P1V

A20P1V

A30P1V

A10P2V

A20P2V

A30P2V

A10P3V

A20P3V

A30P3V

A10P4

A20P4V

A30P4V

A1PROV

A2PROV

A3PROV

*A1TER

*A2TER

*A3TER

BRA14P

BRB14P

INTRLK

INTRLK

SIGRET

SIGRET

SIGRET

SIGRET

SIGRET

SPARE

SPARE

SPARE

SPARE

SPARE.

SPARE

SPARE

SPARE

SPARE

CONNECTOR PIN

FUNCTION

J2

nK

CHANNEL 1, SINGLE STEP CONTROL

J2

E

CHANNEL 2» SINGLE STEP CONTROL

J2

K

CHANNEL 3» SINGLE STEP CONTROL

J2

DM

CHANNEL 1» MEMORY LOAD

J2

DA

CHANNEL 2» MEMORY LOAD

J2

L

CHANNEL 3. MEMORY LOAD

J2

R

CHANNEL 1. HOP CONSTANT

J2

HH

CHANNEL 2» HOP CONSTANT

J2

CHANNEL 3» HOP CONSTANT

J2

nC

CHANNEL 1» MARGINAL CHECK LATE» STROBE CONTROL

J2

D

CHANNEL 2» MARGINAL CHECK STROBE CONTROL

J2

U

CHANNEL 1, MARGINAL CHECK STROBE CONTROL

J2

CC

CHANNEL 2» MARGINAL CHECK STROBE CONTROL LATCH 7

J2

an

CHANNEL 1. MULTIPLICAND DIVISOR REGISTER

J2

N

CHANNEL 2. MULTIPLICAND DIVISOR REGISTER LATCH 7

J2

M

CHANNEL 3, MULTIPLICAND DIVISOR REGISTER LATCH 7

J2

F

CHANNEL 1» MULTIPLIER REGISTER LATCH

J2

CHANNEL 2. MULTIPLIER REGISTER LATCH

J2

nu

CHANNEL 3» MULTIPLIER REGISTER LATCH

J2

J

CHANNEL 1. OPERATION CODE REGISTER LATCH

J2

H

CHANNEL 2. OPERATION CODE REGISTER

OPERATION CODE REGISTER LATCH

J2

G

CHANNEL 3, OPERATION CODE REGISTER


J2

B

CHANNEL 1» OPERATION CODE REGISTER


J2

C

CHANNEL 2» OPERATION CODE REGISTER


J2

A

CHANNEL 3, OPERATION CODE REGISTER


J2

np

CHANNEL 1> OPERATION CODE REGISTER LATCH

J2

Z

CHANNEL 2» OPERATION CODE REGISTER LATCH

J2

nx


J2

S


J2

ns


J2

DG


J2

nD

CHANNEL 1. PRODUCT REMAINDER LATCH

J2

av

CHANNEL 2» PRODUCT REMAINDER LATCH.

J2

EE

CHANNEL 3. PRODUCT REMAINDER LATCH

J2

W

CHANNEL 1, RESET MEMORY tRROR INDICATION

J2

CHANNEL 2. RESET MEMORY ERROR INDICATION

J2

aw

CHANNEL

3.

RESETS MEMORY ERROR INDI CAT ION

J2

DD

BUFFER REGISTER A, PARITY BIT

J2

nB

BUFFER REGISTER B PARITY SIT

J2

nY

LTE INTERLOCK FOR LTE USE ONLY

J2

az


J2

P

SIGNAL RETURN. DC REGULATED

J2

X


J2

Y


J2

BB

SIGNAL RETURN. REGULATED DC

J2

FF

SIGNAL

RETURN. REGULATED i;C

J2

T

J2

V

J2

aF

J2

â^j n(\|

J2

J2

no

J2

PR

J2

AA

J2

GG

NOTE *DENOTES INPUTS TO COMPUTER. nlNDICATES LOWER CASE LETTER

Figure 3-2.

Computer Interface Signals (Sheet 2)

3-3

NAME

CONNECTOR PIN

_F_U_N_C_T_I_O_N

A1G5VN

A2.G5VN

A3G5VN

A1PBVN

A2PBVN

A3PBVN

A1WDA

A2WDA

A3WDA

A1XDA

A2XDA

A3XDA

A1YDA

A2YDA

A3YDA

A1ZDA

A2ZDA

A3ZDA

B01N

B02N

B03N

INTRLK

INTRLK

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

SR07

SR08

SR09

SR1.0

SR11

SR12

SR13

SR14- J3

SRI5

SRI 6

SR17

SR18

SR19

SR20

SR21

SR22

SR23

SR24

SR25

SR26

SR27

SPARE

SPARE

SPARE

SPARE

SPARE

SPARE

SPARE

SPARE

SPARE

SPARE

SPARE

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3.

J3

J3

J3

J3

J3

J-3

J3

J3

J3

J3

J3

J3

J3

J3

J3

J3

.

•

.

C

CHANNEL 1, TIMING SYNC FOR DATA ADAPTER

n'Y


np

CHANNEL 3, TIMING SYNC FOR DATA ADAPTER,

ns


nA


R


nB


K


N


F


J


HH


H


nH


QK

CHANNEL 3, TIMING SYNC FOR DATA ADAPTER.

G


M


nj

CHANNEL

3». TIMING

SYNC FOR DATA ADAPTER

DD

2.048

MC TIMING

nF

2.048

MC TIMING

a\f

2.048

MC TIMING

W


X


E

.

SIGNAL RETURN

LINE 07-A1XDA

L

SIGNAL RETURN

LINE 08-A2WUA

P

SIGNAL RETURN. LINE 09-A3PBVN .

S

SIGNAL RETURN. LINE 10-A3YDA

z

SIGNAL RETURN, LINE 11-A2PBVN

ⁿ C

. SIGNAL RETURN, LINE 12-A1ZOA

Q^

. SIGNAL

R.ETURN, LINE 13-A1YDA

QE

SIGNAL RETURN, LINE 14-A2XOA .

nG

SIGNAL RETURN, LINE 15-A2ZDA

nl

SIGNAL RETURN, LINE 16-A3WDA

nN

SIGNAL RETURN, LINE 17-A3G5VN

nR

SIGNAL RETURN, LINE 18-A1G5N

nT

SIGNAL RETURN, LINE 19-A1WDA

nu

SIGNAL RETURN, LINE 20-B01N

nw .

SIGNAL RETURN, LINE 21-B02N

nx

SIGNAL RETURN, LINE 22-A2YJA

nz

SIGNAL RETURN, LINE 23-A3ZDA

CC

SIGNAL

RETURN/LIN E 24-A3XOA

EE

SIGNAL RETURN, LINE 25-BC3N

FF

SIGNAL RETURN, LIKE 26-A3XDA

GG

SIGNAL RETURN, LINE 27-A2G5VN

A

B

D

T

U

V

Y

nM

nQ

AA

BB

NOTE #DENOTES INPUTS TO COMPUTER, nlNDICATES LOWER CASE LETTER

Figure 3-2. Computer Interface Signals (Sheet 3)

3-4

NAME

CONNECTOR

PIN

FUNCTION,

A1AI3V

J4

nM

CHANNEL 1» ACCUMULATOR THIRD DELAY LATCH

A2AI3V

J4

nz

CHANNEL 2. ACCUMULATOR THIRD DELAY LATCH

A3AI3V

J4

nQ

CHANNEL 3» ACCUMULATOR THIRD DELAY LATCH

A1PIOV

J4

GG

CHANNEL 1, PROCESS INPUT-OUTPUT

A2PIOV

J4

U

CHANNEL 2» PROCESS INPUT-OUTPUT

A3PIOV

J4

u

CHANNEL 3» PROCESS INPUT-OUTPUT

EP01

J4

w

ERROR SIGNAL 01

EP02

J4

nR

ERROR

SIGNAL 02

.

.

EP03

J4

T

ERROR SIGNAL 03

EP04

J4

AA

ERROR SIGNAL 04

EP06

J4

V

ERROR

SIGNAL 06

'

•

.

EP07

J4

nN

ERROR SIGNAL 07

INTRLK

J4

nG


INTRLK

J4

nH


SR28

J4

A

SIGNAL

RETURN*

LINE

28-EP06

SR29

J4

B

SIGNAL RETURN*

LINE

29-A1PIOV.A3PIOV

SR30

J4

P

SIGNAL RETURN*

LINE

30-A2AI.3

SR31

J4

S

SIGNAL

RETURN. LINE

31-EP03

SR32

J4

X

SIGNAL RETURN. LINE

32-EP01

SR33

J4

z

SIGNAL RETURN. LINE

33-THEKM

THERM 2,

SR34

J4

np

SIGNAL RETURN. LINE

34-EPC7

SR35

J4

as

SIGNAL RETURN. LINE

35-EPC2

SR36

J4

BB

SIGNAL

RETURN. LINE. 36-EP04

SR37

J4

CC

SIGNAL RETURN. LINE

37-A3AI3V

SR38

J4

HH

SIGNAL

RETURN, LINE

38-A1AI3V

THERM1

J4

Y

THERMISTOR

1 LEAD 1

THERM2

J4

D

THERMISTOR

1 LEAD 2

SPARE

J4

E

SPARE

J4

F

SPARE

J4

G

SPARE

J4

H

SPARE

J4

J

SPARE

J4

K

SPARE

J4

L

SPARE

J4

M

SPARE

J4

N

SPARE

J4

R

SPARE

J4

aA

SPARE

J4

nB

SPARE

J4

aC

SPARE

J4

nD

SPARE

J4

a£

SPARE

J4

nF

SPARE

J4

nl

SPARE

J4

nj

SPARE

J4

nK

SPARE

J4

nT

SPARE

J4

PU

SPARE

J4

av

SPARE

J4

nw

SPARE

J4

nx

SPARE

J4

QY

SPARE

J4

DD

SPARE

J4

EE

SPARE

J4

FF

NOTE *DENOTES INPUTS TO COMPUTER, nINDICATES LOWER CASE LETTER

Figure 3-2.


3-5

$NAME. CONNECTO R \ PIN FUNCTION . A1EAMV J5 • np CHANNEL •!» EVEN' MEMORY,$

NAME.

CONNECTO R

\ PIN

FUNCTION .

A1EAMV

J5

•

np

CHANNEL •!» EVEN' MEMORY, ERROR

:

'

„

A2EAMV

J5 :

nz

CHANNEL 2

EVEN

MEMORY ERROR

-

.;,

A3EAMV

J5

AA

CHANNEL 3»

EVEN MEMORY ERROR .

^

•

A1EBMV

J5

U

CHANNEL

.

A2EBMV

J5

nj

CHANNEL

.

.

.

.

A3EBMV

J5

'

n<

CHANNEL

1 » OD D MEMORY ERROR

2» ODD•MEMORY .ERROR

3» ODD MEMORY. ERROR

-

••

,.

*A1DATAV

J5

R

*A2DATAV

J5

GG

*A3DATAV

J5

nB

CHANNEL 1, COMPUTER DATA INPUT

CHANNEL 2» COMPUTER DATA INPUT

CHANNEL 3» COMPUTER DATA INPUT

*A1HALTV

J5

P

CHANNEL 1> HALT SIGNAL

-.'

.

,

*A2HALTV

J5

A

CHANNEL 2» HALT SIGNAL-

*A3HALTV

J5

G

CHANNEL 3» HALT SIGNAL

"

.

•.

*A1INTCV

J5

N

*A2INTCV

J5

.

FF

*A3INTCV

J5

nC

CHANNEL 1» INTERRUPT COMPUTER

CHANNEL 2» INTERRUPT COMPUTER

-CHANNEL 3» INTERRUPT COMPUTER-

A1TLCV

J5

T

CHANNEL 1» SIMULTANEOUS MEMORY ERROR

A2TLCV

J5

S

A3TLCV

J5

al



EP05

J5

H

ERROR SIGNAL 05

;

EP08

J5

Z

EP09

J5

EN

ERROR SIGNAL 08

ERROR SIGNAL 09

EP10

J5

V

ERROR SIGNAL 1C

EP11

J5

E

.

.

EP12

J5

DQ

;.

EP13

J5

B5

ERROR SIGNAL 11

ERROR.SIGNAL 12

ERROR SIGNAL 13

INTRLK

J5

'K

LTE

INTERLOCK FOR LTfc USE ONLY

.

,

INTRLK

J5

L


SR39

J5

6

SIGNAL RETURN. LINE 39-EP10

SR40

J5

C

SR41

J5

.w

SR42

J5

QA

SR43

J5

a'D

SR44

J5

nH

SIGNAL RETURN* LINE 40-.THERM3»THERM4

SIGNAL RETURN. LINE 41-EP09

SIGNAL RETURN* LINE 42-EP11

SIGNAL RETURN, LINE 43-EPG5 .

SIGNAL RETURN 44-1 NTC» HALT, TLC, EAK AND t.BM

SR45

J5

ns

SR46

J5

nx

SIGNAL RETURN LINE 45-EP08

SIGNAL RETURN, LINE 46-DATAV FOR CHANNELS. 1, 2,

cc

SR47

J5

SIGNAL

RETURN, LINE 47-EP13 .

:

SR90

J5

nR

SIGNAL RETURN LINE 90-EP12

THERM4

J5

D

THERMISTOR

2 LEAD 2

.

THERMS

J5

Y

THERMISTOR 2 LEAD

1

'

SPARE

J5

F

SPARE

J5

J

SPARE

J5

M

SPARE

J5

X

SPARE

J5

aE

SPARE

J5

nF

SPARE

J5

nG

SPARE

J5

aw

SPARE

J5

nT

SPARE

J5

nu

SPARE

J5

nv

SPARE

J5

nw

SPARE

J5

ay

SPARE

J5

DD

SPARE

J5

EE

SPARE

J5

HH

NOTE ^DENOTES INPUTS TO COMPUTER, nlNDICATES LOWER CASE LETTER


3-6

NAME

CONNECTOR

i

PIN

FUNCTION'

INTRLK

J6

K


INTRLK

J6

L


SR48

J6

H

SIGNAL RETURN, LINE

48-V1

05

SR49

J6

N

SIGNAL RETURN, LINE

49-V1

21

SR50

J6

P

SIGNAL RETURN, LINE

50-V1

15

SR51

J6

R

SIGNAL RETURN, LINE

51-V1

07

SR52

J6

nC

SIGNAL RETURN,

LINE

52-V1

04

SR53

J6

nD

SIGNAL RETURN, LINE.

53-V1

13

SR54

J6

n£

SIGNAL RETURN, LINE

54-V1

14

SR55

J6

aF

SIGNAL RETURN, LINE

55-V1

20

SR56

J6

QG

SIGNAL RETURN,

LINE

56-V1

24

•

SR57

J6

J

SIGNAL RETURN, LINE

57-V1

06

SR58

J6

nH

SIGNAL RETURN,

LINE

58-V1

23

SR59

J6

Ql

SIGNAL RETURN, LINE-

59-V1

22'

SR60

J6

nj

SIGNAL RETURN,

LINE

60-V1

16

SR61

J6

nK

SIGNAL RETURN, LINE

61-V1

62-V1

Oo" '

SR62

J6

nM

SIGNAL RETURN, LINE

01

SR63

J6

DU

SIGNAL RETURN,

LINE

63-V1

12

SR64

J6

nv

SIGNAL RETURN, LINE

64-V1

65-V1

66-V1

67-V1

19.

SR65

J6

aw

SIGNAL RETURN, LINE

18

SR66

J6

ax

SIGNAL RETURN, LINE

17

SR67

J6

DY

SIGNAL RETURN, LINE

09

SR68

J6

EE

SIGNAL RETURN, LINE

68-V1

17

SR69

J6

FF

SIGNAL RETURN, LINE

69-V1

10

SR70

J6

GG

SIGNAL RETURN, LINE

70-V1

02.

SR71

J6

HH

' SIGNAL

RETURN,

LINE

71-V1

03

*V1 01

J6

A

6

VDC,

LINE 1

*V1 02

J6

B

6

VDC,

LINE 2

*V1 03

J6

C

6

VDC,

LINE 3

*V1 04

J6

D

6VDC,

LINE 4

*V1 05

J6

E

6VDC,

LINE 5

*V1 06

J6

F

6 VDC,

LINE 6

*V1 07

J6

T

6VDC,

LINE 07

*V1 08

J6

U

6VDC,

LINE 08

*V1 09

J6

V

6VDC,

LINE 09

*V1 10

J6

w

6VDC,

LINE 10

*V1 11

J6

X

6VDC,

LINE 11

*V1 12

J6

Y

6VDC,

LINE 12

*V1 13

J6

Z

6

VDC,

LINE 13

*V1 14

J6

nA

6

VDC,

LINE 14

*V1 15

J6

S

6

VDC,

LINE 15

*V1 16

J6

aN

6

VDC,

LINE 16

*V1 17

J6

ap

6

VDC,

LINE 17

*V1 18

J6

no

6VDC,

LINE 18

*V1 19

J6

aR

6

VDC,

LINE 19

*V1 20

J6

nS

6

VDC,

LINE 20

*V1 21

J6

DZ

6

VDC,

LINE 21

*V1 22

J6

AA

6

VDC,

LINE 22

*V1 23

J6

BB

6

VDC,

LINE 2?

*V1 24

J6

CC

6

VOC,

LINE 24

SPARE

J6

G

SPARE

J6

M

SPARE

J6

aB

SPARE

J6

SPARE

J6

DO

NOTE

*OENOTES

INPUTS

TO COMPUTER,

nINDICATt S

LOWER

CASE

LETTER

Figure 3-2.


3-7

NAME

*ETI-1

*ETI-2

INTRLK

INTRLK

SRMEMOl

SRMEM02

SRMEM03

SRMEM04

SRMEM05

SRMEM06

SRMEM07

SRMEM08

SRMEM09

SRMEM10

SRMEM11

SRMEM12

SR73

SR75

SR76

SR77

SR78

SR79

SR80

SR82

SR83

SR85

*V1MEM1

*V1MEM2

*V1MEM3

*V20AM1

*V20BM2

*V20BM1

*V20AM2

*V20 01

*V20 02

*V3MEM1

»V3MEM2

*V3 01

*V3 02

*V3 03

*V3 04

*V3 05

*V3 06

*V3 07

*V3 08

*V3 09

*V3 10

*V5MEM1

#V5MEM2

*V5 01

*V5 02

SPARE

SPARE

SPARE

SPARE

CONNECTOR PIN

FUNCTION

J7

E

ELAPSED TIME INDICATOR 1

J7

F

ELAPSED TIME INDICATOR 2

J7

GG

LTE. INTERLOCK FOR LTt USE ONLY

J7

HH


J7

^:

A

MEMORY SIGNAL RETURN*. LINc 01-V20bMl

J7

B

MEMORY SIGNAL RETURN. LINE 02-V3MEM1

J7

.

C


J7

D

MEMORY SIGNAL RETURN. LINE 04-V20AM1

J7

U

MEMORY SIGNAL RETURN. LINE 05-V20BM2

J7

V

MEMORY SIGNAL RETURN. LINE .06-V3MEM2

J7

Y

MEMORY SIGNAL RETURN, LINE 07-V5MEM1

J7

aB


J7

G

MEMORY SIGNAL RETURN, LINE 09-V20AM2

J7

no

MEMORY SIGNAL RETURN LINE 10-V1MEM3

J7

AA

MEMORY SIGNAL RETURN, LINE 11-V1MEM2

J7

.H

J7

nD

SIGNAL RETURN. LINE 73-V5 02

J7

J

SIGNAL, RETURN. LINE

75-V5 01

J7

M


J7

nG


J7

nl

SIGNAL RETURN. LINE 78-V3 01. V3 02

J7

.

nj

SIGNAL RETURN. LINE 79-V3 03, V3 04

J7.

DM

SIGNAL

RETURN. LINE SO-V3 05, V3 08

J7

nx

.SIGNAL RETURN. LINE 82-V3 09.

J7

nZ

SIGNAL

RETURN. LINE

. 83-V3 07. V3 10

J7

"

EE

SIGNAL RETURN, LINE 85-V3 06

J7

nR

6

VDC, LINE 01, MEMORY

J7

BB

6


J7

CC

6

VDC, LINE

03,

MEMORY

J7

nA

20

VDC, LINE 1, EVEN MEMORY

J7

nN

20

VDC, LINE 02, ODD MEMORY

J7

W

20

VDC LINE 01 ODD MEMORY

J7

nT

20

VDC, LINE 2, EVEN MEMORY

J7

L

20

VDC. LINE 01

J7

nF

20

VDC. LINE 02.

J7

X

-3 VDC, LINE 01 MEMORY

J7

np

-3 VDC. LINE 02, MEMORY

J7

nH

-3

VDC, LINE 01

J7

N

-3

VDC. LINE 02

J7

P

-3

VDC, LINE 03

J7

R

-3

VDC, LINE 04

J7

S

-3

VDC, LINE 05

J7

nv

-3

VDC, LINE 06

J7

nY

-3

VDC. LINE 07

J7

nH

-3

VDC, LINE 08

J7

aw

-3

VDC, LINE 09

J7

FF

-3

VDC, LINE 10

J7

Z

12 -VDC, LINE 01, MEMORY

J7

ns

12


J7

K

12

VDC, LINE 01

J7

n£

12

VDC, LINE 02

J7

T

J7

aC

J7

DU

J7

DD

NOTE *DENOTES INPUTS TO COMPUTER. nINDICATtS LOWER CASt LETTER


3-8

NAME

CONNECTOR PIN

_F_U_N_C_T_I_O_N

A1A1V

J8

T

CHANNEL 1, OPERAND ADDRESS 3IT 1

A2A1V

J8

nM

CHANNEL 2» OPERAND ADDRESS BIT 1

A3A1V

J8

np

CHANNEL 3. OPERAND ADDRESS BIT 1

A1A2V

J8

DD


A2A2V

J8

BB


A3A2V

J8

AA


A1A3V

J8

nN

CHANNEL 1» OPERAND ADDRESS oIT 3

A2A3V

J8

CC


A3A3V

J8

nQ

CHANNEL 3» OPERAND ADDRESS oIT 3

A1A4V

J8

FF


A2A4V

J8

GG


A3A4V

J8

ol


A1A5V

J8

R

CHANNEL .1* OPERAND

ADDRESS BIT 5

A2A5V

J8

aw


A3A5V

J8

nj


A1A6V

J8

nv


A2A6V

J8

QY

CHANNEL 2» OPERAND ADDRESS 3IT 6

A3A6V

J8

nK


A1A7V

J8

A

CHANNEL 1, OPERAND ADDRESS BIT 7

A2A7V

J8

X


A3A7V

J8

nR


A1A8V

J8

EE

CHANNEL 1, OPERAND ADDRESS BIT 8

A2A8V

J8

HH


A3A8V

J8

S


A1A9V

J8

Y


A2A9V

J8

C


A3A9V

J8

W


A1TRSV

J8

F

CHANNEL 1. TRANSFER REGISTER OUTPUT

A2TRSV

J8

E

CHANNEL 2. TRANSFER REGISTER OUTPUT

A3TRSV

J8

D

CHANNEL 3» TRANSFER REGISTER OUTPUT

INTRLK

J8

K


INTRLK

J8

L

LTE INTERLOCK FOR LTE USE ONLY .

SR86

J8

V

SIGNAL RETURN* LINE 86 OPERAND ADDRESS BITS Al,A2» A3»A7, AND A9 FOR CHANNELS 1.2.AND3

SR87

J8

z

SIGNAL RETURN. LINE 87 TRSV» CHANNELS 1»2» AND 3

SR88

J8

nl

SIGNAL RETURN. LINE 88 OPERAND ADDRESS BITS A4.A5»

A6. AND A8 FOR CHANNELS 1

2.

AND 3

SPARE

J8

B

SPARE

J8

G

SPARE

J8

H

SPARE

J8

J

SPARE

J8

M

SPARE

J8

N

SPARE

J8

P

SPARE

J8

u'

SPARE

J8

aA

SPARE

J8

nB

SPARE

J8

nC

SPARE

J8

nD

SPARE

J8

nE

SPARE

J8

nF

SPARE

J8

nG

SPARE

J8

nH

SPARE

J8

as

SPARE

J8

nT

SPARE

J8

nu

SPARE

J8

nx

NOTE *DENOTES INPUTS TO COMPUTER. ÎNDICATES LOWER CASE LETTER


3-9

DATA ADAPTER

COMPUTER

i

JN

B

Power

1

Program Prog Control Element

vv

I

•

1

1

J20

v v |

Power

1

Rur

J15

y.

B

HALTV

»'|

« J ° 5

i

* Lot ch

i-

J10 vv

\

Power

H

+20

1

'

J21 w

\

TB«v

„ JOS

Computer

^-»-

Power

'ower

Relay

+6

Data

Supply

Sequencing

+12

Assy

AI3V

„

J04

r

Selector

-3

J ° 9 »

Data Control Element

1

s

Addres

1 TRS

i

Re 9' ste

r Bits

~ Lotch

C1RD

— Al Thr

A9

C4RD

C4RDN

CCSL

DOMS

Interrupt

Accel

Tags

1 Arithmetic

i

Real Time

Processor

Processor

Element

*-

AI3

Latch

EXTERNAL

'

DATAV

« J0 5

EQUIPMENT

A1V thru A9V

tJOS

PIOV

, J04

INTCV

„ JOS

JlSv v

Timing Element

I

60(1-2-3) N

,

JOS

G5VN

. JOS

J05

(W-X-Y-Z) DA

J03

PBVN

I

Memory Control

|

Element

I

I

I

TLCV

,J05

JlSv v

I

I

Memory

Error

Select

EAMV

JOS

Monitor

Registers

Error

Monitor

EBMV

J05

Figure 3-3. Computer - Data Adapter Intercon- nection Block Diagram

₃_-₁₀


COMPUTER

Timing Element

Timing

Gate

Generator

Phase

Clock

Generator

Generator

1

1

.

Module Switching Voltages* Memory & Logic Voltages *

+6 VDC to Logic*

! ' Muitiply-Divide Element

JOKvl

" \

^J⁰⁶ V,1

ff 1

J07vv 1

1

Power

Power

Power

„

J1 9

jj J0 7 V.V

J06

xx

\v

ff

J14

Power

Sequencing

&

Relay Assy

j

TO Error Checking

Figure 3-4. Computer and LVDC-ME Intercon- nection Block Diagram

3-11

r

r

L ^L

COMPUTER

Program Control Element

Operation

Code

Register

DATA ADAPTER

^"Î

Note 1

Data Control Element

J' ⁶ «

J03 _«

J03 _< ₍

AI3V

^: PBAVN

W6

TRSV

1

^ _x J02

V> J02

» ^J ° ²

. J02

_f

Timing

Generator

»

Display

Selection

Switch

Sel Ace.

JI6

A1V thru A9V

HLTX

JI6

„

INTCV

_C_S_T

*^ «

CSTN

DIN

JU/

ss |-

HOPC1V

OP1V thru OP4V

^^r iv

iniu

v^f •* T

h» _J₀₂

w J02

;

xv

.J02

.J02

.J02

JCj 2

Instruction Module, Sector Syllable, Duplex/Simplex

Data Module, Sector,

HOP- Syllab1e,Duplex/Simpl

Figure 3-5.

Block Diagram

3-12

Computer - ATOM Interconnection

ATOM

~1

Note:

1.

See Figure 3-3 for Computer and Data Adapter Interconnections

SECTION IV

TEST EQUIPMENT AND SPECIAL TOOLS.

4-1.

TEST EQUIPMENT.

4-2.

STANDARD TEST EQUIPMENT.

4-3.

The standard test equipment recommended to maintain the computer is listed in

figure

4-1.

4-4.

SPECIAL TEST EQUIPMENT.

4-5.

The special test equipment required to maintain the computer is listed in figure

4-2.

-

'

'

.'

.

.

'

.

;

'.-•'.-•

'''•''•.-'"

•

'

'•'• •

:

4-6.

SPECIAL TOOLS.

4-7.

The special tools recommended to maintain the computer are listed in figure 4-4.

Name

Model or Type

Vendor

Differential

Voltmeter

803- B

John Fluke Mfg. Co. , Inc.

Volt- Ohm- Ammeter

630- A

Triplett Electrical Instrument Co,

Oscilloscope

585A

Tektronix, Inc.

Oscilloscope Adapter

81

Tektronix, Inc.

Oscilloscope

Plug- In Unit

M

Tektronix, Inc.

Figure 4-1.

Standard Test Equipment Table

4-1

_N_a_m_e

_B_o_o_k _C_a_r_t

Equipment Test Stand

Manufacturer's

Designation

IBM 6900039

IBM 6940100

Index No.

(Figure ₄_-₃₎

Description

Movable book case, used for . storage of prime and test equipment manuals and logic diagrams.

Supports the computer and provides cooling air during test.

Launch Vehicle

IBM 6902000 MD1

Used to test and evaluate com-

Digital Com-

puter operation.

puter-Manual

Exerciser

Test Program

IBM 6001225

Contains a program which,

Tape

when loaded into the computer memory, permits the Launch Vehicle Digital ^Computer-Manual Exerciser to check each functional part of the computer that can be exercised by a program.

Figure 4-2.

Special Test Equipment Table

4-2


Figure 4-3.

Special Test Equipment

'.-iiî-rt-'-vtr

4-3

Name

Manufacturer's

Index No.

Designation

(Figure 4-5)

Handling Dolly

IBM 658042

Lift Handles

IBM D-656101

3

Memory Handle

IBM 658044

2

Page Extractor

IBM 657922

1

Test Point

Adapter

Number to be sup- plied.

Torque Tool Kit

Number to be sup- plied.

Figure 4-4.

Special Tools Table

Description

Supports computer while being maintained.

Provide a means for handling and lifting the computer during general handling activity.

Used to disengage memory from its mating receptacle. Also recommended for general handling of memory.

Used to mechanically engage or disengage the page connector from its mating receptacle.

Use to provide access to test points on page assemblies.

Contains special torque tools required for torquing those items replaced during laboratory maintenance.

4-4


Figure 4-5.

Special Tools

4-5/4-6

SECTION V

PREPARATION FOR USE, STORAGE AND SHIPMENT

5-1.

PREPARATION FOR USE.

.

5-2.

The computer is shipped in a reuseable shipping container (part number 6019994,

figure 5-1).

corder (part number 6019637). To remove the computer from the container,

as follows:

Included in the container, although not shown in figure 5-1,

,

:

is a shock re-

J

proceed

a. Turn pressure equalizer screw (on shipping container) two turns counterclockwise.

b. Unlatch and remove container cover.

c. Remove the four mounting bolts securing the computer to the container frame.

,'•."

"

. WARNING

•••

.

:

The computer shall be lifted by at least two persons. Otherwise, a person may be injured or the computer damaged.

d. Attach the lift handles to the computer, as described in paragraph 5-8; remove the

computer from the container and place on a handling dolly or test stand.

section IV.)

(Refer to

e. Reinstall the mounting bolts for safekeeping.

f. Remove the shock recorder after removing the four socket head screws which attach it to its bracket; then replace socket head screws in bracket for safekeeping.

g.

Open the shock recorder.

gl.

Remove the spool that contains the recorded portion of chart paper (figure 5-2).

CAUTION

When removing chart paper, handle chart

paper

carefully.

Cut (do not tear) the chart

paper to detach recorded portion. The

paper is pressure sensitive,

and data may

be obliterated by rough or excessive handling.

g2.

Cut the chart paper, remove it from the spool, and replace the spool in the

recorder.


5-1

Desiccant Receptacle

Mounting Bolts (4)

Figure 5-1.

Reuseable Shipping Container

Figure 5-2.

Removing Roll Chart From Shock Recorder

5-2

Shock Recorder

Pressure

Bracket

Equalizer

Screw


NOTE

The recorder clock mechanism will operate until its spring mechanism has unwound. If the recorder is not to be used immediately, do not rethread the chart paper. Instead, tape the loose end of the chart paper to the writing plate. (See figure 5-2.) This procedure saves paper and protects the styluses which would otherwise rest on the hard surface of the plate.

g3.

Rethread the chart paper onto the takeup spool (figure 5-3), or tape the paper to

the writing plate.

g4.

Close and latch the shock recorder.

g5.

Reinstall the shock recorder (handle side up) in the shipping container.

g6.

On a blank portion of the removed section of chart paper, record the

Government Bill of Lading Number

Receiving Location and Receiving Individual's Signature

Unit Name, Part Number, and Serial Number

Container Serial Number and Recorder Serial Number

Data and Local Time recorder was opened.

(A)

TAKEUP

SUPPLY

( B )

ROLL

CHART PARTIALLY

INSTALLED

FEED DIAGRAM

₍_C )

ROLL CHART COMPLETELY INSTALLED

Figure 5-3 . Installing Roll Chart in Shock Recorder


₅_-₃

h.

Ship removed section of chart paper to:

Saturn Programs Office, Department 839

IBM Space Guidance Center

Owego, New York, 13827

'

hi.

Use a vacuum cleaner to clean the interior of container if foreign material or debris

is in the shipping container.

i. Secure cover on shipping container; then store container for reuse.

5-2A.

INSPECTION AND TEST.

5-2B.

After the computer has been unpacked, proceed as follows:

a. Examine the exterior of the computer for mechanical damage, noting any evidence

of impact or other

missing connector dust covers. If extensive abnormalities are noted, remove covers and inspect interior of the computer. (Refer to Section K for disassembly instructions.)

severe mechanical stress.

Check for loose screws and broken or

b. Remove and store connector dust covers.

c. Perform an electrical checkout of the computer. out Procedures for Saturn LVDC and LVDA.)

5-3.

PREPARATION FOR STORAGE.

(Refer to Technical Manual, Check-

5-4. The computer is stored in a reuseable shipping container (part number 6019994, figure 5-1). The computer is prepared for storage as follows:

a.

Install dust covers (part number 6036037) on the eight computer connector jacks.

al.

Unlatch and remove shipping container cover.

a2.

Use a vacuum cleaner to clean interior of container if foreign material or debris

is in the shipping container.

b.

Remove mounting bolts from computer shipping container.

bl.

Attach lift handles to computer as described in paragraph 5-8.

WARNING

The computer shall be lifted by at least two persons. Otherwise, a person may be injured or the computer damaged.

c. Place computer on container mounting frame and secure with mounting bolts. mounting bolts with a torque of 250inch-pounds.

Tighten

d. Place 17 units of desiccant in receptacle provided.

5-4


NOTE

The 17 units of desiccant are packaged in three bags. The package part number, units of desiccant per package, and the quantity of each part number used are as follows:

IBM Part Number

No. of Units

Quantity Used

6019623

8

2

6019653

1

1

e. Secure cover on shipping container.

f. Turn pressure equalizer screw fully

clockwise.

NOTE

During storage, the container humidity indicator should be checked at least once a week (more often if high humiditycondi- tions.prevail). If the "40" sector of the humidity indicator turns pink, the tainer dessicant should be replaced.

5-5.

PREPARATION FOR SHIPMENT.

5-6. The computer is shipped in a reuseable shipping container (part number 6019994, figure 5-1). Included in the container is a shock recorder (part number 6019637). The computer is prepared for shipment as follows:

a.

Install dust covers (part number 6036037) on the eight computer connector jacks,

al.

Unlatch and remove container cover.

b.

Remove mounting bolts

from computer shipping container.

WARNING

The computer shall be lifted by at least two persons. Otherwise, a person may be injured or the equipment damaged.

c. Place computer on container mounting frame and secure with mounting bolts. mounting bolts with a torque of 250 inch-pounds.

Tighten


5-5

CAUTION

Verify that shock recorder styluses are marked "100g". Otherwise, recorder will not be capable of recording excessive shock with accuracy.

cl. Remove the shock recorder after removing the four socket head screws which

attach the recorder to its bracket. keeping.

Replace socket head screws in bracket for safe-

c2.

Open the shock recorder and check for damage.

d.

Thread roll chart onto takeup spool of shock recorder.

(See figure 5-3.)

dl.

Close cover and strike recorder sharply against floor.

Open cover and verify that

all three styluses have made a discernable impression on the chart paper.

NOTE

A

full roll of chart paper is long enough

to

record shock for a period of 60 half

days (30 days). The numbers on the left-

hand margin indicate the number of half

days remaining on the roll.

is capable of running for eight days (16 half

days). Verify that the number on the left- hand margin is 16 or greater at the point where recording starts. Reorder chart paper from the following address: -

The mechanism

Electrical Standards, Dept. 331 Attention: Manager IBM Space Guidance Center Owego, New York, 13827

d2.

On the chart paper record the

Government Bill of LadingNumber

Sending Location and Sending Individual's Signature

Unit Name, Part Number and Serial Number

Container Serial Number and Recorder Serial Number

Date and Local Time recorder was started

5-6


NOTE

The chart paper is calibrated in A.M. and P.M. hours, but it is not necessary to

align the paper with the local time.

write the local time at the point where the recorder was started. •:,.••

Simply

.

d3.

Wind the shock recorder,

styluses are tracking.

and verify that the paper is moving and that all three

d4.

Close and latch the shock recorder,, but do not lock the latch.

e.

Remove socket head screws from shock recorder mounting bracket.

f.

Install shock recorder on bracket, using socket head screws previously removed.

g.

Place 17 units of desiccant in receptacle provided.

'

.

'-.

'•'.'••"-.

;

'

.

•'••-•;•'•'•:••.': '•;•-;•'

'

NOTE.-' '-^'''••v- ^: "':,.;.- ^: 'v^--'v

The 17 units of desiccant are packaged in

'•',-.

•

••

< three ;bags. ; The package part number, units of desiccant per package, and the quantity of each part number used are as follows:

IBM Part Number

No. of Units

Quantity Used

6019623

8

2

6019653

1

1

h. Secure cover on shipping container.

i. Turn pressure equalizer screw fully clockwise.

5-7.

GENERAL COMPUTER HANDLING.

5-8.

of the computer. Two computer lift handles.are needed for computer handling; one

handle is mounted on the left side of the computer and the other handle is mounted on the

right side of the computer.

Computer lift handles (IBM Tool Number D-656101) are used for general handling

Mount the computer lift handles as shown in figure 5-4.


'

5-7

Figure 5-4.

₅_-₈

Computer Lift Handle, Mounted


SECTION VI

PREVENTIVE MAINTENANCE

No preventive maintenance is performed on the breadboard models.

6-1/6-2

SECTION VH

CHECKOUT

7-1. OPERATING TEST PROCEDURES.

7-2.

Digital Computer and Data Adapter Checkout Procedures Laboratory Maintenance Instructions.

Instructions for testing the computer are located in the Saturn V Launch Vehicle

7-1/7-2

SECTION vm

TROUBLE ISOLATION

This section is not applicable for breadboard equipments.

8-1/8-2

SECTION DC

REPAIR

9-1.

REPAIR.

9-2. Laboratory repair of the computer is limited to replacing page assemblies and

toroid memory assemblies. Laboratory replaceable assemblies are listed in figure 9-1. The methods for replacing such assemblies are described in this section. The computer

is mounted on an equipment test stand (IBM part

number 6940100) during repair.

9-3. PAGE ASSEMBLY REPLACEMENT. (See figure 9-2.) The page assemblies are accessable after removing the computer logic cover. To replace a page assembly proceed as follows:

a. Remove the logic cover by removing and storing the 14 mounting screws and washers located around the outer edge of the cover.

b. Locate the page assembly to be replaced.

NOTE

(Refer to figure 9-3.)

Do not remove page assembly captive mounting screws from page assembly until after the page assembly is removed from computer.

Assembly

Location

Assembly

Location

6110211

A4A11

6110238

A1A20

6110212

A4A12

6110239

A5A9, A5A10

6110213

A1A3, A2A3,

A3A3

6110240

A5A11

6110214

A1A7

6110251

A1A4, A2A4, A3A4,

6110215

A1A8

A4A4

6110216

A1A9

6110252

A5A3

6110217

A1A10

6111500

A6A2, A6A3

6110218

A1A5

6125408

A5A5

6110219

A1A11

6125409

A5A6

6110230

A1A12

6125420

A4A5, A4A6, A4A7,

6110231

A1A13

A4A8, A4A9,

6110232

A1A14

A4A13, A4A14

6110233

A1A15

6125423

A5A7, A5A8

6110234

A1A16

6125424

A5A12

6110235

A1A17

6125425

A5A13

6110236

A1A18

6125426

A5A14

6110237

A1A19

6125427

A5A15

Figure 9-1.

Laboratory Replaceable Assemblies

9-1

MEMORY COVER

TOROID

MEMORY

ASSEMBLIES

COVER MOUNTING SCREW (22) AND WASHER

ELECTRICAL CONNECTORS U5 THROUGH J8)

MOUNTING SCREW (4 PER ASSY) AND WASHER

ELECTRICAL CONNECTORS (Jl THROUGH J4)

PAGE ASSEMBLY (43)

PAGE MOUNTING SCREW (2) AND WASHER

Figure 9-2.

Computer,

Partially Disassembled

LOGIC COVER

COVER MOUNTING SCREW(14) AND WASHER

9-2


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6125420 VOTER, TIMING 4 M-D

|

[ 6125420 VOTER, TIMING

| 6I17W5 TERMINAL BIOCK

| 6125420 VOTER, TIMING 4 ARITH.

| 6M2995 TERMINAL BLOCK

| 6125420 VOTER, TIMING 4 OP CODE

|

|

6112995 TERMINAL BLOCK

6125420 VOTER. OPCODES

MINAL BIOCK

VPAClIV ASSV

CLOCK DRIVER

MINAL BLOC<

]

|

*6 I 61 10232 MEM

)

|

THMETI

&|

[

6125425 VOTER. TR. REG 4MEM.

6112995 TERMINAt BIOCK

5| 6125424 VOIER. ADD. REG & MEM

M

PAR! I

RM1NAL

|

9|

?|

|

6M2995 TERMINAL BLOCK

6)25408 VOTER MEM. TIM.4

6II02SI CAPACITY ASSY

. 611 2995 TERMI NAL BLOCK

c.

Unscrew the two page assembly captive mounting screws until free of mounting holes.

NOTE

Remove page assemblies with a page insertion- extraction tool (figure 4-4), hereafter referred to as extractor tool.

d. Place extractor tool over top of page assembly; then push locking knob toward page

assembly, thus locking tool to assembly.

e. Squeeze extractor tool handle to its limit (disengaging page assembly connector); then pull page assembly straight out.

CAUTION

Hold page assembly firmly to safeguard dropping when releasing extractor tool.

f. Release page assembly from extractor tool by pushing in the locking knob and moving knob away from page assembly.

g. Remove and store mounting screws and associated fiber washers from page assembly.

NOTE

Page assembly removal is now complete. To install the replacement page assembly proceed with step h.

h. Install previously removed page assembly mounting screws and fiber washers (IBM

part numbers 6110636 and 6113634) in replacement page assembly.

i. Place extractor tool over top of replacement page assembly; then push locking knob toward page assembly, thus locking tool to assembly.

CAUTION

Verify that A side of page assembly faces downward when inserting page assembly into computer. Otherwise connector pins will not mate with receptacle.

j. Insert page assembly into proper computer logic channel location.

9-4

k. Push in extractor tool locking knob; then move knob away from page assembly, thus

releasing tool from page assembly.

1.

Turn in the two page assembly mounting screws; then torque screws to 15 inch- '

'•.:•-.-

.

"-.'-.

'

V:

-

i

pounds.

m.

(IBM

Secure computer logic cover by turning in cover mounting screws and washers

part numbers 6072520 and 6048641); then, using the cross-over method, torque •-•'

cover mounting screws to 10 inch-pounds;

9-4. TOROID MEMORY ASSEMBLY REPLACEMENT. (See figure 9-2.) The toroid

memory is accessable after removal of the computer memory cover. toroid memory assembly proceed as follows:

To replace a

a. Remove the memory cover by removing and storing the 22 mounting screws and washers located around cover edge.

NOTE

Memory assembly connectors mate with connectors J2 and J3 of memory mounting plate assembly.

,

•

NOTE

The replacement of the toroid memory assembly

is simplified by the use of the memory handle. •

When attaching memory handle to memory

(Refer to figure 4-4.)

assembly,

END to shoulder screws at connector end of

memory assembly.

attach gripper marked CONNECTOR

.

b. Slide memory handle grippers under four shoulder screws on top of memory

assembly; then place tool keeper over memory handle shoulder screw, thus securing

tool to assembly.

(See figure 9-4.)

•

-

CAUTION

.

Hold memory handle firmly to safeguard dropping memory assembly during removal of memory assembly mounting screws. •.•:• •

c. Remove and store the four memory assembly mounting screws and associated washers.

9-5

b.

jvr-j

I ^© 'nnnnnnnnnani

MEMORY HANDLE KEEPER

MEMORY HANDLE GRIPPER

MEMORY HANDLE SHOULDER SCREW

MEMORY ASSEMBLY SHOULDER SCREW

Figure 9-4.

NOTE:

PHANTOM AREA INDICATES MEMORY ASSEMBLY

Memory Handle Secured to Memory Assembly

NOTE

The memory assembly connector is a rack- and-panel type and will disengage from its < mating receptacle on the memory distribution board as the memory assembly is lifted

out.

d. Pull on memory handle just enough to disengage memory assembly connector; then

offset assembly enough to clear adjacent memory assembly and pull assembly

out.

straight

e. Remove memory handle from memory assembly.

NOTE

Toroid memory assembly removal is now

complete.

assembly proceed with step f.

To install a replacement memory

NOTE

When attaching memory handle to memory assembly, attach gripper marked CONNECTOR END to shoulder screws at connector end of memory assembly.

9-6

I.

Slide memory handle grippers under four shoulder screws on top of replacement

memory assembly; then place tool keeper over memory handle shoulder screw, thus

securing tool to assembly. (See figure 9-4.)

CAUTION

Hold memory assembly and memory handle firmly to safeguard dropping during installation.

g. Insert replacement memory assembly into proper memory distribution board loca-

tion; then verify that connector and receptacle are properly mated.

h. Turn in memory assembly

mounting screws with associated washers (IBM part

numbers 6035770 and 6113635); then torque screws to 15 foot-pounds.

i. Install memory cover and turn in mounting screws with associated washers (IBM

part numbers 6076307 and 6048641); then using the cross-over

10 inch-pounds.

method torque screws to

9-7/9-8

SECTION X

DIAGRAMS

10-1.

10-2.

DIAGRAMS.

The diagrams included in this section are the drawings required to maintain the

computer.

Figure 10-1.

Figure 10-2.

Figure 10-3.

Figure 10-4.

Figure 10-5.

Figure 10-6.

Figure 10-7.

Figure 10-8.

Figure 10-9.

Figure 10-10.

Figure 10-11.

Figure 10-12.

Figure 10-13.

Figure 10-14.

Figure 10-15.

Figure 10-16.

Figure 10-17.

Figure 10-18.

Figure 10-19.

Figure 10-20.

Figure 10-21.

Figure 10-22.

Figure 10-23.

Figure 10-24.

Figure 10-25.

Figure 10-26.

Figure 10-27.

Figure 10-28.

Figure 10-29.

Figure 10-30.

Figure 10-31.

Figure 10-32.

Figure 10-33.

The drawings consist of the following:

Clock Drivers Logic Diagram (4 Sheets) Decoupling Capacitors (Channel 1) Logic Diagram (4 Sheets) Delay Lines Logic Diagram (2 Sheets) Multiply-Divide Element Logic Diagram (12 Sheets) Add-Subtract Element Logic Diagram (4 Sheets)

Transfer Register Bits 10-TRS and Control Logic Diagram (2 Sheets) Memory Buffer Control and Parity Counter Logic Diagram (2 Sheets) Operation Code Register Logic Diagram (4 Sheets) Timing Gate Generator Logic Diagram (2 Sheets) Phase Generator Logic Diagram (2 Sheets)

Memory Module Registers Logic Diagram (2 Sheets)

HOP Constant Serializer

(2 Sheets) Memory Timing Logic Diagram (4 Sheets)

Memory

Transfer Register Bits 1-9 Logic Diagram (4 Sheets) Address Register and Memory Address Decoder Logic Diagram (4 Sheets) Memory Sector Registers Logic Diagram (2 Sheets) Hi-Y Memory Address Decoder Logic Diagram (2 Sheets) Decoupling Capacitors (Channel 4) Logic Diagram (4 Sheets)

Operation Code Voters Logic Diagram (4 Sheets) Timing Gate and Operation Code Voters Logic Diagram (4 Sheets) Timing and Add-Subtract Voters Logic Diagram (4 Sheets) Timing Voters Logic Diagram (4 Sheets) Timing and Multiply-Divide Voters Logic Diagram (4 Sheets)

Oscillator and Buffer Logic Diagram (2 Sheets) Clock Generator Timing Logic, Logic Diagram (4 Sheets) Timing and Multiply-Divide Voters Logic Diagram (4 Sheets) Multiply-Divide Voters, Logic Diagram (4 Sheets) Decoupling Capacitors (Channel 5) Logic Diagram (4 Sheets)

Memory Timing Voters Logic Diagram (8 Sheets) Memory Address Decoder Voters Logic Diagram (8 Sheets) Memory Buffer Registers Logic Diagram (12 Sheets) Address Register and Memory Module Register Voters Logic Diagram (4 Sheets)

and Memory Read Latches Logic Diagram

Error Detector Logic Diagram (8 Sheets)

(

10-1

Figure 10-34.

Transfer Register and Memory Module Register Voters Logic Diagram

Figure 10-35.

(4 Sheets) Transfer Register Voters Logic Diagram (6 Sheets)

Figure 10-36.

Memory Clock Driver and TCV Logic Diagram (2 Sheets)

Figure 10-37.

Memory Sense Amplifiers Logic Diagram (2 Sheets)

Figure 10-38.

Memory Inhibit Drivers Logic Diagram (2 Sheets)

Figure 10-39. Memory Y-Address Drivers Logic Diagram (4 Sheets) Figure 10-40. Memory Hi-X Address Drivers Logic Diagram (4 Sheets)

Figure 10-41.

Memory Lo-X Address Drivers Logic Diagram (2 Sheets)

Figure 10-42.

X Memory Address

Diode Matrix Schematic Diagram (2 Sheets)

Figure 10-43.

Y Memory Address

Diode Matrix Schematic Diagram

(2 Sheets)

Figure 10-44.

Memory Input-Output Panel Schematic Diagram (2 Sheets)

Figure 10-45. Memory Distribution Panel Schematic Diagram (4 Sheets)

Figure 10-47.

Interconnection Al Back Panel, List for LVDC

Figure 10-48.


List for LVDC

Figure 10-49.


List for LVDC

Figure 10-50.

Computer, Rear View

Figure 10-51.

Terminal Block, Pin Identification, Channels 1, 4, and 5

10-3.

10-4.

SIGNAL TRACING.

Signals may be categorized into two groups:

• Signals that appear at the input-output connectors.

• Signals

that originate in, and are used solely by, the computer.

Locating these two types of signals and finding points in the computer where they may be observed requires two different procedures.

10-5.

TRACING INPUT-OUTPUT SIGNALS.

These signals may be located by referring

to the interface listing, figure 3-2. The signals may be checked by probing the A4 and

A5 back panels at terminal blocks A4J1 through A4J4, and A5J5 through A5J8. figure 10-50.)

(See

NOTE

The A5J7 terminal block has the same pin layout as A4J4, with a different orientation.

The terminal blocks are directly wired to the input-output connectors and the terminal

block pins have the same corresponding designation as the connector pins. To trace an input-output signal into the logic, refer to the interconnection back panel listings, figures

10-47 through 10-49.

The signal can be found under the "Net Name" column.

10-2

j

NOTE

Signals originating outside the back panel (listing) being used, may require the reference designator prefix that is automat- ically assigned to all signals. Thus, if a signal cannot be found under the alphabetic portion of the listing, be sure to look under the portion of the listing which contains reference designator prefixes.

Once the signal is found in the listing, all the pin locations, by reference designator, are listed under the "Page-Pin" and "Bib-Pin" columns. The reference designator can then be used to find the signal in the logic. (See figures 10-1 through 10-35.)

NOTE

The reference designator for each MIB-logic diagram is located on the right hand margin, white symbols on a blackbackground.

10-6. TRACING INTERNALLY GENERATED SIGNALS. These signals may be located

by referring to the Signal-Origin List, figure 10-46. The signal-origin list refers the

reader to the appropriate MIB-logic diagram by reference

through 10-41.) On the MIB-logic diagram are references to test point locations on the logic page. If a signal is to be checked for which a test point is not provided, then one of the terminal blocks on the A4 or A5 back panels may make the desired signal available. (In addition, most of the channel 4 page pins are available from the rear of the A4 back panel.) Look up the signal name in the appropriate interconnectionback panel listing and determine whether or not the signal goes to a terminal block. If the signal is used on

both panels Al (A2 and A3 also apply for redundant circuits) and A4, the listing will show

a reference to a terminal block, reference designator A1EX or A4EX. to identify pin locations.)

designator. (See figures 10-1

(See figure 10-51

NOTE

A one-to-one correspondence exists between

pins on the A4 and Al terminal blocks due to

the printed

terminal blocks. (See figure 1-2.)

circuit cables interconnecting the

If the signal goes to a memory module from a location in channel 5, a reference to

terminal blocks A5E3, A5E5, or A5E7 will occur. Some of these locations are available for probing. (See figure 10-51 to identify pin locations. Only the upper pins, rows A and B, are available for probing.) The points where signals appear on the memory module and memory distribution panel are illustrated in figures 10-44 and 10-45. These points are not available for probing.

10-3

NOTES:

1

See Glossary or Index for Signal Definitions

2.

See Logic Symbols Appendix for Definition of Logic Symbols Dotted Line (if any) Indicates Internal ULD Connection "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate it Prefix Reference Designations as Follows: A1A3A

Figure 10-1.

Clock Drivers,

Logic Diagram (Sheet 1 of 4)

Wl

•WN

10-4

BOP

CGPNP

CGQP'

THRU - PINS

PIN

SIGNAL

1

2

3

i4

5

6

7

8

CGPP

9

10

11

12

13

14

15

PIN

SIGNAL

16

17

18

19

20

21

ZF

22

YF

23

CGPNP

24

WF

25

XF

26

27

28

29

30

Figure 10-1.

Clock Drivers,

CONNECTOR PINS

PIN

SIGNAL

PIN

SIGNAL

1

WN

51

V5

3

W5

53

V5

5

WDA

55

VI

7

SIG RET

57

SIG RET

9

W7

59

SIG RET

11

SIG RET

61

V3

13

Wl

63

SIG RET

15

W8

65

SIG RET

••

17

W2

67

CGPNP

19

W3

69

X3

21

SIG RET

71

XI

23

SIG RET

73

V3

25

W4

75

V3

27

W6

77

V3

29

VI

79

X2

31

VI

81

X4

33

CGRP

83

X6

35

SIG RET

85

X5

37

V3

87

SIG RET

39

BOP

89

XN

41

CGQP

91

SIG RET

43

VI

93

X8

45

CGPP

95

X7

47

V5

97

XDA

49

V5

Logic Diagram (Sheet 2)

XI

10-5

Yl

CGRNP'

NOTES:

Y8

I


2.

See Logic Symbols Appendix for Definition of Logic Symbols

3.

Dotten Line (if any) Indicates Internal ULD Connection

YN

4.

"N .U ." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It

5.

Prefix Reference Designationsas Follows:A1A3B

Figure 10-1.

Clock Drivers,


10-6

LVDC

BOP

CGPNP

CGQNP

-24

ZDA

-25

THRU - PINS

CONNECTOR PINS

PIN

SIGNAL

PIN

SIGNAL

1

16

2

17

3

18

4

19

5

20

6

21

ZF

7

22

YF

8

CGPP

23

CGPNP

9

24

WF

10

25

XF

11

26

12

27

13

28

•*,

14

29

15

30

Figure 10-1;

Clock Drivers,

PIN

SIGNAL

PIN

SIGNAL

2

. ZDA

.52

V5

4

Z7

•:

54

CGPP

6

Z8

56

VI

8

•

SIG

RET

58

CGQNP

10

ZN

60

BOP

12

SIG RET

62

V3

14

Z5

64

SIG RET

16

Z6.

66

CGRNP

18

Z4

68

VI

20

Z2

70

VI

22

;V3

72

Y6

24

V3

74'

Y4

26

V3

76

SIG RET

28

Zl

78

SIG RET

30

•Z3

80

•

Y3

32

CGPNP -

82

Y2

34

SIG RET

84

Y8

.

36

SIG RET

86

Yl

38

V3

88

SIG RET

40

SIG RET

90

Y7

42

SIG RET

92

SIG RET

44

VI

94

YDA

46

V5

96

Y5

48

V5

98

YN

50

V5


-7.8

10-7

Figure 10-2.

^\ 1

•

e

16

(i

14

g

M

//

A

6

"1$

/f

ft

a

fo

11

H

a

tli

li

14

7

7

7

7

7

7

Cl

Al

ri

Cl

A3

t

A4

f

Cl

AS

Cl

Aft

Ci

A^^

Cl

A3

Cl

All

C3

A

10

C3

AM

HOI'f. 1,2

1

1

^? f

'

'

7

;

J

?

f

/

•i—

''

J '

f

f

(f

a

a

a

⁸

a

Tl

«

Tf

C

"4

3

r/

<\

/-/

<\

Tl

<j

r/

\

'6

'7

"e

'3

)

ⁱ 1

f

7

7

,»

f

1

a

4

7

7

7

7

7

?

<:/

<:;

Cl

AH

Cl

All

Cl

AIS

Ci

A19

C£

AI6

Ci

AJO

C3

All

CJ

A3I

tr^

û >i

g

16

A

7

7

*

e

a

e

a

8

SIG RET

VS

Decoupling Capacitors (Channel 1), Logic Diagram (Sheet 1 of 4)

10-8

Pin

1

3

.5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

SIS fffT

CONNECTOR

Signal

A/\SVB1

MSVB1

SIG RET

SIGRET

V4MOD3

V3

V3

V3

V3

V4MOD6

V5

1

;

V4MOD2

VI

VI

VI

VI

V4MOD4

SIGRET

SIGRET

SIG RET

SIG RET

V4MOD5

Pin

51

53-

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

PINS

•

Signal

; SIG RET

' SIG

RET

SIGRET. SIG R ^; ET SIG RET SIG RET

V3

V3

V3

V3

SIG RET

VI

VI

VI

VI

SIG RET

SIG RET

SIG RET

SIG RET

SIG RET

SIG RET

SIG RET

MSVB2

MSVB2

7

7

C*

/)/;

C4

/«5

^

;7

7

7

7

C4

/««

c*

/Jc'6

C3

A/J

CS

Ail

n !

TPlI

â

8

fl

?

^\

TPIt

?

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TPl.t

¥

1

T?r+

,

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7

7

,}

jpf5

,1 ,

,

C4

A16

C4

ASi

C«

AI9

C*

/•3J

CJ

»W

CJ

>w

(J

0

^

s

a

NOTES:

See Glossary or Index for Signal Definitions See Logic Symbols Appendix for Definition of Logic Symbols Dotted Line (if any) Indicates Internal ULD Connection "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It

5. Prefix Reference Designations as Follows: A1A4A

4.

3.

2.

1

.

Figure 10-2.v- Decoupling-Capacitors^(Channel

1), ^; Logic Diagram (Sheet 2)

10-9

A/I/I

NU2

NV3

NU 4

HU S

Y4HIOD t

Figure 10-2.

10

l(.

_i₄

e

~1? _W

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B

>i

14

fl

10

/{

14

fl.

^—ⁿ >l

A

fi

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l-t

s

^~^v /^

14

Al

tf

cr

A3

A4

Cf

A&

Ct

NOTl I

J

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7

1

i

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I

1

3

^S 7

1

i—

^J

/

/

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_/ J

1

7—

^? ₇

i

f

7

1

orr

i

vs

J

s

7

j

f

s

7

1

— ?

J

1

f

J

S

7

—T

s

7

1

3

S~

7

A6

ft

<ct

A>0

C1

Tf*

\

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.

.

It

t*

S

7

TfS

w—*— j

It

14

3

1

9

I

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10

11

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Tf6

1

TPf

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TP6

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a

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/*

'

3

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7

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3

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7

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7

7

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J

7

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g;

CJ

All

r.i

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73-

_i_e /•t

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14

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.'.•f

-

ft

W~

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.

a

^r- _f_f

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a

ia

n

^f^*

sic.

Decoupling Capacitors (Channel 1), Logic Diagram (Sheet 3)

10-10

VI-

1

•

•-•

.

"1

5

7

'T

5

7

5

7

1

f

i

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7

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7

T

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a

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TPII

[

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1

7S-*

11

M.

/

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1

7

/

T

i.

J

^S

'

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14

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"

16

It

14

TPI3

I

3

7

r/>>4

I

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i

S

7

TflS

id '

il

14

* 1

TPIl

n t

J j '

7

-

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X^'

A14

Cf

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J"

7

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It

1*

S

7

rfia

, \

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7

£1

SJJ

Cl

A54

All

C.1

ft

⁾^l /*

0

73—

V

H

e

/i *

e

w

It

H

a

73—

it

ft

e

10

it

•y

o

10

Ig

14.

e

ⁱ^q

fi

&—

CONNECTOR PINS

Pin

2

4

6

e

10

12

14

16

18

20

22

24

26

Signal

V3

1

'

V4 MODI

VI

1

SIGRET

1

Pin

52

54

56 •

58

60

62

64

66

68

70

72

74

76

Signal

V3

1

NU3

VI

1

SIG RET

1

1

28

78

NU2

30

VI

80

V5

32

82

34

1

84

36

86

1

38

NU5

88

NU1

40'

SIGRET

90

V5

NOTES:

1

.

42

44

46

48

50

1

NU4

V3

92

94

96

98

i

V4 MOD7


2. See Logic Symbols Appendix for Definition

of Logic Symbols

3. Dotted Line (if any) Indicates Internal ULD Connection

4. "N.U." Indicates that ULD is Not Installed

although Page is "Wired" to Accommodate It

5. Prefix Reference Designations as Follows: A1A4B

•j/c ntr

Figure 10-2.

Decoupling Capacitors (Channel 1), Logic-Diagram (Sheet 4)

TP5

LL44SX

Figure 10-3.

Delay Lines,

TPI5

W7

vn

DDISA-

IN

"

X3

ra

Y l

rw

A

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a

f-

X)

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ft

A 13

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13

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\

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8

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A

A34

— '/f

\A33] 1

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A

/i

|~^

p]4££


1

i

A 14

y

>U3

Xl/?

,

/

/27

/

A34

f

S

f

S

5TP

I>I4

CiH

7.6 t,lZ

J TPft

^-^X^/^<⁷

AA*

r/'/j

« yv//

A

a,i4\

^-^f^>ê^*

/,/

e.n

10-12

OL44

BOH

<•

«-|

DL-31 — 5 BOW— ^

OLD 10

/>^

J_

9,i3

3,5

OLD

*«,

,

TPi

TP

1

JO

2412

A4- IZ

V

, ⁹ I

'

fi

si

L."

1

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2

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!

i

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i

'

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|

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|

2L£^J

^! J!

JTP4-I

•

J

•

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rj

r/=/'?^'~i ^T^f^>ⁱ⁸ r ^'^-^ •'•'^ â ⁿ

OLD

At

1

10

;TPIO

TP

8l -s'^^ i

t

•L.

--

1

\-j \

1

i

i \

i

*

l^r^lr

3

.

1

1

-L'

'

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1

|I0««> ' ^/>V£|

1 cir,»«

-

3

L

j

'>

*

i T*

L

TI

»

•

77

!

7

••——rih,- -M

i

Vf, rftff ⁴ -

•

'

1

L. _s , _c

_w _r

r.»».

,

f/- ,

pl'J

7

'M

• î/4

in

f.i,

ll

CONNECTOR PINS

Pm

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31 •

33

35

37

39

41

43

45

47

49

Signal

WN

SIGRET

MRON

MRO

V3

ACCON

YN

PQR

ACCO

MDON

VI

STP

'

PQRN

PRN

Pin

51

53

55

57

"59

61

63

65

67

69

71

73

75'

77

79

81

83

85

87

89

91

93

95

97

Signal

ZN

PR

NU

A ION

XN

.

.

NUN

.Z2

Y8

X3

A10

'

W7

•"MDO

' STPN

DL31

DL44

-

BON

V5

NOTES:

¹^.

See Glossary or Index for Signal Definitions See Logic Symbols-Appendix for Definition of Logic Symbols Dotted Line (if any) Indicates Internal ULD Connection "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It Prefix Reference Designations as Follows: A1A5A

Figure 10-3. :; Delay Lines, _; Logic Diagram (Sheet 2)

10-13

Figure 10-4.

DL44

Multiply-Divide Element, Logic Diagram (Sheet 1 of 12)

10-14

Yi

HQ1Y •

p^vN

_P_&_V

n •

•

vow

tlN

P3N

V4NIOD 4 •

KUNV •

A

Alt

-~\K

14

A IO

Alt,

A

Alt

A

Ali

— 1?

A

A13

n

10

1

A ¹⁴

JL :

Aid

— I'

.A

_A_/₉

7P/3

•

PIN

TPI7

1NN

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

OPIV'

51"

G7VN

3

P1VN ,

53

Q8V

5

PCVN

55

'

DTMN

7

VOYN

57

RUNV

9

VOY

•-

59

VOYV

11

MR2

61

PBV

•

13

V]

63

G4VN

15

OP4VN

65

P3N

17

DL44

67

TMVN

-•'

19

G2V

69

DTM

21

PR10

71

TMV

23

PQR

73.

G3VN

25

MD7V

75

P2N

27

TTLV

77

PIN

29

AI3V

79

G7V

31

DL31

81

G1VN

33

STP

83

TM

35

PR 2V

85

PAV

37

HOY

87

G6VN

39

OP3VN

89

G4V

41

OP2VN

91

DTMVN

43

HOYN

93

DTMV

45

G6V

95

TMN

47

PCV

97

G5VN

49

ZN

TPlO

fJM

TMM

Pin

Signal

1

SIG RET

2

HOYV'N

3

W2

4

OP2V

5

6

T8CV

7

8

9

P2VN

10

DTMVN

11

G2V

12

13

14

15

G7VN

THRU PINS

Pin

Signal

16

V3

17

G5V

18

NU

19

20

VI

•

21

V4MOD4

'

22

23

P3VN

24

G4VN

25

HOYV

26

27

G3VN

28

TMVN

29

76

30

X7

NOTES:

1

.



of Logic Symbols

3. Dotted Line (if any) Indicates Internal ULD

Connection

4. "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It


Figure 10-4.

Multiply-Divide Element, Logic Diagram (Sheet 2)

10-15

wz

HOff

T3CV

£JJ

^Lⁱ

AJ

26 ~Mf

A

A 10

Vf

~\-

8

r

l_

A.

AID

V1 —[—

I 8

—

j _s

A

_£/Jj

*>

7

It — MO

hGV

f>JV\'

X 7

.

,

g-

2-

it

A

All

A)

VI

f ⁴

1

j-

—

19

/7

—

|S

A

AS,

MD4

•

_A_t

r

HO

PIVH

r*N

«i3.

4T

/T7

U

7

10

•h

--'--

J

J

L^

j

/

/)/0

/

/«//

/7

/

rp3

_O

f

5

rt

TPI5

f

X

NIDI

/V>i>^

MOSN

Figure 10-4.

Multiply-Divide Element,


10-16

CSV

; THRU PINS

Pin

Signal

Pin

Siqnal

.1

SIG RET

16

V3

2

HOYVN

17

G5V

3

W2

18

NU

4

OP2V

19

5

20

VI

6

TBCV

21

V4MOD4

7

22

8

23

P3VN

9

P2VN

24

G4VN

10

DTMVN

25

HOYV

11

G2V

26

12

27

G3VN

13

28

TMVN

14

29.

26

15

G7VN

30

X7

Figure 10-4.


M04

MD4N

See Glossary or Index for Signal Definitions See Logic Symbols Appendix for Definition of Logic Symbols- Dotted Line (if any) Indicates Internal ULD Connection "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It

5. Prefix Reference

Designations as Follows: A1A7B

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

MD5N

52

Z6

4

MD5

54

MD2N

6

MD6

56

TBCV

8

MD6N

58

MDON

10

MD7N

60

Kl

12

X7

62

KIN

14

MD7

64

K2N

16

MD4N

66

P2VN

18

MD3

68

P3VN '-

20

V4MOD4

70

K2

22

V3

72

HOYVN

24

SIG RET

74

SG2N

26

NU

76

SG2

28

78

HOYV

30

MD4

80

PROVN

32

MD2

82

PROV

.

34

W2

84

ESDV

36

86

ESDVN

38

OP2V

88

SG1N

40

MD3N

90

PR

IN

42

TRSV

92

TFDVN

44

MDO

94

PR1

46

VI

96

SGI

48

V]

98

TFDV

50

G5V

Logic Diagram

(Sheet 4)

10-17

Â ^*

It?

.4 '

¥

64W.

H'i

ft

#

tei

-

MY* -

OTMVM

6/W

SGJ

£

46

se/,v

AK2

6IM

***

.

feitt—4

_«_'_"_—_^

Atf

x/C/V —

'

gffH.V-

TMON

"<-r~\

^

uL

1

S7

ft

wv^ set

4?

Z+

-ÊH _,_j

10

AY

4I5\

X7

TKVN

Figure 10-4.

_—

^fⁱ^f

r}

Multiply-Divide Element;

sec*

SC2

\4>\"

10

Logic Diagram (Sheet ¹ 5)

•>TP4

10-18

NOTES:

1. See Glossary or Index for Signal Definitions

2. See Logic Symbols Appendix for Definition of Logic Symbols


4. "N.U. Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It

5. Prefix Reference Designations as Follows: Al ASA

^ 4W

£

xv^ —4-

ruM

2-

-17

~

/

\

M—.

f4f0/V

H'l

f£ f

e?v

L

^J^?

A.

A!T_

~\7

£

A 10

f

G7V

>f

A

omvw — ^

«/'f

HOf^

GIV

— |

—\j

\AX

«

1

ID

lew —IL

//?

—,,

SMW— &•

J_]
A

A13

_J

TF'O

if

H2

—\7

A

fl

, f \

fS f

errtw- 4 f

=£f

A

fl

; —\J

SfM- 1

= 1

/H

J

AY

am

" ^

.-a.

Ft'PK-

*1

^J

—\^s

S S

A?4

1

A

CONNECTOR PINS

Pin

1

Siqnal

Pin

Signal

MR2N

51

MD7N

53

_

PR6

55

X7

G6V

'

57

,W2

Y7

59

MR2

61

VOYVN

63

G3V

HOYV

65

Z4

AV

67

TMVN

G2V

69

P3VN

71

G7VN

73

HOYVN

MD7V

75

G4V

SG2N

77

G1V

SG2

79

G1V

Ql

81

G1VN

PR6N

83

AVN

P1VN

85

Q1N

87

G6VN

89

G4VN

91

DTMVN

93

DTMV

95

^:

SGI

97

SG1N

/

r?S

'

THRU P

INS

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

413 '

Pir

Siqnal

Pin

Siqnal

1

SIG RET

'

16

V3

2

17

ZDHN

3

EMDN

, •

1R

VOYV

4

SMDN

19

PR6

5

FMDN

20

ZDLN

i

G2VN

22

G1YN

8

CDN

23

G7V

9

G6VN

24

G7VN

11

TMVN

26

DTMVN

12

CD

27

DTMV

13

G6V

28

VI

14

PR6N

29

Y7

15

G5V

30

G1V

24

1 'P I

S

]

Figure 10-4.



10-19

UOYVN

MMV

_F_i_g_u_r_e ₁₀_-₄_.

.:;,=I . -

GIM

"iD:*(

UOYVN

Multiply-Divide Element, Logic Diagram (Sheet 7)

10-20

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

TFD

50

G5V

4

MD4N

52

MR IV

6

MD5

54

8

56

MD6N

10

MD5N

58

PR4

12

TFDN

60

14

MD2

62

16

BSD

64

18

M03

66

20

V4MOD4

68

22

V3

70

24

PR4N

72

26

ESDN

74

SG2N

28

SIG RET

76

SG2

30

MD4

78

32

80

34

82

Z4

36

84

38

MD2N

86

40

MD3N

88

SG1N

42

MD6

9G

44

92

46

G3VN

94

48

VI

96

SGI

98

G2VN

TFDN

TFO

5MDN

MO4

§1

2J

T

AilJ

Y7

^^~^^

ZDHN — £ EMDN — S â -

MD5

V4MOD4

IT _A

A35

~lft

A

V4MOM

Y 7

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A54

—|io

10

14

.

3

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A?*

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!^

A

VID4N — LS

A

I

V7

Si

EMDN

^

K3

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MD5N

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A/53

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S-

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!2

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Y7

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PINS

Pin

Siqnal

Pin

Signal

1

SIG RET

16

V3

2 17

ZDHN

3 EMDN

18

VOYVN

4 SMDN

19

'

PR6

5 FMDN

20

ZDLN

6 HOYVN

21

TMDN

7 G2VN

22

G1VN

8 CDN

23

G7V

9 GGVN

24

G7VN

10 HOYV

25

G2V

11 TMVN

26

DTMVN

CD

12 27

DTMV

13 G6V

28

VI

14 PR6N

29

Y7

15 G5V

30

.

GIV

NOTES:

fe

_f

TPIT

ESDN

1

,


2.

See Logic Symbols Appendix for Definition

of Logic Symbols

3.

Dotted Line {if any) Indicates Internal ULD ^J

Connection

4.

"N

U,"

Indicates that ULD is Not Installed


5.

Prefix Reference Designations as Follows: A1A8B

Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 8)

10-21

HCYV

Figure 10-4.

^lⁱ zu?

*v-

~\

kJ

\Af9

\A&>

AttfM


YS

Jt

6

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\/itsr- 7

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M-\9

O2

yg-

46

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C6

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7X^9


10-22

Figure 10-4.

NOTES:




4. "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate it

5. Prefix Reference Designations as Follows:A1A9A

1

.

THRU PINS

Pin

Signal

Pin

Siqnal

1

HOYVN

16

TMVN

2

17

G4VN

3

26

18

W8

4

Y8

19

5

XI

20

6

P2VN

21

7

22

V4MOD4

8

ZN

23

SIG RET

9

VI

24

V3

10

25

P3VN

11

26

12

27

13

28

14

29

PR

15

PRN

30

TMV

CONNECTOR PINS

Pin

Siqnal

Pin

Signal

1

MR]

51

MR1V

3

MR2N

53

G7V

5

MRO

55

7

MRON

57

PAV

9

AI2V

59

MR IN

11

MR2

61

XN

13

MR1VN

63

15

HOYV

65

17 '

67

19

69

21

V3

71

23

SIG RET

73

SG2N

25

AI2VN

75

27

TTLV

77

AVN

29

SG2

79

Q1N

31

Ql

81

V4MOD4

33

STP

83

Q8

35

AV

85

OP1V

37

87

G5VN

39

OP3VN

89

G3V

41

PIVN

91

43

93

45

95

SGI

47

VI

97

G2V

49

OP2V

Multiply-Divide Element,: Logic Diagram (Sheet 10)

10-23

Y£

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Figure 10-4. Multiply-Divide Element, Logic Diagram (Sheet 11)

10-24

wa

p

TBCV—nnn

A13VN- -

13

A

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A

1

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1

A

2

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VI-

1

3

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?

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S

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Figure 10-4.


TP3

THRU PINS

Pin

Signal

Pin

Siqnal

1

HOYVN

16

TMVN

2

17

G4VN

3

26

18

W8

4

Y8

19

. 5

XI

20

6

P2VN

21

7

22

V4MOD4

8

ZN

23

SIG RET

9

VI

24

V3

10

25

P3VN

11

26

12

27

13

28

14

29

PR

15

PRN

30

TMV

CONNECTOR PINS

Pin

Signal

Pin

Siqnal

2

Z6

52

VOYV

4

Y8

.

54

PR

6

PR6

56

. TBCV

8

58

P1VN

10

60

Kl

12

62

KIN

14

'PR 10

64

K2N

16 .

XI

66

P2VN

18

PR6N

68

P3VN

20

70

K2

22

PR4N

72

HOYVN

24

74

PRN

26

PR4

76

PRO

28

78

AI3V

30

80

PROVN

32

PR

IN

82

PROV

34

VV8

84

ESDV

36

PR2

86

ESDVN

38

PR1

88

TMV

40

G2V

90

PR 2V

42

TMVN

92

TFDVN

44

G4VN

94

PR2VN

46

ZN

96

AI3VN

48

PR2N

98

TFDV

50

PRON

NOTES



3. Dotten Line (if any) Indicates Internal ULD Connection



1

.

Logic Diagram

(Sheet 12)

10-25

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Figure 10-5. Add-Subtract Element, Logic Diagram (Sheet 1 of 4)

10-26

THRU PINS

Pin

Signal

Pin

Signal

1

ZERN

16

ACCO

2

A1V

17

G6VN

3

AI1V

18

RAC

4

G4V

19

PAVN

5

20

OP1VN

6

OP2VN

21

7

CSTV

22

OP2V

8

ANDN

23

AI3V

9

AUN

24

C

10

AI4

25

CN

11

OP4V

26

OP3VN

12

PCV

27

B

13

BN

28

G3VN

14

TBCV

29

1,1

30

G5VN

Figure 10-5.

Add-Subtract

Element,

TP*

ZER

ZERW

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

SIGRET

51

PBVN

3

V3

53

OP3V

5

PBV

55

CSTV

7

AVN

57

G4V,

9

TRSVN

59

A5V

11

G6V

61

SHFV

13

TRSV

63

A6V

15

A2V

65

Z3

17

AI2V

•

67

G7VN

19

TBCV

69

'PCV

21

TTLV

71

OP4VN

23

Q8V

.

73

G5V

25

OP4V

75

V7

27

IOREG

77

INTV

29

PIOV

79

G1VN

31

G2VN

81

P3VN

33

Wl

83

AV

35

G1V

85

HOYV

37

G6VN

87

VOYVN

39

X3

89

EXMVN

41

VI

91

OP1V

43

ZN

93

45

G5VN

95

OP3VN

47

G7V

97

G3VN

49

PAV

NOTES:

1

.



of Logic Symbols


Connection





10-27

Y4M0DJ

t

V4MOD3

Figure 10-5.

NOTES:

I

. See Glossary or Index for Signal Definitions

2.


3.

Dotted Line (if any) Indicates Internal ULD Connection

4.

"N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It

5.

Prefix Reference Designations as Follows: Al A10B

Add-Subtract Element, Logic Diagram (Sheet 3)

TPK

[

OL.44

AI3M

AI3

10-28

V4M003

ypia

/ICC IN

•ACC1

V4MOD3

HOFC1V

TP*

DL3I

TBCK

THRU PINS

Pin

Signal

Pin

Signal

1

ZERN

16

ACCO

2

A1V

17

G6VN

3

AI1V

18

RAC

4

G4V

19

PAVN

5

20

OP1VN

'6 .

OP2VN

21

7

CSTV

22

OP2V

8

ANDN

23

A13V

9

AUN

24

C

10

AI4

25

CN

11

OP4V

26

OP3VN

12

PCV

27

B

13

BN

28

G3VN

14

TBCV

29

15

30

G5VN

Figure 10-5.

Add-Subtract. Element,

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

52

PIOV

4

OP2VN

54

PCVN

6

OP1VN

56

OP2V

8

ACCO

58

OP3V

10

ACC1

60

Y7

12

62

14

UTR

64

Wl

16

DL44

66

18

PBV

68

VI

20

SHFV

70

X3

22

AUN

72

AION

24

TRSV

74

23

26

76

V4MOD3

28

PAVN

78

AI2VN

30

AI1V

80

AI1N

32

UTRV

82

AI2

34

HOPC1V

84

AI3N

36

DL31

86

AI2N

38

ACC1V

88

AIO

40

WN

90

AI2V

42

A1V

92

AI3

44

A2V

94

All

46

AI3VN

96

SIG RET

48

OP1V

98

-3VDC(V3)

50

AI3V


10-29

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j* ^^-

.,

^j~

C/i/^ — &

/

"~i

/

TJT-M

ri

,

IAS ./«?1

i

x

4 V

⁷

,

Figure

10-6. Transfer Register Bits 10-TRS and Control, Logic Diagram (Sheet 1 of 2)

10-30

NOTES:


1




5. Prefix Reference

.

Designations as Follows: A1A11A

" T

A ⁷

fIS

VI —\3

8

A

A

l

J

A

I

?

i

VI —I

rt

Yt

777

1 a_

= 2

~\9

A

t

—\/e

A 7

A t

—| 7

A

15

A

5

a

AH

1

3

A

I

t

.

¹ TP t£

T

T

"I'SH

".no

TRII

Tt

TRW

13DH

—'-h A

—^

— <*•

fe

>,,

*'

,

•*

3

JTI

°CVN ^

I

f

S

n

C2SH

GSv

G£ VN

n

GIV

ft

CDS

PdV

C.7VN

dlVN

-

—

1

-

A

A

|J

IS

*-

'-f

A

—17

'A

A

3

A

—

17

*•

A

AH

j?

f-

—

A

A14

n

Sf

?rxv

— s

1

A^ ^

Ib

ij

HOft —L-f- u

PCY

*//

& A3?

^

C

p3—-43^-
i.

V4

MCUi —

1 al

19

A

\

.=

1

s

\ A

*-*

i

A J

zs —— ₁₇

|

16

*^

f£

A

'f

VI —I ⁹

ft

f

"~ t ^— ¹⁵

AB ^ M

A

A

l

j

i

/>!

" 5/f 7KN

fA f

67y

CONNECTOR

PINS

Pin

Signal

Pin

Signal

1

G3V

51

AI2V

3

RUNV

53

BRB11

5

RUNVN

55

A5V

7

G3VN

57

BRB13

9

59

MBOV

11

Y6

61

8RB10

13

63

BRA 10

15

OP2V

65

BRA 11

17

67

MAOV

19

69

BRA 13

21

71

23

EXMVN

73

TRIO

25

75

BRB12

27

CLTR

77

BRA12

29

G2VN

79

TR12

31

TRSN

81

TR9D

33

HOPV

83

35

85

37

87

39

TRS

89

X2

41

SHFV

91

TR9DN

43

93

TR11

45

95

47

TR13

97

49

A6V

THRU PINS

Pin

Signal

Pin

Signal

1

SIG RET

16

V3

2

AV

17

G5V

3

G7V

18

TTT

4

19

PBV

5

PAV

20

G7VN

6

GIV

21

STO

7

G1VN

22

G2V

8

PCVN

23

VI

9

SRTR

24

X2

10

TBR

25

V4MOD2

11

Wl

26

Z8

12

27

PCV

13

28

CDS

14

29

G6VN

15

30

Figure 10-6. Transfer Register Bits 10-TRS and Control, Logic Diagram (Sheet 2)

10-31

f

⁽

PAV — 4f

S

Iff,

/ f

n>v — £•

•tl-fij

'

*

A30

AiC

s

,

It

f

7V

1}

\

/

t

Givt t — IjL

%QY

— I* .

A

Alt

£-,

n

A

d

tit

AVN

-^

, /f

-1 *

10

*•

eiy

e

6J\fH — 2

pcv — it

XK — Z

A23

~~A~

A 15

^

p

wi

o

i';

— 19

| tf

tf^l-'ODi —1—

U

n ;

A y

IZ ,

ptvn —£•

n i

_*

AVM — -%

2

G2V

¥1

_r_n .

OfJ V

VI

OP1VN

rj

2-

^

op^ vtj — ii

OP4Y

VI

5 TC I'M

£-

^/^J

4

A^^

"19

A

Alt,

|7

A

Alb

A

A

It

1 10

A

A3

|J

A

A

t

\/0

A£

A

A

i

~\IO

A /*

IK

,'4

K

7

10

ⁿ r j

7

L^

J

—

/.,. i.

*tt

•'

>/5

5

^ ^L

•

TSW

, a/r

„.

rrr

M~

A3S

\ 1

i

6

r

A

AM

K/-p _L_A

—1*

A

A34

7

\A't

'"a

⁷

A

Alt

g

/v/A/ —/o

/>,?/

£

fy

4V

tyi

fcv

=-

—\io

'^

A

AS

A

STO— &

GJ V,M — -J-

Civ

- -

4-

A f,M — 8-

r/v

VJMC3?

—19

A

All.

s

r

L_

(

U

—I ³

A

AS

1}

a

\

jj

;

2U

.

£J

_&₆_V _Jl

A

A 33

^1

V4MOD2

T J

i_ l

^r

/

A33

V4MOD2

G7VM

G1VM

PC/W

T »4

4-

~-

^

A

AI9

A

AD

*1

«J

_J

/

X^5

/

*34

TP/7

'

5

?

J /

AH

I

AS

TP&

<

5

/•

J

I 5

A 33

CA-/"

Figure 10-7. Memory Buffer Control and Parity Counter, Logic Diagram (Sheet 1 of 2)

10-32

IB

TRtr —A

SBR2H

'

CKf —'-£

\

-\>

A

Alt

Aft

~~\9

M

All

^' H—

_U

—\i

Ai&

CKP — -fj

PDDN Tftiv — —¥; '*

IB

Sff#2

U_

—\7

A

~~\IO

A

/6

—\/o

*->

If

U-l

- ———

1*

7

j

5

y

Ail

1

T»/3

r

~

^

P

.

— i

1

'

/ fit

>

1}

PAV — —

A 7

A3*

ze

TfllN

16

TR1V

YN

J

Al)

—\ 7

—&•

A

»

At

0

a

r

L

A

A14

JL

A/4

V4MOW-I—

— ]3

L

A

/

f

A l

A l

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

OP2VN

52

V]

4

OP1VN

54

ZN

6

SRTR

56

TTT

8

SBRZ

58

SBRY

10

PAR

60

STO

12

TR1N

62

CDS

14

OP3V

64

16

G7V

66

Y6

18

PAY

68

Wl

20

V3

70

G5V

22

SIG RET

72

PCVN

24

Z8

74

OP4V

26

YN

76

G2V

28

G5VN

78

30

G1VN

80

32

G6V

82

AVN

34

CBRN

.

84

PBV

36

V4MOD2

86-

RDV

38

TR1V

88

G4VN

40

G7VN

90

G3VN

42

AV

92

44

STOVN

' 94

TBR

46

G6VN

96

G1V

48

SBRX

98

PCV

50

WN

-

PODN

a A a

FAR

Wl

/}

a

~\IO

A

All

"I*

1

A J /

1

\ —\3

\A

A 1 /

—

IV 1 "^

—\/o

^"

,j

A

A HO

Al

n

,.,,

.

/J

A

IN

V4MOD2

Y6

sgK r

WN

— 1 ?

A

A *

6

r

L

-f—

La

— \9

A

—\io

13,

<J

A

A10

—\y

A

/

7

7

f

J

/

A 4

1

/

r*

j

j

"

•

9

f

fa

J

o

.

r

u

1

|3

*

\ A J

J"

^~ -

THRU PINS

1

f>ct>

sefir

SBKl

Pin

Signal

Pin

Signal

I

SIG RET

16

V3

2

AV

17

G5V

3

G7V

18

TTT

4

19

PBV

5

PAV

20

G7VN

6

G1V

21

STO

7

G1VN

22

G2V

8

PCVN

23 ,

VI

9

SRTR

24

X2

10

TBR

25

V4MOD2

11

Wl

26

Z8

12

27

PCV

13

28

CDS

14

29

G6VN

15

30

NOTES-.

1

.

Sec Glossary or Index for Signal Definitions

2. jec Logic Symbols Appendix for Definition

of Logic Symbols

3. Dotted Lino (if any) Indicates Internal ULD

Connection

4. "N.U." Indicates that ULD is Not Installed althougli Page is "Wired" to Accommodate It

5. Prefix Reference Designations as Follows: A1A11 B

Figure 10-7. Memory Buffer Control and Parity Counter, Logic Diagram (Sheet 2)

10-33

V4 MOD 5

TR13V

22

PAV — 23

X

k

7

v,

8

r

L

A ⁿ |J

X

B

k

A

—|

t

A

9

^

k,

8

3

U ^,

*ft

^

A

—1

X

A

3

i,

3

7

a

?

5

S

*

^

f

A

<

z

r-5

i ¹

n

y

^

C7VN 22 V4 MOD 5-

GGV

£

G5VN-— g

*

PAV

GoV

OPIN

OPEN

OP3KI

OP4N

I

A8

^J _g

S

_

.,.„

^HÔ^P

1

§,_HOP N

(!)

TP6

W6

-

INT—a

H

10

X

A

k

IZ.

J7

MTr -J

¹³

t

A

k

11

12

1

0

VI-

^v 'r _U

—| 9

;

k

J

r^

L_

A

11

-

X \

r

A

12

_^_M_i 1 _— INTBN

—

--A ¹ ^^— ¹^N^T^B

FCD

V4 MOD 5—i

V4 MODS r

u

A

A15

•5-

"_

"

A16

3

r

i

A1S

I

Aie

s

5

PAV

CSVN

G7V

^H²

;=is

*

1

2

A

A33

V4-MODS-

8

f

V4MOD5

1

LS

E2-

OPIN

~~l»

A

A34

-Is-

A

A27

-|io

A

AZ7

14

&

g?|=3 |

A9V

PAV

*

^

A8V

•

1

£

G1VN

G7VN

OP3

A

AZ6

A

AZ6

MOPN

HOYVN

VOYVN

X2-

*

A

B

EXMN

INTBN

1

*

W N-

r

I

Vl

r

^

T

A

A1O

A

AID

~l»

A

A3

=hr

_A

A *

i

^

|3

r

7

«

5

1

,— I 5 ,

A34

l 5

AZ7

1

,

If

*)

.U

I

A3

^T S

5 ,

f

1

I

5

"lA*""

TP11

OP2

OP2N

E.XM

EXMN

INTAN

INTA

Figure 10-8. Operation Code Register, Logic Diagram (Sheet 1 of 4)

10-34

NOTES:

1

.

PAV

GSV

CGVN

FCD

-"El

V4 MODS—I;

e

A

3

1

5

1

1

A:

31

A31

1

3

la

t

i,

3

1

5

A.

32

A3Z

TRltV

13

VOYVN

THRU PINS

Pin

Signal

Pin

Signal

1

OP3N

16

FCD

2

OP1

17

PAV

3

18

G6V

•

4

19

5

20

6

21

G5V

7

22

G6VN

8

23

9

24

A9V

10

25

A8V

11

26

12

27

13

28

G5VN

14

29

OP1N

15

30

OP3

OP3N

_F_C_D



of Logic Symbols


Connection




V4MOD5

TR1OV—22

PAV

CBVN

CSV

PAV

CIV

C2VN

P6VN

f

1

»

16 -

A

S

5

â

INTA—a

VI-

B

|

c

J

A »

—17

A

A13

1

iz)
A

A

C

1

~|9

A

1

^_,

b

i i-

A

C

A C

-tr

A

3

1

5

A7

I

A 7

OP4

OP4N

INTN

IN T

CONNECTOR

PINS

Pin

Signal

Pin

Signal

1

HOP

51

OP4

3

OP2N

53

Y6

5

OP1N

55

TR11V

7

HOYVN

57

OP2

9

SIG RET

59

TR10V

11

V3

61

Z2

13

VI

63

G1V

15

65

VOYVN

17

TR12V

67

G2VN

19

V4MOD5

69

CSTV

21

OP1

71

HOYV

23

G1VN

73

EXMN

25

G4VN

75

27

TR13V

77

29

G7V

79

31

WN

81

33

OP3N

83

35

W6

85

37

X2

87

39

OPS

89

41

OP4N

91

EXM

43

INTCV

93

45

G7VN

95

PBVN

47

97

INT

49

Figure 10-8. Operation Code Register,


10-35

VA MOD s

\'4 MOD 5

*

~OPW

-

Figure 10-8. Operation Code Register, Iagic Diagram (Sheet 3)

10-36

SSF-

PAV-

GGV-

A33

VI-

—19

8

A

r

A3 7

1

V4 MODS

|e

-hr

_A

A34

FCD

1

1

—l

3

3

I

AZ7

I

A34

OP1-J3

OPZV — -

OP3N

V4 MOD5-

-

CP4V

A

A34

!i

A 5

A35

— 13

A

A35

1

Hi

S

5

TP12

o

TTLN

TTL

-STON

NOTES:

1

.




4. "N.U . Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It


CONNECTOR

PINS

Pin

Signal

Pin

Signal

2

STON

52

4

OP2V

54

Y6

6

A8V

56

A9V

S

OP4V

58

10

SIG RET

60

TR5V

12

V3

62

14

VI

64

16

PAV

66

TR1V

18

TTL.

68

SHF

20

V4MOD5

70

TR6V

22

G5VN

72

24

TR8V

74

26

76

28

G5V

78

30

80

TR2V

32

82

TR7V

34

G6V

84

G6VN

36

86

38

88

40

TR9V

90

42

OP3V

92

PIO

44

TR4V

94

46

TR3V

96

48

98

50

.

THRU PINS

Pin

Signal

Pin

Siqnal

1

OP3N

16

FCD

2

OP1

17

PAV

3

18

G6V

4

IV

5

20

6

21

G5V

7

22

G6VN

8

23

9

24

A9V

10

25

A8V

11

26

12

27

13

28

G5VN

14

29

OP1N

15

30

Figure 10-8. Operation Code Register,


10-37

s^ ¹

A24

AZ4

W7

1^4V/2' N

G3VN

G2VN

G6VN

&TVN •

•

AVN

V4MOD1

InP

V4MODI

14

31

W7

0 _

A

A33

W7

AVN —2

V4MOHI

AZ3I

A

Alfel"

-] ₉

6 A .

[

I

Alfe

V4MOD1

W7

AV

A

.42.

A'i

AVN

G4V

J^-

WM001-

'••4 MODI

132.

f A l

AIZ

9

A

A 19

.=5

3

TPI7

- GIN

TPII

-&3N

m &5N

AIZ

_T

5,

C75

W7

V4MOP1

Y4MOD1

T?

A Z

A

A8

7*

~F£

|

I Aft

W7

GIVN

AVN ^_⁵^t

A'?

A23

TP3

-ez

TPO

_&₄ _N

Figure 10-9. Timing Gate Generator, Logic Diagram (Sheet 1 of 2)

10-38

AVM-

&6V-

V4MDP1-

V4M0DI-

Pin

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

r?

î & a

—1 ₉

A

A14

~~1

a

TPI3

1

A 14. ^•^y

1

-G7M

&7

CONNECTOR PINS

Siqnol

G2

G2N

G1VN

G3N

G3

G2V

G4N

G3VN

G6VN

G4

G4VN

G5VN

A

Pin

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

Signal

AN

G5N

GIN

G7V

Gl

G5

G4V

G6

AV

G5V

G6N

G7N-

G7

G6V

W7

AVN

^W⁷

-f ²

TPZ

THRU PINS

TPie

Pin

Siqnol

Pin

Siqna 1

1

G1V

16

G2VN

2

G7VN

17

G3V

3

18

AVN

4

19

5

20

6

21

VI

7

22

W7

8

23

9

24

10

V3

25

V4MOD1

11

26

12

27

SIG RET

13

28

14

29

15

30

Y5

NOTES:

1

.



of Logic Symbols


Connection

4. "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate U


Figure 10-9.

Timing Gate Generator, Logic Diagram (Sheet 2)

10-39

Figure 10-10.

W7

GZVHI

6TVM

/XVN

-*

2

/v,

AIO

A

ftlT

V4MOB1

V4MOD1 -

~~I9

e

A

Leal

n

vs—

PBV

d

13

A

s

n

d

hzl

3

T

LâJ

TP.3

-PA.N

TBCM

TOO

Phase Generator, Logic Diagram (Sheet 1 of 2)

10-40

Figure 10-10.

TP5

Phase Generator,

PBN

PB

PCN

PC

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

52

4

54

VI

6

56

PEN

8

58

.PCVN

10

60

12

62

14

W7

64

16

PAV

66

18

G3V

68

20

70

PA

22

72

G2VN

24

74

G7VN

26

76

28

78

V3

30

TBC

80

SIG RET

32

82

AVN

34

84

PBV

36

86

PAN

38

88

G1V

40

90

PBVN

42

PAVN

92

Y5

44

PB

94

PCN

46

PCV

96

V4MOD1

48

98

PC

50

THRU PINS

Pin

Signal

Pin

Signal

1

G1V

16

G2VN

2

G7VN

17

G3V

3

18

AVN

4

19

5

20

6

21

VI

7

22

W7

8

23

9

24

10

V3

25

V4MOD1

11

26

12

27

SIG RET

13

28

14

29

15

30

Y5

NOTES:

1

.







10-41

CDSV

DSSN

G6V

C7VN

DUPDN

DMC

Zfi- —I ⁷

j|

W

»

A

A

2

IZ

^

A

A

3

â

A sjl

VI- ~~]s

A

3

3

TP 1

flR^]Ar-^-DMi

A a

A 6

I

ISSN— $

DM I

DM0-

_a

13

AZ

A

VI-

8

A1

— ]9

A

A l

5

[3

I

A1

TPE

-DUPDN

PBV—Tj?j A

_e f«{J=SA>4

DM2

CM3N

&

fi

A

A

A31

A3O

V4 MOD 6 ~~]|0 - IM a

<*=:=>— 2

1H/3N

^

—

REI— §

A

A31

a.

^J 3

I

A31

VZO N

V4 MOD 6^—1 ₃

DM2

DM3

RED V4 MOD 6

IM S

MTTN

^RÊÎ

MSS N

Figure 10-11.

Memory Module Registers,


10-42

EB-

DSS j| G1V — rj S7V — ^K

DUPDN — 13

DM1

IM1

VI-

&.

DUPIN

—\7

A

Ate

A

AI5

\ â

A

A15

—

V4 MOD 6

M.

12

i

1

,1

-U

TP 8

1

I

M-DM O

TP13

IMO

CDSV-

C1VN-

G2V-

VI

DSS-

G2VN-

G3V-

3 A

A17

VI-

e

—I ⁹

A

A 3

=rr

H

A

AtO

za-

El

—17

A

A3

10

1

,1

I

A 3

I

A1O

DM2

DMZN

TP5

Tf »3

i

J)

5

5_

1

TF

DM3

OM3N

REI

V4MODS

IM O

REI

|io

CONNECTOR PINS

IMBN

-IMAN

Pin

Signal

Pin

Signal

1

ISS

51

SIG RET

3

G1VN

53

5

G7VN

55

MFFN

7

HOPV

57

OMAN

9

MZON

59

DMBN

11

PCV

61

28

13

ISSN

63

15

65

17

67

19

V4MOD6

69

IMBN

21

71

23

73

25

75

G5V

27

77

29

G7V

79

31

81

MSSN

33

G6V

83

G6VN

35

DSSN

85

G3V

37

CDSV

87

G4VN

39

GIV

89

V3

41

DSS

91

IMAN

43

G2V

93

G4V

45

MTTN

95

PBV

47

G2VN

97

G5VN

49

VI

NOTES:

1

.

V4 MODC_—|io

DMO

RED

DMBN



of Logic Symbols

3. Dotten Line (if any) Indicates Internal ULD

Connection




THRU PINS

Pin

Signal

Pin

Signal

1

DUPDN

16

DM0

2

G6V

17

DM1

3

G1VN

18

PCV

4

G7VN

19

DM2

5

GIV

20

DM3

6

PAV

21

G7V

7

G2V

22

G2VN

8

G3V

23

9

RED

24

REI

10

IM2

25

IMO

11

G5V

26

IM1

12

G4V

27

G6VN

13

PBV

28

G4VN

14

29

DUPIN

15

IM3

30

G5VN

Figure 10-11.

Memory Module Registers, Logic Diagram (Sheet 2)

10-43

W5—1 7

warns

PCV

AID j

DM I

PCV

G4V

G6VN

DMO -

S

VI-

8

1

U 1

~1«

A

A 9

~\s-

Â 2

A

<z- —|to

A 3

Y7-n,o

^H^PÎ -Â

DC

I3J

Y7-^

-^

A

35

1O

A

AZ6

XM — ^ / i

e

3

AZ6

.

la

5-

A

ASS

--

"

IT

n

2,

L3

3

.1

1

Iz

\

-4-,

—i—

I

I-Z&

I ,

TP17

_o

5

5

WS

053-

PCV-

G3VN-

G5V-

W5

PCV

G5VN

G~7V

NOTES:

1

.





PAV

G5VN

G7V

DSIM

-HPI

A17|

^V¹

8

PA17

13

A

although Page is "Wired " to

Accommodate It

5. Prefix Reference Designations as Follows: Al A14B

[31 5

G1V

G6V

A)7

TPG

O

• HP1N

HOPC1N

•RUN

HOPCI

•REX

C5VN

TPB

Figure 10-12.

HOP Constant Serializer and Memory Read Latches, Logic Diagram (Sheet 1 of 2)

10-44

DUPDN

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

_F_i_g_u_r_e ₁₀_-₁₂_.

THRU PINS

Siqnal

DUPDN

G6V

G1VN

G7VN

G1V

PAV

G2V

G3V

RED

IM2

G5V

G4V

PBV

1M3

Pin

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Siqnal

DM0

DM1

PCV

DM2

DM3

G7V

G2VN

REI

IMO

IM1

G6VN

G4VN

DUPIN

G5VN

RE.DN

RE.D

CONNECTOR PINS

Pin

Signal

Pin

2

52

4

HOPC1

54

6

56

8

58

10

60

12

62

14

Y7

64

16

PAV

66

IS

AV

68

20

V4MOD6

70

22

XN.

72

24

AVN

74

26

DS2M

76

28

OP1V

78

30

DS4

80

32

82

34

84

36

86

38

X2

88

40

90

42

DS2

92

44

94

46

IS4

96

48

98

50

Signal

W5

DSIM

IS2

DS1

VI

DS3

G3VN

SYLC1V

151

IS3

S1GRET

V3

HOP Constant Serializer and Memory Read Latches, Logic Diagram (Sheet 2)

10-45

MOP

STOVN

13,

*

V4 MOD7-

^ ^{^}

A

5

9

1 ]

X

A

^X s

¹ T

''

_e

-A15 — ¹^N^H^B ^S

V4 MOO7 -

—|

S

INHB S

s

A

; k

13

" ~

VI-

-

10

TTLV

y

J7_

—

A

Z3

VI

-

1

7

1KITV

/

V

13,

GGV-^

A

&

VI

-

—| 3

PAV

§•

k

RUNVK/^^

A

6

1^

VI-

OP1 VN

cj

3

OPZVN

OP3V

j|

Ê

A^

OPZVN

OP4V

VI- - 3

§

²

VI -

t

A

t,

7

1 7

ia

OP3V-H 4

~

OP4V

/ ^

w<

A 31

VI-

1 10

t 1Z

RUNVN — —

Ai !4

J

X

^

J

A

24

27-

—1

3

G7VN

1

X

V

i

PAV

i

A

31

M

M^LT V

^

X

k

A

30

V4 MOD7-

~1 °>

6

c

t,

A

3q

=

1^

u.

t

^

f.

?s

Y1

-

~]

10

C7VN

Û

A

1,

13

*

C6V

*

>

A

?r

J

_

V4 MOD7-

s

CSTN

S.

>

A

!V

2?

"

"^3— ^R^D

!

I

5

3]

I

TPG

§ 1

_n _D

^L lA ₂ 4- ^J - ^MÔ ^P

3 1 5 AV>

3|

I

|5

lA23|

*

(

RUN

„

.

.

RUNN

-££*-« ^T

,

I?

A

C7V

2.

A3Z

2'

r-

~|7

PAV

A

MOP ^

14

A25

A

G3VN

A

7

*-

C4 V

7-

~~|1Z

A

K/OP

a

AZ5

Z"

r-

—17

RD

A

3

A53

PAV

Si

A

Z

A7 ¹ !

Z1

r-

~~h

PAVN

A

£

A3.1

GZV

7^

A

RD ^

3.

AZG

G5VN

A

3

A14

Y1

—(7

MOP

A

PB V

4

AZ7

INHB S

1

PBVN

k

A

A2O

MOP

'

.1

"

— )!Z

9

A

AZ7

*,

A

G5VN

MOP

A34

Y1

i

~13

A

^£ -i

]

r

^

j I

^f 1 j

4,

3

1

iJ

5

f

11

f

^G⁶^V xr,

,

8 A27

-

J,

[

L

a.

~|9

A

A2G

~~ts-

A

[2

-"

i

_A₁ o

6

5

^] d

]

J TP

Q

s ,

= *

TP9

Figure 10-13.

Memory Timing,


SINKN

SINK

10-46

G7VN

V4 MOD 7

UTRV

SL.D N

NOTES:

1

.

SYLC1N

PBV

»

GGV — K

13

-

RD

G7VN

2

A

A2

A

A9

Z7 -

1

i

²

PCV

CSV

G7VN

—13

A

A.Z

V4 MOD 7 - ~1 ⁹

8.

f

A

AIO

1 ⁸

-b-

A

All

G7VN

EXMVN

SVI.C1N


1

IS

!j

315

AIO

3

1

1

All

,

5





SYLIKl

SYLON

CONNECTOR PINS

Pin

Siqnol

Pin

Signal

1

CSTN

51

3

G1VN

.53

Yl

5

HOPV

55-

SYLON

7

OP4V

57

PAVN

9

59

SYLIN

11

PCV

61

Z7.

-

13

C5T

63

PBVN

15

UTRV

65

RD

17

STOVN

'

•,67

G2VN

19

RUNN

69

INHBS

21

HAL TV

71

23

RUN

•

•

-73

25

OP2VN

:

75

27

TTLV

77

PBV

29

INTV

79

PCVN

31

SYLCI

'81

TR'l 3V

33

G6V

83

35

EXMVN

85

G3V

37

X4

•

87

39

OP1VN

89

XN

41

OP3V

91

43

TR4V

93

45

G7VN

.

95

EXMV

47

RUNVN

97

GSVN

49

THRU PINS

Pin

Sianal

Pin

Signal

1

PAV

16

PCV

2

PBV

17

G3VN

3

RD

18

G1V

4

G7V

•'

.

19

SINK

5

20

6

G2V

21

G4V

7

22

8

G2VN

23

PAVN

9

24

XN

10

VI

25

V3

11

26

12

SIGRET

27

13

28

G6VN

14

29

15

30

V4MOD7

Figure 10-13.

Memory Timing,


10-4-7

SINK

h/FFVN

MSSVN

Figure 10-13.

W3

SYNCN

SYMC

SYNC-

vt

coc-

¹³

VI—TS

8

A

AS

"

N

⁼ t5~

A

X4-

13

~|10

A

A4

.-U

J

EA.C

V4 MOD7

/ -

8

r

i

i

la

~~1 ³

A

A17

-Is-

A

A18

^Z^S ~110

eec

EBP^ ^

^fâiAel ^tô

NOTES:

³

3

AB

r

A

4

5

§_

i

TF

i

â

e

1

At

7

S

I 5

A1B

TP4

"— H

CMC

CNCN

MAO

MBO

}

See Glossary or Index for Signol Definitions

2.


3.

Dotted Line (if any) Indicates Infernal ULD Connection

4.


5.


Memory Timing, Logic Diagram (Sheet 3)

10-48

"—110

CMC — S

A

A 3

VI-

e

f

L

v,

l~

u

CNCN

Y3-

—

~l»

A

A3

"3"

A

~l«>

A

A

2

YNCN

A

A

3

PAV

G3VN

G4V

7

1

L^

HA 3

r- ,

I

5

'

—-r-coc

M^F"*-

_P_A_Z

I

£

TP 7

^J 9

COCN

RDM

RDMN

THRU PINS

Pin

Signal

1 PAV

2 PBV

3 RD

4 G7V

5

6 G2V

7

8 G2VN

9

10 VI

11

12 SIG RET

13

14

15

Pin

Siqnal

16

PCV

17

G3VN

18

GIV

19

SINK

20

21

G4V

22

23

PAVN

24

XN

25

V3

26

27

28

G6VN

29

30

V4MOD7

TER

TE.R

PAV

Z

421

Y3

13

G3VN

G4V

!g

1

A

A 14

RD

Z

A

PBV

AZO

Y3

— 17

G3VK 4

12.

A

AM

GEV

RD

iV

^lâ -

Y3

PAVW

PCV

2.

¹⁰

—

13

A

A

7

&2VM — 14

Giv — 54

RD

XM

li

V1

J

P

I

A

A

7

~~l»

A

A^ l

"l

J

a

«! _i

5

14

1

14

J

TfS

RE.CN

I

All

TP1

5

TIMEM

I

~!LL

₁₉

La

A

J

I

5

TIME

A£0

A20

CONNECTOR PINS

Pin

Siqnal

Pin

Signal

2

G3VN

52

SYNC

4

54

Y3

6

DMA

56

EAC

8

CNC

58

MTT

10

60

MTTVN

12

V3

62

Z5

14

VI

64

GIV

16

PAV

66

MSSVN

18

RDM

68

TER

20

70

G2V

22

RDMN

72

EBC

24

IMA

74

1MB

26

MSS

76

G4V

28

MBO

78

SYNCN

30

G7V

80

EBP

32

MFF

82

TLC

34

MAO

84

G6VN

36

W3

86

MFFVN

38

X4

88

ZN

40

90

SIG RET

42

92

MZOVN

44

EAP

94

DMB

46

TIME

96

V4MOD7

48

RECN

98

MZO

50

COC

Figure 10-13.

Memory Timing,


10-49

W3

•EDACIM

•EDAC

W3

coc — » FSAN— IMA — *

&

A

A3Z

14

W3- ~~I3

CN4C

PSA

IM A

VI

1

8

"

13

A

A32

A

AZ5

H9

A

AZ5

SYNC

IM A

J)

-ty

_A

A16

]3£

-

-

—)7

A

A) 3

VI- ~13

HOPV

RUNVN

&

-

^r A

A13

!2

IZ

—

0,

3.

3

I 5

AZS

TP

i

3J

I

|A18|

[5 ,

O

TPS

EIACN

E.IAC

E.ADM

W3-

-

DMA-

EAIM

W 3

!

IMA

!

V4 MOO 7

V4 MOD7

8

L

E.ADMN

W3

S

DMA

•

W3

IMA-

EAIMN-

AG

AG

A

A13

-fsr

i §

^ A13

A _a

A14

I 5

A14

BRAO

BRAON

EDOX

EDOY

MZO

V4MOD 7

17

V4MOD7-

DMAVN—

~^—

DMAVN

^

IMAV N

IMAVN

V4 MOD7-

SYNCN

—

-M05YN

V4MOD7-

MTTVN

&

—I ³

A 9

A34

—]io

A 7

A33

rî

A33

NOTES:

FSAN

FSA

See Glossary or Index for Signal Definitions See Logic Symbols Appendix for Definition of Logic Symbols

3 Dotted Line .if any) Indicates Internal ULD

Connection

4 "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate It

5 Prefix Reference Designations as Follows: AT A16A

[3

I

LA33

-MZSYNC

Figure 10-14.

Memory Error Detector, Logic Diagram (Sheet 1 of 8)

10-50

EAR

DMA

TIM E

EDAC

E7

S

ii

â

VI-

A

A 3

~~P9

A

A17

14

T^

VI

13

- —

e

A

A1O

— 13

A

A1O

1Z

3

A1O

TP9

o

EA1MN

VI"

&.

EAPN-J2

H7-

1

*

EDACN

TIM E

DMA — â

\$

A

A3

A

A

Z

~l ³

A

A

3

IMAVN

EDACN

EIACN

DMAVN

V1-

- —

-

VI-

^S

T1O

A

AZZ

A

AZ3

—)io

A

A15

^

A

A15

V4MOD7

1 ₇

DMAVN) —

7

!f

¹ d

r* _z

¹

±

1Z

^J Is

X

A15

-— EÔM

4

TP7

-EAC

DMAVN

IMAV N

TP5

EAIM

DMA

IM A

E.APN

CONNECTOR PINS

Pin

1

3

5

7

9

11

13

15

17

19

Signal

YN

MZO

ED2X

ED2Y

MTT

V3

VI

EDOX

EDOY

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49 COC

ED6X

ED6Y

MSS

ED4X

ED4Y

MFF

MZOVN

W3

EAC

HOPV

RUNVN-

EAP

TIME

RECN

Pin

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

Signal

SYNC

Y3

DMA

MTTVN

27

CNC

DMAVN

MOSYN

M2SYNC

IMAVN

IMA

SYNCN

BRAO

BRAON

MSSVN

MFFVN

M4SYNC

SIG RET

M6SYNC

EAM

V4MOD7

IMAVN

EAM

THRU PINS

M4SYNC

Pin

Signal

Pin

1

16

2

17

3

18

4

19

5

20

6

21

7

22

8

23

9

24

10

25

V.SSVN

M6SYNC

11

26

12

27

13

28

14

29

15

30

Signal

Figure 10-14.



10-51

coc

FSBN

DMB

CNC

FS3

DMB

W3 —

EBDM- ¹³

0MB

EBIM

1MB

_- AC

y/3-

V4 MOOT

e

V4MOD7

L|

A L.

A13j

.'

!}

A

A14

W3

E.BDMNI

V4MOO 7-

*

- V4 MOD 7 ~~11O_

DMBVN

IMBVN

SYNCN

V4 MOD 7

_M_H_O_V_N

₁₁₃

La

3

•EDBCN

EDBC

i

AI3

5 BRBO

I 5,

A)4

BRBON

Ml SYNC

COC

FSBM

E.IBCN

ELIBC

FSBN

FSB

NOTES:

1




4. "N.U." Indicates rha: ULD is Not Installed although Page is "Wired" to Accommodate It


V4MOD7

OMBVN

IMBVN-

V4 MOD 7

SYNCN-

V4 M OD 7

MTTVN

_A₃₃

-M3SYNC

Figure 10-14.

Memory Error Detector, Logic Diagram (Sheet 3)

10-52

Z7

E.BDMN

ELBDM

EBIM N

EBIM

IMBVN

E.DBCN

E.IBCN

DMBVN

v—lio

-eac

_M_F_F_V_N

MSSYNC

V4 MOO 7 - DMBVN

IMBV N V4 MOD 7-

²

—I ³

/^7

—lio

5YNC N

â

A

A35

9

V4MOD7 -

MSSVN

—is

A -M1SYNC

A35

A3S

DMBVN

—

IMBV N

EBP-

THRU PINS

'

-ELBM

Pin

Signal

Pin

Signal

'

1

16

2

17

3

18

4

19

5

20

6

21

7

22

8

23

9

24

10

25

11

26

12

27

13

28

14

29

15

30

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

52

RECN

4

V4MOD7

54

TIME

6

EBM

56

EBP

8

M7SYNC

.

58

RUNVN

10

SIG RET

60

HOPV

12

M5SYNC

62

EBC

14

MFFVN

64

W3

16

MSSVN

66

MZOVN

18 .

BRBON

68

MFF

20

BRBO

70

ED5Y

22

SYNCN

72

ED5X

24

74

.MSS

26

1MB

76

ED7Y

28

IMBVN

78

ED7X

30

M3SYNC

80

32

M1SYNC

82

EDIY

34

DMBVN

84

ED1X

36

CMC

86

VI

38

27.

88

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92

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94

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Figure 10-14.



10-53

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10-54

NOTES:

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5

BRA3

55

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7

BRA4

57

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9

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11

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61

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13

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63

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15

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65

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17

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67

19

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69

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21

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71

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23

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73

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25

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75

27

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79

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81

33.

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37

87

39

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91

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10-56

NOTES:

1

.

See Glossary or Index for Signal

Definitions





rt/7

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CONNECTOR

PINS

Pin

Signal

Pin

Signal

2

EBP

52

4

54

6

56

8

58

V.I

10

60

12

62

14

64

V3

16

BRB13

66

SIG RET

18

68

BRB7

20

BRB13N

70

BRB5

22

BRB14N

72

BRB7N

24

74

BRB5N

26

BRB14

76

BRB6N

28

BRB11

78

BRB8N

30

BRB9

80

BRB6

32

82

BRB3N

34

BRB9N

84

BRB1N

36

BRB10N

86

BRB8

38

BRBUN

88

BRB2

40

BRB12N

90

BRB1

42

PB01

92

BRB4

44

BRB10

94

BRB3

46

BRB12

96

BRB2N

48

98

BRB4N

50

Figure 10-14.



10-57

RUNVU

Figure 10-15.

Transfer Register Bits 1-9, Logic Diagram (Sheet 1 of 4)

THiN

Tflt

10-58

7V?J/V

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

SIG RET

51

3

53

BRB1

5

55

BRA1

1

57

AI1V

9

59

11

61

G6VN

13

63

RUNV

15

65

G7V

17

67

TR1N

19

69

MD2V

21

71

G1V

23

73

SRTR

25

75

PAV

27

TR3

77

DIN

29

79

RUNVN

31

81

PBVN

33

83

PCV

35

85

G1VN

37

VI

87

G7VN

39

BRB2

89

V4MOD2

41

BRA3

91

TR1

43

93

TR2

45

BRA2

95

W6

47

BRB3

97

STO

49

THRU PINS

Pin

Slqnol

Pin

Sianal

1

SIG RET

16

TR3DN

2

TR3D

17

-3VDC(V3)

3

TR7

18

Y4

4

TR5

19

X8

5

TR4

20

6

TR9

21

V)

7

V4

22

8

TR6

23

9

24

CLTR

10

25

TBR

11

26

MBOV

12

27

SRTR

13

28

n

14

29

MAOV

15

30

NOTES:

1 See Glossary or Index for Signal Definitions


of Logic Symbols


Connection


although Page is "Wired" to Accommodate it

5. Prefix Reference Designations as Follows: Al A18A

Figure 10-15.

Transfer Register Bits 1-9, Logic Diagram (Sheet 2)

10-59

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10-60

NOTES:

1

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rff

Tf>

9


7K6OH


of Logic Symbols


Connection


5. Prefix Reference


Tfl

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

TR6

52

Y4

4

TR4

54

BRA7

.

6

SRTR

56

BRAS

8

58

BRA9

10

60

BRB9

12

62

AVN

14

64

EXMVN

16

TR5

66

X5

18

68

TBR

20

70

BRB7

22

72

BRB8

24

X8

74

TR8

26

BRA4

76

28

BRAS

78

30

MAOV

80

TR7

32

BRB5

'82

TR9DN

34

6RA6

84

36

G5V

86

TR9

38

88

40

CLTR

90

42

BRB6

92

44

MBOV

94

TR9D

46

BRB4

96

W6

48

INTV

98

Z2

50

G3VN

THRU PINS

Pin

Signal

Pin

Slqnol

1

SIG RET

16

TR3DN

2

TR3D

17

V3

3

TR7

18

V4 .

4

TR5

19

X8

5

TR4

20

6

TR9

21

VI

-

7

V4MOD2

22

8

TR6

23

9

24

CLTR

10

25

TBR

11

26

MBOV

12

27

SRTR

13

28

Z2

14

29

MAOV

15

30

Figure 10-15.


10-61

TRSV

^Z⁽ —C5.

131

12

All 13,

VI—19

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Figure 10-16.

Address Register and Memory Address Decoder, Logic Diagram (Sheet 1 of 4)

_A_H

TP1

TP15

AZN

_a A8 N

10-62

21

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Figure 10-16.

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31 5

A

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"

Pin

Signal

Pin

Signal

1

AX6N

51

3

AX4N

53

Y4

5

A3V

55

OS4

7

57

A8

A3N

9

SIGRET

59'

IS4

11

V3

61

Zl

13

AX2N

63

15

65

TR1V

17

AX7N

67

19

V4MOD6

69

TR6V

21

AX3N

71

A3

23

TR8V

73

A9

25

AX1N

75

27

A2V

77

29

A1V

79

TR2V

31

AX5N

81

TR7V

33

EXMDN

83

G6VN

35

AXON

85

A7

37

87

39

TR9V

89

41

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91

43

A l

93

45

A2

95

47

VI

97

49

THRU P.INS

Pin

Signal

_P_i_n

Signal

1

16

2

17

S4

3

18

4

19

5

20

6

21

TA

7

22

8

23

S4N

.

9

24

G1V

10 25

A7N

11

26

EXMV

12

27

13 28

14 29

A8N

15

30

NOTES:

1

.






Address Register and Memory Address Decoder, Logic Diagram (Sheet 2)

10-63

^T^R⁵^V

TR5 V

V4 MODS

EXMV

Figure 10-16.

A4AN

Tp a

A4N

TR4V

TA

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12

1

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A

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10

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A

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A.26

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s.

s

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A4 N

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A7V —

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I

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ll

3

A1O

I

A17

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5.

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5,

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A

A24

8

M

AYO N

AY3N

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>! ASN

10-64

TR3V

TA-

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Z2—110

TA

V4 MOD6-

A4V -

T10

A5N

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AG N

Â

A30

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A4N

A5N—SA

2J—1~1.

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A4V-

ASV

ASV

S4

Figure 10-16.

ACAN

AY7N

AXIOM

AXBON

_T_P₁

AGN

-AY2N

P-AY5N

CONNECTOR PINS

Pin

Signal

Pin

Signal'

2

AX7ON

52

4

A7V

54

Y5

6

ASV

56

A6

8

AX10N

58

10

AX5ON .

60

TR5V

12

VI

62

Z2

14

51G RET

64

G1V

16

PAV

66

AY7N

18

AXOON

68

A5

20

V4MOD6

70

22

AX4ON

72

A4V

24

AX6ON

74

AY5N

26

TA

76

AY4N

28

AX2ON

78

AY3N

30

G7V

80

AY1N

32

WN

82

,

ASV

34

G6V

84

A YON

36

EXMVN

86

Y3

38

X5

88

40

AVN

.90

42

AX SON

92

'

AY2N

44

TR4V

94

A6V

46

TR3V

96

A4

48

G5VN

:

98

AY6N

50

THRU PINS

P,'n

S ignal

Pin

- Signal

1

-16

"''.'

'

•'.'"•;

2

17"

•

-"54

-

"'

3

-

18

4

19

5

20

6

21

TA

7

22

8

.-

23

S4N

9

24

G1V

10

25

A7N

11

26

EXMV

12

27

13

28

14

29

ASN

.

15

30

NOTES:

1

2.

3.

4.

5.







10-65

PBV

1

L

J

A17

I

A

Aie

A Aia ^J

A(7

I

Aia ⁵^, ^_

(

TPS

I SI

IStN

PBV

C6V

HOPV

&7VM

Z1-

.

â

V1-

e

q

G7V— a

A

All

A

A.4

3

A

A S

ll

A 1

A

S

1Z

ISS -

GGV-

G~7VN-

Z l

An

C4VN

8

A

AS

Gj

-tr

A

A l

21 —]7

A

A3

DSS-— £

C5VN— £

GSV

U

VI-

8

A

AZ3

WN Qî

|A30

CDSV

PCV

. Jg-lio

u

A

A3O

*

U

1

I

3|

M

Z!

PBV— GW —a -1

I5S — S

I

AS

5 053

DS3N

1 5_

A l

DSS — ^

- 23

1 GGVN

T ?l

I

IAZS

I

• >

DSS

DSSN

G7V

j—110

[A30

-17

A1Z ⁱ^l

A

1

TRSV^

^

A

AZ9

£1

VI- ~1»

6

A

A3)

X

1

|AJ:

E

IS S

I

A 4

5 ISZ

I £.

A S

(

1

TF ^S U

1SZN

DS4

DS4N

DS1

CDSV-

G3VN-

G4V-

VI

"Iff

A

A3Z

1*

X3

— I'o

HOPV-— ¹³

A

A32

TRSV

—

A

A?)

IZ

»

rJ

3|

I S

]A3Z

ISS N

TPZ

DSIN

DSS

^Z J-|3

V—19

r

u

A U

A16

-tr

A

A 3

21

—110

1

S

3

Figure 10-17.

Memory Sector Registers,


I

Ate

i

A 3

5 DSZ

5,

O

TP3

DSZN

10-66

Sfl

intr

1*1

iBTJl

i

1

PBV

^z :^3

1

_A

,

HOPV—* A1Z 1

I

_c -,v_!3 * pL

VI

"

VI

1

'

1

6 A

AS

1

1

1

3 I

AS

5

1

A13 "T ~ A13 ""

CIVN^ 5 A*|«»"

v

HOPV—!2^ _C Z,

VI

1

. _T _ ,

8

A

3

l

&

Î^S³

|

AZ 6

AZ 6

1

'

1

• ISJI

IS 4

f4

Î^S ³

^k A Â ZS- f i ⁸ —" *

N

" ^V —

11 A

,— J

n

A13*

Z<-|3

1

™^L\"

IS<;

•> A13

o

^T^P '°

^V³ -TIO_

A

AZO

*«**—

TBRV

MAOV

EXMV

BRB8

if

»

û

A

A33

Y5 —IID

â

A

AZ7

TBRV — §

MBOV

»

EXMV

û

VI

L"

TA— *

EXMVN — —

A.

A34

—

, _s

A

-N-

A

A27

—17

A

A3S

r-J

_I_s_s ^3gZ

l

T * f

z'-isH

«vN=fr£J

G3V

2|AZ4

^B^R ^—

V5-

—I'o

A

Ail

I

TBRV

MAOV

EXMV

BRB7

1

1

*

A

.A33

—|IO

A

AZB

YS

S

TP8

O

^lⁱ _A £ ₀ ⁵ — -DS1WN

TBRV

MBOV

E.XMV

4

¥ a

VI

r§

1

1 VI

A

A34

"19

A

A21

f,

)

U I 5 _

AZ1

1

a 1

3 I

A27

5 ,

nî u

EXMVN

L ^Q

~J

A 3

1

a

A28 J A28

~)3

A

A35

5

o

1

D52MN

CONNECTOR PINS

THRU PINS

Pin

Signal

Pin

1 PCV

3 G4V

51

53

55

57

V3 59

5 G3VN

7 DSSN

9

11 SIG RET

13

15 G2VN

61

VI 63

65

67

69

17 G3V

19 DSS

21 G5VN

73

25 G4VN

27 G5V

29 G7V

31

33

35

37

39

41

43

45

47 97

95

93

23 CDSV

75

77

79

71

81

83

85

87

89

91

WN

G6V

ISSN

X5

PBV

TRSV

ISS

G7VN

49

Signal

Pin

Signal

1 DS2M

2 EXMV

3 DS1MN

4 TA

5 DS1M

7

8 IS

IN

Y5

DS4

HOPV ••

IS4

Zl 6

G1V

MAOV

G1VN

G2V

10

9

TBRV

MBOV

BRB8

BRA8

G6VN

11

12

13

14

15

NOTES:

Pin

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Signal

DS2MN

DS1

EXMVN

DS1N

DS3

DS2N

IS3

IS2

IS1

IS2N

DS2

DS3N

IS3N

1

.


2. Sec Logic Symbols Appendix for Definition

of Logic Symbols


BRB7

BRA7

Connection




Figure 10-17.

Memory Sector Registers,. Logic Diagram (Sheet 2)

10-67

V4 MOD 6 -

DSIN-^

CS2N —

DS3N —

V4 MODS-

A3PADN

^

DS1N

DSZN-

DSEMN

V4 MOD S -

1

*

*

^K

—]3

A

A3PAONI

DS1

DSZN

D53N

A2Z

L

A r.

A30

V4 MOD £ -

—]3

PAD

IS 1

1

1

I SEN < a

IS3N

H

A

A 23

A

A3O

n

^J 3

I

A30

TPE

AVION

A U

!i

A 5

V4 MODS-

"1 5

IS 1

IS2N

1

§

is a —-

A

A

4

PAD

-

A

A

5

P

r ¹

V4 MOD € -

EX.MD

DS1M

â

-

A

—|io

A14

TPI3

DSEMN

A 5

AI4

!L^>L AYSON

-3

I

A14

Figure 10-18.

PADN

PAD

EXMD-

PAD-

A3-

A3PADN

NOTES:

1

.






Hi-Y Memory Address Decoder, Logic Diagram (Sheet 1 of 2)

10-68

V4 MODS

DS1N

DSZ

053N

STM

iU

ft

«

A9PADN-

V4 MODS

A3PADN

TP3

AY3ON

V4 MODS

13

V4 MOD £ -

—17

A3 PADN

DS1N

•

^D^S^T

DS:

8(~T~

^

*•

A9PA.DN

DS1

DS2

DS3

TA'

E.XMVN

DS1M

DS2M

E.X.MDN

THRU PINS

EXMV- Pin

Signal

TA-

] DS2M

2 EXMV

3 DS1MN

4 TA

5 DSIM

6

7

8 IS1N

9

10

11

12

13

14

15

Pin

Signal

16

DS2MN

17

DS1

18

EXMVN

19

DS1N

20

DS3

21

DS2N

22

IS3

23

IS2

24

ISI

25

IS2N

26

DS2

27

28

DS3N

29

ISSN

30

4

^ f

1|

«

A

1

AZO

TPI7

AY7ON

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

AY5ON

52

V ]

4

AY7ON

54

Y5

6

AY4ON

56

A9

8

AY6ON

58

10

60

12

62

Zl

14

DS2M

64

G1V

16

PAV

66

18

DSIM

68

AY20N

20

V4MOD6

70

AVION

22

IS3

72

AY3ON

24

DS3

74

26

TA

76

28

DS2

78

30

G7V

80

AYOON

32

82

IS!

34

EXMDN

84

G6VN

36

EXMVN

86

38

88

V3

40

EXMD

90

SIG RET

42

EXMV

92

44

IS2

94

46

96

48

98

DS1

50

Figure 10-18.

Hi-Y Memory Address Decoder,


10-69

Figure 10-19.

A3V5MOD1

.

1

g.

/o

«

/4

a

W

ii

H

s

I"

-#

8

—io

Ii

14

C1

A1

Cl

Cl

A.I

Cl

J

\

5

r

i

i

r

•

3

/

^j /

^

NOTC.I.Z

)

.1

7

I

,7

j-

^

«

e

Cl

Cl

Cl

*I4

Cl

a Ail

10

If

14.

Cl

AS

i

f

t

I

MSVBZ i

p^

r

7

7

7

7

CZ

fa

Ci

A^^

C2

A3

Cl

AZS

C3

A10

C3

Alt

8

a

a

«

8

a

\

TP 5

\

TP«

f

7P 7

\

TP8

f

TP9

I

7

Cl

*IS

n ci

A 13

;

>

7

r

Ct

A16

Ct

430

C3

An

CJ

431

a

%n

/2

14

a

16

if

It

7

⁷

&_^

6

6

f

0

a

-SJG

RET

Decoupling Capacitors (Channel 4), Logic.Diagram (Sheet 1 of 4)

10-70

^lf.

^p y

NOTES:

1

.

7

7

7

7

7

7

f«f

All

C4

Ail

Alt

Alt,

CJ

Ali

C J

Ail

8

[

TP11

ff

1

«

TPtZ

\

TPI3

«

I

7

'

7

>

C4

A IS

C4

til

C4

C4

A33

»

'

TPf4

1

'

C3

\AIO\

TP15

I'

C J

AJ4

8

6

a

a

V

See Glossar) ^ or

Index for

Signal Defini



4. "N.U." Indicates that ULD is Not Installed although Page Is "Wired" to Accommodate It


CONNECTOR

PINS

Pin

Signal

Pin

Signal

1

MSVB1

51

SIG RET

3

MSVB1

53

SIG RET

5

SIG RET

55

SIG RET

7

S1G RET

57

SIG RET

9

A2V5MOD5

:59

SIG RET

11

V3

61

SIG RET

13

V3

63

V3

15

V3

65

V3

17

V3

67

V3

19

A3V5MOD1

69

V3

21

V5

71

SIG RET

23

V5

73

VI

25

V5

.

75

VI

27

V5

77

VI

29

A3V5MOD3

79

VI

31

VI

81

SIG RET

.

33

VI

83

SIG RET

35

VI

85

SIG RET

37

VI

87

SIG RET

39

A3V5MOD4

89

SIG RET

41

SIG RET

91

SIG RET

43

SIG RET

93

SIG RET

45

SIG RET

95

MSVB2

47

SIG RET

97

MSVB2

49

A3V5MOD5

Figure 10-19.


10-71

A

/f

1V5 Ml 001

1 VSMOC •

—

A1VSMOD5

A

I V5 HIOH 3

A 2 Y!, HIOD4-

ft

10

11

_&

e

16

li

It

g

fi

_Ji

a

to

11

'+

g.

to

/f

•4

g :

10

11

/*

a

—To

li

14

A l

d

At

( j

Ct

ff

C7

Nore. i

;

j

s

7

3

s

7

1

3

1

J

1

)

^f 7

1

f

f

•f

}

S

7

1

T

s

7 o TPI

ViO

S/6

Figure 10-19.


10-72

Tfll

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

V3

52

V3

4

V3

54

V3

6

V3

56

V3

-

,

8

V3

58

,

A1V5MOD5

TPI3

10

A2V5MOD4

60

VI

12

VI

62

VI

14

VI

64

VI

16

VI

66

VI

18

VI

68

SIG RET

20

SIGRET

70

SIG RET

22

SIGRET

72

SIGRET

24

SIGRET

74

SIG RET

26

SIGRET

76

SlGRET

.

.

28

SIGRET

78

A1V5MOD4

30

VI

80

V5

TPIS

32

VI

82

V5

.

34

VI

84

V5

36

VI

86

V5

38

A2V5MOD3

88

A1V5MOD3

40

SIG RET

90

V20

42

SIGRET

92

V20

44

SIG RET

94

V20

46

SIG RET

96

V20

48

A2V5MOD1

98

A1V5MOD1

50

V3

NOTES:

SIG f?£T






Figure 10-19.


10-73

AfYSMODS

A3VSMODS

JIPIO

⁽³⁾

(7 )

j/r&taPS-

'SMOIO -

A1W4 -

NU

>1SF~

a r\eJ-

NU

. 13

(.Jl-

t.3

/ 8

NU

(57;- -OTP/f

-*4

u &— AISTOVN

I

NU

A f

l/ _r lU2^-'

lj^f-H5^-w

AfSI-tF -

(87)-

4

^NÛ

NU

Figure 10-20.

Operation Code Voters, Logic Diagram (Sheet 1 of 4)

41SHFV

1.8 CtM

(77)

(«l)

/.jfNU

10-74

AirsMOOs trysts

A&S4tO03

AIM

₄ _N_U /y

j

NU

XJ/J ¹

NOTES:


2. See Logic Symbols Appendix for Definition " of Logic Symbols

3. Dotted Line (if any) Indicates Infernal ULD Connection



1

.

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

A3V4MOD5

51

3

53

5

A2V5MOD5

55

7

57

9

A1PIO

59

A1STON

11

A1V5MOD5

61

V3

13

V3

63

VI

15

VI

65

SIG RET

17

SIGRET

67

AIPIOV

19

"69

21

A1HOPV

71

23

73

V3

25

75

VI

27

77

29

A3V5MOD5

79

A1SHFV

31

A2V5MOD5

81

33

A1V5MOD5

83

A1W4

35

A1X1

85

SIG RET

37

87

39

89

41

A1HOP

91

A1SHF

43

A3V5MOD5

93

45

A2V5MOD5

95

A1STOVN

47

A1V5MOD5

97

49

A1W4

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

2

SIGRET

17

3

VI

18

4

V3

19

5

20

6

21

7

22

8

SIG RET

23

9

VI

24

10

V3

.

25

11

26

12

27

13

SIGRET

28

14

VI

29

15

V3

30

Figure 10-20.

Operation Code Voters,


10-75

JtVSMODS

AJVSMOD^.

A3\&*OO5

xl/OPIN

Figure 10-20.

Operation Code Voters,


(48)

10-76

s

t)

f t

.,,nn»u

(L,t)

CM)

Figure 10-20.

- ;.

-

/

'

f ?

>

/O

^

NU

N

6

#

V

⁴ i

6

/

/ «l

r*

rA

t

AH

>J

7 '\>

NU

4 _?_s

^/^J

I

»l

NU

_J_^₇ ^/^/

n TP ₁

S Kf

£3

| r

⁷ ^NÛ ^C «

ê ^NÛ ^--(,9)

A1VV4 —| .

t;

t°

I".

NU

T- ⁽^M^l ? ⁸⁾ H,

f

2

7

/>»

XV 'f

81'

r^

/y

f »l

NU ^J

tf *7

A _t_O ^-^/OP3V

S_ NU

_-_< ₃₀

^_

kk

NU

^</

/j

r

NU ^

(_48)

CONNECTOR

PINS

Pin

Signal

Pin

Signal

2

NU1

52

4

NU2

54

6

NU3

56

8

A10P3

58

10

60

A10P2VN

12

62

A10P3N

14

A1W4

64

16

A10P3VN

66

18

68

A10P2N

20

70

22

A10P2

72

24

74

A1W4

26

76

28

A1W4

78

A1W4

30

80

A1V5MOD5

32

A10P2V

82

A2V5MOD5

34

84

A3V5MOD5

36

86

38

88

40

A10P3V

90

A10P1VN

42

92

AIOPJN

44

94

46

A10P1V

96

48

98

50

A10P1

THRU PINS

Pin

Signal

Pin

Slqnal

1

16

A3V5MOD5

2 .

SIGRET

17

NU)

3

VI

18

NU2

4

V3

19

NU3

5

20

6

2!

7

22

8

SIGRET

23

A2V5MOD5

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

A1V5MOD5

NOTES:






1

.

Operation Code Voters, Logic Diagram (Sheet 4)

10-77

AtrSMODI

AfYSMOOl

A3¥S#ODI

AIY2

4166

(3)

(7)

\

NU

A*

NU

NU i

a

TP9

.JI,

\

S3)

1.8

a?)

(70

13 («)

LjfN U

I.

i4JS

â

tf—

4/66N .

t»7

CJ1>

)

•

NU

_ it,

51, S3

g^/^

-0/-PS

^

//r/U . fJ_

AIf

^

J

NU g.

NU

(^

1.8 CIM

NU

Figure 10-21.



10-78

4W54tat>l

Ail/SMOfil

ASt&MOfl

A1Y2

NOTES:




4. "N.U." Indicates that ULD is Not Installed although Page is "Wired " to Accommodate It


1

.

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

A3V5MOD1

51

3

53

5

A2V5MOD1

55

7

57

9

A1G6

59

A1G3N

11

A1V5MOD1

61

V3

13

V3

63

VI

15

VI

65

SIG RET

17

SIG RET

67

A1G6V

19

69

21

A1G7VN

71

23

73

V3

25

75

VI

27

77

29

A3V5MOD1

79

A1G6VN

31

A2V5MOD1

81

33

A1V5MOD1

83

A1Y2

35

A1Y2

85

SIG RET

37

87

39

89

41

A1G7N

91

A1G6N

43

A3V5MOD 1

93

45

A2V5MOD1

95

A1G3VN

47

A1V5MOD1

97

49

A1Y2

THRU PINS

Pin

Siqnal

Pin

Siqnal

1

16

2

SIG RET

17

3

V

]

18

4

V3

19

5

20

6

21

7

22

8

SIG RET

23

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

V

I

29

15

V3

30

Figure 10-21.



10-79

t'VSMODl

A3IKW.*

/f/EXM -

m£

A1X3-

fjN U

SM7

1_

NU

— ^/EXMV

NU

^fNuUe—4lNu JL ₍_?_t₎

C7Z)

(70)

4/TTI

(efc)

^r^j

4 ^

ifN U

^M^> ,j

^

^~ ^NÛ

_J_.₄_/_S

zisJ

i NU

NU

/ j

⁷

TNU

/

7 NU

/</EVMVI

⁷ ^W

• >?/TTLV

(34)

NU

.£_

₍_J_O >

rîu^pL^j

|_ DDI

_

_ 1

' / ^.5 N

Figure 10-21.

Timing Gate and Operation Code Voters, Logic Diagram (Sheet 3)

-f C

-f 0

-JF

10-80

Ft

Figure 10-21.

CONNECTOR

PINS

Pin

Signal

Pin

Signal

2

NU1

52

4

NU2

54

6

NU3

56

8

AUNT

58

10

60

A1EXMVN

12

62

A10P4

l"4

A1W2

64

16

A10P4V

66

18

68

A1EXMN

20

70

22

A1TTL

72

24

74

A1W2

26

76

28

A1W8

78

A1X3

30

80

A1V5MOD5

32

A1TTLV

82

A2V5MOD5

34

84

A3V5MOD5

36

86

38

88

40

A1INTV

90

A1EXMV

42

92

A1EXM

44

94

46

A10P4VN

96

48

98

50

A10P41

THRU PINS

Pin

Signal

Pin

Signal

1

16

A3V5MOD5

2

SIGRET

17

NU1

3

VI

18

NU2

4

V3

19

NU3

5

20

6

21

7

22

8

SIG RET

23

A2V5MOD5

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

A1V5MOD5

NOTES:






1

.



10-81

A! V5MOOI

Â^f^Y^S^MÔ^W

A3t5*OPi

A2V2

or

NU

NU

AMMOD3 ~

MZZ

—

J/ACC/ ~

(55)

~

,if

Figure 10-22.

7P9

3 "CI 6,13. ₄_I_G_I_V

rj

Lg_

|

NU

(,g

j NU »i*? _r

n,)

. —

( 2.7 )

-oTPIl

Z-",

^—/!ACCIV

/ NU

_L

tf—

A/GIN

C8T>

(8 ¹ *)

rH

MI

,

ÎNU

hi

^

(51,53)

Atf

NU

^NÛ

f.fJ

(80

>.S NU

A7

Timing and Add-Subtract Voters,


10-82

JW5*fOt>/

A!i>5At00l

ASf5#ff0/

A2Y2

Jf

NOTES:




4. "N.U." Indicates rhat ULD is Not Installed although Page is "Wired" to Accommodate It


Figure 10-22.


CONNECTOR PINS

Pin

Signal

Pin

Signal

1

A3V5MOD1

51

3

53

5

A2V5MOD1

55

7

57

9

A1G1

59

A1ACC1

11

A1V5MOD1

61

V3

13

V3

63

VI

15

VI

65

SIG RET

17

SIG RET

67

A1G1V

19

69

21

A1G2VN

71

23

73

V3

25

75

VI

27

77

29

A3V5MOD1

79

AJG1VN

31

A2V5MOD1

81

33

A1V5MOD1

83

A1Z2

35

A2Y2

85

SIG RET

37

87

39

89

41

A1G2N

91

A1G1N

43

A3V5MOD3

93

45

A2V5MOD3

95

A1ACC1V

47

A1V5MOD3

97

49

A2Y2

THRU PINS

Pin

Signal

Pin

Signal

1

16

2

SIG RET

17

3

VI

18

4

V3

19

5

20

6

21

7

22

8

SIG RET

23

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30


10-83

<"l/3V00;

^; 2V5MOD?.

A3YZ,VOO*

Figure 10-22.



10-84

CONNECTOR

PINS

Pin

Signal

Pin

Signal

'i

NU1

52

4

NU2

54

6

NU3

56

8

A1AI1

58

10

60

A1AI2V

12

62

A1AI3N

14

A2Y2

64

16

A1AI3VN

66

18

68

A1AI2

20

70

22

A1AI3

72

24

74

A2W8

26

76

28

A2W2

78

A2W2

30

80

A1V5MOD3

32

A1AI3V

82

A2V5MOD3

34

84

A3V5MOD3

36

86

38

88

40

A1AMV

90

A1UTRV

42

92

A1UTR

44

94

46

AIAI2VN

96

48

98

50

A1AI2N

ft-

THRU PINS

Pin

Signal

Pin

Signal

I

16

A3V5MOD3

2

SIG RET

17

NU1

3

VI

18

NU2

4

V3

19

NU3

5

20

6

21

7

22

8

SIG RET

23

A2V5MOD3

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

V)

29

15

V3

30

A1V5MOD3

Figure 10-22.

NOTES:






J

.



10-85

A3VSMOP1

NU

fJL.

4/PAV

tf.W.

r.s

<yn

LL

A2Y5MOD1

AWSMOD1

AcY S

.

(SB)

(SI)

NU

T*at2

J

NU

13

(27, SI, S3)

)7i3//

7

NU

JV

4/PB

.-.

(87)

^=

Figure 10-23.

Timing Voters,


10-86

4ws#a>t

A3r5#0£t A2YSM00I

All2

.NU /y

j

_N_U

f./J

li '

AIJ

7.14

NOTES:



3. Dotted Line {if any) Indicates Internal ULD Connection



1

.

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

A3V5MOD1

51

3

53

5

A2V5MOD1

55

7

57

9

A1PA

59

A1G5

11

A1V5MOD1

61

V3

13

V3

63

VI

15

VI

65

SIG RET

17

SIG RET

67

A1PAV

19

69

21

A1PCV

71

23

73

V3

25

75

VI

27

77

29

A3V5MOD1

79

A1PBV

31

A2V5MOD1

81

33

A1V5MOD1

83

A2Y2

35

A1Z2

85

SIG RET

37

87

39

89

41

At PC

91

A1PB

43

A3V5MOD1

93

45

A2V5MOD1

95

A1G5V

47

A1V5MOD1

97

49

A2Z2

THRU PINS

Pin

Signal

Pin

Signal

1

16

2

SIG RET

17

3

VI

18

4

V3

19

5

20

6

21

7

22

8

SIG RET

23

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

Figure 10-23.

Timing Voters,


10-87

A3V5MQD\

(54}

tl

T"

1C

*

1

NUJsJ

7

8\l

if

? ™£ ^

/

-7 _^

7

g\l

NU

/*.?/

f

5(7

ⁱ ^

NU _£

tf

A2X 3 —

— ffi

NU

n

J"

?

A.

7 S\1

"a-*

I

usIt

£ NU

^/5

,

- ¹

*!/

ry

NU | /y

^-

^/ffj

*-*gV - 4/G4V

.

.

.

> NU |#

X.W

, _R₈₅

jfjNU L/_ ₍₈_f_c₎

*\"f ^-*™>™

«yNU /

X^

_M_? ,

-7 NU /<

4tJ

(

^

70)

u«

•

•

• •.

(7t,'

,

r/

;

1C

2

^.

*

NU

1

7\s\r

1

ii-(

74,^8)

^ ^T -%£\2- << ^/^£⁴ ^

7 8\r

NU

AV

V

; j|/

,/

NU

^ /

£ NU

/

^y^

_?

NU _A -

« 4 /< ?

(

c

( •

,„

;

A2X I

J

10

-

^ 1

£*_l^

NU

îj

f

T

\

'W

™ y fj

i

ikr

,

NU

4//

/y

^£

*. —

8)-

f

_![

7

SI'

NU

ry

A1VI-]

3 $

NU

All

I

[

ho

ME 7

¹

o mi

/

w

/4

^

.

NU //

^«

,

<y NU J

1 0

0

NU

~l

1

1

3 ¹ _A₄

(48)

|

_J

^rnn\(fci

^V

(3 ,,

^ ₀₎

Figure 10-23.

Timing Voters, Logic Diagram (Sheet 3)

(C

in

— JE

-

•>e

10-88

Figure 10-23.

Timing Voters,

THRU PINS

Pin

Signal

Pin

Signal

1

16

A3V5MOD1

2

SIGRET

17

NU1

3

VI

18

NU2

4

V3

19

NU3

5

20

6

21

7

22

8

SIGRET

23

A2V5MOD1

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

V]

29

15

V3

30

A1V5MOD1

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

NU1

52

4

NU2

54

6

NU3

56

8

A1TBC

58

10

60

A1G4VN

12

62

A]PAN

14

A2W8

64

16

A1PAVN

66

18

68

A1G4N

20

70

22

A1PCN

72

24

74

A2X3

26

76

28

A2X1

78

A2Y2

30

80

A1V5MOD1

32

A1PCVN

82

A2V5MODI

34

84

A3V5MOD1

36

86

38

88

40

A1TBCV

90

A1G4V

42

92

A1G4

44

94

46

A1PBVN

96

48

98

50

A1PBN

NOTES:





5. Prefix Reference Designations os Follows: A4A8B

1

.


10-89

ttVSMODI

AfVSMCDl

A3VSMODI

•

A2W 6 •

^L³¹

17)

r=^

'*

V/(7(S

(.57)

\-i4J4

_

---tS

NU

Ufi

tf

13

•o rP9

(ilL+J/A V

.NU £tf ^

₍_M ₎

^—'

[ ;.<?iNU

1,8 I NU

-QTPfl

f<—/trQ6v

L

N U ^_

(,35

J/AN '

Figure 10-24.

Timing and Multiply-Divide Voters,

NU

A/0

zijjv

-§

13

i

-o TP8

NU

NU

f.a

^£^.^'^J

.(77)

£#JNU

^x««

/.J| NU


10-90

NOTES:

1

.






Figure 10-24.


CONNECTOR PINS

Pin

Signal

Pin

Signal

1

A3V5MOD1

51

3

53

5

A2V5MOD1

55

7

57

9

A1A

59

A1Q8

11

A1V5MOD1

61

V3

13

V3

63

VI

15

VI

65

SIG RET

17

SIG RET

67

A1AV

19

69

21

A1G7V

71

23

73

V3

25

75

VI

27

77

29

A3V5MODI

79

A1AVN

31

A2V5MOD1

81

33

A1V5MOD1

83

A2W6

35

A2Y2

85

SIG RET

37

87

39

89

41

A1G7

91

A1AN

43

A3V5MOD4

93

45

A2V5MOD4

95

A1Q8V

47

AIV5MOD4

97

49

A2W6

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

2

SIG RET

17

3

V)

18

4

V3

19

5

20

6

21

7

22

8

SIG RET

23

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30


10-91

4/I/5V0ZM

><A5VCD4

A3WWO4

>I;MR

Figure 10-24.



10-92

M-

_r

NOTES:

N U /£

₍₃₈₎

CONNECTOR PINS

Pin

Signol

Pin

Signal

2

NU1

52

4

NU2

54

6

NU3

56

8

AIPRON

58

10

60

A1MR1VN

12

62

A1PR2

14

A2W5

64

16

A1PR2V

66

18

68

A1MR1N

20

70

22

A1PRO

72

24

74

A2Z4

26

76

28

A2W5

78

A3Z2

30

80

A1V5MOD4

32

A1PROV

82

A2V5MOD4

34

84

A3V5MOD4

36

86

38

88

40

A1PROVN

90

A1MR1V '•'-

42

92

A1MR1

44

94

46

A1PR2VN

96

48

98

50

A1PR2N

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

A3V5VOD4

2

SIG RET

17

NU1

3

VI

18

NU2

4

V3

19

NU3

5

20

6

21

7

22

8

SIG RET

23

A2V5MOD4

9

V)

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

Vi

29

15

V3

30

A1V5MOD4

1

See Glossary or Index for Signal Definition s

2.


3.

Doffed Line (if any) Indicates Inferno) ULD Connection

4.


5.


Figure 10-24.



IA4A9BI

10-93

Figure 10-25.

osc

NOTES:

^B^F^R

SHP

BFR

SHP

BFR

SHP

TP16

[

TP6

I

TP18

1

TP10

IA1

TP9

IA1

TP13

IA1

•

BOT3

1

. See Glossary or Index for Signal Definitions

2.


3.


4.


5.

Prefix Reference Designations as Follows:

A4A11A (left page), A4A11B (right page)

Oscillator and Buffer,


10-94

BOT1

BO1N

BO1

BOT2

BO2N

B02

BOS

BO3N

BOS

THRU - PINS

PIN

SIGNAL

PIN

SIGNAL

1

16

2

17

3

18

BOT2

4

19

5

20

6

21

7

22

8

23

BOT1

9

24

10

25

11

26

12

27

13

28

BOT3

14

29

15

30

CONNECTOR PINS

PIN

SIGNAL

1 SIGRET

3 SIGRET

5 SIGRET

SIGRET

.7

9 SIGRET

11 V20

13 V20

15 V5

17 V5

19 VI

^!

21 VI

23 SIG RET

25 SIG RET

27 SIG RET

29 SIG RET

31 SIG RET

33 V3

35 V3

37 V20

39 V20

41 V5

43 V5

45 SIGRET

47 SIG RET

49 SIG RET

PIN

SIGNAL

51

SIG RET

53

SIG RET

55

VI

•

57

VI

59

V3

61

V3

63

V20

65

V20

67

SIG RET

69

SIG RET

71

SIG RET

73

SIG RET

75

SIG RET

77

V5

79

V5

81

VI

83

VI

85

V3

87

V3

89

SIG RET

91

SIG RET

93

SIG RET

95

SIG RET

97

SIG RET

CONNECTOR PINS

PIN

2

4

6

8

SIGNAL

V5

1

VI

10

12 BO2

14 SIG RET

16

18 1

VI

20 V3

22 V3

24 BO2N

26 SIG RET

28

30

32 1

34 V3

36 V3

38 SIG RET

40 SIG RET

42 THERM1

44 VI

46

48 BO1

50 THERM2

VI

PIN

SIGNAL

52

V5

'

54

V5

56

BO1N

58

SIG RET

60

62

1

64

VI

66

68

70

1

72

SIGRET

74

SIG RET

76

V3,

78

V3

80

BO3N

82

SIG RET

84

86

1

88

BO3

90

VI

92

VI

94

V5

96

98

1

Figure 10-25.

Oscillator and Buffer,


10-95

Figure 10-26.

-AJ*N

Clock Generator Timing Logic,

Pin

,

2

3

4

5

6

7

8

9

10

11

12

13

14

15

AJAVH

CONNECTOR PINS

Pin

Signal

1

A2RPN

3

VI

5

A2RP

7

VI

9

11

i

13

A1RPN

15

VI

17

A1RP

19

VI

21

BOS

23

V3

25

BO1

27

V3

29

31

1

33

SIG RET.

35

37

1

39

41

BO2

43

SIG RET

45

SIG RET

47

V5

49

V5

Pin

Signal .

51

.

vs.

53

V5

55

SIG RET

57

59

61

63

65

67

69

71

73

75

77

79

81

83

V3

85

87

1

89

91

.

VI

93

95

i

97

THRU PINS

Signal

Pin

Signal

16

BOS

17

A3P

18

A3PN

19

A1S

A1SN

20

A2S

A2SN

21

22

A3R

23

A3RN

A2P

24

BO2

A3SN

25

A2PN

ASS

26

BO1

A3Q

27

A3QN

AIP

28

A1PN

A2Q

29

A2QN

A1Q

30

A1QN


10-96

AJPN

Figure 10-26.

^f^- ri^

A

Alt

Ifl

T

A

ASS

NOTES:

Li f.

A3*

3

1

A35

5

AZS

₁

See Glossory or Index for Signal Definitions

2.

See Logic. Symbols Appendix for Definition of Logic Symbols

3.


4.


5.

Prefix Reference Designations as Follows: A4A12A

6.

Asterisk indicates load resistor not connected.

Clock Generator Timing Logic, Logic Diagram (Sheet 2)

10-97

VI —\r

A1SVN

V!

BOI

VI

A

AIS

—\tc

A

Aft

^£

MS

—19

r

A

AB

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1—I •

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VI

/IIP — 2

V I

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A

A 9

A

~\ ^K

A

AtS

-,-

1

,o\

n — |7

A2SVN

VI

801

VI

—

i

A

AZ9

— \'°

A &

t??

A

AZ9

¹ — 1

I

j

A

Ail

VI —I—

—1*

Is.

BOIA

VI

*

, „

VI

AtS V

'3

-, _M _T

/4

/123

—1«

42>

I

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12

1

J

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3

j

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I

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XZ,?

3 / 5

£

S

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5

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t<f Alt

At?

•— c>7/>»

AIPN

r-AIP f

ff/f.5

'

r

?"K.*'/ *4AI7

A IPPN

,„

<.,tcfn' ³

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t~*rnn

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9 >/",

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BOJA

1

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1

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A

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A

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A3 l

VS

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AJ'SN

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/«/^/V

42.SH

A3SH

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AIO

L ao

11

13

IP

S4K

id

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3

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BO2 f

â 2*12

A25

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F.FL

A28

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1

1

CKD

S'OJ/'

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13

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1 * A 5

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7

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Msif

1 7

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n

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13

7

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TPIt

^"s*

TPI,

' ^

* ^J^S *

•"

J2

It

.

f

* T

-A

"Tyr

W f

(S

7^8 II

MV

19

rMsv

.^^_

V

i. A20

1

TMV

11

a

13

t

a

S

At2J

,.„,

"* ™

tfu ^L ~ ^

rrtr

AISVN

p^-LxjJ w

Figure 10-26.



10-98

aoi

eoj

•BOS*

*IQ

AIQP

A3K

A31H

A3KPN

NOTES:

1

.



3. Doited Line (if any) Indicates Internal ULD Connection



Pin

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Figure 10-26.


CONNECTOR PINS

Signal

Pin

Signal

VI

52

V5

BO3P

54

A3RPN

V3

56

A2QP

V3

58

BO1P

A3PP

60

BO2P

V3

62

SIGRET

V)

64

SIG RET

66

A2PPN

J_

68

A3QPN

SIGRET

70

A2QP

72

A1PP

74

A2PP

1

76

VI

78

A3PPN

80

1

SIGRET

82

A1PPN

84

A2QPN

86

A1QP

88

SIG RET

90

V3

92

A3RP

94

J_

SIG RET

96

A1QPN

V5

98

VI

V5

THRU PINS

Signal

Pin

Signal

16

BO3

17

A3P

18

A3PN

19

A1S

A1SN

20

A2S

A2SN

21

22

A3R

'

23

A3RN

A2P

24

BO2

A3SN

25

A2PN

A3S

26

BO1

A3Q

27

A3QN

A1P

28

A1PN

A2Q

29

A2QN

A1Q

30

A1QN


10-99

Figure 10-27.

t> V5MX1 •

A3V2-

C ¹ ?)

/>rysi<00'f-

AJt'SMODt-

A3W 2 -

JIP3N -

NU

xJ?

N U

--W(

-2jj/

La

TP9

\I3_

^ HCI g,IS

1.8

CIM

6.13

1,8 NU;

1,8

NU

/J

NU

y/^

Us 'If=r

_k_{_} _^

(97)

-IB



10-100

4W5M00I

/WSM00I

Awssawi _A₂_>_r_a

Figure 10-27.

THRU PINS

Pin

Signal

Pin

Sianal

1

16

2

SIGRET

17

3

VI

18

4

V3

19

5

20

6

21

7

22

8

SIGRET

23

9

VI

24

V3

10 25

11 26

12 27

13 SIGRET

28

VI

14 29

V3

15 30

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

A3V5MOD1

51

3

53

5.

A2V5MOD1

55

7

57

9

A1G2

59.

A1P3N

11

•A1V5MOD1

61

V3

13

V3

63

VI

15

VI

65

SIG RET

17

SIG RET

67

A1G2V

19

69

21

A1G5VN

71

23

73

V3

25

75

VI

27

77

29

A3V5MOD1

79

A1G3V

31

A2V5MOD1

81

33

A1V5MOD1

83

A3W2

.

35

A3Y2

85

SIG RET

37

87

39

89

41

A1G5N

91

A1G3

43

A3V5MOD4

93

45

A2V5MOD4

95

A1P3VN

47

A1V5MOD4

97

49

A3Y2

NOTES:

1

.



3. Dotten Line (If any) Indicates Internal ULD Connection





10-101

*s*wou

A3WWO

^/MOVM—

I4A\

— t

,

4

43*

*

• d ^r^-

a

NU

\

sj

^ -£- ; >

/,_

i±

2fc

7 8\t

w

»/9

_-^-

7*|/

NU

>^/

13

^/

7gl/

i

*

MU

/y

«x? —

_£ _

\1U

rs«) — r-iyr

C5ZJ — ^

t^

x

f

5

&

X .

f

J_

7

8\l

II?

42/

1 3

1

X

9

-A.

•

-i.'

j

7g|/

Û

^/<f

7l«ir

NUlii

#/5| ^

//

Figure 10-27.

,y <7

/

4< f ' '

y/f/oYvM

/

N U

^/J

M

,jj»

^

N U /

,„, ,

C\T pr n

7 //

^5

^N U

>*/V

jJN U

] v//

.

/^r

jj_

^

'

^

_f₄₂₎

_f₄₄ .

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j

.

( W)

,,.^.

^

-

r

1C

^f /

,

/

^

s

Nl)

4 ;

/ 8\

/*y

XfV7

r

g\

7

NU

f

»\

,

NU-

f

3_

¹⁵

SJ

43XJ

//

—

10

— i *

I*'

NU

4t

f

6

(9 8) -

r

r* 'r

J.

Afi

I 7

fll

i

NU

41 /

fS

rj

.a.

r

i

i

-All

7

.*

Nil

4s 0

/j

3

s ^V 'l

NU

lo

5 H

o r/>^

^/ ^/^/ ^<f

NU

4JJ

^

x

₇ NU-

—

^ /VC ^>^V V»J

158)

(7t

⁾

or/ »//

7

"u

7

NU

-*/^

^^ f34)

<y

gp-00 )

10

<J

NU

Z41t

(48)

i

i

i

i



IB

-,£

10-102

Of

* ^;

',

r'f

y,p, _N

(64)

.—

( J 7 ) -

,i

,

.

(10)

1

'/—It

T

m

NU kJ

1

\

I

i;|f|

rvr

tff

f t f/ _A₃ ^,«.

t

78\>

.NU

_a

₇ NU

,f _/

NU

r

//

_e NU

^x

fiB)

'

¹^C

f

}

3

J

^ 2

NU

47

1

7|8f

TMV

I

'W

NU

4ft

1

?\t\

^NÛ

,f

<,

^r V

f3

'H,

₃ r/

ff

^NÛ

./

,

^NÛ •&•

/ 7 1 )

(38)

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

NU1

52

4

NU2

54

6

NU3

56

8

A1P2N

58

10

60

A1VOYVN

12

62

A1P1N

14

A3W2

64

16

A1PIVN

66

18

68

AWOYN

20

70

22

AWOY

72

24

74

A3X3

26

76

28

A3XJ

78

A3W8

30

80

A1V5MOD4

32

A1VOYV

82

A2V5MOD4

34

84

A3V5MOD4

36

86

38

88

40

A1P2VN

90

A1HOYVN

42

92

A1HOYN

44

94

46

A1HOYV

96

48

98

50

A1HOY

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

A3V5MOD4

2

SIG RET

17

NU1

3

VI

18

.

NU2

4

V3

19

NU3

5

20

6

21

7

22

8

SIG RET

23

A2V5MOD4

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

A1V5MOD4

NOTES:

1

,


2.


3.

Doffed Line (if any) Indicates Internal ULD Connection

4.


5.


Figure 10-27.

Timing and Multiply-Divide Voters, Logic Diagram (Sheet 4)

10-103

A3V5HOD1

/«3YZM9)- "â

4ITFD

J

(1 )

C3

NU

a

.W£Z ~

AlV^HOD 4

•" rfi4JI_

(49-

; (83 —

4/ESDN-

_N_U

a

a

l£Z=r

W.--.NU

L^ZUw

-o TP9

⁶^,¹³

6,13^.

6,13

4ITFDV

I.S

₆₉

I.S _N_U

-*;*

',8

Figure 10-28.

Multiply-Divide Voters,

AfTFDN- NU

(8f)

I

- =

1^"

&

^7=^

siul-y

Lhi

-o 7X=S

j*

6. a.

r.s

(77 J

NU

/*«

6>3. ₍_S_O

NU

4 7


10-104

— 4•*

15

J1ESD

NU

^

-

(.53)

»

-05

tf

_ _o rrHQ

i—

-

fP

1

/•/w

//

J

HC f (,'J,

JTW J

422

4S

'

'

7,/£

f/tf

41

7fc

c '

Î 2

NU

A£4

//

/

NU' f.V

tiv

41?

I

i

1

\

>,S

NU

?!?;

?

;

f .NU

/y

J

N U rf'./i /pe l

^7

4V

l J

^

7,/<f

NU

46

CONNECTOR

PINS

THRU PINS

Pin

Signal

Pin

• Signal

Pin

Slqnal

Pin

Siqnal

1

A3V5MOD4

51

1

16

3

53

2

SIG RET

17

5

A2V5MOD4

55

3

VI

18,

7

57

4

V3

-

19

9

A1TFD

59

A1ESDN

5

20

11

A1V5MOD4

61

V3

6

21

13

V3

.

63

VI

7

22

15

VI

65

SIG RET

8

SIG RET

23

17

SIGRET

67

A1TFDV

9

VI

24

1.9

69

10

V3

25

21

A1ESDV

71

11

26

'

^

23

73

V3

12

27

'

25

75

VI

13

SIG RET

28

27

77

14

VI

-.

29

29

A3V5MOD4

79

'AITFDVN

15

V3

30

31

A2V5MOD4

81

33

A1V5MOD4

83

A3W6

35

A3W8

85

SIG RET

NOTES:

37

87

1

.


39

89


41

A1ESD

91

A1TFDN

of Logic Symbols

43

A3V5MOD4

93

3. Dotted Line {If any) Indicates Internal ULD

45

A2V5MOD4

95

A1ESDVN

Connection

47

A1V5MOD4

97

49

A3Y2


Figure 10-28.

5. Prefix Reference Designations as Fol lows: A4A14A

Multiply^-Divide Voters,


10-105

*JVywQD*r ~~—'

\it)

LSI)—

b*

—,

f 51r-2

-r—

*s—

^r

,

NU

J

7

«r

T**'

sf

7

i)N U

2(££/_

/,

r

13

*L.

s a

AS

7_

NU

_A_M %- (88)

N

A>

*

!h—*^.««

7^

/O

,

NU

£

r

rfr

ir>

T|-tf

e\

rr

?3

f

^fâ

X

,

NU'

X?,

7

«r/ r

NU

^<w ^{^•^?

-OTf/

7

a

f

c

f!

NU

4ft

NU

₄₁₃

—

-f- (+z>

•*- (« )

.

,

^

C ⁷ ?-)

»

(

x/

f

10

%

2

V

3

rf

NU

7

Xj /*

*r f

rr

iff

1

^~

7

NUl^

g\f

J

Û \

k li

N

^

LJ

?<

1

^f ⁴ ⁸⁾

S_

^/^/

NU

7 NU

"j~

to

NU \

<*tf

—OTPII

-ir

_£

t 1

/^ f

^

X /

5

IS

7

*y

"[

J

»

&\

i

NU'

7

7

(9IJ

NU

-«^

_£_

r -^

NU

JI3

NU

^/V

. "-nT-i

⁾

GDI

S

10

NU

?Jfl">

Figure 10-28.

Multiply-Divide Voters, Logic Diagram (Sheet 3)

»e

r

74

J /MD?V

/

/g,^

>4

5

f

^-

,

T

1

1

1

1

J

(3 4

10-106

Figure 10-28.

CONNECTOR

PINS

Pin

Signal

Pin

Signal

2

NU1

52

4

. NU2

54

6

NU3

56

8

A1DTMN

58

10

60

A1MD2V

12

62

A1TM

14

A3Y2

64

16

A1TMV

66

18

68

A1MD2

20

70

22

A1DTM

72

24

74

A3Y2

26

76

28

A3Y2

78

A3W6

30

80

A1V5MOD4

32

A1DTMV

82

A2V5MOD4

34

84

A3V5MOD4

36

86

38

88

40

A1DTMVN

90

A1MD7V

42

92

A1MD7

44

94

46

A1TMVN

96

48

98

50

A1TMN

THRU PINS

Pin

Signal

Pin

Signal

]

16

A3V5MOD4

2

SIG RET

17

NU1

3

VI

18

NU2

4

V3

19

NU3

5

20

6

21

7

22

8

SIG RET

23

A2V5MOD4

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

V)

29

15

V3

30

A1V5MOD4

NOTES:






I

.

Multiply-Divide Voters,


|A4A14B|

10-107

Figure 10-29.

NU1

NU2

sicfecr-

A"

MS

More i.z

A

/

— Jo

'.T

/u

f-

/

6

a

;

—J

Cl

IO

10

J

J

A6

M

'+

»2

7

8 .

/

t

~~>S"

/*

c»

/ij

5

7

s

s

ft

M

"?

li

7

14

<5

to

c.\

'

i

J2

5-

If-

A4

7

m

Ct

e.

f

r '-

A14

/o

Cl

12

ft

A5

f-

8

Cl

⁷

SVgf

|

f«CK

All

|

PANEL

|CONN£CTION

VB ?

i

7

C J

a

|

7

C5

a

/33

»/5

TP5

7

<TJ

«

1

'

C3

a

/«**

A19

TP6

7

r.?

«

1

⁷

C3

a

-«s

AI6

TP 7

7

CJ

a

1

7

C3

e

/«?y

A 10

TP8

7

f j

/«/o

8

I 7

C3

AIT

a

TP9

7

CJ

a

i

7

C3

&

x«

*31

• SJG

V1

VI

RET

Decoupling Capacitors (Channel 5), Logic Diagram (Sheet 1 of 4)

10-108

SIG RFT-

7 All

_?

C*

«£

S

TP1O

}

7

7

7

7

fw"

Alt

C4-

Alt

9 7

7PI3

C4

AI3

a

C4- 5

AZ7

TP1*

7

]

TPIS

0

[

7

C4

4/0

7 C4

All

•^ ^

a

g

r

7

••^^

C4

/«/«

6

04 »J

>U.J

7

7

04 a

>t^0

r^

A34

a

VJ

V3

Pin

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

CONNECTOR PINS

Signal

MSVB1

MSVB1

SIGRET

SIGRET

NU1

V3

V3

V3

V3

NU2

VI

VI

VI

VI

A3V5MOD2

vi

VI

VI

VI

A3V5MOD6

SIG RET

SIG RET

SIG'RET

SIG RET '

A3V5MOD7

Pin

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

'

Signal

SIGRET

SIGRET

SIGRET

SIG RET

SIGRET

SIG RET

V3

V3

V3

V3

SIGRET

V3

V3

V3

V3

SIGRET

SIG RET

SIG RET

SIG RET

SIG RET

SIG RET

SIG RET

MSVB2

MSVB2

^:

NOTES:

I.




4. "N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate If


Figure 10-29.


10-109

AlVSMODt

AIV 5 HODI

A1V5MOD1

Ai VSMOD 7

AlVSMODt

A/1//

Figure 10-29.

B

—ns

û r4

e

~r<>

_>_t

14

ci

NOTE. I

1

)

^f

7

^,^/ J '"

^f 1

'f>

>f.

—M.

e

1C

^r^z i&

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1"

li.

14

3

Cl

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f

7

1

i

^S

7

/

^t 1

7

/

J

^S 7

e /

" '15

l£

f>

A /

^j j

?

or/" f

NUZ

/Vl/J

,

J

jr

7

S

1

1

?

f

7

t

s

7

1

i

J

7

J

S

Ail

C1

A 10

Alt

1

is-* 11 — : j

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a

7

a a

It

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.

~'j i

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I

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10

}

It

14

i

J

l g

N>

li

14

•

If

11 It

8

li 11

/ i

1

7

7

I

1 ••

*

J

7 J

/j

J J

- i

TP3

Afc

C/

Ail

AM

to

It

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A

7? /^

14

a

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ifl

/^

14

e

^f^t ,'£

:«

S

•It

1£

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•

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5/6 Kf.T


10-110

VI •

Til

—3 ₅

Cl

*

73-*

It If

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'

J

J i

c;

If

A/I

>4/a

1*

Cl W~

1

î

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All

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'a

i

'

L

W—*— T. 3

v

—7 _j 7

C.1

a

¹⁰ li

li

S

/4

All 0-

7

AI3

1

<9 /

e

J

n ro

j

fl

'O

J" !

il

416 H-

.

f

7

f£

AU /4

ATW*

VTPtS

.

,a

1

/,

e

5

Cl

73-""

/;

J

5

Cl

,

77T~

It

7 A13

/*

7

AID

1+

a

/

a

3

10

li

3

S

Cl

¹⁰

S

if

7 Ail

14

7

A34

/•f

A

TV/6

o

JPn

I

a

—r

Cl

10

11

3

S

Cl

Î^D

s

if

7

AM

]&

7

A/I

n

1

3

1

a

J

S

Cl

Cl

if _K

7

'*-r— ^l

A3S

/*

1

NOTES.

CONNECTOR PINS

Pin

Sianal

2

V3

A

6

1

8

10

NU1

12

VI

14

16

16

20

SIGRET

22

1

24

26

28

J_

30

VI

32

34

36

1

38

A2V5MOD2

40

SIG RET

42

44

46

i

48

A2V5MOD6

50

V3

Pin

Signal

52

V3

54

56

i

58

A2V5MOD7

60

V)

62

64

1

66

68

SIGRET

70

1

72

74

76

JL

78

A1V5MOD7

80

NU3

82

84

86

1

88

A1V5MOD2

90

NU2

92

i

94

96

98

A1V5MOD6

1. Sec Glossary or Index for Signal Definitions



Connection

4. "N.U. indicates that ULD is Not Installed


5. P-'cfix Reference Designations as Follows: A5A3B

Figure 10-29.


10-111

A1Y3

Figure 10-30.

NOTES:






1

.

Memory Timing Voters,


10-112

Al VSMOD7

AZV5MCD7

A3V5M3D7

LSI)

³^;

4

kil l

.*••

K.1I

1

I

THRU PINS

Pin

Signal

Pin

Sianal

1

16

2

SIG RET

17

3

VI

18

4

V3

19

5

20

6

21

7

22

8

SIG RET

23

9

V I

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

Figure 10-30.


CONNECTOR PINS

Pin

Signol

Pin

Signal

]

A1Y3

51

EP15A

3

A1Y3

53

A1M7SYNCV

5

A1Y3

55

A1M5SYNCV

7

A1Y3

57

A1EBM

9

59

A2EBM

11

SIG RET

61

A3EBM

13

SIG RET

63

A1M3SYNCV

15

A1M3SYNC

65

A1M1SYNCV

17

A2M3SVNC

67

A3V5MOD7

19

A3M3SYNC

69

A2V5MOD7

21

A1M1SYNC

71

A1V5MOD7

23

A2M1SYNC

73

A1BRBO

25

A3M1SYNC

75

A2BR80

27

A1M5SYNC

77

A3BRBO

29

A2M5SYNC

79

A1BRBON

31

A3M5SYNC

8!

A2BRBON

33

A1M7SYNC

83

A38RBON

35

A2M7SYNC

85

EP15

37

A3M7SYNC

87

V3

39

A1EBMV

89

V3

41

A2EBMV

91

A1X4

43

A3EBMV

93

A1Y3

45

EP16A

95

A1BRBOV

47

VI

97

A1BRBOVN

49

V I


10-113

A3VSMflD7

AZVSMOD7

AIVSM007 •

AllNWE S

(to)

(Sfcl

Jl

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AV

T,

A

A

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A

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NU

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9,

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NU

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A)0

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NU

AIT

I ¹

7

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LJ

7

7

Û 7

7

13

NOTES:

3

TP1

V I

A3 0

£ ,

oTPg

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^^

NU

A

3

NU

16

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—

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MIWHBSV

A2INHBSV

-_ _W |.

^^;o

NU A —

A1PUMN

^

I A

.

i

6

IB i

'NU

A!

J| T

2

4

«*v

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T

T?l<

i

TMV

A.Z9

J0 1

19,

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A? 2

7

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*

X P

L f

N

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J—MIM

A 9

i r.

7

1— /HUNVN

— A 30

7

IJ

V I

»

»

A23

1 W

c

]e i

NU

All

7

U

:

NU

A16

IQ


Figure 10-30.


3. Dotten Line (if any) Indicates Infernal ULD Connection





10-114

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

52

A1CSTV

4

54

6

A1TLCV

56

8

58

A1RUN

10

A1SYLOVN

60

A1X4

12

A2SYLOVN

A2INHBSV

14

*2

64

A1INHBSV

16

66

18

A1TLC

68

20

A1X4

70

A1INHBS

22

AIX4

72

A1RUNV

24

A1X4

74

26

76

28

78

NU1

30

A1CST

80

NU2

32

A3V5MOD7

82

NU3

34

A2V5MOD7

84

NU4

36

A1V5MOD7

86

NU5

38

88

A1RUNVN

40

90

42

A1SYLON

92

44

A1Z5

94

46

96

48

98

A1RUNN

50

Figure 10-30.


Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

'5

THRU PINS

Signal

Pin

16

SIG RET

17

VI

18

V3

19

20

21

22

SIG RET

23

VI

24

V3

25

26

27

SIG RET

28

VI

29

V3

30

W<0

Signal


10-115 »

A2Y3

AlBRA O

(75>

(.77)

Figure 10-30.

NOTES:






1

.



10-116

t-f

i

H>

Figure 10-30.

TMI

T-II .T

J>

NL

g A11

HI

.(45")

A1EAM

<£o™

t

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A32

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i

t A2< »

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13

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7

^V Î

*-«M

At

^

A 2V

A>V

Pin

(43-)-

L

?j^

^t NL

* A18

H_

r

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—h

1

—^

Is

_3JNL

1*3

.1

P

s O

L

DDI

L

AI7 ¹⁴ • e»«

V I

1

1

A34J

|

J

THRU PINS

Signal

Pin

Siqnol

1

16

2

SIG RET

17

3

VI

18

4

V3

19

5

20

6

21

7

22

8

SIG RET

23

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

CONNECTOR PINS

Pin

S ignol

Pin

A2Y3

.

51

3

A2Y3

53

5

A2Y3

55

7

A2Y3"

57

9

59

II

SIG RET

61

13

SIG RET

63

15

A1M2SYNC

65

17

67

19

69

21

A1MOSYN

71

23

73

25

75

27

A1M4SYNC

77

29

79

31

81

33

A1M6SYNC

83

35

85

37

87

39

A1EAMV

89

41

91

43

93

45

95

47

VI

97

49

VI

Signal

A1M6SYNCV

A1M4SYNCV

A1EAM

A1M2SYNCV

A1MOSYNV

A3V5MOD7

A2V5MOD7

A1V5MOD7

A 1 BRAO

A1BRAON

V3

V3

A1X5

•A2Y3

A1BRAOV

A1BRAOVN



10-117

AIXS

;ZLL

fTg NU

Ji A3Z

A.SVSM3D7•

A1V5MOD7- ffl

AIRD M

•

I5IM7

a,

IS]AZ4

A1X5

A1MAO

(5fc>

CS+)

AIZS -

A1 KD

-

<ZM -

^,

1

.

[N _A
12

bi-

ll

11

n

~~2"

^

~

I"

T

A

l«

t

yiv

3

t

N II

A

ID

q

P

6

If

N

A

1

U

7

5

IC

'

13

7

13

7

13

TSî

~3?lVl8 .

NU

_^

M

NU

13

13

oTPB

;

7

7

V I

AZ

VI

A9

Nil

A14

TPS

8

a

14

> .

14

^{^}⁴

, _T_J .

(7t)

Figure 10-30.


A1ROMM

(8JL}

AlfeJBO

TM/

A1

i.A8

13

IS

, |e

1

Z

6

T'

,4<

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»

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|

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N

_g. Ai

i

U

7

13

i

,

1l«

.

i

?

«

II

A: S

N

7

'3

8

6

»

e

e

vr

y«3a

V

A2

I

3

Nil

A16

Logic Diagram- (Sheet 7)

1

¹

(90)

41

32

-I F

7 ^r - H

-

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<

K

r-|

1 I

/i w

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j V

10-118

AIX5

r

f

AIZ5-

f

II

)

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f

V J

t

I \

L

J

Figure 10-30.

1

to

I t

_ _•

NU

A t S

,

_9^S.i

2 TMV

t /a.6

.

.

sJi 1

'"S TMV

f

A"^l

TO NU

72

A4

Js ¹

2

TMV

t A S

T

n NU

a

Is|l

6

A6

5

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13

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13

s

0

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3 HCI

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,

11

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, TV>1

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13

7

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A12

NU

A13

^

14

A1SYLC1V

«*

f fl

1

r

L)|?3

LJ

^

7

NU

A14

14


CONNECTOR PINS

Pin

Signal

Pin

Signal

2

52

A1RDV

4

54

6

A1SYLC1V

56

8

58

A1MAO

10

A1SYLIVN

60

A1Z5

12

62

A2RDMV

14

64

A1RDMV

16

66

18

A1SYLC1

68

20

A1X5

70

A1RDM

22

A1T5

72

A1MAOV

24

A1X5

74

26

76

28

78

A2RDMVN

30

A1RD

80

A1RDMVN

32

A3V5MOD7

82

34

A2V5MOD7

84

36

A1V5MOD7

86

A1RDMN

38

88

A1MBOV

40

90

42

A1SYLIN

92

44

A1X5

94

46

96

48

98

A1MBO

50

THRU PINS

Pin

Signal

Pin

Signal

1

16

2

SIG RET

17

3

V

]

18

4

V3

19

5

20

6

21

7

22

8

SIG RET

23

9

V

I

24

10

V3

25

1

1

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

NOTES:

1

.


S

Definitions

2.

See

S

Logic Symbols Appendix for Definition

0

of Logic Symbols

3.

Dotted Line (if any) Indicates Internal ULD

C

Connection

C

4.


'



10-119

/t/l/S AtODi-

•

#OOt--

JMXON- NU'

^l

(^)-

(55)

(S1)-

^. CO

42.9

7£

_J_._?_,_f

J1X 5-

Alt!:

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M

Tttr

4/9

Figure 10-31.

a

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7

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ê ^v^/

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— il/.<3VN

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A1114N -

AlAJtlN

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Memory Address Decoder Voters,

•.,_J£-

NU

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-10

-46

10-120

NOTES:

I

.






Figure 10-31.


CONNECTOR PINS

Pin

Signal

Pin

Signal

1

A1AX3VN

51

3

A2AX3VN

53

5

55

7

57

9

A1AXON

59

A1AX3N

11

61

13

63

A2AX1VN

15

A1AX6N

65

A1AX1VN

17

67

A1AX4N

19

69

21

A1AX1N

71

23

A2AX4VN

73

A2X5

25

AIAX4VN

75

A2X5

27

A1AX2VN

77

A1X6

29

A2AX2VN

79

A1AX5VN

31

81

A2AX5VN

33

83

35

A1AX2N

85

37

A2AX7VN

87

A1AX5N

39

A1AX7VN

89

41

A2X5

91

43

A1AXOVN

93

A1AX7N

45

A2AXOVN

95

A2AX6VN

47

97

A1AX6VN

49

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

2

SIG RET

17

A 1X6

3

V3

18

4

VI

19

(47,49,51,

5

53)

6

20

7

21

8

22

9

23

10

24

A2V5MOD6

11

25

A3V5MOD6

12

SIG RET

26

A1V5MOD6

13

V3

27

14

VI

28

15

29

30


10-121

6

A3V5 MO46

1

~i f

NU

4

9

e '\

7MY

j S

-i.

'\

At.?

JMXXN -

A/X6

-^

ft

N

4

S

^

-1

r*

4

A

'1

f

'2

V

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JtAXtOH

(88V

(.8t)

AIXt

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f

j£j _y

'

a

NU

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8 >\

TMf

₄

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,;

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S

/[

TM?

It

4

Figure 10-31.

/

^ ——c,m

^>^J

⁷ "ss "— •

>J

7

"n

S

6

1}

rj

oTPIO

ê _"_x

s

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S

6

tf

13

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7

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13

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Aff

6

7

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l\

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JJ4

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ft

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NU

46

s

f

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8

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r*i? a

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4>7

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jatjiia .

AW40W I

f 7

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S'[

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7

2

;

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\f

NU

r

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4/6 \

8

W

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f\

f f

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? M

4f6

&

rtJdJf?^ ^

,

V



10-122

NOTES:


2. See Logic Symbols Appendix for Definition of .Logic Symbols




Figure 10-31.


CONNECTOR PINS

Pin

Signal

Pin

Signal

2

A1AX70N

52

A1AXOOVN

4

54

A2AXOOVN

6

56

SIG RET

8

A2AX60VN

58

V3

10

A1AX60VN

60

A1AX70VN

12

A1AX50N

62

A2AX70VN

14

64

A1AX20N

16

66

18

SIG RET

68

20

A2AX40VN

70

A2AX50VN

22

AIAX40VN

72

A1AX50VN

24

V3

74

V]

26

AIAX40N

76

A1V5MOD6

28

78

A1AXION

30

80

32

A2AX20VN

82

34

A1AX20VN

84

A1AX60N

36

A2AX10VN

86

38

A1AX10VN

88

40

A1AX30N

90

A1AXOON

42

92

44

94

46

VI

96

A2V5MOD6

48

A2AX30VN

98

A3V5MOD6

50

A1AX30VN

THRU PINS

Pin

Signal

Pin

Signal

].

16

2

SIG RET

17

A1X6

3

V3

18

4

VI

19

5

20

6

21

7

22

8

23

9

24

A2V5MOD6

10

25

A3V5MOD6

1

1

26

A1V5MOD6

12 SIG RET

27

13 28

V3

14 29

VI

15 30


10-123

? MOQ

•

(S)

(?)

/Ô)

(. II)

'

-

-•

—-«

t7

'0 t

/

*•§

L

N

^(

ft

U

y

«

7>

^/

/I

"> if

f

,J

9 />

<?>

i\

if _i

„

^-^m f\

N

/I

8

U

:

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^

S

^r^* /i.

r ?

â

i

8

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4

I

ii

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f ;

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4

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Figure 10-31.

f

6

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f

U

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s

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7

f

H

4JJ

f/

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VI

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f

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7

a

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f

f

47

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(70-r

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)

—r

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f?

19

N

a

U

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f

4

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ir

W

7

8

T/l

4

2

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1

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7

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N

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8

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4

8

J

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8

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4, '7

N

*

4

f

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f

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7 'I

1

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f

4. '0

ru

f

r?

13

f

IS

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f -

rj

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r

If ?

8

ft

r/

1

7

7

-nTt

f

7

$

r/

417

H

it/J

•>g

r/

jfff

w

A/4

¹⁴

//

14

j xr-ftrf,

,

*^



»«

f E

10-124

TUP 11

(*V)'

NOTES:





5. Prefix Referenco Designations as Follows: A5A8A

1

.

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

A1AY3VN

51

3

A2AY3VN

53

5

55

7

57

9

A 1 AVON

59

A1AY3N

11

61

13

63

A2AY1VN

15

A1AY6N

65

A1AY1VN

17

67

A1AY4N

19

69

21

A1AYIN

71

23

A2AY4VN

73

A2X4

25

A1AY4VN

75

A2X4

27

A1AY2VN

77

A2X6

29

A2AY2VN

79

A1AY5VN

31

81

A2AY5VN

33

83

35

A1AY2N

85

37

A2AY7VN

87

A1AY5N

39

A1AY7VN

89

41

A2X4

91

43

A1AYOVN

93

A1AY7N

45

A2AYOVN

95

A2AY6VN

47

97

A1AY6VN

49

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

2

SIG RET

17

A2X6

3

V3

18

4

VI

19

5

20

6

21

7

22

8

23

9

24

A2V5MOD6

10

25

A3V5MOD6

11

26

A1V5MOD6

12

SIG RET

27

13

V3

28

14

VI

29

15

30

Figure 10-31.

Memory Address Decoder Voters, Logic Diagram (Sheet 6)

10-125

A1VSM0D6

A3V5 #006

1*8 -sc

-fD

-f£

AWOOH

4M/T0//—

NU

n/irzott- Nil

<$ -

4'AYtOft

AZXf

^M⁴ Li

-oTPIO

a

_\_A_I₂ —A2A/30W

(««- -OTP£

iW

AUY4CH

₍₃_o₎

_{_}

4A7

M

414

NU

M

_/_j_/_j

7 S

Mir fJ

_'_— AIAYWM

_^_/_/

7

/UAY4MN

Figure 10-31.



-16

10-126

NOTES


2. See Logic Symbols Appendix for Definition of Logic Symbols Dotted Line (if any) Indicates Internal ULD Connection

"N.U.

although Page is ''Wired" to Accommodate It Prefix Reference Designations as Follows: A5A8B


CONNECTOR PINS

Pin

Signal

Pin

Signal

2

A1AY70N

52

A1AYOOVN

4

54

A2AYOOVN

6

56

SIG RET

8

A2AY60VN

58

V3

10

A1AY60VN

60

A1AY70VN

12

A1AY50N

62

A2AY70VN

14

64

A1AY20N

16

66

18

SIG RET

68

20

A2AY40VN

70

A2AY50VN

22

A1AY40VN

72

A1AY50VN

24

V3

74

VI

26

A1AY40N

76

A1V5MOD6

28

78

A1AY10N

30

80

32

A2AY20VN

82

34

A1AY20VN

84

A1AY60N

36

A2AY10VN

86

38

A1AY10VN

88

40

A1AY30N

90

A1AYOON

42

92

44

94

46

VI

96

A2V5MOD6

48

A2AY30VN

98

A3V5MOD6

50

A1AY30VN

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

2

SIG RET

17

A2X6

3

V3

18

4

VI

19

5

20

6

21

7

22

8

23

9

24

A2V5MOD6

10

25

A3V5MOD6

11

26

A1V5MOD6

12

SIG RET

27

13

V3

28

14

VI

29

15

30

Figure 10-31.

Memory Address Decoder Voters, Logic Diagram (Sheet 8)

10-127

A15BKIV•

A/TKI V

V!

_—

430

14

rj

a

a

A\J 2

A

422

//>/

-S#At

0

AfSS/W

M4SA4

*•/

r

A'CffRM

vr •

'

f2

j

J^ff

rr

-£•

fl

~\

_A_t₅

7/V

•SffiAM

Figure 10-32.

Memory Buffer Registers, Logic Diagram (Sheet 1 of 12)

10-128

CONNECTOR PINS

Pin

Signal

Pin

Signal

1

BRA2N

51

3

BRA2

53

A1TR4V

5

BRAIN

55

M6SA4

7

BRA1

57

M4SA4

9

M2SA4

59

11

M6SA2

61

13

A1CERVN

63

MOSAIC

15

A1TR1V

65

A1TR7V

17

M4SA1

67

19

MOSA4

69

M4SA7

21

A1SBRZV

71

M6SA10

23

M4SA2

73

25

M2SA2

75

M4SA10

27

M2SA1

77

M2SA7

29

MOSAIC

79

M2SA10

31

M6SA1

81

MOSA7

33

MOSA2

83

M6SA7

35

BRA4N

85

BRA7

37

A1TR2V

87

A1TR10V

39

SIG RET

89

BRA 10

41

VI

91

43

BRA4

93

BRA7N

45

V3

95

BRA10N

47

97

49

NOTES:


1


.

of Logic Symbols


Connection




Figure 10-32.

Memory Buffer Registers,


10-129

tiffS M

MM*3

rr

A13

A1TR3V —

13

U

to

-M6S/I5

TPt

TP2

o

o

rr

/H6S4S

1/£

A9

a

_I_/_/

A

Aft\

\ff_

rr

<S\

X

\\4fS _

Figure 10-32.

yt

/t

\AtO\

t —\9

4

AfO _F

\At A


^-

A/0 s

y

AI7\


10-130

CONNECTOR

PINS

Pin

Signal

Pin

Signal

2

52

4

BRA13N

54

V3

6

BRA11N

56

BRAS

8

58

VI

'

10

BRA 13

60

SIGRET

12

A1TR13V

62

A1TR5V

14

BRA 11

64

BRA8N

-

16

M6SA11

66

MOSA5

18

MOSA11

68

M6SA3

20

M2SA13

70

MOSA3

22

M2SA11

72

M2SA3

24

M4SA13

74

M2SA5

26

76

M4SA5

28

M6SA13

78

A1SBRYV

30

M4SA11

80

MOSA8

32

82

M4SA3

34

A1TR11V

84

A1TR3V

36

MOSA13

86

A1CBRVN

38

88

M6SA5

40

90

M2SA8

42

M4SA8

92

BRA3

44

M6SA8

94

BRA3N

46

A1TR8V

96

BRAS

48

98

BRA5N

50

Figure 10-32.


NOTES:

1

.



of Logic Symbols


Connection


although Page is "Wired" to Accommodate it

5. Prefix Reference Designations as Follows:A5A9B


10-131

Figure 10-32.

rf

M-

a

14

a

AtCBKVN- ^mÂ^]^J² ^_

A

429\

A

AH

M1SA+

MJSA4

JPI

-ZL

o 415

VI

Uo~i _J_-_H

A \ i

SI7SA4-

*'/-

(3

AZTR4V—& \

A ! SSftt K — ^

AIT

vr

rf>9

o

^/^f^?

O

Memory Buffer Registers, Logic Diagram (Sheet 5)

10-132

JISAT-

jff

r A 7

MSSA7

M7SA7

4

4J4

4

434

— ]/

t4

j

4 2

434

~\7

4 f4

A27

W ~]'<

4

⁾

to

427

4

436

~\9

n

f2\

~\

/ I

4

4JS

A^T/t7^ —£

A2SBKIY — ⁷ _

4lf£K M J2-

rr—

p

1

1

W'

LA

~\9

4

426

^J^l iss

y

438

CONNECTOR

Pin

Signal

Pin

1

BRB2N

51

3

BRB2

53

5

BRB1N

55

7

BRB1

57

9

M3SA4

59

11

M7SA2

61

13

A2CBRVN

63

\5

A2TR1V

65

17

M5SA1

67

19

M1SA4

69

21

A2BRZV

71

23

M5SA2

73

25

M3SA2

75

27

M3SA1

77

29

M1SA1

79

31

M7SA1

81

33

M1SA2

83

35

BRB4N

85

37

A2TR2V

87

39

SIG RET

89

41

VI

91

43

BRB4

93

45

V3

95

47

97

49

PINS

Signal

A2TR4V

M7SA4

M5SA4

M1SA10

A2TR7V

M5SA7

M7SAIO

M5SA10

M3SA7

M3SA10

M1SA7

M7SA7

BRB7

A2TR10V

BRB10

BRB7N

BRB10N

>

S-

f

JfSSafO

417JAW

rr—

Ai TKIOV— ^

Aisatiy-L

A ?

4J7

—|/

A X

420

~~\>l

A tJ

A20

~~\J

A /

420

—\7

A

413 ^-|

A

414 /3

rt

c

7/7 AtceRM M.

•\

w—

-

gtBflf

r^ -

(_

0007

\

&

A

421

~\9

A

421

~\f

4

414

t?

~\

rf

-*{L*-

f

f

4f4

NOTES:

1

.



of Logic Symbols


Connection




Figure 10-32.



10-133

Figure 10-32.



10-134

CONNECTOR PINS

Pin

Signal

Pin

Signal

2

52

4

BRB13N

54

V3

6

BRB11N

56

BRB8

8

58

VI

10

BRB13

60

SIGRET

12

A2TR13V

62

A2TR5V

14

BRB11

64

BRB8N

16

M7SA1 1

66

M1SA5

18

M1SA11

68

M7SA3

20

M3SA13

70

M1SA3

22

M3SA11

72

M3SA3

24

M5SA13

74

M3SA5

26

76

M5SA5

28

M7SA13

78

A2SBRYV

30

M55A11

80

M1SA8

32

82

M5SA3

34

A2TR1V

84

A2TR3V

36

M1SA13

86

A2CBRVN

38

88

M7SA5

40

90

M3SA8

42

M5SA8

92

BRB3

44

M75A8

94

BRB3N

46

A2TR8V

96

BRB5

48

98

BRB5N

50

NOTES:



of Logic Symbols


Connection




Figure 10-32.



10-135

410S/I6

Figure 10-32.

vi-

A??

W- ~~|9

\

a A

VI

e

A2-)

T

A

Ail

io

,m

13

^J nLJI

i

i

A^9

I

A 22

MffMf-

*--

e

VI-

A/TRIV

AtCBftVH

VI

BRA&tJ

VI-

13

Â I —

A S T

a

~v

A

A9

—\7

2

A 14

All

~\V

A 13

All

VI ~~I»

A/PAftV

/3

A

An

7

vl

/_3_

e

VI

e

VI

a

A TP**

A/O

~~|9

A

*|

J

AlO

~\9

A

An

—\9

A

A 16

3|

T

\AIO

1

Art]

/

Ate

6

\

S

s

o

BRA 14

, L

'

BRA HP

¹

TPI

I ⁵



•BRA'S

10-136

AirK/Z V

A1SBRXV

AlCBfiM

VI —1»

a

VI

a

A

A 28

~l»

^J ^J

r

A i

A35

45S

TP/8

f

⁵

a**/:

CONNECTOR PINS

Pin

Signal

Pin

\

BRA9

51

3

BRA6N

53

5

BRA6

55

7

A1TR6V

57

9

BRA9N

59

\ \

M2SA1 4

61

13

MOSA14

63

15

A1TR9V

65

17

MOSA6

67

19

M4SA6

69

21

M2SA6

71

23

MOSA6

73

25

M6SA6

75

27

M4SA9

77

29

79

31

M2SA9

81

33

M6SA9

83

35

BRA14N

85

37

V3

87

39

VI

89

41

BRA 14

91

43

A1PARV

93

45

A10BRVN

95

47

SIGRET

97

49

BRA14P

Signal

M6SA14

M4SA14

M6SA12

MOSA12

A1TR12V

M4SA12

M2SA12

BRA12N

A1SBRXV

BRA 12

NOTES:

1

.



of Logic Symbols


Connection




Figure 10-32.



10-137

xyjj"A6

M5SA6

/tf7SA6

VI

AtSBRXV

AiTP&V

AICBKVM

VI

Figure 10-32.

9

7

— —

a

VI

8

A 14

A3O

—\fc

A

A30

— |/

"A

430

~\7

A

-423

—1/2

A

AZ3

A

A1'3

A

A2 ¹ )

~\9

A

429

T

A

A2Z

}

13

2

14

to

~1

J

/J

"n

^J —'

r

³

^r

7"X

<

S

j 5

AZ2

'-:

,

A4JS49

M5S49

417S49

VJ

4 Z

—17

A

AtC,

9

~\k

A

Aft.

—jj>

4

X?/li

—17

•?9

t4

13

2

£

A2.SBRXV

' JZCBW

^2

_„.

'VI

«

/<

/3S

JiJ

XI TPI

/1/5

—15

X

X/5

J

^

3

/

AfS

5

I

kT

~|9

^ x5 I

5

46 xs

Memory Buffer Registers, Logic Diagram (Sheet 11)

10-138

«W 4

'4JS4f4

KSSAU

M7S/I/4

~\f

A

x)9

—\j

A

49

13

2

_

~~\7

A 14

AH

t

~\k

A

13- fl

V) —|W

13

A 7

A/7

VI

13

a

A

A/0

~\9

A

A/0

tz

~|

^J

.3-

/

r

AIO

rp<-

o

S

'

vr

a

T

A

I S

A,7 All

VI — \9

a

A

Ata

I

s

Aie

CONNECTOR

PINS

Pin

Signal

Pin

Signal

2

BRB12

52

SIG RET

4

A2SBRXV

54

A2CBRVN

6

56

A2PARV

8

58

BRB14

10

60

VI

12

62

V3

14

BRB12N

64

BRB14N

16

M3SA12

66

M7SA9

18

M5SA12

68

M3SA9

20

A2TR12V

70

22

M1SA12

72

M5SA9

24

74

M7SA6

26

76

M1SA6

28

78

M3SA6

30

M7SAI2

80

M5SA6

32

82

M1SA9

34

84

A2TR9V

36

86

M1SA14

38

88

M3SA14

40

90

BRB9N

42

NASSAU

92

A2TR6V

44

M7SA14

94

BRB6

46

96

BRB6N

48

98

BRB9

50

BRBUP

Jf/J/l/S •

MJ5/I/Z

MSSJ/2

M7SAr?

— }//

A />

A3*

—\ r

A A*

A21

~}fS

A

/J

A21

— jj.

A 2

All

VI —|7

S

A 6

A34

1

7

AT; A

Z±J J

IS

AZCBRVU

VI

——

8

A

AZB

—] 9

x)

AZB

^ / 1

VI

e

~l*

/

-4J5

3j

7

|>4?«

7

X35

NOTES:

1

.


S

5

0

,

BffBIZH

B&BI2

Definitions


of Logic Symbols

3. Dorted Line (if any) Indicates Internal ULD

Connection




Figure 10-32.



10-139

41 VSUODt •

4?&MODt-

A3\/SMOO<i> •

All/OKI

(as)

NU

⁴¹

^c

~f TMY

_z

76\!

.NU

AS!

8l

.NU

A34

^NÛ

^NÛ

^/^y

•orPS

^NÛ

-

^M

-OTP/0

iff J-

4wr

(5)

^NÛ y- can

fT9)

ras;-

tll'M W (73)-

(TSlr

1

NU

rW

/J

?W

NU /J

NU

₄_J₅

NU

^NÛ

if

NU

«

7

<*NU X-

h^-r55)

£ NU

JICNAM

an

Figure 10-33.

Address Register and Memory Module Register Voters, Logic Diagram (Sheet 1 of 4)

-ic -ia

HO

10-140

(37)

—\

—

(39)— »

fn) —

(89)— •

( /9

~""1

r?

^,ⁱ to

s

-7

i

7

^

.?

i

10

I

2

SI

J

14,

U

N

4

^

SI/

7

U

A

ir

U

7

N

i

S\f

u 1

(V |

«L

7

t\

u

/;

A

I

sj

a

a

a

!£.

ij

N

4

7

1

|;

r*

/i

ni

fr

>f

r

k \i

U

rg

N

X

/

N U

X< '/

f

6

a

/J

//

CONNECTOR PINS

,

Pin

Signal

Pin

Signal

1

51

3

A1A7V

53

A1HOPC1

5

55

7

57

A1A8V

9

59

11

A1A7

61

A1IMAVN

13

A1A9V

63

15

65

\7

67

19

A1DMAVN

69

21

71

23

73

25

VI

75

27

V3

77

A 1 OMAN

29

SIGRET

79

31

81

33

83

A1HOPC1V

35

A1A8

85

37

87

39

89

41

A1A9

91

A1IMAN

43

VI

93

SIG RET

45

V3

95

VI

47

SIG RET

97

V3

49

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

A3V5MOD6

2

SIG RET

17

(74, 2)

3

VI

18

(4,

6)

.

4

V3

19

(4,

6)

5

20

6

21

7

22

8

SIG RET

23

A2V5MOD6

j

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

A1V5MOD6

OTP3

f

ff

AS

/ j*j ₃_i >

/|NU"| 14 ftT-f

|^/tf

| ^

7 NU ,* ^/y

,

,

.

"'^

'TPIL

a f/

j 10

/ JUM/IVN

<f NU /

jf9

(d3>

x' NU // W

, ₆_;_r₎

NOTES:

1

.

Sec Glossary or Index for Signal Definitions


of Logic Symbols



although Page is

"Wired " to Accommodate It


Figure 10-33.

Address Register and Memory Module Register Voters, Logic Diagram (Sheet 2)

10-141

4/VSMOD6-

A3VSMOO6 '

At'A 4

Ob)

(•79)

tt,

₄

04)

NU

-OTfJ

w~

*]!

NU

— JIAIY

â

⁷

— (89)

(86)

41At

(581

f2f)

^f^t

NU

4}

w

W

•4jNu1</

7

t\l

NU

NU

I

wr

^NÛ

Ur^l(

N U

2\4X\

j]

tf

^f^j

/y

(98)

—orrg

<y[NTn /

NU

_X_/_/ ¹⁴

₍_S₆₎

Cf8)

I

7rs >4

⁷

(34)

r— tf.NUl/_ n "^//| ~

(30)

(0

\

IAMJI—aLM

LP?JZ_

I-

*u! _J

_ ~

f48J

(43)

Figure 10-33.


10-142

/)S-

_B_f_-

C

J-

A1A3

NOTES:

1

.

_N_U

Â^S

m

AN â

lit

-OTP3

â

i

NU

fj

NU

AJ6

(14)

_

w

NU

_a

J/JsF ¹

2 TMV a

NU

JtS â

-OTPIt

J—AH3V

-!— (18)






CONNECTOR

PINS

Pin

Signal

Pin

Signal

2

52

4

54

6

56

8

A1A6

58

10

60

A1A2V

12

62

A1A3

14

64

16

A1A3V

66

18

68

A1A2

20

70

22

A1A5

-72

24

74

26

76

28

78

30

80

A1V5MOD6

32

A1A5V

82

A2V5MOD6

34

84

A3V5MOD6

36

86

38

88

40

A1A6V

90

A1A1V

42

92

A1A1

44

94

46

A1A4V

96

48

98

50

A1A4

Pin

THRU PINS

Signal

Pin

Siqnal

1

16

A3V5MOD6

2

SIG RET

17

(74, 2)

3

VI

18

(4,

6)

4

V3

19

(4,

6)

5

20

6

21

7

22

8

SIG RET

23

A2V5MOD6

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

A1V5MOD6

Figure 10-33.


10-143

AZZff

A1CBRW

0 0

NOTES

1

.


Definitions



4. "N.U.




Figure 10-34.

Transfer Register and Memory Module Register Voters,


a

10-144

(

IT )

-

i in. -.

(45,51)

_F_i_g_u_r_e ₁₀_-₃₄_.

1

TO

<l

NU

A 2 9

_

I'M

,1

1

11

t

TM V

i

T M

iL

13

fi

Ail

,

-lit

P, XV

(45)

0

A-SBR.X-

C"»V-

1

jo

.

!

TF3

NU *u

6

1' ^,

e

~S

THRU PINS

Pin

Signal

Pin

Sianal

1

16

2

SIGRET

17

3

VI

18

4

V3

19

5

20

6

21

7

22

8

SIGRET

23

9

VI

24

10

V3

25

26

1?

77

13

SIGRET

28

14

VI

29

15

V3

30

v

I

A?4 L-^SBRxv

CONNECTOR

PINS

Pin

Signal

Pin

Signal

I

NU

51

3

A3W4

53

A2SBRYV

5

A2Z5

55

A1SBRYV

7

NU

57

A1TBR

9

59

11

SIG RET

61

13

SIG RET

63

A2SBRXV

15

A1SBRX

65

A1SBRXV

17

67

A3V5MOD2

19

69

A2V5MOD2

21

A1SBRX

71

A1V5MOD2

23

73

A1CBRN

25

75

27

A1SBRY

77

29

79

A1CBRN

31

81

33

A1SBRY

83

35

85

37

87

V3

39

A1TBRV

89

V3

41

91

A2Z5

43

93

A2Z5

45

95

A1CBRVN

47

VI

97

A2CBRVN

49

VI

99

Transfer Register and Memory Module Register Voters, Logic Diagram (Sheet 2)

10-145

4IV5MODC:

.

AA'UMOOt

f-

(Z?,74,7

«)

AIHI2OH

.

J/M7TN

Jf-

(96)

r-

^/

e— r,r/»r

f»-H

-

NUl5_

_A ;»

fc

A1MSSN

; $

J

f

4

(2g.7< f-,78)

—

(SQ-

r

<

/

~j ₂

1

7|«l'

T"MIS

1 3

.f

K^

/

7?i

NU

//

7 N U

//

„„.

^

.-^

^y j

(88J

7

8\t

NU

/^

,y NU

/

, _g₆ .

X^ ¹ -^

A /^

5

NU

5

^ '

OTf'/O

7 eli

74fA rj

» ^.'

.

vr

1

'!«!/

NU

fj

^

N U < •

,„,

—

7

"fix.

Jl'

w

w

«

7

N

^

^

*!'

ultf

«T

«/

NU|/J

X.?)

BMOW-J

,

ran

'i ^j

NU

<*!•

^

*•

f

i

A,

/

3

fi,

x>/5

/"

/v

si

NU

' /

1

X

_f y

/y

7 81!

^5-

i- SH — ^j[— ^f⁴⁴⁾

(98)

7 el ¹

3 N

~^T'

U

V

fj

1

•«r

— il

NU r ₀

-,

*

n _h t

'

. r>> -

7 /y

*a

<? NU

v

/

x^~

^ fiffTfn

,-r-^\

f56)

^

7 NU | /./,«,,

XV |

OTP//

,

M I

X V

x- NU

X?.V

_f_j f

r/

£

N U

X/V

r

10 » .

^

> z

~i

,,r^

'

" "

-"'

,-,„,

"

/-aî

'^

Figure 10-34.


1—

it

\ &

* *•

10-146

A>

NOTES:


1

2. See Logic Symbols Appendix for

.

Definition

of Logic Symbols




CONNECTOR PINS

Pin

Signal

Pin

Signal

2

NU1

52

4

NU2

54

6

NU3

56

8

A1IMBN

58

10

60

A1MTTVN

12

62

A1MFFN

14

64

16

A1MFFVN

66

18

68

A1MTTN

20

70

22

A1DMBN

72

24

74

26

76

28

78

30

80

A1V5MOD6

32

A1DMBVN

82

A2V5MOD6

34

84

A3V5MOD6

36

86

38

88

40

A1IMBVN

90

A1MZOVN

42

92

A1MZON

44

94

46

A1MSSVN

96

48

98

50

A1MSSN

THRU PINS

Pin

Signal

Pin

Siqnal

1

16

A3V5MOD6

2

SIG RET

17

NU1

3

VI

18

NU2

4

V3

19

NU3

5

20.

6

21

7

22

8

SIG RET

23

A2V5MOD6

9

VI

t-i

10

V3

25

11

26

12

27

13

SIG RET

28

14

VI

29

15

V3

30

A1V5MOD6

Figure 10-34.


10-147

xJ / vSMODf

•

•Vi?

A3\/SMOOi '

•vt

f85)

To NlTU

4lf

-iJS.<>

m

^NÛ

NU

~-% %

insr

_-_^ zisir

^NÛ ^{^}

[gjr

NUI /y

INU

-TPtO

—

(S)

^£ ^NÛ -*- (81)

e NU

Figure 10-35.

Transfer Register Voters,

r/f 13

(33V

(4,4)

^NÛ

⁵

/ £!/

iNU

INU

•^

NU

NU

/y

/y

. f67)

^/ â

0 NU

A ITK9V

_^_- (5<I )

TPII

^_^z^" A tO

/• NU

NU Y

₍₂₃₎


10-148

NOTES:

1 .

See Glossary or Index for Signal Definition s





Pin

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31 "

33

35

37

39

41

43

45

47

49

CONNECTOR PINS

Signal

Pin

Signal

51

A1TR7V

53

A1TR11

55

57.

A1TR9V

59

A1TR7

61

A1TR10V

A1TR8V

63

.

65

67

A1TR13V

69

71

73

VI

75

V3

77

A1TR13

SIGRET

79

81

83

A 1 TR11V

A1TR9

85

87

89

A1TR8

91

A1TR10

VI

93

SIGRET

V3

95

VI

SIG RET

97

V3

THRU PINS

Pin

S iqnal

Pin

Signal

1-

16

A3V5MOD2

2 SIG RET

17

(2,

28, 78)

VI

3 18

(4,

6)

4 19

V3

(4,

6)

5 20

6 21

7 22

8 SIG RET

23

A2V5MOD2

VI

9 24

V3

10 25

11 26

12 27

13 SIG RET

28

VI

14 29

15

V3

30

A1V5MOD2

Figure 10-35.

Transfer Register Voters, Logic Diagram (Sheet 2)

10-149

JIT fit

(Ik)

f€3)

^

A3

,

,j-

ts

—j-

6,

Sfjt

7

B]l

"£•)

(

a

781;

NU

y

-*/' .

v ^ «(/

^1U

^

GJ4

/y

_o_r_f ,j

e.» _f

/

^

NU

xJjj"

N U

£ J2

( t4 !>

'

vj

~ 9

NU

^

s

I ⁶ — -oTPIO

(,

[ SI

r

dal/

x>«y

<*

1

tf['

NU

4 ¹ //

r

/.,-

f,

f

pT *

i

^<?

^5

<$• NU

V/^"

j//

<-J,TK, _V

-v-

v- ¹⁰ - ¹

/

fo/ \

Ob)

₅

/

/*/

-.»

-„, ,

^* ⁴ )

;

>f//'^5

1

NU k,

s

7 S\f

™so if

^?

?&

_N_U

u

7 at

^JNU

/*/

⁽²⁸⁾ -n<t,

ft

^

t

4)

»-^-^ ^f

.

1

'0

slU

«tf

£

&

J .

r\3\

nv

4/S

_^

'

rj

7

flF

hfjNU

IZJ^// ⁷

/y

^2

> ~

:

1

71^1^

NU

#^7

" w

^Jⁱ^£

A-. c

NU w

V

1

'

.

(t «

Ll ,-/»,*

r]n

a NU

A/./I

/

1 " U

nTPII

7 VI

A,0

SB

— fc

-fD

14 i _f ra} _V

] / (- ₅₆ ,

| /^

/ ^- o \

tf

#

* '

A/rvfv

I**'

/N U _v

X/Jf

,,,,

^ ^

' (24)

—;

tOff-f^~n

.9 Lv*l

J xrf

'

I

'

(48)

Figure 10-35.


10-150

NOTES:

1

.





5. Prefix Reference


CONNECTOR PINS

Pin

Signal

Pin

Signal

2

52

4

54

6

56

8

AITR6

58

10

.60

A1TR3V

12

62

A1TR2

14

64

16

A1TR2V

66

18

68

A1TR3 .

20.

70

22

A1TR5

72

24

74

26

76

28

78

30

80

A1V5MO02

32

A1TR5V

82

34

.84

36

86

38

88

40

AITR6V

90

A1TR1V

42

'

92

A1TR1

44

94

46

A1TR4V

96

48

98

50

A1TR4

THRU PINS

Pin

Signal

Pin

Signal

1

16

A3V5MOD2

2

SIG RET

17

(28,

2, 78)

3

VI

18

(4, if.)

4

V3

19

(4,

6)

5

20

6

21

7

22

8

SIG RET

23

A2V5MOD2

9

VI

24

10

V3

25

11

26

12

27

13

SIG RET

28

14

V4

29

15

V3

30

A1V5MOD2

Figure 10-35.


10-151

A3W4 —

A3V5M0D2

A1TR12.

A3K5 —

A1SBR7

-

(i7; —

(IT)

— i

Figure 10-35.

-

t

10

12

1

J.

t

r

i

2.

e

NU

Afl

8

1

TM V

A? 9

|b

₁

TM/

A?2

1

NU

A15

t

— I

8

NU

A 1

It

rn.v

I

9

T

i,

e

1

AZ

7

5

⁶

13 £

7

12

7

13

e

5

£_

^r

*s

13 _

OTP t

V

_A

I

₃₀

V I

A23

NU

Alt

o T»5

VI

A.10

V I

A l

A1TK W

i-Ae ™

.

AISBkt/

A2SBRZV

(35^-1

A3X5 -

AlPA R — (451- —

c*?;—'

T

Id

1

.

TMV

7

13

V I

A30

14.

IB ₁

I

NU|n

A^4|

7

7

VI

A23

*-(*>

?

^.

T»

NU

A17

1

f3 7

NU

A16

1,

w

g

^.

l»

NU

AS

S— oTP1 l

,t

J«J

Th

win '-H

i

1 7

V I

A10

, 4

/

M

Ic

i

TMV

I

A4

13

7

vr

A 3

li

— A 2 PA Rv

NOTES:

1

.






Transfer Register Voters,. Logic Diagram (Sheet 5)

- o

_{ ^^

10-152

L>f

A3W4

<Ci }

^L.

Â

iZ

1

NU

A12

- T

I*!

1

TMV

. t

s

tf

Tfll'

NU

A?*

_T.

< NU'

*—OTP|!

^

li_

»

^' «

F

"H

VI

A34

NU

A27

NU

A20

CONNECTOR PINS

,

'''•' '

[(. ,:

W(il)

•

Pin

Signal

Pin

Signal

1

51

SIGRET

3

A1TR12

53

A3X5

5

55

V3

7

57

A3X5

9

59

A1TRSN

11

A2TR12V

61

13

A1TR12V

63

15

A1SBRZ

65

V3

17

67

19

69

21

71

A1TRSVN

23

A1TRSV

73

A3W4

25

75

VI

27

A2SBRZV

77

A3X5

29

A1SBRZV

79

A1CDSV

31

A1TRS

81

33

83

35

85

AICDS

37

A3W4

87

39

A1PARV

89

41

A2PARV

91

A1V5MOD2

43

A1PAR

93

A2V5MOD2

45

95

A3V5MOD2

47

97

VI

49

SIGRET

'

AICDS .- -

(?*)

-i -

.

8

NU

S—oTPI?

~n?' ^L

1

T

"

. t AJ5

Z TMV

li-

V I

A 34

It

1NU

AZfl

1

riaiu

lilV

r

li_

U_

NU

NU

AZO

THRU PINS

H

!±_

- A1COSV

(83)

Pin

Signal

Pin

Signal

1

16

2

17

3

18

4

19

5

20

6

21

7

22

8

23

9

24

10

25

11

26

12

27

13

28

14

29

15

30

Figure 10-35.


10-153

AnRDMVN

MmSTRP3

MmSYNCV1)

-MmRDPl

-MmRDP2

-MmRDP3

-

,

MCD-1

.

A -

MCD-2

-

a -

-

MCD-2.

^* -

MmSTROB

AnRDMV -

NOTES:

AnlNHBSV

MmMCL

MmMCN

1.


2.


3.

Dotted Line (if any) lndicates Internal ULD Connection

4.

"N.U." Indicates that ULD is Not Installed although Page is 'Wired" to Accommodate it

5.


A6AMA6A1, where M = Memory Module ~ssealyNumber 1Trough 4

6.

Terminals with Numbers Prefixed by "A" are Located on the MIB. All Others are Located on the Printed Circuit Board

7.

m Represents the Memory hdule Number 0 through

3

8.

n

is a

1 if m is an Even Number,

and a 2 if m

is an Odd Number

9. Asterisk Indicates Narrower Output Pulse than , from Receding MCD-2 Circuit

Figure 10- 36.

Memory Clock Driver and TCV, Logic Diagram (Sheet 1 of 2)

10-154


PWR RET

SIG RET

Âⁿ^V²⁰^—^< Î

SIG RET

SIG RET

TERMINAL AREA

-El

PIN

SIGNAL

]

MmTSE2

2

MmTSEl

3

V5

4

V5

5

6

7

VI

8

VI

9

10

TCVADJ

11

AnM20

12

AnM20ID

13

AnM20ID

14

AnRDMV

15

V3

16

V3

17

AnRDMVN

18

SIG RET

19

SIG RET

20

MnSYNCV

21

AnINHBSV

PIN

SIGNAL

22

MmMCN

23

MmMCL

24

PWR RET

25

PWR RET

26

MmSTRPl

27

MmSTRP2

28

AnM20ID

29

AnM20ID

30

MmlNH2

31

MmlNH4

32

MmlNH6

33

MmlNHS

34

MmlNHIO

35

MmlNH12

36

MmlNHU

37

V3

38

MmTCV

39

MmTCV

40

SIG RET

41

SIG RET

42

MmSTROB

20fl

MmCRX—-AA/V-

MmCRY—v-

_M_m_T_C_V

•PWR RET

TERMINAL AREA- E2

PIN

SIGNAL

PIN

SIGNAL

1

MmCRX

6

MmSTRPl

2

MmCRX

7

MmSTRPS

3

MmTCV

8

MmRDP3

4

MmTCV

-9

MmRDP2

5

SIG RET

TERMINAL AREA

- E 4

PIN

SIGNAL

PIN

SIGNAL

1

MmCRY

6

MmRDP2

2

MmCRY

7

MmSTRPl

3

MmTCV

8

MmSTRP2

4

MmTCV

9

MmRDPl

5

SIG RET

1'.

Figure 10-36.

Memory Clock Driver and TCV, Logic Diagram (Sheet 2)

I A6AMA6A1J


10-155

Figure 10-37.

Memory Sense Amplifiers,


10-156


LVUlu-

W!»"

A>

MmSL9A(6B) —

MmSL9B(6A)_

TERMINAL AREA -

E l

MmSLllA(48) —

MmSLUB(4A)

—MmSA9(6)

PIN

SIGNAL

PIN

SIGNAL

1

MmSL14B

16

MmSL7A

2

MmSL14A

17

MmSL6B

3

MmSL13B

18

MmSL6A

4

MmSL13A

19

MmSLSB

5

MmSL12B

20

MmSLSA

6

MmSL12A

21

MmSL4B

7

MmSLllB

22

MmSL4A

8

MmSLllA

23

MmSL3B

9

MmSLlOB

24

MmSL3A

10

MmSLlOA

25

MmSL2B

11

MmSL9B

26

MmSL2A

12

MmSL9A

27

MmSLIB

13

MmSLSB

28

MmSLlA

14

MmSLSA

15

MmSL7B

^—^M^m^SÂ^l^l⁽⁴⁾

MmSL13A(2B)—

MmSL13B(2A)_

^—^M^m^SÂ¹^.³⁽²⁾

TERMINAL AREA -E

3

Pin

Signal

1

MmSTROB

2

3

4

TPSA14

5

TPSA13

6

TPSA12

7

TPSA1 1

8

TPSA10

9

TPSA9

10.

V3

11

TPSA7

12

13

VI

14

V5

15

SIG RET

16

SIGRET

17

V5

18

VI

19

20

TPSA8

21

V3

22

TPSA6

23

TPSA5.

24

TPSA4

25

TPSA3

26

TPSA2

-

27

TPSA1

28

29

Pin

Signal

^;

30

MmSTROB

31

32

33

MmSA14

34

MmSA13

35

MmSA12 .

36

MmSAll

37

MmSAlO

38

MmSA9

39

V3

40

MmSA7

41

42

VI

43

V5

44

SIG RET

45

SIGRET

46

V5

47

VI

48

49

MmSAS

50

V3

51

MmSA6

52

MmSAS

53

MmSA4

54

MmSA3

55

MmSA2

56

MmSAl"

57

58

Figure 10-37.

Memory Sense Amplifiers, Logic Diagram (Sheet 2)


|A6AMA3AI|

₁₀_-₁₅₇

MmSTRPl .

MmSTRP2

MmTVC— »—

r

••

BRA1 —

a —

BRB1 —

B —

BRA6 —

BRB6—

P

BRA 11 —

a —

BRB11 —

—

P

BRA2—

ID

— MmlNHl

BRB° —

ID

P —

,1

'1

TP3

TP4

)

1_

1

"

ID

TP13

.,

ID

—

MmlNH6

— MmlNHl 1

BRA7 —

_B_R_B â ₇ H

fl —

BRA 12—

BRB1° —

&~~

,

,

ID

TP9

ID

T

.

— MmlNH2

—

MmlNH7

MmlNHl 2

BRA3 —

BRB3

—

_I_D

— MmlNH3

P

—

TP11

f

BRAS —

BRB8—

_I_D

-MmlNHS.

P

—

f

r

TP14

BRA 13 —

BRB?3—

ID

— MmlNH13

P

—

I

f

L i

NOTES:



Figure 10-38.

of Logic Symbols



5. Prefix Reference Designations as Follows:

A6AMA7A1, where M = Memory Module Assembly Number iTFirough 4

6. Represents the Memory Module Number

m

0 through 3

is a 1 if

n

m

If

7.

m is an Even Number,

and a 2 if

it an Odd Number

8. m is an Even' Number, a

=AlBRAOVand

0=A2BRAOVN

9. m is an Odd Number, a

If

0 = A2BRBOV

=AlBRBOVNand

Memory Inhibit Drivers, Logic Diagram (Sheet 1 of 2)

10-158

ChangecM January1965

B

<-

F

r

r

/

•

•'

•

•

•

a —

BRB4 —

TP2

1

i

D

TP12

BRA9 —

—

BRB9 —

B —

a

10

—

—

MmlNHf

MmlNH9

•

'•'

_: .

.

'.-.- .

•

BRAS—

BRB5 —

BRA10—

BRB10—

'

_T_P₅

1

D

TPIO

¹^D

— MmlNHH

H

f-

TERMINAL AREA E2

PIN

SIGNAL

PIN

SIGNAL

1

AnM20

6

MmlNH9

2

MmlNHl .

7

MmlNHl 1

3

MmlNH5

8

MmlNHl 3

4

MmlNHS

9

AnM20

5

MmlNH7

TERMINAL AREA E4

PIN

SIGNAL

P|N

SIGNAL

1

0

26

BRA9

2

a

27

BRB11

3

BRA1

28

BRA 11

4

BRB1

29

BRB13

5

BRA3

30

BRA13

6

BRB3

31

PWR RET

7

BRA5

32

PWR RET

8

BRB5

33

PWR RET

9

BRA7

34

MmSTRPl

10

BRB7

35

MmSTRP2

11

BRA6

36

AnM20

12

BRB6

37

AnM20

13

BRA4

38

MmlNH2

14

BRB4

39

MmlNH4

15

BRA2

40

MmlNH6

16

BRB2

41

MmlNHS

17

BRB10

42

MmlNHtO

18

BRA12

43

MmlNH12

19

BRB12

44

MmlNHM

20

BRA14

45

V3

21

BRB14

46

MmTCV

22

BRA10

47

MmTCV

23

BRB8

48

SIG RET

24

BRAS

49

SIGRET

25

BRB9

50

Figvire 10-38.

Memory Inhibit Drivers, Logic Diagram (Sheet 2)

.[A6AMA7A1I

—MmlNHS

-MmlNHlO

Changed 4 January1965

₁₀_-₁₅₉

MmSTRP ¹

E

MmHEYO

lAYOOVN

<

AnAYlOVN—4

MmHIYO

MmCRY

I

I

MmEDIYO

1

MmLIYO

XnAYOVN

(

1

MmLEYO

AnAYWN

(

E

r

R

E

MmHEYl

i

MmHIYl

i

>—MmEDIYl

1

ÂmLIYl

1

MmLEYl

E

i r H

Figure 10-39.

Memory Y-Address Drivers,


10-160

A r.

AnAY20VN—(

c

D

E

F

r

f

^r

^r

AnAY2VN-H

H

C

1

I

1

E

E

I

TERMINAL AREA - E 1

PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

SIGNAL

PIN

SIGNAL

20

MmLIY6

21

22

MmLEY7

23

24

MmL|Y7

MmLEYO

25

26

MmLEYS

MmLlYO

27

28

MmLlYS

MmLEY2

29

30

MmLEYS

MmLIY2

31

32

MmLIY3

MmLEY4

33

34

MmLEYl

MmLIY4

35

36

MmLIYl

MmLEY6

37

38

<

— p-

^M^m^HÊ^Y²

MmHIY2

I— MmEOIYZ

MmLIY2

MmLEY2

AnAYSOVN—4

AnAYSVN

(

i

TERMINAL AREA- E3

1

I

E

':

1

PIN

SIGNAL

PIN

SIGNAL

1

23

2

MmHEYO

24

MmHIY4

3

25

4

MmHIYO

26

MmHEYS

.5

27

6

MmHEYl

28

MmHIYS

7

29

8

MmHIYl

30

9

31

MmHEY6

10

32

MmHIY6

11

33

MmHEY7

12

MmHEY2

34

MmHIY7

13

35

MmCRY

14

MmHIY2

36

MmCRY

15

37

AAnTCV

16

MmHEY3

38

MmTCV

17

39

18

MmHIY3

40

MmRDP2

19

41

MmSTRPl

20

42

MmSTRPZ

21

43

MmRDPl

22

MmHEY4

MmHEY3

MmHIYS

>

— -MmLIY3

:'

MmLEY3

-MmEDIY3

TERMINAL AREA - E 4

A6AMA5A1

PIN

SIGNAL

PIN

SIGNAL

1

MmTCV

18

V3

2

19

EDMY

3

AnM20

20

VI

4

AnAYTVN

21

5

AnAYSVN

•22

PWRRET

6

AnAYSVN

23

PWR RET

7

AnAYOVN

24

AnAY60VN

8

AnAYlVN

25

AnAY40VN

9

AnAY2VN

26

AnAY20VN .

10

AnAY4VN

27

AnAYlOVN

11

AnAY6VN

28

AnAYOOVN

12

SIG RET

29

AnAYSOVN

13

SIGRET

30

AnAYSOVN

14

31

AnAY70VN

15

VI

32

AnM20.

16

EDmY

33

17

V3

34

MmTCV

Figure 10-39.

Memory Y-Address Drivers, Logic Diagram (Sheet 2)


₁₀_-₁₆₁

(B)

MmSTRP ¹

AnAY'HWN

<

(C)

MmRDP2

(D)

MmTCV • "••

(E)

MmCRY

(F)

MmSTRP2

Ar.AY4VN

<

//-^\

(H)

MmRDP l

MmEDEY

1

f

,,

1

^M^m^HÊ^Y⁴

MmHIY4

AnAY50VN_

1

MmEDIY4

^• ^M^m^LÎ^Y⁴

-MmLEY4

AnAY5VN^—<

1

I

F

/B

MmHEYS

AAmHIYS

r T>,

J"

E

_

'

i

t— MmEDlYS

MmLlYS

MmLEYS

k

/• u

Figure 10-39.

Memory Y-Address Drivers, Logic Diagram (Sheet 3)

10-162

A-»

o ^j

$\ 1 > F [ — MmHEY6 MmHEY7 AnAY60VN— < AnAY70VN ^ MmMIVA 1 '$

\

1

>

F

[

—

MmHEY6

MmHEY7

AnAY60VN— <

AnAY70VN

^

MmMIVA

1

'

'

<

>—MmEDIYZ

i

1

MmEDIY6

f

1

Mm l IY 7

AnAYTVN^— <

Mm) FVA

JuLml FV7

F

:

1

i

NOTES:

MmEDIYO

MmEDIYl

MmEDIY2 ——

MitiEDIY3

MmEDIY4

MmEDlYS

MmEDIY6

MmEDIY7^

MmCRY

MmEDEY

1.


2.


of

Logic Symbols

3.


4.

"N.U." Indicates that ULD is Not Installed although Page is "Wired" to Accommodate it

5.


A6AMA5A1, where M = Memory Module Assembly Number 1 TRrough 4

6.

m

Represents the Memory Module Number

0 through 3

7.

n

is a

1 if

m is an Even Number, and a 2 if

m

is an Odd Number.

Figure 10-39.

Memory Y-Address Drivers,


_E_D

—EDmY


10-163

Mm SIR PI

AnAXOOVN^—<

»

MmCRX

MmRDP3

AnAXOOVN

1

MmSTRPl

—

1 ^-~

₍ »—

—

E

I

E

NOTES:

,

MmSlEO

MmSllO

(

1

MmEDIO

MmSOlO

AnAXlOVN — <

1 i—

1 >—

AnAXlOVN— , _'

₍

_>_—

—

I

E

E

1

,

,

i

1

f*.

¹ B

MmSlEl

MmSlll

f

P

1

i

MmEDM

'

'

f

U

MmSOIl

MmSOEl

5

J

1

.


2.


of

Logic Symbols

3.


4.


5.


A6AMA1A1 where M_= Memory Module Assembly Number 1 through 4

6.

m


0 through 3

7.

n

is a

1 if

m is an Even Number, and a 2 if

m

is an Odd

Number

Figure 10-40.

Memory Hi-X Address Drivers,


10-164


8

D

f

f

r,

⁾

AnAX20VN— <

AnAX20VN H

(

^—

¹ « >—

1

••

i

E

-

1

K

I

TERMINAL AREA - E1

PIN

SIGNAL

PIN

SIGNAL

1

MmLEX7

23

2

MmLIX7

24

MmEDI3

3

MmEDI7

25

MmSOIS

4

MmLEX6

26

5

MmLIX 6

•27

MmSOE3

6

MmLEXS

28

7

MmLIXS

29

MmSOI2

8

MmLEX4

30

9

MmLIX4

31

MmSOE2

10

MmEDI6

32

MmEDI2

11

MmSOI7

33

MmSOIl

12

MmSOE7

34 MmSOEl

13

MmSOI6

35 MmEDIl

14

MmSOE6

36 MmSOlO

15

MmEDIS

37 MmSOEO

16

MmSOIS

38 MmEDIO

17

MmSOES

18

MmSOH

19

MmSOE4

20

MmEDU

21

22

MmEDEX

A6AMA1A1I

MmSlE2

kl—CllO

AnAXSOVN

(

_

1

1

> MmSlES

>~

MmSTRPI

(0)

1

MmEDI2

MmSOI2

PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

* 20

21

22

AnAXSOVN—<

'

(

^«

'

1

TERMINAL AREA - E 2

SIGNAL

PIN

SIGNAL

MmTCV

23

PWRRET

24

AnAX2VN

AnM20

25

AnAXOOVN

AnAX70VN

26

AnAXOVN

AnAXTVN

27

AnAX20VN

AnAXSOVN

28

AnAXlVN

AnAXSVN

26

AnAX40VN

AnAXSOVN

30

AnAXSVN

AnAX4VN

31

AnAX60VN

AnAXlOVN

32

AnM20

AnAX6VN

33

SIG RET

34

MmTCV

SIG RET

35

AnSYLOVN

36

VI

EDmX

V3

V3

EDmX

VI

AnSYLlVN

PWRRET

MmRDP3

(C)

^: -AnSYLlVN

(D)

MmTCV

/[)

1

i— MmEDIS

MmSOI3

MmSOE3

1

'•

MmEDEX

flO

X

TERMINAL AREA - E 3

PIN

SIGNAL

PIN

SIGNAL

1

MmRDP2

23

2

MmRDP3

M

MmSIE4

3

MmSTRPS

25

4

MmSTRPl

26

MmSllS

5

T7

MmSlES

6

MmTCV

28

MmSll2

7

MmTCV

29

MmSlE2

8

MmCRX

30

MmSllI

9

MmCRX

31

MmSlEl

10

MmSll7

32

MmSllO

11

MmSlE7

33

MmSlEO

12

34

MmLIXS

13

MmSH6

35

MmLEXS

14

36

MmLIX2

15

MmSlE6

37

MmLEX2

16

38

MmLIX1

17

MmSllS

39

MmLEXl

18

40

MwiLIXO

19

MmSllES

41

MmLEXO

20

42

21

43

22

MmSlU

44

Figure 10-40.

Memory Hi-X Address Drivers, Logic Diagram (Sheet 2)


₁₀_-₁₆₅

MmEDEX-

(B) MmSTRPl-

(A)

AnAX'(CYN- — (

(C) MinRDPS-

(D) AnSYLlVN-

(E)

MmTCV-

/

ff)

(G)

(H)

MmCRX-

AnSYLOVN-

MmRDP3-

J—

AnAX40VN-

(J) MmSTRPl-

(K)

MmEDEX-

<-

'

<

,;

:

-

•

1 r"

( »—

T

•—

—

E

E

MmSlE4

AnAXSOVN— ,

I

MmSlU

i

H-MmEDI4

MmSOU

AnAX50VN — <

Î

t

1

:

$1 ; E _ MmSlES. MmSllS \ ( h- H- MmEDIS 1 * 1 MmSOlS$

1

;

E

_

MmSlES.

MmSllS

\

(

h-

H- MmEDIS

1

*

1

MmSOlS

(

t—

MmSOES

E

1

1

Figure 10-40.

Memory Hi-X Address Drivers, Logic Diagram (Sheet 3)

)«

fr

/i/

f

If

10-166


$tn ° n( \ E AnAX60VN -4 i 1 i *— 1 F J 1$

tn

° n( \

E

AnAX60VN -4

i

1

i *—

1

F J

1

•

<

"-}

^ r

i

AnAX6QVN-<

i »—

E

1

•J i

*<

'

,

.MB.S1E6

(

MmSH6

1

MmEDI6

MmS016

MmSOE6

NOTES:

AnAX70VN—(

AnAX70VN

1

1

i

₁ h—

,

--*•

E

^^

-

₍ h-MmEDI7

— MmSOI7

E

u_cr>E7

MmEDIO

MmFD] 1

MmED12

MmED13

MmED14

MmEDlS

ED

ED

—€OmX

MmED16 —

MmED17

MmfDEX

MmCRX

1.


2.


of

Logic Symbols

3.


4.


5.

Prefix Reference Designations as Fol lows:

A6AMA1A1 where _M = Memory Module Assembly Number 1 through 4

6.

m


0 through 3

7.

n

is a 1 if m is an Even Number,

and a 2

if

m

is an Odd Number

Figure 10-40.

Memory Hi-X Address Drivers,



10-167

MmRDP2

AnAXOVN-

<

•*

MmTCV

AnAX4VN

(

MmRDP?

1

E

MmLEXO

»

MmLIXO

-

MmEDIO

1

•MmEDU

'

MmLIX4

»

MmLEX4

E

NOTES:

AnAXlVN—-<

AnAXSVN

1

I

I

.,

_

E

1

-E

1

B

MmLEXl

MmLIXl

MmEDU

> '

f )

1 •>

c r

t r

' r

MmEDIS

MmLIXS

MmLEXS

I. 3 W

1

.


1.


of Logic Symbols

.

.

3.


4.


5.

frefix Reference Designations as Follows:

A6AMA1A2, where _M = Memory Module Assembly Number 1 through 4

6.

m Represents the Memory Module Number 0 through 3

7.

n

is a

1 if m

is an Even Number,

and a 2

if

Figure 10-41.

m'is an Odd Number

Memory Lo-X Address Drivers,


10-168


M

1

D

r f

r

A

„

A V OV / M

AnAX3VN^—4

MmLIX2

Mm EDI 2

i

>

r

)

Mm£DI6

AnAXTVN ^-^

C

1

r

H C

TERMINAL AREA- E 1

PIN

SIGNAL

PIN

SIGNAL

1

MmEDIO

20

MmSOE4

2

MmSOEO

21

MmSOI4

3

MmSOlO

22

MmSOES

4.

Mm

EDI 1

23

MmSOIS

5

MmSOEl

24

MmEDI5

6

MmSOIl

25

MmSOE6

7

MmEDI2

26

MmSOI6

8

MmSOE2

27

MmSOE7

9

28

MmSOI7

10

MmSOI2

29

MmEDI6

11

30

MmLIX4

12

MmSOES

31

MmLEX4

13

32

MmLIXS

14

MmSOIS

33

MmLEXS

15

MmEDIS

34

MmLIX6

16

35

MmLEX6

17

MmEDEX

36

Mm EDI 7

18

37

MmLIX7

19

MmEDU

38

MmLEX7

TERMINAL AREA- E3

PIN

SIGNAL

PIN

1

23

2

24

3

MmLEXO

25

4

MmLIXO

26

5

MmLEXl

27

6

MmLIXl

28

7

MmLEX2

29

8

MmLIX2

30

9

MmLEXS

31

10

MmLIXS

32

11

MmSlEO

33

12

MmSllO

34

13

MmSlEl

35

14

MmSlll

36

15

MmSlE2

37

16

MmSH2

38

17

MmSlE3

39

18

MmSllS

40

19

41

20

MmSlE4

42

21

43

22

MmSlU

SIGNAL

MmSlES

MmSllS

MmSlE6

MmSll6

MmSlE7

MmSH7

MmCRX

MmCRX

MmTCV

MmTCV

.

MmSTRPl

MmSTRP3

MmRDP3

MmRDP2

\

,

kj _m i iya

MmEDI7

— MmLEX7

| A6AMA1A2|

-MmEDEX

TERMINAL AREA - E 4

PIN

SIGNAL

PIN

SIGNAL

1

MmTCV

19

EDmX

2

20

VI

3

AnM20

21

AnSYLlVN

4

AnAX70VN

22

PWRRET

5

AnAXTVN

23

PWRRET

6

AnAXSOVN

24

AnAX2VN

7

AnAXSVN

25

AnAXOOVN

8

AnAXSOVN

26

AnAXOVN

9

AnAX4VN

27

AnAX20VN

10

AnAXlOVN

28

AnAXIVN

11

AnAX6VN

29

AnAX40VN

12

SIG RET

30

AnAXSVN

13

SIG RET

31

AnAX60VN

14

AnSYLOVN

32

AnM20

15

VI

33

16

EDmX

34

MmTCV

17

V3

35

18

V3

36

Figure 10-41.

Memory Lo-X Address Drivers,



10-169

Figure 10-42.

X Memory Address Diode Matrix, Schematic Diagram (Sheet 1 of 2)

10-170

_*_<_,

Figure 10-42.

•- *<««

r:M

|A6AMA2|

A6AMA2, where _M = Memory Module Assembly Number

X Memory Address Diode Matrix, Schematic Diagram (Sheet 2)

Changed4 January 1965

10-171

Figure 10-43.

Y Memory Address Diode Matrix,

Schematic Diagram (Sheet 1 of 2)

10-172

A <r

B *-

C t~

P >-

E

>•

f t

»•

<r

$•

V

<r

M

H

»

V

V

V

U *

G

H

J

K

L

*

*

P

R

S

7

V *

rTI r"3

^

uO

51

t-.i

1

r"

:

r

.~,f,

~ i

i>£,f.I>*~

r ân

'£,%

|A6AMA4|

-OILIV718Z

-OILEY7180

-OILIY6I78

-OIIEV6I76

-O(LIYS) 86

-OILEY5I84

—OILIY*! 74

—OIIEY4172

—01LIY3190

—o|l£Y3)68

—OILIY2I70

—OIUY2168

—O(LIYI) 9*

-odEYtl 92

—0(UYO)66

-OHEWI64

Figure 10-43.

NOTES:

See Glossary or Index for Signal Definitions See Logic Symbols Appendix for Definition of Logic Symbols Dotted Line (if any) Indicates Internal ULD Connection "N.U." ndicates that ULD is Not Installed although Page is "Wired" to Accommodate It Prefix Reference Designations as Follows:

A6AMA4, where M = Memory Module Assembly Number

Y Memory Address Diode Matrix, Schematic Diagram (Sheet 2)


10-173

TC

V

t p

If

s

Cl

X X

C5

TERMINAL AREA El

Pin

•

Signal

Pin

Signal

1

2

3

MmSA14

4

MmSA13

5

MmSAl 2

6

MmSAll

7

MmSAlO

8

MmSA9

9

V3

10

MmSA7

11

12

VI

13

V5

14

SIG RET

15

SIG RET

16

V5

17

VI

18

19

MmSA8

20

V3

21

MmSA6

22

MmSAS

23

MmSA4

24

MmSA3

25

MmSA2

26

MmSAl

27

28

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*5-7 thru 5-8 Added		4 Jan	65
6-1		Original
6-2 Blank		Original
7-1		Original
7-2 Blank		Original
8-1		Original
8-2 Blank		Original
9-1 thru	9-2	Original
*9-3		4 Jan 65
9-4 thru 9-7 9-8 Blank		Original Original

10-159	4 Jan	65
10-160	Original
*10-161	4 Jan 65
10-162	Original
*10-163 thru
10-169	4 Jan 65
10-170	Original
*10-171	4 Jan 65
10-172	Original
*10-173	4 Jan 65
10-174	Original
*10-175	4 Jan 65

Page No.		_I_s_s_u_e
Title		Original
A		Original
i		Original
ii	Blank	Original
iii thru v		Original
vi	Blank,	Original
3-1 thru 3-12		Original
4-1 thru 4-5		Original
4-6	Blank .	Original
5-1 thru 5-5		.Original
5-6 Blank .		Original
6-1		.Original
6-2 Blank		Original
7-1		Original
7-2 Blank		Original
8-1		Original
8-2 Blank		.Original
9-1 thru 9-7		.Original

Section				Title					Page
m	INTERFACE AND				,				3- 1
	3-1.	Interface				.			3-1
	3-3.	Adjustments						.	3-1
IV	TEST EQUIPMENT AND SPECIAL TOOLS								4-1
	4-1.	Test Equipment							4-1
	4-2.	Standard Test							4-1
	4-4.	Special Test Equipment.							4-1
	4-6.	Special Tools.	.						f 4-1
V	PREPARATION FOR USE, STORAGE AND SHIPMENT							.	5-1
	5-1.	Preparation for Use							5-1
	5-2A.	Inspection and Test				.".'			5-4
	5-3.	Preparation for Storage				'.'	'		5-4
	5-5.	Preparation for							5-5
	5-7	General Computer Handling							5-7
Vl"	PREVENTIVE								6-1
VH	CHECKOUT								7-1
	7-1.	Operating Test Procedures							7-1
VEQ	TROUBLE ISOLATION								8-1
IX	REPAIR								9-1
	9-1.	Repair							9-1
X	DIAGRAMS								10-1
	10-1.	Diagrams							10-1
	10-3.	Signal Tracing							10-2

Figure			Title	Page
10-19 Decoupling Capacitors (Channel 4), Logic Diagram (4 Sheets)				10-70
10-20	Operation Code Voters, Logic Diagram (4 Sheets)			10-74
10-21	Timing Gate and Operation Code Voters,
	Logic Diagram (4 Sheets)			10-78
10-22	Timing and Add-Subtract Voters, Logic Diagram
	(4 Sheets)			10-82
10-23	Timing Voters, Logic Diagram (4 Sheets)			10-86
10-24	Timing and Multiply-Divide Voters, Logic Diagram
	(4 Sheets)			10-90
10-25	Oscillator and Buffer, Logic Diagram (2 Sheets)			10-94
10-26	Clock Generator Timing Logic, Logic Diagram
	(4 Sheets)			10-96
10-27	Timing and Multiply-Divide Voters, Logic Diagram
	(4 Sheets)			10-100
10-28	Multiply-Divide Voters, Logic Diagram (4 Sheets)			10-104
10-29	Decoupling Capacitors (Channel 5), Logic Diagram
	(4 Sheets)			10-108
10-30 Memory		Timing Voters, Logic Diagram (8 Sheets)		10-112
10-31 Memory Address Decoder Voters, Logic Diagram
	(8 Sheets)			10-120
10-32	Memory Buffer Registers, Logic Diagram (12 Sheets)			10-128
10-33	Address Register and Memory Module Register
	Voters,	Logic Diagram (4 Sheets)		10-140
10-34 . Transfer Register and Memory Module Register
	Voters,	Logic Diagram (4 Sheets)		10-144
10-35	Transfer Register Voters,		Logic Diagram (6 Sheets)	10-148
10-36	Memory Clock Driver and TCV, Logic Diagram
(2 Sheets)				10-154
10-37 Memory Sense Amplifiers, Logic Diagram (2 Sheets)				10-156

10-39	Memory Y-Address Drivers, Logic Diagram
	(4 Sheets)			10-160
10-40	Memory Hi-X Address Drivers, Logic Diagram
	(4 Sheets)			10-164
10-41	Memory Lo-X Address Drivers, Logic Diagram ' (2 Sheets)			10-168
10-42 X Memory Address		Diode Matrix, Schematic Diagram
(2 Sheets)				10-170
10-43 Y Memory Address		Diode Matrix,	Schematic Diagram
	(2 Sheets)			10-172
10-44	Memory Input-Output Panel, Schematic Diagram
	(2 Sheets)			10-174
10-45	Memory Distribution Panel, Schematic Diagram
	(4 Sheets)			10-176
10-46	Signal Origin List (8 Sheets)			10-180

J2	nK	CHANNEL 1, SINGLE STEP CONTROL
J2	E	CHANNEL 2» SINGLE STEP CONTROL
J2	K	CHANNEL 3» SINGLE STEP CONTROL
J2	DM	CHANNEL 1» MEMORY LOAD
J2	DA	CHANNEL 2» MEMORY LOAD
J2	L	CHANNEL 3. MEMORY LOAD
J2	R	CHANNEL 1. HOP CONSTANT
J2	HH	CHANNEL 2» HOP CONSTANT
J2		CHANNEL 3» HOP CONSTANT
J2	nC	CHANNEL 1» MARGINAL CHECK LATE» STROBE CONTROL
J2	D	CHANNEL 2» MARGINAL CHECK STROBE CONTROL
J2	U	CHANNEL 1, MARGINAL CHECK STROBE CONTROL
J2	CC	CHANNEL 2» MARGINAL CHECK STROBE CONTROL LATCH 7
J2	an	CHANNEL 1. MULTIPLICAND DIVISOR REGISTER
J2	N	CHANNEL 2. MULTIPLICAND DIVISOR REGISTER LATCH 7
J2	M	CHANNEL 3, MULTIPLICAND DIVISOR REGISTER LATCH 7
J2	F	CHANNEL 1» MULTIPLIER REGISTER LATCH
J2		CHANNEL 2. MULTIPLIER REGISTER LATCH
J2	nu	CHANNEL 3» MULTIPLIER REGISTER LATCH
J2	J	CHANNEL 1. OPERATION CODE REGISTER LATCH
J2	H	CHANNEL 2. OPERATION CODE REGISTER OPERATION CODE REGISTER LATCH
J2	G	CHANNEL 3, OPERATION CODE REGISTER OPERATION CODE REGISTER LATCH
J2	B	CHANNEL 1» OPERATION CODE REGISTER OPERATION CODE REGISTER LATCH
J2	C	CHANNEL 2» OPERATION CODE REGISTER OPERATION CODE REGISTER LATCH
J2	A	CHANNEL 3, OPERATION CODE REGISTER OPERATION CODE REGISTER LATCH
J2	np	CHANNEL 1> OPERATION CODE REGISTER LATCH
J2	Z	CHANNEL 2» OPERATION CODE REGISTER LATCH
J2	nx	CHANNEL 3. OPERATION CODE REGISTER LATCH
J2	S	CHANNEL 1. OPERATION CODE REGISTER LATCH
J2	ns	CHANNEL 2. OPERATION CODE REGISTER LATCH
J2	DG	CHANNEL 3. OPERATION CODE REGISTER LATCH
J2	nD	CHANNEL 1. PRODUCT REMAINDER LATCH
J2	av	CHANNEL 2» PRODUCT REMAINDER LATCH.
J2	EE	CHANNEL 3. PRODUCT REMAINDER LATCH
J2	W	CHANNEL 1, RESET MEMORY tRROR INDICATION
J2		CHANNEL 2. RESET MEMORY ERROR INDICATION
J2	aw	CHANNEL	3. RESETS MEMORY ERROR INDI CAT ION
J2	DD	BUFFER REGISTER A, PARITY BIT
J2	nB	BUFFER REGISTER B PARITY SIT
J2	nY	LTE INTERLOCK FOR LTE USE ONLY
J2	az	LTE INTERLOCK FOR LTE USE ONLY
J2	P	SIGNAL RETURN. DC REGULATED
J2	X	SIGNAL RETURN. DC REGULATED
J2	Y	SIGNAL RETURN. DC REGULATED
J2	BB	SIGNAL RETURN. REGULATED DC
J2	FF	SIGNAL	RETURN. REGULATED i;C
J2	T
J2	V
J2	aF
J2	^a^j n(\\|
J2
J2	no
J2	PR
J2	AA
J2	GG

C	CHANNEL 1, TIMING SYNC FOR DATA ADAPTER
n'Y	CHANNEL 2, TIMING SYNC FOR DATA ADAPTER
np	CHANNEL 3, TIMING SYNC FOR DATA ADAPTER,
ns	CHANNEL 1, TIMING SYNC FOR DATA ADAPTER
nA	CHANNEL 2, TIMING SYNC FOR DATA ADAPTER
R	CHANNEL 3, TIMING SYNC FOR DATA ADAPTER
nB	CHANNEL 1, TIMING SYNC FOR DATA ADAPTER
K	CHANNEL 2, TIMING SYNC FOR DATA ADAPTER
N	CHANNEL 3, TIMING SYNC FOR DATA ADAPTER
F	CHANNEL 1, TIMING SYNC FOR DATA ADAPTER
J	CHANNEL 2, TIMING SYNC FOR DATA ADAPTER
HH	CHANNEL 3, TIMING SYNC FOR DATA ADAPTER
H	CHANNEL 1, TIMING SYNC FOR DATA ADAPTER
nH	CHANNEL 2, TIMING SYNC FOR DATA ADAPTER
QK	CHANNEL 3, TIMING SYNC FOR DATA ADAPTER.
G	CHANNEL 1, TIMING SYNC FOR DATA ADAPTER
M	CHANNEL 2, TIMING SYNC FOR DATA ADAPTER
nj	CHANNEL 3». TIMING		SYNC FOR DATA ADAPTER
DD	2.048	MC TIMING
nF	2.048	MC TIMING
a\f	2.048	MC TIMING

W		LTE INTERLOCK FOR LTE USE ONLY
X		LTE INTERLOCK FOR LTE USE ONLY
E	.	SIGNAL RETURN	LINE 07-A1XDA
L		SIGNAL RETURN	LINE 08-A2WUA
P		SIGNAL RETURN. LINE 09-A3PBVN .
S		SIGNAL RETURN. LINE 10-A3YDA
z	SIGNAL RETURN, LINE 11-A2PBVN
ⁿ C	. SIGNAL RETURN, LINE 12-A1ZOA

QE	SIGNAL RETURN, LINE 14-A2XOA .
nG	SIGNAL RETURN, LINE 15-A2ZDA
nl	SIGNAL RETURN, LINE 16-A3WDA
nN	SIGNAL RETURN, LINE 17-A3G5VN
nR	SIGNAL RETURN, LINE 18-A1G5N
nT	SIGNAL RETURN, LINE 19-A1WDA
nu	SIGNAL RETURN, LINE 20-B01N
nw .	SIGNAL RETURN, LINE 21-B02N
nx	SIGNAL RETURN, LINE 22-A2YJA
nz	SIGNAL RETURN, LINE 23-A3ZDA
CC	SIGNAL	RETURN/LIN E 24-A3XOA
EE	SIGNAL RETURN, LINE 25-BC3N
FF	SIGNAL RETURN, LIKE 26-A3XDA
GG	SIGNAL RETURN, LINE 27-A2G5VN
A
B
D
T
U
V
Y

NAME	CONNECTOR	PIN		FUNCTION,
A1AI3V	J4	nM	CHANNEL 1» ACCUMULATOR THIRD DELAY LATCH
A2AI3V	J4	nz	CHANNEL 2. ACCUMULATOR THIRD DELAY LATCH
A3AI3V	J4	nQ	CHANNEL 3» ACCUMULATOR THIRD DELAY LATCH
A1PIOV	J4	GG	CHANNEL 1, PROCESS INPUT-OUTPUT
A2PIOV	J4	U	CHANNEL 2» PROCESS INPUT-OUTPUT
A3PIOV	J4	u	CHANNEL 3» PROCESS INPUT-OUTPUT
EP01	J4	w	ERROR SIGNAL 01
EP02	J4	nR	ERROR	SIGNAL 02	.			.
EP03	J4	T	ERROR SIGNAL 03
EP04	J4	AA	ERROR SIGNAL 04
EP06	J4	V	ERROR	SIGNAL 06	'	•	.
EP07	J4	nN	ERROR SIGNAL 07
INTRLK	J4	nG	LTE INTERLOCK FOR LTE USE ONLY
INTRLK	J4	nH	LTE INTERLOCK FOR LTE USE ONLY
SR28	J4	A	SIGNAL	RETURN* LINE	28-EP06
SR29	J4	B	SIGNAL RETURN* LINE		29-A1PIOV.A3PIOV
SR30	J4	P	SIGNAL RETURN* LINE		30-A2AI.3
SR31	J4	S	SIGNAL	RETURN. LINE	31-EP03
SR32	J4	X	SIGNAL RETURN. LINE		32-EP01
SR33	J4	z	SIGNAL RETURN. LINE		33-THEKM			THERM 2,
SR34	J4	np	SIGNAL RETURN. LINE		34-EPC7
SR35	J4	as	SIGNAL RETURN. LINE		35-EPC2
SR36	J4	BB	SIGNAL	RETURN. LINE. 36-EP04
SR37	J4	CC	SIGNAL RETURN. LINE		37-A3AI3V
SR38	J4	HH	SIGNAL	RETURN, LINE	38-A1AI3V
THERM1	J4	Y	THERMISTOR 1 LEAD 1
THERM2	J4	D	THERMISTOR 1 LEAD 2
SPARE	J4	E
SPARE	J4	F
SPARE	J4	G
SPARE	J4	H
SPARE	J4	J
SPARE	J4	K
SPARE	J4	L
SPARE	J4	M
SPARE	J4	N
SPARE	J4	R
SPARE	J4	aA
SPARE	J4	nB
SPARE	J4	aC
SPARE	J4	nD
SPARE	J4	a£
SPARE	J4	nF
SPARE	J4	nl
SPARE	J4	nj
SPARE	J4	nK
SPARE	J4	nT
SPARE	J4	PU
SPARE	J4	av
SPARE	J4	nw
SPARE	J4	nx
SPARE	J4	QY
SPARE	J4	DD
SPARE	J4	EE
SPARE	J4	FF

NAME	CONNECTOR		i PIN		FUNCTION'
INTRLK		J6	K	LTE INTERLOCK FOR LTE USE ONLY
INTRLK		J6	L	LTE INTERLOCK FOR LTE USE ONLY
SR48		J6	H	SIGNAL RETURN, LINE 48-V1		05
SR49		J6	N	SIGNAL RETURN, LINE 49-V1		21
SR50		J6	P	SIGNAL RETURN, LINE 50-V1		15
SR51		J6	R	SIGNAL RETURN, LINE 51-V1		07
SR52		J6	nC	SIGNAL RETURN, LINE 52-V1		04
SR53		J6	nD	SIGNAL RETURN, LINE. 53-V1		13
SR54		J6	n£	SIGNAL RETURN, LINE 54-V1		14
SR55		J6	aF	SIGNAL RETURN, LINE 55-V1		20
SR56		J6	QG	SIGNAL RETURN, LINE 56-V1		24 •
SR57		J6	J	SIGNAL RETURN, LINE 57-V1		06
SR58		J6	nH	SIGNAL RETURN, LINE 58-V1		23
SR59		J6	Ql	SIGNAL RETURN, LINE- 59-V1		22'
SR60		J6	nj	SIGNAL RETURN, LINE 60-V1		16
SR61		J6	nK	SIGNAL RETURN, LINE 61-V1 62-V1		Oo" '
SR62		J6	nM	SIGNAL RETURN, LINE		01
SR63		J6	DU	SIGNAL RETURN, LINE 63-V1		12
SR64		J6	nv	SIGNAL RETURN, LINE 64-V1 65-V1 66-V1 67-V1		19.
SR65		J6	aw	SIGNAL RETURN, LINE		18
SR66		J6	ax	SIGNAL RETURN, LINE		17
SR67		J6	DY	SIGNAL RETURN, LINE		09
SR68		J6	EE SIGNAL RETURN, LINE 68-V1			17
SR69		J6	FF SIGNAL RETURN, LINE 69-V1			10
SR70		J6	GG SIGNAL RETURN, LINE 70-V1			02.
SR71		J6	HH ' SIGNAL RETURN, LINE 71-V1			03
*V1 01		J6	A	6	VDC, LINE 1
*V1 02		J6	B	6	VDC, LINE 2
*V1 03		J6	C	6	VDC, LINE 3
*V1 04		J6	D	6VDC, LINE 4
*V1 05		J6	E	6VDC, LINE 5
*V1 06		J6	F	6 VDC, LINE 6
*V1 07		J6	T	6VDC, LINE 07
*V1 08		J6	U	6VDC, LINE 08
*V1 09		J6	V	6VDC, LINE 09
*V1 10		J6	w	6VDC, LINE 10
*V1 11		J6	X	6VDC, LINE 11
*V1 12		J6	Y	6VDC, LINE 12
*V1 13		J6	Z	6	VDC, LINE 13
*V1 14		J6	nA	6	VDC, LINE 14
*V1 15		J6	S	6	VDC, LINE 15
*V1 16		J6	aN	6	VDC, LINE 16
*V1 17		J6	ap	6	VDC, LINE 17
*V1 18		J6	no	6VDC, LINE 18
*V1 19		J6	aR	6	VDC, LINE 19
*V1 20		J6	nS	6	VDC, LINE 20
*V1 21		J6	DZ	6	VDC, LINE 21
*V1 22		J6	AA 6		VDC, LINE 22
*V1 23		J6	BB 6		VDC, LINE 2?
*V1 24		J6	CC 6		VOC, LINE 24
SPARE		J6	G
SPARE		J6	M
SPARE		J6	aB
SPARE		J6
SPARE		J6	DO
NOTE	*OENOTES	INPUTS	TO COMPUTER, nINDICATt S LOWER CASE			LETTER

J7			E	ELAPSED TIME INDICATOR 1
J7			F	ELAPSED TIME INDICATOR 2
J7			GG	LTE. INTERLOCK FOR LTt USE ONLY
J7			HH	LTE INTERLOCK FOR LTE USE ONLY
J7	^:		A	MEMORY SIGNAL RETURN*. LINc 01-V20bMl
J7			B	MEMORY SIGNAL RETURN. LINE 02-V3MEM1
J7	.		C	MEMORY SIGNAL RETURN. LINE 03-V1MEM1
J7			D	MEMORY SIGNAL RETURN. LINE 04-V20AM1
J7			U	MEMORY SIGNAL RETURN. LINE 05-V20BM2
J7			V	MEMORY SIGNAL RETURN. LINE .06-V3MEM2
J7			Y	MEMORY SIGNAL RETURN, LINE 07-V5MEM1
J7			aB	MEMORY SIGNAL RETURN. LINE 0-V5MEM2
J7			G	MEMORY SIGNAL RETURN, LINE 09-V20AM2
J7			no	MEMORY SIGNAL RETURN LINE 10-V1MEM3
J7			AA	MEMORY SIGNAL RETURN, LINE 11-V1MEM2
J7			.H
J7			nD	SIGNAL RETURN. LINE 73-V5 02
J7			J	SIGNAL, RETURN. LINE		75-V5 01
J7			M	SIGNAL RETURN. LINE 76-V20 01
J7			nG	SIGNAL RETURN. LINE 77-V20 02
J7			nl	SIGNAL RETURN. LINE 78-V3 01. V3 02
J7		.	nj	SIGNAL RETURN. LINE 79-V3 03, V3 04
J7.			DM	SIGNAL RETURN. LINE SO-V3 05, V3 08
J7			nx	.SIGNAL RETURN. LINE 82-V3 09.
J7			nZ	SIGNAL RETURN. LINE		. 83-V3 07. V3 10
J7	"		EE	SIGNAL RETURN, LINE 85-V3 06
J7			nR	6	VDC, LINE 01, MEMORY
J7			BB	6	VDC, LINE 02, MEMORY
J7			CC	6	VDC, LINE 03, MEMORY
J7			nA	20	VDC, LINE 1, EVEN MEMORY
J7			nN	20	VDC, LINE 02, ODD MEMORY
J7			W	20	VDC LINE 01 ODD MEMORY
J7			nT	20	VDC, LINE 2, EVEN MEMORY
J7			L	20	VDC. LINE 01
J7			nF	20	VDC. LINE 02.
J7			X	-3 VDC, LINE 01 MEMORY
J7			np	-3 VDC. LINE 02, MEMORY
J7			nH	-3	VDC, LINE 01
J7			N	-3	VDC. LINE 02
J7			P	-3	VDC, LINE 03
J7			R	-3	VDC, LINE 04
J7			S	-3	VDC, LINE 05
J7			nv	-3	VDC, LINE 06
J7			nY	-3	VDC. LINE 07
J7			nH	-3	VDC, LINE 08
J7			aw	-3	VDC, LINE 09
J7			FF	-3	VDC, LINE 10
J7			Z	12 -VDC, LINE 01, MEMORY
J7			ns	12	VDC, LINE 02, MEMORY
J7			K	12	VDC, LINE 01
J7			n£	12	VDC, LINE 02
J7			T
J7			aC
J7			DU
J7			DD

NAME	CONNECTOR PIN		_F_U_N_C_T_I_O_N
A1A1V	J8	T	CHANNEL 1, OPERAND ADDRESS 3IT 1
A2A1V	J8	nM	CHANNEL 2» OPERAND ADDRESS BIT 1
A3A1V	J8	np	CHANNEL 3. OPERAND ADDRESS BIT 1
A1A2V	J8	DD	CHANNEL 1» OPERAND ADDRESS BIT 2
A2A2V	J8	BB	CHANNEL 2» OPERAND ADDRESS BIT 2
A3A2V	J8	AA	CHANNEL 3» OPERAND ADDRESS BIT 2
A1A3V	J8	nN	CHANNEL 1» OPERAND ADDRESS oIT 3
A2A3V	J8	CC	CHANNEL 2. OPERAND ADDRESS BIT 3
A3A3V	J8	nQ	CHANNEL 3» OPERAND ADDRESS oIT 3
A1A4V	J8	FF	CHANNEL 1» OPERAND ADDRESS BIT 4
A2A4V	J8	GG	CHANNEL 2» OPERAND ADDRESS BIT 4
A3A4V	J8	ol	CHANNEL 3» OPERAND ADDRESS BIT 4
A1A5V	J8	R	CHANNEL .1* OPERAND ADDRESS BIT 5
A2A5V	J8	aw	CHANNEL 2» OPERAND ADDRESS BIT 5
A3A5V	J8	nj	CHANNEL 3» OPERAND ADDRESS BIT 5
A1A6V	J8	nv	CHANNEL 1» OPERAND ADDRESS BIT 6
A2A6V	J8	QY	CHANNEL 2» OPERAND ADDRESS 3IT 6
A3A6V	J8	nK	CHANNEL 3» OPERAND ADDRESS BIT 6
A1A7V	J8	A	CHANNEL 1, OPERAND ADDRESS BIT 7
A2A7V	J8	X	CHANNEL 2» OPERAND ADDRESS BIT 7
A3A7V	J8	nR	CHANNEL 3» OPERAND ADDRESS BIT 7
A1A8V	J8	EE	CHANNEL 1, OPERAND ADDRESS BIT 8
A2A8V	J8	HH	CHANNEL 2. OPERAND ADDRESS BIT 8
A3A8V	J8	S	CHANNEL 3» OPERAND ADDRESS BIT 8
A1A9V	J8	Y	CHANNEL 1» OPERAND ADDRESS BIT 9
A2A9V	J8	C	CHANNEL 2» OPERAND ADDRESS BIT 9
A3A9V	J8	W	CHANNEL 3» OPERAND ADDRESS BIT 9
A1TRSV	J8	F	CHANNEL 1. TRANSFER REGISTER OUTPUT
A2TRSV	J8	E	CHANNEL 2. TRANSFER REGISTER OUTPUT
A3TRSV	J8	D	CHANNEL 3» TRANSFER REGISTER OUTPUT
INTRLK	J8	K	LTE INTERLOCK FOR LTE USE ONLY
INTRLK	J8	L	LTE INTERLOCK FOR LTE USE ONLY .
SR86	J8	V	SIGNAL RETURN* LINE 86 OPERAND ADDRESS BITS Al,A2» A3»A7, AND A9 FOR CHANNELS 1.2.AND3
SR87	J8	z	SIGNAL RETURN. LINE 87 TRSV» CHANNELS 1»2» AND 3
SR88	J8	nl	SIGNAL RETURN. LINE 88 OPERAND ADDRESS BITS A4.A5»
			A6. AND A8 FOR CHANNELS 1	2.	AND 3
SPARE	J8	B
SPARE	J8	G
SPARE	J8	H
SPARE	J8	J
SPARE	J8	M
SPARE	J8	N
SPARE	J8	P
SPARE	J8	u'
SPARE	J8	aA
SPARE	J8	nB
SPARE	J8	nC
SPARE	J8	nD
SPARE	J8	nE
SPARE	J8	nF
SPARE	J8	nG
SPARE	J8	nH
SPARE	J8	as
SPARE	J8	nT
SPARE	J8	nu
SPARE	J8	nx

Note:
1.	See Figure 3-3 for Computer and Data Adapter Interconnections

4-1.	TEST EQUIPMENT.
4-2.	STANDARD TEST EQUIPMENT.
4-3.	The standard test equipment recommended to maintain the computer is listed in
figure	4-1.
4-4.	SPECIAL TEST EQUIPMENT.
4-5.	The special test equipment required to maintain the computer is listed in figure
4-2.	-	'	'	.'	.	.	'	.	;	'.-•'.-•	'''•''•.-'"	•	'	'•'• •	:
4-6.	SPECIAL TOOLS.
4-7.	The special tools recommended to maintain the computer are listed in figure 4-4.

Differential	Voltmeter	803- B	John Fluke Mfg. Co. , Inc.
Volt- Ohm- Ammeter		630- A	Triplett Electrical Instrument Co,
Oscilloscope		585A	Tektronix, Inc.
Oscilloscope Adapter		81	Tektronix, Inc.
Oscilloscope	Plug- In Unit	M	Tektronix, Inc.

Launch Vehicle	IBM 6902000 MD1	Used to test and evaluate com-
Digital Com-		puter operation.
puter-Manual
Exerciser
Test Program	IBM 6001225	Contains a program which,
Tape		when loaded into the com- puter memory, permits the Launch Vehicle Digital ^Computer-Manual Exerciser to check each functional part of the computer that can be exercised by a pro- gram.

Name	Manufacturer's	Index No.
Name	Designation	(Figure 4-5)
Handling Dolly	IBM 658042
Lift Handles	IBM D-656101	3
Memory Handle	IBM 658044	2
Page Extractor	IBM 657922	1
Test Point
Adapter	Number to be sup- plied.

5-1.	PREPARATION FOR USE.	.
5-2.	The computer is shipped in a reuseable shipping container (part number 6019994,

g.	Open the shock recorder.
gl.	Remove the spool that contains the recorded portion of chart paper (figure 5-2).
			CAUTION
	When removing chart paper, handle chart
	paper	carefully.	Cut (do not tear) the chart
	paper to detach recorded portion. The
	paper is pressure sensitive,			and data may
	be obliterated by rough or excessive handling.
g2.	Cut the chart paper, remove it from the spool, and replace the spool in the

Figure 5-1.	Reuseable Shipping Container
Figure 5-2.	Removing Roll Chart From Shock Recorder
5-2

g4.	Close and latch the shock recorder.
g5.	Reinstall the shock recorder (handle side up) in the shipping container.
g6.	On a blank portion of the removed section of chart paper, record the

h. Ship removed section of chart paper to:
	Saturn Programs Office, Department 839
	IBM Space Guidance Center
	Owego, New York, 13827	'
hi. Use a vacuum cleaner to clean the interior of container if foreign material or debris

5-2A.	INSPECTION AND TEST.
5-2B.	After the computer has been unpacked, proceed as follows:

a.	Install dust covers (part number 6036037) on the eight computer connector jacks.
al.	Unlatch and remove shipping container cover.
a2.	Use a vacuum cleaner to clean interior of container if foreign material or debris

b.	Remove mounting bolts from computer shipping container.
bl.	Attach lift handles to computer as described in paragraph 5-8.

IBM Part Number	No. of Units	Quantity Used
6019623	8	2
6019653	1	1
e. Secure cover on shipping container.
f. Turn pressure equalizer screw fully	clockwise.
	NOTE

a.	Install dust covers (part number 6036037) on the eight computer connector jacks,
al.	Unlatch and remove container cover.
b.	Remove mounting bolts	from computer shipping container.

c2.	Open the shock recorder and check for damage.
d.	Thread roll chart onto takeup spool of shock recorder.	(See figure 5-3.)
dl.	Close cover and strike recorder sharply against floor.	Open cover and verify that