DMC.

6/1/16, 6:08 PM

;
; File:
NodeA.asm
; Author:
M. Metlitz
; Date:
22 Apr 2016
;
; Specify processor
list P=PIC12F752
; Include file for standard definitions
#include "P12F752.inc"
; Specify configurations
__config (_CP_OFF & _WDT_OFF & _PWRTE_ON & _FOSC_INT)
;
; Reset Vector
;
; Variable definitions
WREG_TEMP
equ
0x41
;temporary W storage for interrupts
STATUS_TEMP equ
0x42
;temporary STATUS storage
PCLATH_TEMP equ
0x43
;temporary PCLATH storage
SHIFTREG
equ
0x44
;shift register
DATA_R
equ
0x45
;file to store information from receive
DATA_W
equ
0x46
;file of data to be written out in transmit
COUNTER
equ
0x47
;counter for shifting in/out data
SHIFT_STATE equ
0x48
;for testing if you're input/output
PAIRED
equ
0x49
;state of switches
org
goto
org
goto
org

0
SETUP
4
ISR
5

;origin, where code starts

;go to setup sequence out of reset
;assign org 4 tp interrupt service routine

SETUP:
;
; Initialize PORTA
;
banksel
movlw
movwf

OSCCON
b'00110000'
OSCCON

BANKSEL
PORTA
CLRF
PORTA
BANKSEL
LATA
CLRF
LATA
BANKSEL
ANSELA
CLRF
ANSELA
BANKSEL
TRISA
MOVLW
b'00000001'
MOVWF
TRISA
banksel
LATA
BSF
LATA, 1
purposes

;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA0 as input for data line from UART
;config on ports
;just for testing and following data in

;
; Initialize PWM
;
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DMC.s

6/1/16, 6:08 PM

banksel
movlw
movwf
banksel
movlw
movwf
banksel
movlw
movwf
banksel
movlw
movwf

CCP1CON
b'00111100'
CCP1CON
PR2
b'11111111'
PR2
CCPR1L
b'01100000'
CCPR1L
T2CON
b'00000111'
T2CON;

;
; Initialize interrupts
;
BANKSEL
INTCON
BSF
INTCON,GIE
BSF
INTCON,3
(IOCIE)
BSF
INTCON,6
BANKSEL
IOCAN
BSF
IOCAN,IOCAN0
INIT_TIMER1:
banksel
movlw
movwf
goto
;
; Initialize timers
;

T1CON
b'01110100'
T1CON
MAIN

;
; Interrupt Vector
;
; Interrupt response
ISR:
PUSH:
movwf
WREG_TEMP
movf
STATUS,W
clrf
STATUS
movwf
STATUS_TEMP
movf
PCLATH,W
movwf
PCLATH_TEMP
clrf
PCLATH
ISR_BODY:
BANKSEL
bcf
(IOCIF)
BANKSEL
btfsc
goto
routine

; makes pwm mode

;value for period
; duty cycle
;prescaler 1:16

;Enable global interrupts

;Enable interrupt on change functionality
;Peripheral Interrupts enabled (PEIE)
;IOC for negative edge register
;Enable negative IOC for data line input RA0

;don't sync, prescale 1:8

;use Fosc/4
;main loop of code

;save WREG
;store STATUS in WREG
;change to file register bank0
;save STATUS value
;store PCLATH in WREG
;save PCLATH value
;change to program memory page0
;ISR should configure Bank as required

INTCON
INTCON,0

;interrupt occured so clear upper level flag

IOCAF
IOCAF,IOCAF0
INIT_HALF_TIME

;check if interrupt was from IOC on RA0

;interrupt was from IOC, go to receive

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DMC.s

6/1/16, 6:08 PM

banksel
btfsc
goto
goto

PIR1
PIR1, TMR1IF
SHIFT_DATA
POP

INIT_HALF_TIME:
BANKSEL
bcf
BANKSEL
BCF

IOCAF
IOCAF,IOCAF0
IOCAN
IOCAN,IOCAN0

;check if interrupt was from timer 1 timeout

;go to routine to shift in data
;interrupt was not from pin, leave routine
;calibrate timer for receive
;clear lower level interrupt flag on RA0
;IOC for negative edge register
;Disable negative IOC for data line input

movlw
banksel
movwf
banksel
movlw
movwf
movlw
banksel
movwf
banksel
BSF
banksel
BSF

b'00000000'
;pre-scale 1:1 for t/2 rate
T1CON
T1CON
;set resptective bits
TMR1H
0xff
TMR1H
0xaf
;set low TMR1 to ~52 for half time of 9600 baud
TMR1L
TMR1L
PIE1
PIE1, TMR1IE
;enable interrupt for timer 1
T1CON
T1CON, TMR1ON
;turn timer 1 on

banksel
BCF
BANKSEL
clrf
BSF
GOTO

LATA
LATA,1
COUNTER
COUNTER
COUNTER,7
POP

SHIFT_DATA:
banksel
write
bcf
banksel
btfsc
goto
NORMAL_SHIFT:
banksel
incf
btfsc
goto
BANKSEL
RLF
banksel
BCF
banksel
movlw
movwf
movlw
movwf
banksel

PIR1

;initialize counter
;flag for t/2 to t transition

;we know we only shift in data to read not

PIR1, TMR1IF
;clear interrupt flag from timer 1 timeout
COUNTER
COUNTER,7
;test t/2 indicator in counter
START_FULL_TIME ;go to routine to start full timer
COUNTER
COUNTER,f
COUNTER,3
DISABLE_TIMER
SHIFTREG
SHIFTREG,f
T1CON
T1CON, TMR1ON
TMR1H
0xff
TMR1H
0x5f
TMR1L
T1CON

;increment counter
;make sure it's below 8
;reached counter max, time to end read
;shift SR left to prepare for read
;turn timer 1 off

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DMC.s

6/1/16, 6:08 PM

BSF
BANKSEL
BTFSS
GOTO
GOTO
WRITE_LO:
BANKSEL
BCF
banksel
BCF
GOTO
WRITE_HI:
BANKSEL
BSF
banksel
BSF
GOTO
START_FULL_TIME:
banksel
BCF
banksel
movlw
movwf
banksel
movlw
movwf
banksel
clrf
banksel
BSF
goto

T1CON, TMR1ON

;turn timer 1 on

PORTA
PORTA, 0
WRITE_LO
WRITE_HI

;read RA0 for data

;need to set lo
;need to set hi

SHIFTREG
SHIFTREG,0
LATA
LATA, 1
POP
SHIFTREG
SHIFTREG,0
LATA
LATA, 1
POP

;write values to SR to store and read later

;clear LSB of SR
;leave ISR
;set LSB of SR
;leave ISR

T1CON
T1CON, TMR1ON
;turn timer 1 off
TMR1H
0xff
TMR1H
TMR1L
0x5f
TMR1L
COUNTER
COUNTER
;remove t/2 flag
T1CON
T1CON, TMR1ON
;turn timer 1 on
POP
;leave ISR to wait for next timeout

DISABLE_TIMER:
banksel
T1CON
BCF
T1CON, TMR1ON
;turn timer 1 off
banksel
PIE1
BCF
PIE1, TMR1IE
;disable interrupt for timer 1
BANKSEL
SHIFTREG
MOVF
SHIFTREG,w
;copy SR contents to working register
BANKSEL
DATA_R
MOVWF
DATA_R
;copy working register to data read file
BANKSEL
SHIFTREG
MOVWF
SHIFTREG
;move same copy to SR, not sure if necessary
BANKSEL
IOCAN
;IOC for negative edge register
BSF
IOCAN,IOCAN0
;Enable negative IOC for data line input
goto
BIT_TESTING
;operations based on what was read in .......
....(This used to be Bit_Testing)
BIT_TESTING:
;banksel
;bsf
banksel
BTFSS
GOTO

LATA
LATA, 4
DATA_R
DATA_R, 6
UNPAIRED
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DMC.s

6/1/16, 6:08 PM

GOTO

PAIRED_PWM

UNPAIRED:
banksel
BCF
BCF
banksel
movlw
movwf
GOTO

LATA
LATA, 4
LATA, 5
CCPR1L
b'01100000'
CCPR1L
POP

PAIRED_PWM
banksel
movlw
movwf
banksel
BTFSC
GOTO
CALL
banksel
BTFSC
GOTO
GOTO

CCPR1L
b'00001111'
CCPR1L
DATA_R
DATA_R, 5
LIGHT_BLUE
OFF_BLUE
DATA_R
DATA_R, 4
LIGHT_RED
OFF_RED

LIGHT_BLUE:
banksel
BSF
GOTO

LATA
LATA, 5
POP

; duty cycle

; duty cycle

OFF_BLUE:;this is what I changed if light doesn't work

banksel
LATA
BCF
LATA, 5
return
LIGHT_RED:
banksel
BSF
GOTO

LATA
LATA, 4
POP

OFF_RED:
banksel
BCF
GOTO

LATA
LATA, 4
POP

clrf
movf
movwf
movf
movwf
swapf
swapf
retfie

STATUS
PCLATH_TEMP,W
PCLATH
STATUS_TEMP,W
STATUS
WREG_TEMP,F
WREG_TEMP,W

POP:
;select bank 0
;store saved PCLATH value in WREG
;restore PCLATH
;store saved STATUS value in WREG
;restore STATUS
;prepare WREG to be restored
;restore WREG keeping STATUS bits
;return from interrupt

; Main body of code

MAIN:
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DMC.s

6/1/16, 6:08 PM

nop
goto
end

MAIN

;kill cycle for better debugging visual

;infinite loop
;end of source code

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